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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */2/*3 * Copyright(c) 2015 - 2018 Intel Corporation.4 */5 6#ifndef _HFI1_SDMA_H7#define _HFI1_SDMA_H8 9#include <linux/types.h>10#include <linux/list.h>11#include <asm/byteorder.h>12#include <linux/workqueue.h>13#include <linux/rculist.h>14 15#include "hfi.h"16#include "verbs.h"17#include "sdma_txreq.h"18 19/* Hardware limit */20#define MAX_DESC 6421/* Hardware limit for SDMA packet size */22#define MAX_SDMA_PKT_SIZE ((16 * 1024) - 1)23 24#define SDMA_MAP_NONE 025#define SDMA_MAP_SINGLE 126#define SDMA_MAP_PAGE 227 28#define SDMA_AHG_VALUE_MASK 0xffff29#define SDMA_AHG_VALUE_SHIFT 030#define SDMA_AHG_INDEX_MASK 0xf31#define SDMA_AHG_INDEX_SHIFT 1632#define SDMA_AHG_FIELD_LEN_MASK 0xf33#define SDMA_AHG_FIELD_LEN_SHIFT 2034#define SDMA_AHG_FIELD_START_MASK 0x1f35#define SDMA_AHG_FIELD_START_SHIFT 2436#define SDMA_AHG_UPDATE_ENABLE_MASK 0x137#define SDMA_AHG_UPDATE_ENABLE_SHIFT 3138 39/* AHG modes */40 41/*42 * Be aware the ordering and values43 * for SDMA_AHG_APPLY_UPDATE[123]44 * are assumed in generating a skip45 * count in submit_tx() in sdma.c46 */47#define SDMA_AHG_NO_AHG 048#define SDMA_AHG_COPY 149#define SDMA_AHG_APPLY_UPDATE1 250#define SDMA_AHG_APPLY_UPDATE2 351#define SDMA_AHG_APPLY_UPDATE3 452 53/*54 * Bits defined in the send DMA descriptor.55 */56#define SDMA_DESC0_FIRST_DESC_FLAG BIT_ULL(63)57#define SDMA_DESC0_LAST_DESC_FLAG BIT_ULL(62)58#define SDMA_DESC0_BYTE_COUNT_SHIFT 4859#define SDMA_DESC0_BYTE_COUNT_WIDTH 1460#define SDMA_DESC0_BYTE_COUNT_MASK \61 ((1ULL << SDMA_DESC0_BYTE_COUNT_WIDTH) - 1)62#define SDMA_DESC0_BYTE_COUNT_SMASK \63 (SDMA_DESC0_BYTE_COUNT_MASK << SDMA_DESC0_BYTE_COUNT_SHIFT)64#define SDMA_DESC0_PHY_ADDR_SHIFT 065#define SDMA_DESC0_PHY_ADDR_WIDTH 4866#define SDMA_DESC0_PHY_ADDR_MASK \67 ((1ULL << SDMA_DESC0_PHY_ADDR_WIDTH) - 1)68#define SDMA_DESC0_PHY_ADDR_SMASK \69 (SDMA_DESC0_PHY_ADDR_MASK << SDMA_DESC0_PHY_ADDR_SHIFT)70 71#define SDMA_DESC1_HEADER_UPDATE1_SHIFT 3272#define SDMA_DESC1_HEADER_UPDATE1_WIDTH 3273#define SDMA_DESC1_HEADER_UPDATE1_MASK \74 ((1ULL << SDMA_DESC1_HEADER_UPDATE1_WIDTH) - 1)75#define SDMA_DESC1_HEADER_UPDATE1_SMASK \76 (SDMA_DESC1_HEADER_UPDATE1_MASK << SDMA_DESC1_HEADER_UPDATE1_SHIFT)77#define SDMA_DESC1_HEADER_MODE_SHIFT 1378#define SDMA_DESC1_HEADER_MODE_WIDTH 379#define SDMA_DESC1_HEADER_MODE_MASK \80 ((1ULL << SDMA_DESC1_HEADER_MODE_WIDTH) - 1)81#define SDMA_DESC1_HEADER_MODE_SMASK \82 (SDMA_DESC1_HEADER_MODE_MASK << SDMA_DESC1_HEADER_MODE_SHIFT)83#define SDMA_DESC1_HEADER_INDEX_SHIFT 884#define SDMA_DESC1_HEADER_INDEX_WIDTH 585#define SDMA_DESC1_HEADER_INDEX_MASK \86 ((1ULL << SDMA_DESC1_HEADER_INDEX_WIDTH) - 1)87#define SDMA_DESC1_HEADER_INDEX_SMASK \88 (SDMA_DESC1_HEADER_INDEX_MASK << SDMA_DESC1_HEADER_INDEX_SHIFT)89#define SDMA_DESC1_HEADER_DWS_SHIFT 490#define SDMA_DESC1_HEADER_DWS_WIDTH 491#define SDMA_DESC1_HEADER_DWS_MASK \92 ((1ULL << SDMA_DESC1_HEADER_DWS_WIDTH) - 1)93#define SDMA_DESC1_HEADER_DWS_SMASK \94 (SDMA_DESC1_HEADER_DWS_MASK << SDMA_DESC1_HEADER_DWS_SHIFT)95#define SDMA_DESC1_GENERATION_SHIFT 296#define SDMA_DESC1_GENERATION_WIDTH 297#define SDMA_DESC1_GENERATION_MASK \98 ((1ULL << SDMA_DESC1_GENERATION_WIDTH) - 1)99#define SDMA_DESC1_GENERATION_SMASK \100 (SDMA_DESC1_GENERATION_MASK << SDMA_DESC1_GENERATION_SHIFT)101#define SDMA_DESC1_INT_REQ_FLAG BIT_ULL(1)102#define SDMA_DESC1_HEAD_TO_HOST_FLAG BIT_ULL(0)103 104enum sdma_states {105 sdma_state_s00_hw_down,106 sdma_state_s10_hw_start_up_halt_wait,107 sdma_state_s15_hw_start_up_clean_wait,108 sdma_state_s20_idle,109 sdma_state_s30_sw_clean_up_wait,110 sdma_state_s40_hw_clean_up_wait,111 sdma_state_s50_hw_halt_wait,112 sdma_state_s60_idle_halt_wait,113 sdma_state_s80_hw_freeze,114 sdma_state_s82_freeze_sw_clean,115 sdma_state_s99_running,116};117 118enum sdma_events {119 sdma_event_e00_go_hw_down,120 sdma_event_e10_go_hw_start,121 sdma_event_e15_hw_halt_done,122 sdma_event_e25_hw_clean_up_done,123 sdma_event_e30_go_running,124 sdma_event_e40_sw_cleaned,125 sdma_event_e50_hw_cleaned,126 sdma_event_e60_hw_halted,127 sdma_event_e70_go_idle,128 sdma_event_e80_hw_freeze,129 sdma_event_e81_hw_frozen,130 sdma_event_e82_hw_unfreeze,131 sdma_event_e85_link_down,132 sdma_event_e90_sw_halted,133};134 135struct sdma_set_state_action {136 unsigned op_enable:1;137 unsigned op_intenable:1;138 unsigned op_halt:1;139 unsigned op_cleanup:1;140 unsigned go_s99_running_tofalse:1;141 unsigned go_s99_running_totrue:1;142};143 144struct sdma_state {145 struct kref kref;146 struct completion comp;147 enum sdma_states current_state;148 unsigned current_op;149 unsigned go_s99_running;150 /* debugging/development */151 enum sdma_states previous_state;152 unsigned previous_op;153 enum sdma_events last_event;154};155 156/**157 * DOC: sdma exported routines158 *159 * These sdma routines fit into three categories:160 * - The SDMA API for building and submitting packets161 * to the ring162 *163 * - Initialization and tear down routines to buildup164 * and tear down SDMA165 *166 * - ISR entrances to handle interrupts, state changes167 * and errors168 */169 170/**171 * DOC: sdma PSM/verbs API172 *173 * The sdma API is designed to be used by both PSM174 * and verbs to supply packets to the SDMA ring.175 *176 * The usage of the API is as follows:177 *178 * Embed a struct iowait in the QP or179 * PQ. The iowait should be initialized with a180 * call to iowait_init().181 *182 * The user of the API should create an allocation method183 * for their version of the txreq. slabs, pre-allocated lists,184 * and dma pools can be used. Once the user's overload of185 * the sdma_txreq has been allocated, the sdma_txreq member186 * must be initialized with sdma_txinit() or sdma_txinit_ahg().187 *188 * The txreq must be declared with the sdma_txreq first.189 *190 * The tx request, once initialized, is manipulated with calls to191 * sdma_txadd_daddr(), sdma_txadd_page(), or sdma_txadd_kvaddr()192 * for each disjoint memory location. It is the user's responsibility193 * to understand the packet boundaries and page boundaries to do the194 * appropriate number of sdma_txadd_* calls.. The user195 * must be prepared to deal with failures from these routines due to196 * either memory allocation or dma_mapping failures.197 *198 * The mapping specifics for each memory location are recorded199 * in the tx. Memory locations added with sdma_txadd_page()200 * and sdma_txadd_kvaddr() are automatically mapped when added201 * to the tx and nmapped as part of the progress processing in the202 * SDMA interrupt handling.203 *204 * sdma_txadd_daddr() is used to add an dma_addr_t memory to the205 * tx. An example of a use case would be a pre-allocated206 * set of headers allocated via dma_pool_alloc() or207 * dma_alloc_coherent(). For these memory locations, it208 * is the responsibility of the user to handle that unmapping.209 * (This would usually be at an unload or job termination.)210 *211 * The routine sdma_send_txreq() is used to submit212 * a tx to the ring after the appropriate number of213 * sdma_txadd_* have been done.214 *215 * If it is desired to send a burst of sdma_txreqs, sdma_send_txlist()216 * can be used to submit a list of packets.217 *218 * The user is free to use the link overhead in the struct sdma_txreq as219 * long as the tx isn't in flight.220 *221 * The extreme degenerate case of the number of descriptors222 * exceeding the ring size is automatically handled as223 * memory locations are added. An overflow of the descriptor224 * array that is part of the sdma_txreq is also automatically225 * handled.226 *227 */228 229/**230 * DOC: Infrastructure calls231 *232 * sdma_init() is used to initialize data structures and233 * CSRs for the desired number of SDMA engines.234 *235 * sdma_start() is used to kick the SDMA engines initialized236 * with sdma_init(). Interrupts must be enabled at this237 * point since aspects of the state machine are interrupt238 * driven.239 *240 * sdma_engine_error() and sdma_engine_interrupt() are241 * entrances for interrupts.242 *243 * sdma_map_init() is for the management of the mapping244 * table when the number of vls is changed.245 *246 */247 248/*249 * struct hw_sdma_desc - raw 128 bit SDMA descriptor250 *251 * This is the raw descriptor in the SDMA ring252 */253struct hw_sdma_desc {254 /* private: don't use directly */255 __le64 qw[2];256};257 258/**259 * struct sdma_engine - Data pertaining to each SDMA engine.260 * @dd: a back-pointer to the device data261 * @ppd: per port back-pointer262 * @imask: mask for irq manipulation263 * @idle_mask: mask for determining if an interrupt is due to sdma_idle264 *265 * This structure has the state for each sdma_engine.266 *267 * Accessing to non public fields are not supported268 * since the private members are subject to change.269 */270struct sdma_engine {271 /* read mostly */272 struct hfi1_devdata *dd;273 struct hfi1_pportdata *ppd;274 /* private: */275 void __iomem *tail_csr;276 u64 imask; /* clear interrupt mask */277 u64 idle_mask;278 u64 progress_mask;279 u64 int_mask;280 /* private: */281 volatile __le64 *head_dma; /* DMA'ed by chip */282 /* private: */283 dma_addr_t head_phys;284 /* private: */285 struct hw_sdma_desc *descq;286 /* private: */287 unsigned descq_full_count;288 struct sdma_txreq **tx_ring;289 /* private: */290 dma_addr_t descq_phys;291 /* private */292 u32 sdma_mask;293 /* private */294 struct sdma_state state;295 /* private */296 int cpu;297 /* private: */298 u8 sdma_shift;299 /* private: */300 u8 this_idx; /* zero relative engine */301 /* protect changes to senddmactrl shadow */302 spinlock_t senddmactrl_lock;303 /* private: */304 u64 p_senddmactrl; /* shadow per-engine SendDmaCtrl */305 306 /* read/write using tail_lock */307 spinlock_t tail_lock ____cacheline_aligned_in_smp;308#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER309 /* private: */310 u64 tail_sn;311#endif312 /* private: */313 u32 descq_tail;314 /* private: */315 unsigned long ahg_bits;316 /* private: */317 u16 desc_avail;318 /* private: */319 u16 tx_tail;320 /* private: */321 u16 descq_cnt;322 323 /* read/write using head_lock */324 /* private: */325 seqlock_t head_lock ____cacheline_aligned_in_smp;326#ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER327 /* private: */328 u64 head_sn;329#endif330 /* private: */331 u32 descq_head;332 /* private: */333 u16 tx_head;334 /* private: */335 u64 last_status;336 /* private */337 u64 err_cnt;338 /* private */339 u64 sdma_int_cnt;340 u64 idle_int_cnt;341 u64 progress_int_cnt;342 343 /* private: */344 seqlock_t waitlock;345 struct list_head dmawait;346 347 /* CONFIG SDMA for now, just blindly duplicate */348 /* private: */349 struct tasklet_struct sdma_hw_clean_up_task350 ____cacheline_aligned_in_smp;351 352 /* private: */353 struct tasklet_struct sdma_sw_clean_up_task354 ____cacheline_aligned_in_smp;355 /* private: */356 struct work_struct err_halt_worker;357 /* private */358 struct timer_list err_progress_check_timer;359 u32 progress_check_head;360 /* private: */361 struct work_struct flush_worker;362 /* protect flush list */363 spinlock_t flushlist_lock;364 /* private: */365 struct list_head flushlist;366 struct cpumask cpu_mask;367 struct kobject kobj;368 u32 msix_intr;369};370 371int sdma_init(struct hfi1_devdata *dd, u8 port);372void sdma_start(struct hfi1_devdata *dd);373void sdma_exit(struct hfi1_devdata *dd);374void sdma_clean(struct hfi1_devdata *dd, size_t num_engines);375void sdma_all_running(struct hfi1_devdata *dd);376void sdma_all_idle(struct hfi1_devdata *dd);377void sdma_freeze_notify(struct hfi1_devdata *dd, int go_idle);378void sdma_freeze(struct hfi1_devdata *dd);379void sdma_unfreeze(struct hfi1_devdata *dd);380void sdma_wait(struct hfi1_devdata *dd);381 382/**383 * sdma_empty() - idle engine test384 * @engine: sdma engine385 *386 * Currently used by verbs as a latency optimization.387 *388 * Return:389 * 1 - empty, 0 - non-empty390 */391static inline int sdma_empty(struct sdma_engine *sde)392{393 return sde->descq_tail == sde->descq_head;394}395 396static inline u16 sdma_descq_freecnt(struct sdma_engine *sde)397{398 return sde->descq_cnt -399 (sde->descq_tail -400 READ_ONCE(sde->descq_head)) - 1;401}402 403static inline u16 sdma_descq_inprocess(struct sdma_engine *sde)404{405 return sde->descq_cnt - sdma_descq_freecnt(sde);406}407 408/*409 * Either head_lock or tail lock required to see410 * a steady state.411 */412static inline int __sdma_running(struct sdma_engine *engine)413{414 return engine->state.current_state == sdma_state_s99_running;415}416 417/**418 * sdma_running() - state suitability test419 * @engine: sdma engine420 *421 * sdma_running probes the internal state to determine if it is suitable422 * for submitting packets.423 *424 * Return:425 * 1 - ok to submit, 0 - not ok to submit426 *427 */428static inline int sdma_running(struct sdma_engine *engine)429{430 unsigned long flags;431 int ret;432 433 spin_lock_irqsave(&engine->tail_lock, flags);434 ret = __sdma_running(engine);435 spin_unlock_irqrestore(&engine->tail_lock, flags);436 return ret;437}438 439void _sdma_txreq_ahgadd(440 struct sdma_txreq *tx,441 u8 num_ahg,442 u8 ahg_entry,443 u32 *ahg,444 u8 ahg_hlen);445 446/**447 * sdma_txinit_ahg() - initialize an sdma_txreq struct with AHG448 * @tx: tx request to initialize449 * @flags: flags to key last descriptor additions450 * @tlen: total packet length (pbc + headers + data)451 * @ahg_entry: ahg entry to use (0 - 31)452 * @num_ahg: ahg descriptor for first descriptor (0 - 9)453 * @ahg: array of AHG descriptors (up to 9 entries)454 * @ahg_hlen: number of bytes from ASIC entry to use455 * @cb: callback456 *457 * The allocation of the sdma_txreq and it enclosing structure is user458 * dependent. This routine must be called to initialize the user independent459 * fields.460 *461 * The currently supported flags are SDMA_TXREQ_F_URGENT,462 * SDMA_TXREQ_F_AHG_COPY, and SDMA_TXREQ_F_USE_AHG.463 *464 * SDMA_TXREQ_F_URGENT is used for latency sensitive situations where the465 * completion is desired as soon as possible.466 *467 * SDMA_TXREQ_F_AHG_COPY causes the header in the first descriptor to be468 * copied to chip entry. SDMA_TXREQ_F_USE_AHG causes the code to add in469 * the AHG descriptors into the first 1 to 3 descriptors.470 *471 * Completions of submitted requests can be gotten on selected472 * txreqs by giving a completion routine callback to sdma_txinit() or473 * sdma_txinit_ahg(). The environment in which the callback runs474 * can be from an ISR, a tasklet, or a thread, so no sleeping475 * kernel routines can be used. Aspects of the sdma ring may476 * be locked so care should be taken with locking.477 *478 * The callback pointer can be NULL to avoid any callback for the packet479 * being submitted. The callback will be provided this tx, a status, and a flag.480 *481 * The status will be one of SDMA_TXREQ_S_OK, SDMA_TXREQ_S_SENDERROR,482 * SDMA_TXREQ_S_ABORTED, or SDMA_TXREQ_S_SHUTDOWN.483 *484 * The flag, if the is the iowait had been used, indicates the iowait485 * sdma_busy count has reached zero.486 *487 * user data portion of tlen should be precise. The sdma_txadd_* entrances488 * will pad with a descriptor references 1 - 3 bytes when the number of bytes489 * specified in tlen have been supplied to the sdma_txreq.490 *491 * ahg_hlen is used to determine the number of on-chip entry bytes to492 * use as the header. This is for cases where the stored header is493 * larger than the header to be used in a packet. This is typical494 * for verbs where an RDMA_WRITE_FIRST is larger than the packet in495 * and RDMA_WRITE_MIDDLE.496 *497 */498static inline int sdma_txinit_ahg(499 struct sdma_txreq *tx,500 u16 flags,501 u16 tlen,502 u8 ahg_entry,503 u8 num_ahg,504 u32 *ahg,505 u8 ahg_hlen,506 void (*cb)(struct sdma_txreq *, int))507{508 if (tlen == 0)509 return -ENODATA;510 if (tlen > MAX_SDMA_PKT_SIZE)511 return -EMSGSIZE;512 tx->desc_limit = ARRAY_SIZE(tx->descs);513 tx->descp = &tx->descs[0];514 INIT_LIST_HEAD(&tx->list);515 tx->num_desc = 0;516 tx->flags = flags;517 tx->complete = cb;518 tx->coalesce_buf = NULL;519 tx->wait = NULL;520 tx->packet_len = tlen;521 tx->tlen = tx->packet_len;522 tx->descs[0].qw[0] = SDMA_DESC0_FIRST_DESC_FLAG;523 tx->descs[0].qw[1] = 0;524 if (flags & SDMA_TXREQ_F_AHG_COPY)525 tx->descs[0].qw[1] |=526 (((u64)ahg_entry & SDMA_DESC1_HEADER_INDEX_MASK)527 << SDMA_DESC1_HEADER_INDEX_SHIFT) |528 (((u64)SDMA_AHG_COPY & SDMA_DESC1_HEADER_MODE_MASK)529 << SDMA_DESC1_HEADER_MODE_SHIFT);530 else if (flags & SDMA_TXREQ_F_USE_AHG && num_ahg)531 _sdma_txreq_ahgadd(tx, num_ahg, ahg_entry, ahg, ahg_hlen);532 return 0;533}534 535/**536 * sdma_txinit() - initialize an sdma_txreq struct (no AHG)537 * @tx: tx request to initialize538 * @flags: flags to key last descriptor additions539 * @tlen: total packet length (pbc + headers + data)540 * @cb: callback pointer541 *542 * The allocation of the sdma_txreq and it enclosing structure is user543 * dependent. This routine must be called to initialize the user544 * independent fields.545 *546 * The currently supported flags is SDMA_TXREQ_F_URGENT.547 *548 * SDMA_TXREQ_F_URGENT is used for latency sensitive situations where the549 * completion is desired as soon as possible.550 *551 * Completions of submitted requests can be gotten on selected552 * txreqs by giving a completion routine callback to sdma_txinit() or553 * sdma_txinit_ahg(). The environment in which the callback runs554 * can be from an ISR, a tasklet, or a thread, so no sleeping555 * kernel routines can be used. The head size of the sdma ring may556 * be locked so care should be taken with locking.557 *558 * The callback pointer can be NULL to avoid any callback for the packet559 * being submitted.560 *561 * The callback, if non-NULL, will be provided this tx and a status. The562 * status will be one of SDMA_TXREQ_S_OK, SDMA_TXREQ_S_SENDERROR,563 * SDMA_TXREQ_S_ABORTED, or SDMA_TXREQ_S_SHUTDOWN.564 *565 */566static inline int sdma_txinit(567 struct sdma_txreq *tx,568 u16 flags,569 u16 tlen,570 void (*cb)(struct sdma_txreq *, int))571{572 return sdma_txinit_ahg(tx, flags, tlen, 0, 0, NULL, 0, cb);573}574 575/* helpers - don't use */576static inline int sdma_mapping_type(struct sdma_desc *d)577{578 return (d->qw[1] & SDMA_DESC1_GENERATION_SMASK)579 >> SDMA_DESC1_GENERATION_SHIFT;580}581 582static inline size_t sdma_mapping_len(struct sdma_desc *d)583{584 return (d->qw[0] & SDMA_DESC0_BYTE_COUNT_SMASK)585 >> SDMA_DESC0_BYTE_COUNT_SHIFT;586}587 588static inline dma_addr_t sdma_mapping_addr(struct sdma_desc *d)589{590 return (d->qw[0] & SDMA_DESC0_PHY_ADDR_SMASK)591 >> SDMA_DESC0_PHY_ADDR_SHIFT;592}593 594static inline void make_tx_sdma_desc(595 struct sdma_txreq *tx,596 int type,597 dma_addr_t addr,598 size_t len,599 void *pinning_ctx,600 void (*ctx_get)(void *),601 void (*ctx_put)(void *))602{603 struct sdma_desc *desc = &tx->descp[tx->num_desc];604 605 if (!tx->num_desc) {606 /* qw[0] zero; qw[1] first, ahg mode already in from init */607 desc->qw[1] |= ((u64)type & SDMA_DESC1_GENERATION_MASK)608 << SDMA_DESC1_GENERATION_SHIFT;609 } else {610 desc->qw[0] = 0;611 desc->qw[1] = ((u64)type & SDMA_DESC1_GENERATION_MASK)612 << SDMA_DESC1_GENERATION_SHIFT;613 }614 desc->qw[0] |= (((u64)addr & SDMA_DESC0_PHY_ADDR_MASK)615 << SDMA_DESC0_PHY_ADDR_SHIFT) |616 (((u64)len & SDMA_DESC0_BYTE_COUNT_MASK)617 << SDMA_DESC0_BYTE_COUNT_SHIFT);618 619 desc->pinning_ctx = pinning_ctx;620 desc->ctx_put = ctx_put;621 if (pinning_ctx && ctx_get)622 ctx_get(pinning_ctx);623}624 625/* helper to extend txreq */626int ext_coal_sdma_tx_descs(struct hfi1_devdata *dd, struct sdma_txreq *tx,627 int type, void *kvaddr, struct page *page,628 unsigned long offset, u16 len);629int _pad_sdma_tx_descs(struct hfi1_devdata *, struct sdma_txreq *);630void __sdma_txclean(struct hfi1_devdata *, struct sdma_txreq *);631 632static inline void sdma_txclean(struct hfi1_devdata *dd, struct sdma_txreq *tx)633{634 if (tx->num_desc)635 __sdma_txclean(dd, tx);636}637 638/* helpers used by public routines */639static inline void _sdma_close_tx(struct hfi1_devdata *dd,640 struct sdma_txreq *tx)641{642 u16 last_desc = tx->num_desc - 1;643 644 tx->descp[last_desc].qw[0] |= SDMA_DESC0_LAST_DESC_FLAG;645 tx->descp[last_desc].qw[1] |= dd->default_desc1;646 if (tx->flags & SDMA_TXREQ_F_URGENT)647 tx->descp[last_desc].qw[1] |= (SDMA_DESC1_HEAD_TO_HOST_FLAG |648 SDMA_DESC1_INT_REQ_FLAG);649}650 651static inline int _sdma_txadd_daddr(652 struct hfi1_devdata *dd,653 int type,654 struct sdma_txreq *tx,655 dma_addr_t addr,656 u16 len,657 void *pinning_ctx,658 void (*ctx_get)(void *),659 void (*ctx_put)(void *))660{661 int rval = 0;662 663 make_tx_sdma_desc(664 tx,665 type,666 addr, len,667 pinning_ctx, ctx_get, ctx_put);668 WARN_ON(len > tx->tlen);669 tx->num_desc++;670 tx->tlen -= len;671 /* special cases for last */672 if (!tx->tlen) {673 if (tx->packet_len & (sizeof(u32) - 1)) {674 rval = _pad_sdma_tx_descs(dd, tx);675 if (rval)676 return rval;677 } else {678 _sdma_close_tx(dd, tx);679 }680 }681 return rval;682}683 684/**685 * sdma_txadd_page() - add a page to the sdma_txreq686 * @dd: the device to use for mapping687 * @tx: tx request to which the page is added688 * @page: page to map689 * @offset: offset within the page690 * @len: length in bytes691 * @pinning_ctx: context to be stored on struct sdma_desc .pinning_ctx. Not692 * added if coalesce buffer is used. E.g. pointer to pinned-page693 * cache entry for the sdma_desc.694 * @ctx_get: optional function to take reference to @pinning_ctx. Not called if695 * @pinning_ctx is NULL.696 * @ctx_put: optional function to release reference to @pinning_ctx after697 * sdma_desc completes. May be called in interrupt context so must698 * not sleep. Not called if @pinning_ctx is NULL.699 *700 * This is used to add a page/offset/length descriptor.701 *702 * The mapping/unmapping of the page/offset/len is automatically handled.703 *704 * Return:705 * 0 - success, -ENOSPC - mapping fail, -ENOMEM - couldn't706 * extend/coalesce descriptor array707 */708static inline int sdma_txadd_page(709 struct hfi1_devdata *dd,710 struct sdma_txreq *tx,711 struct page *page,712 unsigned long offset,713 u16 len,714 void *pinning_ctx,715 void (*ctx_get)(void *),716 void (*ctx_put)(void *))717{718 dma_addr_t addr;719 int rval;720 721 if ((unlikely(tx->num_desc == tx->desc_limit))) {722 rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_PAGE,723 NULL, page, offset, len);724 if (rval <= 0)725 return rval;726 }727 728 addr = dma_map_page(729 &dd->pcidev->dev,730 page,731 offset,732 len,733 DMA_TO_DEVICE);734 735 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {736 __sdma_txclean(dd, tx);737 return -ENOSPC;738 }739 740 return _sdma_txadd_daddr(dd, SDMA_MAP_PAGE, tx, addr, len,741 pinning_ctx, ctx_get, ctx_put);742}743 744/**745 * sdma_txadd_daddr() - add a dma address to the sdma_txreq746 * @dd: the device to use for mapping747 * @tx: sdma_txreq to which the page is added748 * @addr: dma address mapped by caller749 * @len: length in bytes750 *751 * This is used to add a descriptor for memory that is already dma mapped.752 *753 * In this case, there is no unmapping as part of the progress processing for754 * this memory location.755 *756 * Return:757 * 0 - success, -ENOMEM - couldn't extend descriptor array758 */759 760static inline int sdma_txadd_daddr(761 struct hfi1_devdata *dd,762 struct sdma_txreq *tx,763 dma_addr_t addr,764 u16 len)765{766 int rval;767 768 if ((unlikely(tx->num_desc == tx->desc_limit))) {769 rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_NONE,770 NULL, NULL, 0, 0);771 if (rval <= 0)772 return rval;773 }774 775 return _sdma_txadd_daddr(dd, SDMA_MAP_NONE, tx, addr, len,776 NULL, NULL, NULL);777}778 779/**780 * sdma_txadd_kvaddr() - add a kernel virtual address to sdma_txreq781 * @dd: the device to use for mapping782 * @tx: sdma_txreq to which the page is added783 * @kvaddr: the kernel virtual address784 * @len: length in bytes785 *786 * This is used to add a descriptor referenced by the indicated kvaddr and787 * len.788 *789 * The mapping/unmapping of the kvaddr and len is automatically handled.790 *791 * Return:792 * 0 - success, -ENOSPC - mapping fail, -ENOMEM - couldn't extend/coalesce793 * descriptor array794 */795static inline int sdma_txadd_kvaddr(796 struct hfi1_devdata *dd,797 struct sdma_txreq *tx,798 void *kvaddr,799 u16 len)800{801 dma_addr_t addr;802 int rval;803 804 if ((unlikely(tx->num_desc == tx->desc_limit))) {805 rval = ext_coal_sdma_tx_descs(dd, tx, SDMA_MAP_SINGLE,806 kvaddr, NULL, 0, len);807 if (rval <= 0)808 return rval;809 }810 811 addr = dma_map_single(812 &dd->pcidev->dev,813 kvaddr,814 len,815 DMA_TO_DEVICE);816 817 if (unlikely(dma_mapping_error(&dd->pcidev->dev, addr))) {818 __sdma_txclean(dd, tx);819 return -ENOSPC;820 }821 822 return _sdma_txadd_daddr(dd, SDMA_MAP_SINGLE, tx, addr, len,823 NULL, NULL, NULL);824}825 826struct iowait_work;827 828int sdma_send_txreq(struct sdma_engine *sde,829 struct iowait_work *wait,830 struct sdma_txreq *tx,831 bool pkts_sent);832int sdma_send_txlist(struct sdma_engine *sde,833 struct iowait_work *wait,834 struct list_head *tx_list,835 u16 *count_out);836 837int sdma_ahg_alloc(struct sdma_engine *sde);838void sdma_ahg_free(struct sdma_engine *sde, int ahg_index);839 840/**841 * sdma_build_ahg - build ahg descriptor842 * @data843 * @dwindex844 * @startbit845 * @bits846 *847 * Build and return a 32 bit descriptor.848 */849static inline u32 sdma_build_ahg_descriptor(850 u16 data,851 u8 dwindex,852 u8 startbit,853 u8 bits)854{855 return (u32)(1UL << SDMA_AHG_UPDATE_ENABLE_SHIFT |856 ((startbit & SDMA_AHG_FIELD_START_MASK) <<857 SDMA_AHG_FIELD_START_SHIFT) |858 ((bits & SDMA_AHG_FIELD_LEN_MASK) <<859 SDMA_AHG_FIELD_LEN_SHIFT) |860 ((dwindex & SDMA_AHG_INDEX_MASK) <<861 SDMA_AHG_INDEX_SHIFT) |862 ((data & SDMA_AHG_VALUE_MASK) <<863 SDMA_AHG_VALUE_SHIFT));864}865 866/**867 * sdma_progress - use seq number of detect head progress868 * @sde: sdma_engine to check869 * @seq: base seq count870 * @tx: txreq for which we need to check descriptor availability871 *872 * This is used in the appropriate spot in the sleep routine873 * to check for potential ring progress. This routine gets the874 * seqcount before queuing the iowait structure for progress.875 *876 * If the seqcount indicates that progress needs to be checked,877 * re-submission is detected by checking whether the descriptor878 * queue has enough descriptor for the txreq.879 */880static inline unsigned sdma_progress(struct sdma_engine *sde, unsigned seq,881 struct sdma_txreq *tx)882{883 if (read_seqretry(&sde->head_lock, seq)) {884 sde->desc_avail = sdma_descq_freecnt(sde);885 if (tx->num_desc > sde->desc_avail)886 return 0;887 return 1;888 }889 return 0;890}891 892/* for use by interrupt handling */893void sdma_engine_error(struct sdma_engine *sde, u64 status);894void sdma_engine_interrupt(struct sdma_engine *sde, u64 status);895 896/*897 *898 * The diagram below details the relationship of the mapping structures899 *900 * Since the mapping now allows for non-uniform engines per vl, the901 * number of engines for a vl is either the vl_engines[vl] or902 * a computation based on num_sdma/num_vls:903 *904 * For example:905 * nactual = vl_engines ? vl_engines[vl] : num_sdma/num_vls906 *907 * n = roundup to next highest power of 2 using nactual908 *909 * In the case where there are num_sdma/num_vls doesn't divide910 * evenly, the extras are added from the last vl downward.911 *912 * For the case where n > nactual, the engines are assigned913 * in a round robin fashion wrapping back to the first engine914 * for a particular vl.915 *916 * dd->sdma_map917 * | sdma_map_elem[0]918 * | +--------------------+919 * v | mask |920 * sdma_vl_map |--------------------|921 * +--------------------------+ | sde[0] -> eng 1 |922 * | list (RCU) | |--------------------|923 * |--------------------------| ->| sde[1] -> eng 2 |924 * | mask | --/ |--------------------|925 * |--------------------------| -/ | * |926 * | actual_vls (max 8) | -/ |--------------------|927 * |--------------------------| --/ | sde[n-1] -> eng n |928 * | vls (max 8) | -/ +--------------------+929 * |--------------------------| --/930 * | map[0] |-/931 * |--------------------------| +---------------------+932 * | map[1] |--- | mask |933 * |--------------------------| \---- |---------------------|934 * | * | \-- | sde[0] -> eng 1+n |935 * | * | \---- |---------------------|936 * | * | \->| sde[1] -> eng 2+n |937 * |--------------------------| |---------------------|938 * | map[vls - 1] |- | * |939 * +--------------------------+ \- |---------------------|940 * \- | sde[m-1] -> eng m+n |941 * \ +---------------------+942 * \-943 * \944 * \- +----------------------+945 * \- | mask |946 * \ |----------------------|947 * \- | sde[0] -> eng 1+m+n |948 * \- |----------------------|949 * >| sde[1] -> eng 2+m+n |950 * |----------------------|951 * | * |952 * |----------------------|953 * | sde[o-1] -> eng o+m+n|954 * +----------------------+955 *956 */957 958/**959 * struct sdma_map_elem - mapping for a vl960 * @mask - selector mask961 * @sde - array of engines for this vl962 *963 * The mask is used to "mod" the selector964 * to produce index into the trailing965 * array of sdes.966 */967struct sdma_map_elem {968 u32 mask;969 struct sdma_engine *sde[];970};971 972/**973 * struct sdma_map_el - mapping for a vl974 * @engine_to_vl - map of an engine to a vl975 * @list - rcu head for free callback976 * @mask - vl mask to "mod" the vl to produce an index to map array977 * @actual_vls - number of vls978 * @vls - number of vls rounded to next power of 2979 * @map - array of sdma_map_elem entries980 *981 * This is the parent mapping structure. The trailing982 * members of the struct point to sdma_map_elem entries, which983 * in turn point to an array of sde's for that vl.984 */985struct sdma_vl_map {986 s8 engine_to_vl[TXE_NUM_SDMA_ENGINES];987 struct rcu_head list;988 u32 mask;989 u8 actual_vls;990 u8 vls;991 struct sdma_map_elem *map[];992};993 994int sdma_map_init(995 struct hfi1_devdata *dd,996 u8 port,997 u8 num_vls,998 u8 *vl_engines);999 1000/* slow path */1001void _sdma_engine_progress_schedule(struct sdma_engine *sde);1002 1003/**1004 * sdma_engine_progress_schedule() - schedule progress on engine1005 * @sde: sdma_engine to schedule progress1006 *1007 * This is the fast path.1008 *1009 */1010static inline void sdma_engine_progress_schedule(1011 struct sdma_engine *sde)1012{1013 if (!sde || sdma_descq_inprocess(sde) < (sde->descq_cnt / 8))1014 return;1015 _sdma_engine_progress_schedule(sde);1016}1017 1018struct sdma_engine *sdma_select_engine_sc(1019 struct hfi1_devdata *dd,1020 u32 selector,1021 u8 sc5);1022 1023struct sdma_engine *sdma_select_engine_vl(1024 struct hfi1_devdata *dd,1025 u32 selector,1026 u8 vl);1027 1028struct sdma_engine *sdma_select_user_engine(struct hfi1_devdata *dd,1029 u32 selector, u8 vl);1030ssize_t sdma_get_cpu_to_sde_map(struct sdma_engine *sde, char *buf);1031ssize_t sdma_set_cpu_to_sde_map(struct sdma_engine *sde, const char *buf,1032 size_t count);1033int sdma_engine_get_vl(struct sdma_engine *sde);1034void sdma_seqfile_dump_sde(struct seq_file *s, struct sdma_engine *);1035void sdma_seqfile_dump_cpu_list(struct seq_file *s, struct hfi1_devdata *dd,1036 unsigned long cpuid);1037 1038#ifdef CONFIG_SDMA_VERBOSITY1039void sdma_dumpstate(struct sdma_engine *);1040#endif1041static inline char *slashstrip(char *s)1042{1043 char *r = s;1044 1045 while (*s)1046 if (*s++ == '/')1047 r = s;1048 return r;1049}1050 1051u16 sdma_get_descq_cnt(void);1052 1053extern uint mod_num_sdma;1054 1055void sdma_update_lmc(struct hfi1_devdata *dd, u64 mask, u32 lid);1056#endif1057