1159 lines · c
1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */2/* Copyright (c) 2015 - 2021 Intel Corporation */3#ifndef IRDMA_DEFS_H4#define IRDMA_DEFS_H5 6#define IRDMA_FIRST_USER_QP_ID 37 8#define ECN_CODE_PT_VAL 29 10#define IRDMA_PUSH_OFFSET (8 * 1024 * 1024)11#define IRDMA_PF_FIRST_PUSH_PAGE_INDEX 1612#define IRDMA_PF_BAR_RSVD (60 * 1024)13 14#define IRDMA_PE_DB_SIZE_4M 115#define IRDMA_PE_DB_SIZE_8M 216 17#define IRDMA_IRD_HW_SIZE_4 018#define IRDMA_IRD_HW_SIZE_16 119#define IRDMA_IRD_HW_SIZE_64 220#define IRDMA_IRD_HW_SIZE_128 321#define IRDMA_IRD_HW_SIZE_256 422 23enum irdma_protocol_used {24 IRDMA_ANY_PROTOCOL = 0,25 IRDMA_IWARP_PROTOCOL_ONLY = 1,26 IRDMA_ROCE_PROTOCOL_ONLY = 2,27};28 29#define IRDMA_QP_STATE_INVALID 030#define IRDMA_QP_STATE_IDLE 131#define IRDMA_QP_STATE_RTS 232#define IRDMA_QP_STATE_CLOSING 333#define IRDMA_QP_STATE_SQD 334#define IRDMA_QP_STATE_RTR 435#define IRDMA_QP_STATE_TERMINATE 536#define IRDMA_QP_STATE_ERROR 637 38#define IRDMA_MAX_TRAFFIC_CLASS 839#define IRDMA_MAX_STATS_COUNT_GEN_1 1240#define IRDMA_MAX_USER_PRIORITY 841#define IRDMA_MAX_APPS 842#define IRDMA_MAX_STATS_COUNT 12843#define IRDMA_FIRST_NON_PF_STAT 444 45#define IRDMA_MIN_MTU_IPV4 57646#define IRDMA_MIN_MTU_IPV6 128047#define IRDMA_MTU_TO_MSS_IPV4 4048#define IRDMA_MTU_TO_MSS_IPV6 6049#define IRDMA_DEFAULT_MTU 150050 51#define Q2_FPSN_OFFSET 6452#define TERM_DDP_LEN_TAGGED 1453#define TERM_DDP_LEN_UNTAGGED 1854#define TERM_RDMA_LEN 2855#define RDMA_OPCODE_M 0x0f56#define RDMA_READ_REQ_OPCODE 157#define Q2_BAD_FRAME_OFFSET 7258#define CQE_MAJOR_DRV 0x800059 60#define IRDMA_TERM_SENT 161#define IRDMA_TERM_RCVD 262#define IRDMA_TERM_DONE 463#define IRDMA_MAC_HLEN 1464 65#define IRDMA_CQP_WAIT_POLL_REGS 166#define IRDMA_CQP_WAIT_POLL_CQ 267#define IRDMA_CQP_WAIT_EVENT 368 69#define IRDMA_AE_SOURCE_RSVD 0x070#define IRDMA_AE_SOURCE_RQ 0x171#define IRDMA_AE_SOURCE_RQ_0011 0x372 73#define IRDMA_AE_SOURCE_CQ 0x274#define IRDMA_AE_SOURCE_CQ_0110 0x675#define IRDMA_AE_SOURCE_CQ_1010 0xa76#define IRDMA_AE_SOURCE_CQ_1110 0xe77 78#define IRDMA_AE_SOURCE_SQ 0x579#define IRDMA_AE_SOURCE_SQ_0111 0x780 81#define IRDMA_AE_SOURCE_IN_RR_WR 0x982#define IRDMA_AE_SOURCE_IN_RR_WR_1011 0xb83#define IRDMA_AE_SOURCE_OUT_RR 0xd84#define IRDMA_AE_SOURCE_OUT_RR_1111 0xf85 86#define IRDMA_TCP_STATE_NON_EXISTENT 087#define IRDMA_TCP_STATE_CLOSED 188#define IRDMA_TCP_STATE_LISTEN 289#define IRDMA_STATE_SYN_SEND 390#define IRDMA_TCP_STATE_SYN_RECEIVED 491#define IRDMA_TCP_STATE_ESTABLISHED 592#define IRDMA_TCP_STATE_CLOSE_WAIT 693#define IRDMA_TCP_STATE_FIN_WAIT_1 794#define IRDMA_TCP_STATE_CLOSING 895#define IRDMA_TCP_STATE_LAST_ACK 996#define IRDMA_TCP_STATE_FIN_WAIT_2 1097#define IRDMA_TCP_STATE_TIME_WAIT 1198#define IRDMA_TCP_STATE_RESERVED_1 1299#define IRDMA_TCP_STATE_RESERVED_2 13100#define IRDMA_TCP_STATE_RESERVED_3 14101#define IRDMA_TCP_STATE_RESERVED_4 15102 103#define IRDMA_CQP_SW_SQSIZE_4 4104#define IRDMA_CQP_SW_SQSIZE_2048 2048105 106#define IRDMA_CQ_TYPE_IWARP 1107#define IRDMA_CQ_TYPE_ILQ 2108#define IRDMA_CQ_TYPE_IEQ 3109#define IRDMA_CQ_TYPE_CQP 4110 111#define IRDMA_DONE_COUNT 1000112#define IRDMA_SLEEP_COUNT 10113 114#define IRDMA_UPDATE_SD_BUFF_SIZE 128115#define IRDMA_FEATURE_BUF_SIZE (8 * IRDMA_MAX_FEATURES)116 117#define IRDMA_MAX_QUANTA_PER_WR 8118 119#define IRDMA_QP_SW_MAX_WQ_QUANTA 32768120#define IRDMA_QP_SW_MAX_SQ_QUANTA 32768121#define IRDMA_QP_SW_MAX_RQ_QUANTA 32768122#define IRDMA_MAX_QP_WRS(max_quanta_per_wr) \123 ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr))124 125#define IRDMAQP_TERM_SEND_TERM_AND_FIN 0126#define IRDMAQP_TERM_SEND_TERM_ONLY 1127#define IRDMAQP_TERM_SEND_FIN_ONLY 2128#define IRDMAQP_TERM_DONOT_SEND_TERM_OR_FIN 3129 130#define IRDMA_QP_TYPE_IWARP 1131#define IRDMA_QP_TYPE_UDA 2132#define IRDMA_QP_TYPE_ROCE_RC 3133#define IRDMA_QP_TYPE_ROCE_UD 4134 135#define IRDMA_HW_PAGE_SIZE 4096136#define IRDMA_HW_PAGE_SHIFT 12137#define IRDMA_CQE_QTYPE_RQ 0138#define IRDMA_CQE_QTYPE_SQ 1139 140#define IRDMA_QP_SW_MIN_WQSIZE 8u /* in WRs*/141#define IRDMA_QP_WQE_MIN_SIZE 32142#define IRDMA_QP_WQE_MAX_SIZE 256143#define IRDMA_QP_WQE_MIN_QUANTA 1144#define IRDMA_MAX_RQ_WQE_SHIFT_GEN1 2145#define IRDMA_MAX_RQ_WQE_SHIFT_GEN2 3146 147#define IRDMA_SQ_RSVD 258148#define IRDMA_RQ_RSVD 1149 150#define IRDMA_FEATURE_RTS_AE 1ULL151#define IRDMA_FEATURE_CQ_RESIZE 2ULL152#define IRDMAQP_OP_RDMA_WRITE 0x00153#define IRDMAQP_OP_RDMA_READ 0x01154#define IRDMAQP_OP_RDMA_SEND 0x03155#define IRDMAQP_OP_RDMA_SEND_INV 0x04156#define IRDMAQP_OP_RDMA_SEND_SOL_EVENT 0x05157#define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV 0x06158#define IRDMAQP_OP_BIND_MW 0x08159#define IRDMAQP_OP_FAST_REGISTER 0x09160#define IRDMAQP_OP_LOCAL_INVALIDATE 0x0a161#define IRDMAQP_OP_RDMA_READ_LOC_INV 0x0b162#define IRDMAQP_OP_NOP 0x0c163#define IRDMAQP_OP_RDMA_WRITE_SOL 0x0d164#define IRDMAQP_OP_GEN_RTS_AE 0x30165 166enum irdma_cqp_op_type {167 IRDMA_OP_CEQ_DESTROY = 1,168 IRDMA_OP_AEQ_DESTROY = 2,169 IRDMA_OP_DELETE_ARP_CACHE_ENTRY = 3,170 IRDMA_OP_MANAGE_APBVT_ENTRY = 4,171 IRDMA_OP_CEQ_CREATE = 5,172 IRDMA_OP_AEQ_CREATE = 6,173 IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY = 7,174 IRDMA_OP_QP_MODIFY = 8,175 IRDMA_OP_QP_UPLOAD_CONTEXT = 9,176 IRDMA_OP_CQ_CREATE = 10,177 IRDMA_OP_CQ_DESTROY = 11,178 IRDMA_OP_QP_CREATE = 12,179 IRDMA_OP_QP_DESTROY = 13,180 IRDMA_OP_ALLOC_STAG = 14,181 IRDMA_OP_MR_REG_NON_SHARED = 15,182 IRDMA_OP_DEALLOC_STAG = 16,183 IRDMA_OP_MW_ALLOC = 17,184 IRDMA_OP_QP_FLUSH_WQES = 18,185 IRDMA_OP_ADD_ARP_CACHE_ENTRY = 19,186 IRDMA_OP_MANAGE_PUSH_PAGE = 20,187 IRDMA_OP_UPDATE_PE_SDS = 21,188 IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE = 22,189 IRDMA_OP_SUSPEND = 23,190 IRDMA_OP_RESUME = 24,191 IRDMA_OP_MANAGE_VF_PBLE_BP = 25,192 IRDMA_OP_QUERY_FPM_VAL = 26,193 IRDMA_OP_COMMIT_FPM_VAL = 27,194 IRDMA_OP_AH_CREATE = 28,195 IRDMA_OP_AH_MODIFY = 29,196 IRDMA_OP_AH_DESTROY = 30,197 IRDMA_OP_MC_CREATE = 31,198 IRDMA_OP_MC_DESTROY = 32,199 IRDMA_OP_MC_MODIFY = 33,200 IRDMA_OP_STATS_ALLOCATE = 34,201 IRDMA_OP_STATS_FREE = 35,202 IRDMA_OP_STATS_GATHER = 36,203 IRDMA_OP_WS_ADD_NODE = 37,204 IRDMA_OP_WS_MODIFY_NODE = 38,205 IRDMA_OP_WS_DELETE_NODE = 39,206 IRDMA_OP_WS_FAILOVER_START = 40,207 IRDMA_OP_WS_FAILOVER_COMPLETE = 41,208 IRDMA_OP_SET_UP_MAP = 42,209 IRDMA_OP_GEN_AE = 43,210 IRDMA_OP_QUERY_RDMA_FEATURES = 44,211 IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY = 45,212 IRDMA_OP_ADD_LOCAL_MAC_ENTRY = 46,213 IRDMA_OP_DELETE_LOCAL_MAC_ENTRY = 47,214 IRDMA_OP_CQ_MODIFY = 48,215 216 /* Must be last entry*/217 IRDMA_MAX_CQP_OPS = 49,218};219 220/* CQP SQ WQES */221#define IRDMA_CQP_OP_CREATE_QP 0222#define IRDMA_CQP_OP_MODIFY_QP 0x1223#define IRDMA_CQP_OP_DESTROY_QP 0x02224#define IRDMA_CQP_OP_CREATE_CQ 0x03225#define IRDMA_CQP_OP_MODIFY_CQ 0x04226#define IRDMA_CQP_OP_DESTROY_CQ 0x05227#define IRDMA_CQP_OP_ALLOC_STAG 0x09228#define IRDMA_CQP_OP_REG_MR 0x0a229#define IRDMA_CQP_OP_QUERY_STAG 0x0b230#define IRDMA_CQP_OP_REG_SMR 0x0c231#define IRDMA_CQP_OP_DEALLOC_STAG 0x0d232#define IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE 0x0e233#define IRDMA_CQP_OP_MANAGE_ARP 0x0f234#define IRDMA_CQP_OP_MANAGE_VF_PBLE_BP 0x10235#define IRDMA_CQP_OP_MANAGE_PUSH_PAGES 0x11236#define IRDMA_CQP_OP_QUERY_RDMA_FEATURES 0x12237#define IRDMA_CQP_OP_UPLOAD_CONTEXT 0x13238#define IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY 0x14239#define IRDMA_CQP_OP_UPLOAD_CONTEXT 0x13240#define IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE 0x15241#define IRDMA_CQP_OP_CREATE_CEQ 0x16242#define IRDMA_CQP_OP_DESTROY_CEQ 0x18243#define IRDMA_CQP_OP_CREATE_AEQ 0x19244#define IRDMA_CQP_OP_DESTROY_AEQ 0x1b245#define IRDMA_CQP_OP_CREATE_ADDR_HANDLE 0x1c246#define IRDMA_CQP_OP_MODIFY_ADDR_HANDLE 0x1d247#define IRDMA_CQP_OP_DESTROY_ADDR_HANDLE 0x1e248#define IRDMA_CQP_OP_UPDATE_PE_SDS 0x1f249#define IRDMA_CQP_OP_QUERY_FPM_VAL 0x20250#define IRDMA_CQP_OP_COMMIT_FPM_VAL 0x21251#define IRDMA_CQP_OP_FLUSH_WQES 0x22252/* IRDMA_CQP_OP_GEN_AE is the same value as IRDMA_CQP_OP_FLUSH_WQES */253#define IRDMA_CQP_OP_GEN_AE 0x22254#define IRDMA_CQP_OP_MANAGE_APBVT 0x23255#define IRDMA_CQP_OP_NOP 0x24256#define IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25257#define IRDMA_CQP_OP_CREATE_MCAST_GRP 0x26258#define IRDMA_CQP_OP_MODIFY_MCAST_GRP 0x27259#define IRDMA_CQP_OP_DESTROY_MCAST_GRP 0x28260#define IRDMA_CQP_OP_SUSPEND_QP 0x29261#define IRDMA_CQP_OP_RESUME_QP 0x2a262#define IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED 0x2b263#define IRDMA_CQP_OP_WORK_SCHED_NODE 0x2c264#define IRDMA_CQP_OP_MANAGE_STATS 0x2d265#define IRDMA_CQP_OP_GATHER_STATS 0x2e266#define IRDMA_CQP_OP_UP_MAP 0x2f267 268/* Async Events codes */269#define IRDMA_AE_AMP_UNALLOCATED_STAG 0x0102270#define IRDMA_AE_AMP_INVALID_STAG 0x0103271#define IRDMA_AE_AMP_BAD_QP 0x0104272#define IRDMA_AE_AMP_BAD_PD 0x0105273#define IRDMA_AE_AMP_BAD_STAG_KEY 0x0106274#define IRDMA_AE_AMP_BAD_STAG_INDEX 0x0107275#define IRDMA_AE_AMP_BOUNDS_VIOLATION 0x0108276#define IRDMA_AE_AMP_RIGHTS_VIOLATION 0x0109277#define IRDMA_AE_AMP_TO_WRAP 0x010a278#define IRDMA_AE_AMP_FASTREG_VALID_STAG 0x010c279#define IRDMA_AE_AMP_FASTREG_MW_STAG 0x010d280#define IRDMA_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e281#define IRDMA_AE_AMP_FASTREG_INVALID_LENGTH 0x0110282#define IRDMA_AE_AMP_INVALIDATE_SHARED 0x0111283#define IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112284#define IRDMA_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113285#define IRDMA_AE_AMP_MWBIND_VALID_STAG 0x0114286#define IRDMA_AE_AMP_MWBIND_OF_MR_STAG 0x0115287#define IRDMA_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116288#define IRDMA_AE_AMP_MWBIND_TO_MW_STAG 0x0117289#define IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118290#define IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119291#define IRDMA_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a292#define IRDMA_AE_AMP_MWBIND_BIND_DISABLED 0x011b293#define IRDMA_AE_PRIV_OPERATION_DENIED 0x011c294#define IRDMA_AE_AMP_INVALIDATE_TYPE1_MW 0x011d295#define IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW 0x011e296#define IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG 0x011f297#define IRDMA_AE_AMP_MWBIND_WRONG_TYPE 0x0120298#define IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH 0x0121299#define IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132300#define IRDMA_AE_UDA_XMIT_BAD_PD 0x0133301#define IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134302#define IRDMA_AE_UDA_L4LEN_INVALID 0x0135303#define IRDMA_AE_BAD_CLOSE 0x0201304#define IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202305#define IRDMA_AE_CQ_OPERATION_ERROR 0x0203306#define IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205307#define IRDMA_AE_STAG_ZERO_INVALID 0x0206308#define IRDMA_AE_IB_RREQ_AND_Q1_FULL 0x0207309#define IRDMA_AE_IB_INVALID_REQUEST 0x0208310#define IRDMA_AE_WQE_UNEXPECTED_OPCODE 0x020a311#define IRDMA_AE_WQE_INVALID_PARAMETER 0x020b312#define IRDMA_AE_WQE_INVALID_FRAG_DATA 0x020c313#define IRDMA_AE_IB_REMOTE_ACCESS_ERROR 0x020d314#define IRDMA_AE_IB_REMOTE_OP_ERROR 0x020e315#define IRDMA_AE_WQE_LSMM_TOO_LONG 0x0220316#define IRDMA_AE_INVALID_REQUEST 0x0223317#define IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301318#define IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303319#define IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304320#define IRDMA_AE_DDP_UBE_INVALID_MO 0x0305321#define IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306322#define IRDMA_AE_DDP_UBE_INVALID_QN 0x0307323#define IRDMA_AE_DDP_NO_L_BIT 0x0308324#define IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311325#define IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312326#define IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313327#define IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314328#define IRDMA_AE_ROCE_RSP_LENGTH_ERROR 0x0316329#define IRDMA_AE_ROCE_EMPTY_MCG 0x0380330#define IRDMA_AE_ROCE_BAD_MC_IP_ADDR 0x0381331#define IRDMA_AE_ROCE_BAD_MC_QPID 0x0382332#define IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH 0x0383333#define IRDMA_AE_INVALID_ARP_ENTRY 0x0401334#define IRDMA_AE_INVALID_TCP_OPTION_RCVD 0x0402335#define IRDMA_AE_STALE_ARP_ENTRY 0x0403336#define IRDMA_AE_INVALID_AH_ENTRY 0x0406337#define IRDMA_AE_LLP_CLOSE_COMPLETE 0x0501338#define IRDMA_AE_LLP_CONNECTION_RESET 0x0502339#define IRDMA_AE_LLP_FIN_RECEIVED 0x0503340#define IRDMA_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504341#define IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505342#define IRDMA_AE_LLP_SEGMENT_TOO_SMALL 0x0507343#define IRDMA_AE_LLP_SYN_RECEIVED 0x0508344#define IRDMA_AE_LLP_TERMINATE_RECEIVED 0x0509345#define IRDMA_AE_LLP_TOO_MANY_RETRIES 0x050a346#define IRDMA_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b347#define IRDMA_AE_LLP_DOUBT_REACHABILITY 0x050c348#define IRDMA_AE_LLP_CONNECTION_ESTABLISHED 0x050e349#define IRDMA_AE_LLP_TOO_MANY_RNRS 0x050f350#define IRDMA_AE_RESOURCE_EXHAUSTION 0x0520351#define IRDMA_AE_RESET_SENT 0x0601352#define IRDMA_AE_TERMINATE_SENT 0x0602353#define IRDMA_AE_RESET_NOT_SENT 0x0603354#define IRDMA_AE_LCE_QP_CATASTROPHIC 0x0700355#define IRDMA_AE_LCE_FUNCTION_CATASTROPHIC 0x0701356#define IRDMA_AE_LCE_CQ_CATASTROPHIC 0x0702357#define IRDMA_AE_QP_SUSPEND_COMPLETE 0x0900358 359#define FLD_LS_64(dev, val, field) \360 (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])361#define FLD_RS_64(dev, val, field) \362 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])363#define FLD_LS_32(dev, val, field) \364 (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M])365#define FLD_RS_32(dev, val, field) \366 ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S])367 368#define IRDMA_MAX_STATS_24 0xffffffULL369#define IRDMA_MAX_STATS_32 0xffffffffULL370#define IRDMA_MAX_STATS_48 0xffffffffffffULL371#define IRDMA_MAX_STATS_56 0xffffffffffffffULL372#define IRDMA_MAX_STATS_64 0xffffffffffffffffULL373 374#define IRDMA_MAX_CQ_READ_THRESH 0x3FFFF375#define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32)376#define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32)377#define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0)378#define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16)379#define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0)380#define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32)381#define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0)382#define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32)383#define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0)384#define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)385#define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32)386#define IRDMA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61)387#define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)388#define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)389#define IRDMA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42)390#define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)391#define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62)392#define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60)393#define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61)394#define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32)395#define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(6, 0)396#define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(5, 0)397#define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)398#define IRDMA_CQPSQ_WS_NODEOP GENMASK_ULL(53, 52)399 400#define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62)401#define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61)402#define IRDMA_CQPSQ_WS_PRIOTYPE GENMASK_ULL(60, 59)403#define IRDMA_CQPSQ_WS_TC GENMASK_ULL(58, 56)404#define IRDMA_CQPSQ_WS_VMVFTYPE GENMASK_ULL(55, 54)405#define IRDMA_CQPSQ_WS_VMVFNUM GENMASK_ULL(51, 42)406#define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32)407#define IRDMA_CQPSQ_WS_PARENTID GENMASK_ULL(25, 16)408#define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(9, 0)409#define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(57, 48)410#define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32)411 412#define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)413#define IRDMA_CQPSQ_UP_USEVLAN BIT_ULL(62)414#define IRDMA_CQPSQ_UP_USEOVERRIDE BIT_ULL(61)415#define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32)416#define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(5, 0)417#define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32)418#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)419#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0)420#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32)421#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32)422#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION GENMASK_ULL(23, 16)423#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0)424#define IRDMA_CQPHC_SQSIZE GENMASK_ULL(11, 8)425#define IRDMA_CQPHC_DISABLE_PFPDUS BIT_ULL(1)426#define IRDMA_CQPHC_ROCEV2_RTO_POLICY BIT_ULL(2)427#define IRDMA_CQPHC_PROTOCOL_USED GENMASK_ULL(4, 3)428#define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48)429#define IRDMA_CQPHC_MIN_DEC_FACTOR GENMASK_ULL(59, 56)430#define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0)431#define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32)432#define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48)433#define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0)434#define IRDMA_CQPHC_DCQCN_F GENMASK_ULL(27, 25)435#define IRDMA_CQPHC_CC_CFG_VALID BIT_ULL(31)436#define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32)437#define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0)438 439#define IRDMA_CQPHC_HW_MAJVER_GEN_1 0440#define IRDMA_CQPHC_HW_MAJVER_GEN_2 1441#define IRDMA_CQPHC_HW_MAJVER_GEN_3 2442#define IRDMA_CQPHC_HW_MAJVER GENMASK_ULL(31, 16)443#define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32)444 445#define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32)446 447#define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0)448#define IRDMA_CQPHC_SVER GENMASK_ULL(31, 24)449#define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9)450 451#define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0)452#define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0)453#define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0)454#define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0)455#define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14)456#define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15)457#define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16)458 459/* CQP and iWARP Completion Queue */460#define IRDMA_CQ_QPCTX IRDMA_CQPHC_QPCTX461 462#define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0)463 464#define IRDMA_CQ_MINERR GENMASK_ULL(15, 0)465#define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16)466#define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32)467#define IRDMA_CQ_EXTCQE BIT_ULL(50)468#define IRDMA_OOO_CMPL BIT_ULL(54)469#define IRDMA_CQ_ERROR BIT_ULL(55)470#define IRDMA_CQ_SQ BIT_ULL(62)471 472#define IRDMA_CQ_VALID BIT_ULL(63)473#define IRDMA_CQ_IMMVALID BIT_ULL(62)474#define IRDMA_CQ_UDSMACVALID BIT_ULL(61)475#define IRDMA_CQ_UDVLANVALID BIT_ULL(60)476#define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0)477#define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48)478 479#define IRDMA_CQ_IMMDATA_S 0480#define IRDMA_CQ_IMMDATA_M (0xffffffffffffffffULL << IRDMA_CQ_IMMVALID_S)481#define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0)482#define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32)483#define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0)484#define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32)485#define IRDMACQ_INVSTAG GENMASK_ULL(31, 0)486#define IRDMACQ_QPID GENMASK_ULL(55, 32)487 488#define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0)489#define IRDMACQ_PSHDROP BIT_ULL(51)490#define IRDMACQ_STAG BIT_ULL(53)491#define IRDMACQ_IPV4 BIT_ULL(53)492#define IRDMACQ_SOEVENT BIT_ULL(54)493#define IRDMACQ_OP GENMASK_ULL(61, 56)494 495#define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0)496#define IRDMA_CEQE_VALID BIT_ULL(63)497 498/* AEQE format */499#define IRDMA_AEQE_COMPCTX IRDMA_CQPHC_QPCTX500#define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0)501#define IRDMA_AEQE_QPCQID_HI BIT_ULL(46)502#define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18)503#define IRDMA_AEQE_OVERFLOW BIT_ULL(33)504#define IRDMA_AEQE_AECODE GENMASK_ULL(45, 34)505#define IRDMA_AEQE_AESRC GENMASK_ULL(53, 50)506#define IRDMA_AEQE_IWSTATE GENMASK_ULL(56, 54)507#define IRDMA_AEQE_TCPSTATE GENMASK_ULL(60, 57)508#define IRDMA_AEQE_Q2DATA GENMASK_ULL(62, 61)509#define IRDMA_AEQE_VALID BIT_ULL(63)510 511#define IRDMA_UDA_QPSQ_NEXT_HDR GENMASK_ULL(23, 16)512#define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32)513#define IRDMA_UDA_QPSQ_L4LEN GENMASK_ULL(45, 42)514#define IRDMA_GEN1_UDA_QPSQ_L4LEN GENMASK_ULL(27, 24)515#define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0)516#define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)517#define IRDMA_UDA_QPSQ_SIGCOMPL BIT_ULL(62)518#define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56)519#define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48)520#define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30)521#define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28)522#define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0)523#define IRDMA_UDA_HDRLEN GENMASK_ULL(24, 16)524#define IRDMA_VLAN_TAG_VALID BIT_ULL(50)525#define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0)526#define IRDMA_UDA_L4PROTO GENMASK_ULL(17, 16)527#define IRDMA_UDA_QPSQ_DOLOOPBACK BIT_ULL(44)528#define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0)529#define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32)530#define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)531#define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0)532 533#define IRDMA_CQPSQ_VSIIDX GENMASK_ULL(17, 8)534#define IRDMA_CQPSQ_TPHEN BIT_ULL(60)535 536#define IRDMA_CQPSQ_PBUFADDR IRDMA_CQPHC_QPCTX537 538/* Create/Modify/Destroy QP */539 540#define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32)541#define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48)542 543#define IRDMA_CQPSQ_QP_QPCTX IRDMA_CQPHC_QPCTX544 545#define IRDMA_CQPSQ_QP_QPID_S 0546#define IRDMA_CQPSQ_QP_QPID_M (0xFFFFFFUL)547 548#define IRDMA_CQPSQ_QP_OP_S 32549#define IRDMA_CQPSQ_QP_OP_M IRDMACQ_OP_M550#define IRDMA_CQPSQ_QP_ORDVALID BIT_ULL(42)551#define IRDMA_CQPSQ_QP_TOECTXVALID BIT_ULL(43)552#define IRDMA_CQPSQ_QP_CACHEDVARVALID BIT_ULL(44)553#define IRDMA_CQPSQ_QP_VQ BIT_ULL(45)554#define IRDMA_CQPSQ_QP_FORCELOOPBACK BIT_ULL(46)555#define IRDMA_CQPSQ_QP_CQNUMVALID BIT_ULL(47)556#define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48)557#define IRDMA_CQPSQ_QP_MACVALID BIT_ULL(51)558#define IRDMA_CQPSQ_QP_MSSCHANGE BIT_ULL(52)559 560#define IRDMA_CQPSQ_QP_IGNOREMWBOUND BIT_ULL(54)561#define IRDMA_CQPSQ_QP_REMOVEHASHENTRY BIT_ULL(55)562#define IRDMA_CQPSQ_QP_TERMACT GENMASK_ULL(57, 56)563#define IRDMA_CQPSQ_QP_RESETCON BIT_ULL(58)564#define IRDMA_CQPSQ_QP_ARPTABIDXVALID BIT_ULL(59)565#define IRDMA_CQPSQ_QP_NEXTIWSTATE GENMASK_ULL(62, 60)566 567#define IRDMA_CQPSQ_QP_DBSHADOWADDR IRDMA_CQPHC_QPCTX568 569#define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0)570#define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0)571#define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0)572 573#define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32)574#define IRDMA_CQPSQ_CQ_CQRESIZE BIT_ULL(43)575#define IRDMA_CQPSQ_CQ_LPBLSIZE GENMASK_ULL(45, 44)576#define IRDMA_CQPSQ_CQ_CHKOVERFLOW BIT_ULL(46)577#define IRDMA_CQPSQ_CQ_VIRTMAP BIT_ULL(47)578#define IRDMA_CQPSQ_CQ_ENCEQEMASK BIT_ULL(48)579#define IRDMA_CQPSQ_CQ_CEQIDVALID BIT_ULL(49)580#define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT BIT_ULL(61)581#define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)582 583/* Allocate/Register/Register Shared/Deallocate Stag */584#define IRDMA_CQPSQ_STAG_VA_FBO IRDMA_CQPHC_QPCTX585#define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0)586#define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0)587#define IRDMA_CQPSQ_STAG_IDX GENMASK_ULL(31, 8)588#define IRDMA_CQPSQ_STAG_IDX_S 8589#define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32)590#define IRDMA_CQPSQ_STAG_MR BIT_ULL(43)591#define IRDMA_CQPSQ_STAG_MWTYPE BIT_ULL(42)592#define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY BIT_ULL(58)593 594#define IRDMA_CQPSQ_STAG_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE595#define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46)596#define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48)597#define IRDMA_CQPSQ_STAG_REMACCENABLED BIT_ULL(53)598#define IRDMA_CQPSQ_STAG_VABASEDTO BIT_ULL(59)599#define IRDMA_CQPSQ_STAG_USEHMCFNIDX BIT_ULL(60)600#define IRDMA_CQPSQ_STAG_USEPFRID BIT_ULL(61)601 602#define IRDMA_CQPSQ_STAG_PBA IRDMA_CQPHC_QPCTX603#define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(5, 0)604 605#define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0)606#define IRDMA_CQPSQ_QUERYSTAG_IDX IRDMA_CQPSQ_STAG_IDX607#define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0)608#define IRDMA_CQPSQ_MLM_FREEENTRY BIT_ULL(62)609#define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT BIT_ULL(61)610#define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0)611#define IRDMA_CQPSQ_MLM_MAC1 GENMASK_ULL(15, 8)612#define IRDMA_CQPSQ_MLM_MAC2 GENMASK_ULL(23, 16)613#define IRDMA_CQPSQ_MLM_MAC3 GENMASK_ULL(31, 24)614#define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32)615#define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40)616#define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0)617#define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0)618#define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0)619#define IRDMA_CQPSQ_MAT_ENTRYVALID BIT_ULL(42)620#define IRDMA_CQPSQ_MAT_PERMANENT BIT_ULL(43)621#define IRDMA_CQPSQ_MAT_QUERY BIT_ULL(44)622#define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0)623#define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX GENMASK_ULL(24, 16)624#define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32)625#define IRDMA_CQPSQ_MVPBP_INV_PD_ENT BIT_ULL(62)626#define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3)627 628/* Manage Push Page - MPP */629#define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff630#define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff631 632#define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(9, 0)633#define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(9, 0)634#define IRDMA_CQPSQ_MPP_PPTYPE GENMASK_ULL(61, 60)635 636#define IRDMA_CQPSQ_MPP_FREE_PAGE BIT_ULL(62)637 638/* Upload Context - UCTX */639#define IRDMA_CQPSQ_UCTX_QPCTXADDR IRDMA_CQPHC_QPCTX640#define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0)641#define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48)642 643#define IRDMA_CQPSQ_UCTX_RAWFORMAT BIT_ULL(61)644#define IRDMA_CQPSQ_UCTX_FREEZEQP BIT_ULL(62)645 646#define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0)647#define IRDMA_CQPSQ_MHMC_FREEPMFN BIT_ULL(62)648 649#define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0)650#define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32)651#define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0)652#define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0)653 654#define IRDMA_CQPSQ_CEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE655#define IRDMA_CQPSQ_CEQ_VMAP BIT_ULL(47)656#define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE BIT_ULL(46)657#define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)658#define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0)659#define IRDMA_CQPSQ_AEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE660#define IRDMA_CQPSQ_AEQ_VMAP BIT_ULL(47)661#define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0)662 663#define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0)664 665#define IRDMA_COMMIT_FPM_BASE_S 32666#define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(5, 0)667#define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0)668#define IRDMA_CQPSQ_FWQE_AESOURCE GENMASK_ULL(19, 16)669#define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0)670#define IRDMA_CQPSQ_FWQE_RQMJERR GENMASK_ULL(31, 16)671#define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32)672#define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48)673#define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0)674#define IRDMA_CQPSQ_FWQE_GENERATE_AE BIT_ULL(59)675#define IRDMA_CQPSQ_FWQE_USERFLCODE BIT_ULL(60)676#define IRDMA_CQPSQ_FWQE_FLUSHSQ BIT_ULL(61)677#define IRDMA_CQPSQ_FWQE_FLUSHRQ BIT_ULL(62)678#define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0)679#define IRDMA_CQPSQ_MAPT_ADDPORT BIT_ULL(62)680#define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0)681#define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0)682#define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32)683#define IRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0)684#define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)685 686#define IRDMA_CQPSQ_UPESD_BM_PF 0687#define IRDMA_CQPSQ_UPESD_BM_CP_LM 1688#define IRDMA_CQPSQ_UPESD_BM_AXF 2689#define IRDMA_CQPSQ_UPESD_BM_LM 4690#define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32)691#define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0)692#define IRDMA_CQPSQ_UPESD_SKIP_ENTRY BIT_ULL(7)693#define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0)694#define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0)695#define IRDMA_CQPSQ_RESUMEQP_QPID GENMASK(23, 0)696 697#define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001698#define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005699 700#define IRDMA_CQPSQ_MAJ_NO_ERROR 0x0000701#define IRDMA_CQPSQ_MAJ_OBJCACHE_ERROR 0xF000702#define IRDMA_CQPSQ_MAJ_CNTXTCACHE_ERROR 0xF001703#define IRDMA_CQPSQ_MAJ_ERROR 0xFFFF704#define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0)705#define IRDMAQPC_IBRDENABLE BIT_ULL(2)706#define IRDMAQPC_IPV4 BIT_ULL(3)707#define IRDMAQPC_NONAGLE BIT_ULL(4)708#define IRDMAQPC_INSERTVLANTAG BIT_ULL(5)709#define IRDMAQPC_ISQP1 BIT_ULL(6)710#define IRDMAQPC_TIMESTAMP BIT_ULL(7)711#define IRDMAQPC_RQWQESIZE GENMASK_ULL(9, 8)712#define IRDMAQPC_INSERTL2TAG2 BIT_ULL(11)713#define IRDMAQPC_LIMIT GENMASK_ULL(13, 12)714 715#define IRDMAQPC_ECN_EN BIT_ULL(14)716#define IRDMAQPC_DROPOOOSEG BIT_ULL(15)717#define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16)718#define IRDMAQPC_ERR_RQ_IDX_VALID BIT_ULL(19)719#define IRDMAQPC_DIS_VLAN_CHECKS GENMASK_ULL(21, 19)720#define IRDMAQPC_DC_TCP_EN BIT_ULL(25)721#define IRDMAQPC_RCVTPHEN BIT_ULL(28)722#define IRDMAQPC_XMITTPHEN BIT_ULL(29)723#define IRDMAQPC_RQTPHEN BIT_ULL(30)724#define IRDMAQPC_SQTPHEN BIT_ULL(31)725#define IRDMAQPC_PPIDX GENMASK_ULL(41, 32)726#define IRDMAQPC_PMENA BIT_ULL(47)727#define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62)728#define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60)729 730#define IRDMAQPC_SQADDR IRDMA_CQPHC_QPCTX731#define IRDMAQPC_RQADDR IRDMA_CQPHC_QPCTX732#define IRDMAQPC_TTL GENMASK_ULL(7, 0)733#define IRDMAQPC_RQSIZE GENMASK_ULL(11, 8)734#define IRDMAQPC_SQSIZE GENMASK_ULL(15, 12)735#define IRDMAQPC_GEN1_SRCMACADDRIDX GENMASK(21, 16)736#define IRDMAQPC_AVOIDSTRETCHACK BIT_ULL(23)737#define IRDMAQPC_TOS GENMASK_ULL(31, 24)738#define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32)739#define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48)740#define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32)741#define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0)742#define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32)743#define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0)744#define IRDMAQPC_SNDMSS GENMASK_ULL(29, 16)745#define IRDMAQPC_SYN_RST_HANDLING GENMASK_ULL(31, 30)746#define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32)747#define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48)748#define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0)749#define IRDMAQPC_WSCALE BIT_ULL(20)750#define IRDMAQPC_KEEPALIVE BIT_ULL(21)751#define IRDMAQPC_IGNORE_TCP_OPT BIT_ULL(22)752#define IRDMAQPC_IGNORE_TCP_UNS_OPT BIT_ULL(23)753#define IRDMAQPC_TCPSTATE GENMASK_ULL(31, 28)754#define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32)755#define IRDMAQPC_SNDSCALE GENMASK_ULL(43, 40)756#define IRDMAQPC_PDIDX GENMASK_ULL(63, 48)757#define IRDMAQPC_PDIDXHI GENMASK_ULL(21, 20)758#define IRDMAQPC_PKEY GENMASK_ULL(47, 32)759#define IRDMAQPC_ACKCREDITS GENMASK_ULL(24, 20)760#define IRDMAQPC_QKEY GENMASK_ULL(63, 32)761#define IRDMAQPC_DESTQP GENMASK_ULL(23, 0)762#define IRDMAQPC_KALIVE_TIMER_MAX_PROBES GENMASK_ULL(23, 16)763#define IRDMAQPC_KEEPALIVE_INTERVAL GENMASK_ULL(31, 24)764#define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0)765#define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32)766#define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0)767#define IRDMAQPC_ISN GENMASK_ULL(55, 32)768#define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0)769#define IRDMAQPC_LSN GENMASK_ULL(55, 32)770#define IRDMAQPC_SNDWND GENMASK_ULL(63, 32)771#define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0)772#define IRDMAQPC_EPSN GENMASK_ULL(23, 0)773#define IRDMAQPC_RCVWND GENMASK_ULL(63, 32)774#define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0)775#define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32)776#define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0)777#define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32)778#define IRDMAQPC_SRTT GENMASK_ULL(31, 0)779#define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32)780#define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0)781#define IRDMAQPC_CWND GENMASK_ULL(63, 32)782#define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32)783#define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0)784#define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32)785#define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(45, 32)786#define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57)787#define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0)788#define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48)789#define IRDMAQPC_RNRNAK_THRESH GENMASK_ULL(56, 54)790#define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0)791#define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32)792#define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0)793#define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8)794#define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0)795#define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16)796#define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0)797 798#define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16)799 800#define IRDMAQPC_UDPRIVCQENABLE BIT_ULL(19)801#define IRDMAQPC_WRRDRSPOK BIT_ULL(20)802#define IRDMAQPC_RDOK BIT_ULL(21)803#define IRDMAQPC_SNDMARKERS BIT_ULL(22)804#define IRDMAQPC_DCQCNENABLE BIT_ULL(22)805#define IRDMAQPC_FW_CC_ENABLE BIT_ULL(28)806#define IRDMAQPC_RCVNOICRC BIT_ULL(31)807#define IRDMAQPC_BINDEN BIT_ULL(23)808#define IRDMAQPC_FASTREGEN BIT_ULL(24)809#define IRDMAQPC_PRIVEN BIT_ULL(25)810#define IRDMAQPC_TIMELYENABLE BIT_ULL(27)811#define IRDMAQPC_THIGH GENMASK_ULL(63, 52)812#define IRDMAQPC_TLOW GENMASK_ULL(39, 32)813#define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0)814#define IRDMAQPC_USESTATSINSTANCE BIT_ULL(26)815#define IRDMAQPC_IWARPMODE BIT_ULL(28)816#define IRDMAQPC_RCVMARKERS BIT_ULL(29)817#define IRDMAQPC_ALIGNHDRS BIT_ULL(30)818#define IRDMAQPC_RCVNOMPACRC BIT_ULL(31)819#define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32)820#define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48)821 822#define IRDMAQPC_QPCOMPCTX IRDMA_CQPHC_QPCTX823#define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0)824#define IRDMAQPC_RQTPHVAL GENMASK_ULL(15, 8)825#define IRDMAQPC_QSHANDLE GENMASK_ULL(25, 16)826#define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32)827#define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0)828#define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32)829#define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0)830#define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32)831#define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0)832#define IRDMA_FW_VER_MAJOR GENMASK_ULL(31, 16)833#define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0)834#define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32)835#define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48)836 837#define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32)838#define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43)839#define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38)840#define IRDMAQPSQ_PUSHWQE BIT_ULL(56)841#define IRDMAQPSQ_STREAMMODE BIT_ULL(58)842#define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59)843#define IRDMAQPSQ_READFENCE BIT_ULL(60)844#define IRDMAQPSQ_LOCALFENCE BIT_ULL(61)845#define IRDMAQPSQ_UDPHEADER BIT_ULL(61)846#define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42)847#define IRDMAQPSQ_SIGCOMPL BIT_ULL(62)848#define IRDMAQPSQ_VALID BIT_ULL(63)849 850#define IRDMAQPSQ_FRAG_TO IRDMA_CQPHC_QPCTX851#define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)852#define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32)853#define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0)854#define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0)855#define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32)856#define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0)857#define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0)858#define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32)859#define IRDMAQPSQ_AHID GENMASK_ULL(16, 0)860#define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57)861 862#define IRDMA_INLINE_VALID_S 7863#define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48)864#define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47)865#define IRDMAQPSQ_REPORTRTT BIT_ULL(46)866 867#define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0)868#define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0)869 870#define IRDMAQPSQ_REMTO IRDMA_CQPHC_QPCTX871 872#define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48)873#define IRDMAQPSQ_VABASEDTO BIT_ULL(53)874#define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54)875 876#define IRDMAQPSQ_MWLEN IRDMA_CQPHC_QPCTX877#define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32)878#define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0)879 880#define IRDMAQPSQ_BASEVA_TO_FBO IRDMA_CQPHC_QPCTX881 882#define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0)883 884#define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0)885#define IRDMAQPSQ_STAGINDEX GENMASK_ULL(31, 8)886#define IRDMAQPSQ_COPYHOSTPBLS BIT_ULL(43)887#define IRDMAQPSQ_LPBLSIZE GENMASK_ULL(45, 44)888#define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46)889#define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0)890#define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48)891#define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0)892#define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12)893 894/* iwarp QP RQ WQE common fields */895#define IRDMAQPRQ_ADDFRAGCNT IRDMAQPSQ_ADDFRAGCNT896#define IRDMAQPRQ_VALID IRDMAQPSQ_VALID897#define IRDMAQPRQ_COMPLCTX IRDMA_CQPHC_QPCTX898#define IRDMAQPRQ_FRAG_LEN IRDMAQPSQ_FRAG_LEN899#define IRDMAQPRQ_STAG IRDMAQPSQ_FRAG_STAG900#define IRDMAQPRQ_TO IRDMAQPSQ_FRAG_TO901 902#define IRDMAPFINT_OICR_HMC_ERR_M BIT(26)903#define IRDMAPFINT_OICR_PE_PUSH_M BIT(27)904#define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28)905 906#define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(18, 0)907#define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(19, 0)908#define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0)909#define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(45, 32)910#define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0)911#define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32)912#define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32)913#define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16)914#define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32)915#define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32)916#define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32)917#define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32)918#define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(5, 0)919 920#define IRDMA_GET_CURRENT_AEQ_ELEM(_aeq) \921 ( \922 (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \923 )924 925#define IRDMA_GET_CURRENT_CEQ_ELEM(_ceq) \926 ( \927 (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \928 )929 930#define IRDMA_GET_CEQ_ELEM_AT_POS(_ceq, _pos) \931 ( \932 (_ceq)->ceqe_base[_pos].buf \933 )934 935#define IRDMA_RING_GET_NEXT_TAIL(_ring, _idx) \936 ( \937 ((_ring).tail + (_idx)) % (_ring).size \938 )939 940#define IRDMA_CQP_INIT_WQE(wqe) memset(wqe, 0, 64)941 942#define IRDMA_GET_CURRENT_CQ_ELEM(_cq) \943 ( \944 (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \945 )946#define IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(_cq) \947 ( \948 ((struct irdma_extended_cqe *) \949 ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \950 )951 952#define IRDMA_RING_INIT(_ring, _size) \953 { \954 (_ring).head = 0; \955 (_ring).tail = 0; \956 (_ring).size = (_size); \957 }958#define IRDMA_RING_SIZE(_ring) ((_ring).size)959#define IRDMA_RING_CURRENT_HEAD(_ring) ((_ring).head)960#define IRDMA_RING_CURRENT_TAIL(_ring) ((_ring).tail)961 962#define IRDMA_RING_MOVE_HEAD(_ring, _retcode) \963 { \964 register u32 size; \965 size = (_ring).size; \966 if (!IRDMA_RING_FULL_ERR(_ring)) { \967 (_ring).head = ((_ring).head + 1) % size; \968 (_retcode) = 0; \969 } else { \970 (_retcode) = -ENOMEM; \971 } \972 }973#define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \974 { \975 register u32 size; \976 size = (_ring).size; \977 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < size) { \978 (_ring).head = ((_ring).head + (_count)) % size; \979 (_retcode) = 0; \980 } else { \981 (_retcode) = -ENOMEM; \982 } \983 }984#define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \985 { \986 register u32 size; \987 size = (_ring).size; \988 if (!IRDMA_SQ_RING_FULL_ERR(_ring)) { \989 (_ring).head = ((_ring).head + 1) % size; \990 (_retcode) = 0; \991 } else { \992 (_retcode) = -ENOMEM; \993 } \994 }995#define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \996 { \997 register u32 size; \998 size = (_ring).size; \999 if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \1000 (_ring).head = ((_ring).head + (_count)) % size; \1001 (_retcode) = 0; \1002 } else { \1003 (_retcode) = -ENOMEM; \1004 } \1005 }1006#define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \1007 (_ring).head = ((_ring).head + (_count)) % (_ring).size1008 1009#define IRDMA_RING_MOVE_TAIL(_ring) \1010 (_ring).tail = ((_ring).tail + 1) % (_ring).size1011 1012#define IRDMA_RING_MOVE_HEAD_NOCHECK(_ring) \1013 (_ring).head = ((_ring).head + 1) % (_ring).size1014 1015#define IRDMA_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \1016 (_ring).tail = ((_ring).tail + (_count)) % (_ring).size1017 1018#define IRDMA_RING_SET_TAIL(_ring, _pos) \1019 (_ring).tail = (_pos) % (_ring).size1020 1021#define IRDMA_RING_FULL_ERR(_ring) \1022 ( \1023 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \1024 )1025 1026#define IRDMA_ERR_RING_FULL2(_ring) \1027 ( \1028 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \1029 )1030 1031#define IRDMA_ERR_RING_FULL3(_ring) \1032 ( \1033 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \1034 )1035 1036#define IRDMA_SQ_RING_FULL_ERR(_ring) \1037 ( \1038 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \1039 )1040 1041#define IRDMA_ERR_SQ_RING_FULL2(_ring) \1042 ( \1043 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \1044 )1045#define IRDMA_ERR_SQ_RING_FULL3(_ring) \1046 ( \1047 (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \1048 )1049#define IRDMA_RING_MORE_WORK(_ring) \1050 ( \1051 (IRDMA_RING_USED_QUANTA(_ring) != 0) \1052 )1053 1054#define IRDMA_RING_USED_QUANTA(_ring) \1055 ( \1056 (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \1057 )1058 1059#define IRDMA_RING_FREE_QUANTA(_ring) \1060 ( \1061 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \1062 )1063 1064#define IRDMA_SQ_RING_FREE_QUANTA(_ring) \1065 ( \1066 ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \1067 )1068 1069#define IRDMA_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \1070 { \1071 index = IRDMA_RING_CURRENT_HEAD(_ring); \1072 IRDMA_RING_MOVE_HEAD(_ring, _retcode); \1073 }1074 1075enum irdma_qp_wqe_size {1076 IRDMA_WQE_SIZE_32 = 32,1077 IRDMA_WQE_SIZE_64 = 64,1078 IRDMA_WQE_SIZE_96 = 96,1079 IRDMA_WQE_SIZE_128 = 128,1080 IRDMA_WQE_SIZE_256 = 256,1081};1082 1083enum irdma_ws_node_op {1084 IRDMA_ADD_NODE = 0,1085 IRDMA_MODIFY_NODE,1086 IRDMA_DEL_NODE,1087};1088 1089enum { IRDMA_Q_ALIGNMENT_M = (128 - 1),1090 IRDMA_AEQ_ALIGNMENT_M = (256 - 1),1091 IRDMA_Q2_ALIGNMENT_M = (256 - 1),1092 IRDMA_CEQ_ALIGNMENT_M = (256 - 1),1093 IRDMA_CQ0_ALIGNMENT_M = (256 - 1),1094 IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1),1095 IRDMA_SHADOWAREA_M = (128 - 1),1096 IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1),1097 IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1),1098};1099 1100enum irdma_alignment {1101 IRDMA_CQP_ALIGNMENT = 0x200,1102 IRDMA_AEQ_ALIGNMENT = 0x100,1103 IRDMA_CEQ_ALIGNMENT = 0x100,1104 IRDMA_CQ0_ALIGNMENT = 0x100,1105 IRDMA_SD_BUF_ALIGNMENT = 0x80,1106 IRDMA_FEATURE_BUF_ALIGNMENT = 0x8,1107};1108 1109enum icrdma_protocol_used {1110 ICRDMA_ANY_PROTOCOL = 0,1111 ICRDMA_IWARP_PROTOCOL_ONLY = 1,1112 ICRDMA_ROCE_PROTOCOL_ONLY = 2,1113};1114 1115/**1116 * set_64bit_val - set 64 bit value to hw wqe1117 * @wqe_words: wqe addr to write1118 * @byte_index: index in wqe1119 * @val: value to write1120 **/1121static inline void set_64bit_val(__le64 *wqe_words, u32 byte_index, u64 val)1122{1123 wqe_words[byte_index >> 3] = cpu_to_le64(val);1124}1125 1126/**1127 * set_32bit_val - set 32 bit value to hw wqe1128 * @wqe_words: wqe addr to write1129 * @byte_index: index in wqe1130 * @val: value to write1131 **/1132static inline void set_32bit_val(__le32 *wqe_words, u32 byte_index, u32 val)1133{1134 wqe_words[byte_index >> 2] = cpu_to_le32(val);1135}1136 1137/**1138 * get_64bit_val - read 64 bit value from wqe1139 * @wqe_words: wqe addr1140 * @byte_index: index to read from1141 * @val: read value1142 **/1143static inline void get_64bit_val(__le64 *wqe_words, u32 byte_index, u64 *val)1144{1145 *val = le64_to_cpu(wqe_words[byte_index >> 3]);1146}1147 1148/**1149 * get_32bit_val - read 32 bit value from wqe1150 * @wqe_words: wqe addr1151 * @byte_index: index to reaad from1152 * @val: return 32 bit value1153 **/1154static inline void get_32bit_val(__le32 *wqe_words, u32 byte_index, u32 *val)1155{1156 *val = le32_to_cpu(wqe_words[byte_index >> 2]);1157}1158#endif /* IRDMA_DEFS_H */1159