73 lines · c
1/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */2/* Copyright (c) 2017 - 2021 Intel Corporation */3#ifndef ICRDMA_HW_H4#define ICRDMA_HW_H5 6#include "irdma.h"7 8#define VFPE_CQPTAIL1 0x0000a0009#define VFPE_CQPDB1 0x0000bc0010#define VFPE_CCQPSTATUS1 0x0000b80011#define VFPE_CCQPHIGH1 0x0000980012#define VFPE_CCQPLOW1 0x0000ac0013#define VFPE_CQARM1 0x0000b40014#define VFPE_CQARM1 0x0000b40015#define VFPE_CQACK1 0x0000b00016#define VFPE_AEQALLOC1 0x0000a40017#define VFPE_CQPERRCODES1 0x00009c0018#define VFPE_WQEALLOC1 0x0000c00019#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */20 21#define PFPE_CQPTAIL 0x0050088022#define PFPE_CQPDB 0x0050080023#define PFPE_CCQPSTATUS 0x0050a00024#define PFPE_CCQPHIGH 0x0050a10025#define PFPE_CCQPLOW 0x0050a08026#define PFPE_CQARM 0x00502c0027#define PFPE_CQACK 0x00502c8028#define PFPE_AEQALLOC 0x00502d0029#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */30#define GLPCI_LBARCTRL 0x0009de7431#define GLPE_CPUSTATUS0 0x0050ba5c32#define GLPE_CPUSTATUS1 0x0050ba6033#define GLPE_CPUSTATUS2 0x0050ba6434#define PFINT_AEQCTL 0x0016cb0035#define PFPE_CQPERRCODES 0x0050a20036#define PFPE_WQEALLOC 0x0050440037#define GLINT_CEQCTL(_INT) (0x0015c000 + ((_INT) * 4)) /* _i=0...2047 */38#define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */39#define PFHMC_PDINV 0x0052030040#define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */41#define GLPE_CRITERR 0x0053400042#define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */43 44#define ICRDMA_DB_ADDR_OFFSET (8 * 1024 * 1024 - 64 * 1024)45 46#define ICRDMA_VF_DB_ADDR_OFFSET (64 * 1024)47 48/* shifts/masks for FLD_[LS/RS]_64 macros used in device table */49#define ICRDMA_CCQPSTATUS_CCQP_DONE_S 050#define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0)51#define ICRDMA_CCQPSTATUS_CCQP_ERR_S 3152#define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31)53#define ICRDMA_CQPSQ_STAG_PDID_S 4654#define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46)55#define ICRDMA_CQPSQ_CQ_CEQID_S 2256#define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22)57#define ICRDMA_CQPSQ_CQ_CQID_S 058#define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0)59#define ICRDMA_COMMIT_FPM_CQCNT_S 060#define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0)61 62enum icrdma_device_caps_const {63 ICRDMA_MAX_STATS_COUNT = 128,64 65 ICRDMA_MAX_IRD_SIZE = 127,66 ICRDMA_MAX_ORD_SIZE = 255,67 ICRDMA_MIN_WQ_SIZE = 8 /* WQEs */,68 69};70 71void icrdma_init_hw(struct irdma_sc_dev *dev);72#endif /* ICRDMA_HW_H*/73