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1/*2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.5 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.6 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.7 *8 * This software is available to you under a choice of one of two9 * licenses. You may choose to be licensed under the terms of the GNU10 * General Public License (GPL) Version 2, available from the file11 * COPYING in the main directory of this source tree, or the12 * OpenIB.org BSD license below:13 *14 * Redistribution and use in source and binary forms, with or15 * without modification, are permitted provided that the following16 * conditions are met:17 *18 * - Redistributions of source code must retain the above19 * copyright notice, this list of conditions and the following20 * disclaimer.21 *22 * - Redistributions in binary form must reproduce the above23 * copyright notice, this list of conditions and the following24 * disclaimer in the documentation and/or other materials25 * provided with the distribution.26 *27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE34 * SOFTWARE.35 */36 37#ifndef MTHCA_DEV_H38#define MTHCA_DEV_H39 40#include <linux/spinlock.h>41#include <linux/kernel.h>42#include <linux/pci.h>43#include <linux/dma-mapping.h>44#include <linux/timer.h>45#include <linux/mutex.h>46#include <linux/list.h>47#include <linux/semaphore.h>48 49#include "mthca_provider.h"50#include "mthca_doorbell.h"51 52#define DRV_NAME "ib_mthca"53#define PFX DRV_NAME ": "54#define DRV_VERSION "1.0"55#define DRV_RELDATE "April 4, 2008"56 57enum {58 MTHCA_FLAG_DDR_HIDDEN = 1 << 1,59 MTHCA_FLAG_SRQ = 1 << 2,60 MTHCA_FLAG_MSI_X = 1 << 3,61 MTHCA_FLAG_NO_LAM = 1 << 4,62 MTHCA_FLAG_FMR = 1 << 5,63 MTHCA_FLAG_MEMFREE = 1 << 6,64 MTHCA_FLAG_PCIE = 1 << 7,65 MTHCA_FLAG_SINAI_OPT = 1 << 866};67 68enum {69 MTHCA_MAX_PORTS = 270};71 72enum {73 MTHCA_BOARD_ID_LEN = 6474};75 76enum {77 MTHCA_EQ_CONTEXT_SIZE = 0x40,78 MTHCA_CQ_CONTEXT_SIZE = 0x40,79 MTHCA_QP_CONTEXT_SIZE = 0x200,80 MTHCA_RDB_ENTRY_SIZE = 0x20,81 MTHCA_AV_SIZE = 0x20,82 MTHCA_MGM_ENTRY_SIZE = 0x100,83 84 /* Arbel FW gives us these, but we need them for Tavor */85 MTHCA_MPT_ENTRY_SIZE = 0x40,86 MTHCA_MTT_SEG_SIZE = 0x40,87 88 MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)89};90 91enum {92 MTHCA_EQ_CMD,93 MTHCA_EQ_ASYNC,94 MTHCA_EQ_COMP,95 MTHCA_NUM_EQ96};97 98enum {99 MTHCA_OPCODE_NOP = 0x00,100 MTHCA_OPCODE_RDMA_WRITE = 0x08,101 MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,102 MTHCA_OPCODE_SEND = 0x0a,103 MTHCA_OPCODE_SEND_IMM = 0x0b,104 MTHCA_OPCODE_RDMA_READ = 0x10,105 MTHCA_OPCODE_ATOMIC_CS = 0x11,106 MTHCA_OPCODE_ATOMIC_FA = 0x12,107 MTHCA_OPCODE_BIND_MW = 0x18,108};109 110enum {111 MTHCA_CMD_USE_EVENTS = 1 << 0,112 MTHCA_CMD_POST_DOORBELLS = 1 << 1113};114 115enum {116 MTHCA_CMD_NUM_DBELL_DWORDS = 8117};118 119struct mthca_cmd {120 struct dma_pool *pool;121 struct mutex hcr_mutex;122 struct semaphore poll_sem;123 struct semaphore event_sem;124 int max_cmds;125 spinlock_t context_lock;126 int free_head;127 struct mthca_cmd_context *context;128 u16 token_mask;129 u32 flags;130 void __iomem *dbell_map;131 u16 dbell_offsets[MTHCA_CMD_NUM_DBELL_DWORDS];132};133 134struct mthca_limits {135 int num_ports;136 int vl_cap;137 int mtu_cap;138 int gid_table_len;139 int pkey_table_len;140 int local_ca_ack_delay;141 int num_uars;142 int max_sg;143 int num_qps;144 int max_wqes;145 int max_desc_sz;146 int max_qp_init_rdma;147 int reserved_qps;148 int num_srqs;149 int max_srq_wqes;150 int max_srq_sge;151 int reserved_srqs;152 int num_eecs;153 int reserved_eecs;154 int num_cqs;155 int max_cqes;156 int reserved_cqs;157 int num_eqs;158 int reserved_eqs;159 int num_mpts;160 int num_mtt_segs;161 int mtt_seg_size;162 int fmr_reserved_mtts;163 int reserved_mtts;164 int reserved_mrws;165 int reserved_uars;166 int num_mgms;167 int num_amgms;168 int reserved_mcgs;169 int num_pds;170 int reserved_pds;171 u32 page_size_cap;172 u32 flags;173 u16 stat_rate_support;174 u8 port_width_cap;175};176 177struct mthca_alloc {178 u32 last;179 u32 top;180 u32 max;181 u32 mask;182 spinlock_t lock;183 unsigned long *table;184};185 186struct mthca_array {187 struct {188 void **page;189 int used;190 } *page_list;191};192 193struct mthca_uar_table {194 struct mthca_alloc alloc;195 u64 uarc_base;196 int uarc_size;197};198 199struct mthca_pd_table {200 struct mthca_alloc alloc;201};202 203struct mthca_buddy {204 unsigned long **bits;205 int *num_free;206 int max_order;207 spinlock_t lock;208};209 210struct mthca_mr_table {211 struct mthca_alloc mpt_alloc;212 struct mthca_buddy mtt_buddy;213 struct mthca_buddy *fmr_mtt_buddy;214 u64 mtt_base;215 u64 mpt_base;216 struct mthca_icm_table *mtt_table;217 struct mthca_icm_table *mpt_table;218 struct {219 void __iomem *mpt_base;220 void __iomem *mtt_base;221 struct mthca_buddy mtt_buddy;222 } tavor_fmr;223};224 225struct mthca_eq_table {226 struct mthca_alloc alloc;227 void __iomem *clr_int;228 u32 clr_mask;229 u32 arm_mask;230 struct mthca_eq eq[MTHCA_NUM_EQ];231 u64 icm_virt;232 struct page *icm_page;233 dma_addr_t icm_dma;234 int have_irq;235 u8 inta_pin;236};237 238struct mthca_cq_table {239 struct mthca_alloc alloc;240 spinlock_t lock;241 struct mthca_array cq;242 struct mthca_icm_table *table;243};244 245struct mthca_srq_table {246 struct mthca_alloc alloc;247 spinlock_t lock;248 struct mthca_array srq;249 struct mthca_icm_table *table;250};251 252struct mthca_qp_table {253 struct mthca_alloc alloc;254 u32 rdb_base;255 int rdb_shift;256 int sqp_start;257 spinlock_t lock;258 struct mthca_array qp;259 struct mthca_icm_table *qp_table;260 struct mthca_icm_table *eqp_table;261 struct mthca_icm_table *rdb_table;262};263 264struct mthca_av_table {265 struct dma_pool *pool;266 int num_ddr_avs;267 u64 ddr_av_base;268 void __iomem *av_map;269 struct mthca_alloc alloc;270};271 272struct mthca_mcg_table {273 struct mutex mutex;274 struct mthca_alloc alloc;275 struct mthca_icm_table *table;276};277 278struct mthca_catas_err {279 u64 addr;280 u32 __iomem *map;281 u32 size;282 struct timer_list timer;283 struct list_head list;284};285 286extern struct mutex mthca_device_mutex;287 288struct mthca_dev {289 struct ib_device ib_dev;290 struct pci_dev *pdev;291 292 int hca_type;293 unsigned long mthca_flags;294 unsigned long device_cap_flags;295 296 u32 rev_id;297 char board_id[MTHCA_BOARD_ID_LEN];298 299 /* firmware info */300 u64 fw_ver;301 union {302 struct {303 u64 fw_start;304 u64 fw_end;305 } tavor;306 struct {307 u64 clr_int_base;308 u64 eq_arm_base;309 u64 eq_set_ci_base;310 struct mthca_icm *fw_icm;311 struct mthca_icm *aux_icm;312 u16 fw_pages;313 } arbel;314 } fw;315 316 u64 ddr_start;317 u64 ddr_end;318 319 MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)320 struct mutex cap_mask_mutex;321 322 void __iomem *hcr;323 void __iomem *kar;324 void __iomem *clr_base;325 union {326 struct {327 void __iomem *ecr_base;328 } tavor;329 struct {330 void __iomem *eq_arm;331 void __iomem *eq_set_ci_base;332 } arbel;333 } eq_regs;334 335 struct mthca_cmd cmd;336 struct mthca_limits limits;337 338 struct mthca_uar_table uar_table;339 struct mthca_pd_table pd_table;340 struct mthca_mr_table mr_table;341 struct mthca_eq_table eq_table;342 struct mthca_cq_table cq_table;343 struct mthca_srq_table srq_table;344 struct mthca_qp_table qp_table;345 struct mthca_av_table av_table;346 struct mthca_mcg_table mcg_table;347 348 struct mthca_catas_err catas_err;349 350 struct mthca_uar driver_uar;351 struct mthca_db_table *db_tab;352 struct mthca_pd driver_pd;353 struct mthca_mr driver_mr;354 355 struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];356 struct ib_ah *sm_ah[MTHCA_MAX_PORTS];357 spinlock_t sm_lock;358 u8 rate[MTHCA_MAX_PORTS];359 bool active;360};361 362#ifdef CONFIG_INFINIBAND_MTHCA_DEBUG363extern int mthca_debug_level;364 365#define mthca_dbg(mdev, format, arg...) \366 do { \367 if (mthca_debug_level) \368 dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \369 } while (0)370 371#else /* CONFIG_INFINIBAND_MTHCA_DEBUG */372 373#define mthca_dbg(mdev, format, arg...) do { (void) mdev; } while (0)374 375#endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */376 377#define mthca_err(mdev, format, arg...) \378 dev_err(&mdev->pdev->dev, format, ## arg)379#define mthca_info(mdev, format, arg...) \380 dev_info(&mdev->pdev->dev, format, ## arg)381#define mthca_warn(mdev, format, arg...) \382 dev_warn(&mdev->pdev->dev, format, ## arg)383 384extern void __buggy_use_of_MTHCA_GET(void);385extern void __buggy_use_of_MTHCA_PUT(void);386 387#define MTHCA_GET(dest, source, offset) \388 do { \389 void *__p = (char *) (source) + (offset); \390 switch (sizeof (dest)) { \391 case 1: (dest) = *(u8 *) __p; break; \392 case 2: (dest) = be16_to_cpup(__p); break; \393 case 4: (dest) = be32_to_cpup(__p); break; \394 case 8: (dest) = be64_to_cpup(__p); break; \395 default: __buggy_use_of_MTHCA_GET(); \396 } \397 } while (0)398 399#define MTHCA_PUT(dest, source, offset) \400 do { \401 void *__d = ((char *) (dest) + (offset)); \402 switch (sizeof(source)) { \403 case 1: *(u8 *) __d = (source); break; \404 case 2: *(__be16 *) __d = cpu_to_be16(source); break; \405 case 4: *(__be32 *) __d = cpu_to_be32(source); break; \406 case 8: *(__be64 *) __d = cpu_to_be64(source); break; \407 default: __buggy_use_of_MTHCA_PUT(); \408 } \409 } while (0)410 411int mthca_reset(struct mthca_dev *mdev);412 413u32 mthca_alloc(struct mthca_alloc *alloc);414void mthca_free(struct mthca_alloc *alloc, u32 obj);415int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,416 u32 reserved);417void mthca_alloc_cleanup(struct mthca_alloc *alloc);418void *mthca_array_get(struct mthca_array *array, int index);419int mthca_array_set(struct mthca_array *array, int index, void *value);420void mthca_array_clear(struct mthca_array *array, int index);421int mthca_array_init(struct mthca_array *array, int nent);422void mthca_array_cleanup(struct mthca_array *array, int nent);423int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,424 union mthca_buf *buf, int *is_direct, struct mthca_pd *pd,425 int hca_write, struct mthca_mr *mr);426void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf,427 int is_direct, struct mthca_mr *mr);428 429int mthca_init_uar_table(struct mthca_dev *dev);430int mthca_init_pd_table(struct mthca_dev *dev);431int mthca_init_mr_table(struct mthca_dev *dev);432int mthca_init_eq_table(struct mthca_dev *dev);433int mthca_init_cq_table(struct mthca_dev *dev);434int mthca_init_srq_table(struct mthca_dev *dev);435int mthca_init_qp_table(struct mthca_dev *dev);436int mthca_init_av_table(struct mthca_dev *dev);437int mthca_init_mcg_table(struct mthca_dev *dev);438 439void mthca_cleanup_uar_table(struct mthca_dev *dev);440void mthca_cleanup_pd_table(struct mthca_dev *dev);441void mthca_cleanup_mr_table(struct mthca_dev *dev);442void mthca_cleanup_eq_table(struct mthca_dev *dev);443void mthca_cleanup_cq_table(struct mthca_dev *dev);444void mthca_cleanup_srq_table(struct mthca_dev *dev);445void mthca_cleanup_qp_table(struct mthca_dev *dev);446void mthca_cleanup_av_table(struct mthca_dev *dev);447void mthca_cleanup_mcg_table(struct mthca_dev *dev);448 449int mthca_register_device(struct mthca_dev *dev);450void mthca_unregister_device(struct mthca_dev *dev);451 452void mthca_start_catas_poll(struct mthca_dev *dev);453void mthca_stop_catas_poll(struct mthca_dev *dev);454int __mthca_restart_one(struct pci_dev *pdev);455int mthca_catas_init(void);456void mthca_catas_cleanup(void);457 458int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);459void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);460 461int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);462void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);463 464int mthca_write_mtt_size(struct mthca_dev *dev);465 466struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);467void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);468int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,469 int start_index, u64 *buffer_list, int list_len);470int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,471 u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);472int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,473 u32 access, struct mthca_mr *mr);474int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,475 u64 *buffer_list, int buffer_size_shift,476 int list_len, u64 iova, u64 total_size,477 u32 access, struct mthca_mr *mr);478void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);479 480int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);481void mthca_unmap_eq_icm(struct mthca_dev *dev);482 483int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,484 struct ib_wc *entry);485int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);486int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);487int mthca_init_cq(struct mthca_dev *dev, int nent,488 struct mthca_ucontext *ctx, u32 pdn,489 struct mthca_cq *cq);490void mthca_free_cq(struct mthca_dev *dev,491 struct mthca_cq *cq);492void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);493void mthca_cq_event(struct mthca_dev *dev, u32 cqn,494 enum ib_event_type event_type);495void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn,496 struct mthca_srq *srq);497void mthca_cq_resize_copy_cqes(struct mthca_cq *cq);498int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent);499void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe);500 501int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,502 struct ib_srq_attr *attr, struct mthca_srq *srq,503 struct ib_udata *udata);504void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq);505int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,506 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);507int mthca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);508int mthca_max_srq_sge(struct mthca_dev *dev);509void mthca_srq_event(struct mthca_dev *dev, u32 srqn,510 enum ib_event_type event_type);511void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);512int mthca_tavor_post_srq_recv(struct ib_srq *srq, const struct ib_recv_wr *wr,513 const struct ib_recv_wr **bad_wr);514int mthca_arbel_post_srq_recv(struct ib_srq *srq, const struct ib_recv_wr *wr,515 const struct ib_recv_wr **bad_wr);516 517void mthca_qp_event(struct mthca_dev *dev, u32 qpn,518 enum ib_event_type event_type);519int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,520 struct ib_qp_init_attr *qp_init_attr);521int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,522 struct ib_udata *udata);523int mthca_tavor_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,524 const struct ib_send_wr **bad_wr);525int mthca_tavor_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,526 const struct ib_recv_wr **bad_wr);527int mthca_arbel_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,528 const struct ib_send_wr **bad_wr);529int mthca_arbel_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,530 const struct ib_recv_wr **bad_wr);531void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,532 int index, int *dbd, __be32 *new_wqe);533int mthca_alloc_qp(struct mthca_dev *dev,534 struct mthca_pd *pd,535 struct mthca_cq *send_cq,536 struct mthca_cq *recv_cq,537 enum ib_qp_type type,538 enum ib_sig_type send_policy,539 struct ib_qp_cap *cap,540 struct mthca_qp *qp,541 struct ib_udata *udata);542int mthca_alloc_sqp(struct mthca_dev *dev,543 struct mthca_pd *pd,544 struct mthca_cq *send_cq,545 struct mthca_cq *recv_cq,546 enum ib_sig_type send_policy,547 struct ib_qp_cap *cap,548 int qpn,549 u32 port,550 struct mthca_qp *qp,551 struct ib_udata *udata);552void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);553int mthca_create_ah(struct mthca_dev *dev,554 struct mthca_pd *pd,555 struct rdma_ah_attr *ah_attr,556 struct mthca_ah *ah);557int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);558int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,559 struct ib_ud_header *header);560int mthca_ah_query(struct ib_ah *ibah, struct rdma_ah_attr *attr);561int mthca_ah_grh_present(struct mthca_ah *ah);562u8 mthca_get_rate(struct mthca_dev *dev, int static_rate, u32 port);563enum ib_rate mthca_rate_to_ib(struct mthca_dev *dev, u8 mthca_rate, u32 port);564 565int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);566int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);567 568int mthca_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num,569 const struct ib_wc *in_wc, const struct ib_grh *in_grh,570 const struct ib_mad *in, struct ib_mad *out,571 size_t *out_mad_size, u16 *out_mad_pkey_index);572int mthca_create_agents(struct mthca_dev *dev);573void mthca_free_agents(struct mthca_dev *dev);574 575static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)576{577 return container_of(ibdev, struct mthca_dev, ib_dev);578}579 580static inline int mthca_is_memfree(struct mthca_dev *dev)581{582 return dev->mthca_flags & MTHCA_FLAG_MEMFREE;583}584 585#endif /* MTHCA_DEV_H */586