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1/* This file is part of the Emulex RoCE Device Driver for2 * RoCE (RDMA over Converged Ethernet) adapters.3 * Copyright (C) 2012-2015 Emulex. All rights reserved.4 * EMULEX and SLI are trademarks of Emulex.5 * www.emulex.com6 *7 * This software is available to you under a choice of one of two licenses.8 * You may choose to be licensed under the terms of the GNU General Public9 * License (GPL) Version 2, available from the file COPYING in the main10 * directory of this source tree, or the BSD license below:11 *12 * Redistribution and use in source and binary forms, with or without13 * modification, are permitted provided that the following conditions14 * are met:15 *16 * - Redistributions of source code must retain the above copyright notice,17 * this list of conditions and the following disclaimer.18 *19 * - Redistributions in binary form must reproduce the above copyright20 * notice, this list of conditions and the following disclaimer in21 * the documentation and/or other materials provided with the distribution.22 *23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.34 *35 * Contact Information:36 * linux-drivers@emulex.com37 *38 * Emulex39 * 3333 Susan Street40 * Costa Mesa, CA 9262641 */42 43#ifndef __OCRDMA_SLI_H__44#define __OCRDMA_SLI_H__45 46enum {47 OCRDMA_ASIC_GEN_SKH_R = 0x04,48 OCRDMA_ASIC_GEN_LANCER = 0x0B49};50 51enum {52 OCRDMA_ASIC_REV_A0 = 0x00,53 OCRDMA_ASIC_REV_B0 = 0x10,54 OCRDMA_ASIC_REV_C0 = 0x2055};56 57#define OCRDMA_SUBSYS_ROCE 1058enum {59 OCRDMA_CMD_QUERY_CONFIG = 1,60 OCRDMA_CMD_ALLOC_PD = 2,61 OCRDMA_CMD_DEALLOC_PD = 3,62 63 OCRDMA_CMD_CREATE_AH_TBL = 4,64 OCRDMA_CMD_DELETE_AH_TBL = 5,65 66 OCRDMA_CMD_CREATE_QP = 6,67 OCRDMA_CMD_QUERY_QP = 7,68 OCRDMA_CMD_MODIFY_QP = 8 ,69 OCRDMA_CMD_DELETE_QP = 9,70 71 OCRDMA_CMD_RSVD1 = 10,72 OCRDMA_CMD_ALLOC_LKEY = 11,73 OCRDMA_CMD_DEALLOC_LKEY = 12,74 OCRDMA_CMD_REGISTER_NSMR = 13,75 OCRDMA_CMD_REREGISTER_NSMR = 14,76 OCRDMA_CMD_REGISTER_NSMR_CONT = 15,77 OCRDMA_CMD_QUERY_NSMR = 16,78 OCRDMA_CMD_ALLOC_MW = 17,79 OCRDMA_CMD_QUERY_MW = 18,80 81 OCRDMA_CMD_CREATE_SRQ = 19,82 OCRDMA_CMD_QUERY_SRQ = 20,83 OCRDMA_CMD_MODIFY_SRQ = 21,84 OCRDMA_CMD_DELETE_SRQ = 22,85 86 OCRDMA_CMD_ATTACH_MCAST = 23,87 OCRDMA_CMD_DETACH_MCAST = 24,88 89 OCRDMA_CMD_CREATE_RBQ = 25,90 OCRDMA_CMD_DESTROY_RBQ = 26,91 92 OCRDMA_CMD_GET_RDMA_STATS = 27,93 OCRDMA_CMD_ALLOC_PD_RANGE = 28,94 OCRDMA_CMD_DEALLOC_PD_RANGE = 29,95 96 OCRDMA_CMD_MAX97};98 99#define OCRDMA_SUBSYS_COMMON 1100enum {101 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1 = 5,102 OCRDMA_CMD_CREATE_CQ = 12,103 OCRDMA_CMD_CREATE_EQ = 13,104 OCRDMA_CMD_CREATE_MQ = 21,105 OCRDMA_CMD_GET_CTRL_ATTRIBUTES = 32,106 OCRDMA_CMD_GET_FW_VER = 35,107 OCRDMA_CMD_MODIFY_EQ_DELAY = 41,108 OCRDMA_CMD_DELETE_MQ = 53,109 OCRDMA_CMD_DELETE_CQ = 54,110 OCRDMA_CMD_DELETE_EQ = 55,111 OCRDMA_CMD_GET_FW_CONFIG = 58,112 OCRDMA_CMD_CREATE_MQ_EXT = 90,113 OCRDMA_CMD_PHY_DETAILS = 102114};115 116enum {117 QTYPE_EQ = 1,118 QTYPE_CQ = 2,119 QTYPE_MCCQ = 3120};121 122#define OCRDMA_MAX_SGID 16123 124#define OCRDMA_MAX_QP 2048125#define OCRDMA_MAX_CQ 2048126#define OCRDMA_MAX_STAG 16384127 128enum {129 OCRDMA_DB_RQ_OFFSET = 0xE0,130 OCRDMA_DB_GEN2_RQ_OFFSET = 0x100,131 OCRDMA_DB_SQ_OFFSET = 0x60,132 OCRDMA_DB_GEN2_SQ_OFFSET = 0x1C0,133 OCRDMA_DB_SRQ_OFFSET = OCRDMA_DB_RQ_OFFSET,134 OCRDMA_DB_GEN2_SRQ_OFFSET = OCRDMA_DB_GEN2_RQ_OFFSET,135 OCRDMA_DB_CQ_OFFSET = 0x120,136 OCRDMA_DB_EQ_OFFSET = OCRDMA_DB_CQ_OFFSET,137 OCRDMA_DB_MQ_OFFSET = 0x140,138 139 OCRDMA_DB_SQ_SHIFT = 16,140 OCRDMA_DB_RQ_SHIFT = 24141};142 143enum {144 OCRDMA_L3_TYPE_IB_GRH = 0x00,145 OCRDMA_L3_TYPE_IPV4 = 0x01,146 OCRDMA_L3_TYPE_IPV6 = 0x02147};148 149#define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */150#define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */151/* qid #2 msbits at 12-11 */152#define OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT 0x1153#define OCRDMA_DB_CQ_NUM_POPPED_SHIFT 16 /* bits 16 - 28 */154/* Rearm bit */155#define OCRDMA_DB_CQ_REARM_SHIFT 29 /* bit 29 */156/* solicited bit */157#define OCRDMA_DB_CQ_SOLICIT_SHIFT 31 /* bit 31 */158 159#define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */160#define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */161#define OCRDMA_EQ_ID_EXT_MASK_SHIFT 2 /* qid bits 9-13 at 11-15 */162 163/* Clear the interrupt for this eq */164#define OCRDMA_EQ_CLR_SHIFT 9 /* bit 9 */165/* Must be 1 */166#define OCRDMA_EQ_TYPE_SHIFT 10 /* bit 10 */167/* Number of event entries processed */168#define OCRDMA_NUM_EQE_SHIFT 16 /* bits 16 - 28 */169/* Rearm bit */170#define OCRDMA_REARM_SHIFT 29 /* bit 29 */171 172#define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */173/* Number of entries posted */174#define OCRDMA_MQ_NUM_MQE_SHIFT 16 /* bits 16 - 29 */175 176#define OCRDMA_MIN_HPAGE_SIZE 4096177 178#define OCRDMA_MIN_Q_PAGE_SIZE 4096179#define OCRDMA_MAX_Q_PAGES 8180 181#define OCRDMA_SLI_ASIC_ID_OFFSET 0x9C182#define OCRDMA_SLI_ASIC_REV_MASK 0x000000FF183#define OCRDMA_SLI_ASIC_GEN_NUM_MASK 0x0000FF00184#define OCRDMA_SLI_ASIC_GEN_NUM_SHIFT 0x08185/*186# 0: 4K Bytes187# 1: 8K Bytes188# 2: 16K Bytes189# 3: 32K Bytes190# 4: 64K Bytes191# 5: 128K Bytes192# 6: 256K Bytes193# 7: 512K Bytes194*/195#define OCRDMA_MAX_Q_PAGE_SIZE_CNT 8196#define OCRDMA_Q_PAGE_BASE_SIZE (OCRDMA_MIN_Q_PAGE_SIZE * OCRDMA_MAX_Q_PAGES)197 198#define MAX_OCRDMA_QP_PAGES 8199#define OCRDMA_MAX_WQE_MEM_SIZE (MAX_OCRDMA_QP_PAGES * OCRDMA_MIN_HQ_PAGE_SIZE)200 201#define OCRDMA_CREATE_CQ_MAX_PAGES 4202#define OCRDMA_DPP_CQE_SIZE 4203 204#define OCRDMA_GEN2_MAX_CQE 1024205#define OCRDMA_GEN2_CQ_PAGE_SIZE 4096206#define OCRDMA_GEN2_WQE_SIZE 256207#define OCRDMA_MAX_CQE 4095208#define OCRDMA_CQ_PAGE_SIZE 16384209#define OCRDMA_WQE_SIZE 128210#define OCRDMA_WQE_STRIDE 8211#define OCRDMA_WQE_ALIGN_BYTES 16212 213#define MAX_OCRDMA_SRQ_PAGES MAX_OCRDMA_QP_PAGES214 215enum {216 OCRDMA_MCH_OPCODE_SHIFT = 0,217 OCRDMA_MCH_OPCODE_MASK = 0xFF,218 OCRDMA_MCH_SUBSYS_SHIFT = 8,219 OCRDMA_MCH_SUBSYS_MASK = 0xFF00220};221 222/* mailbox cmd header */223struct ocrdma_mbx_hdr {224 u32 subsys_op;225 u32 timeout; /* in seconds */226 u32 cmd_len;227 u32 rsvd_version;228};229 230enum {231 OCRDMA_MBX_RSP_OPCODE_SHIFT = 0,232 OCRDMA_MBX_RSP_OPCODE_MASK = 0xFF,233 OCRDMA_MBX_RSP_SUBSYS_SHIFT = 8,234 OCRDMA_MBX_RSP_SUBSYS_MASK = 0xFF << OCRDMA_MBX_RSP_SUBSYS_SHIFT,235 236 OCRDMA_MBX_RSP_STATUS_SHIFT = 0,237 OCRDMA_MBX_RSP_STATUS_MASK = 0xFF,238 OCRDMA_MBX_RSP_ASTATUS_SHIFT = 8,239 OCRDMA_MBX_RSP_ASTATUS_MASK = 0xFF << OCRDMA_MBX_RSP_ASTATUS_SHIFT240};241 242/* mailbox cmd response */243struct ocrdma_mbx_rsp {244 u32 subsys_op;245 u32 status;246 u32 rsp_len;247 u32 add_rsp_len;248};249 250enum {251 OCRDMA_MQE_EMBEDDED = 1,252 OCRDMA_MQE_NONEMBEDDED = 0253};254 255struct ocrdma_mqe_sge {256 u32 pa_lo;257 u32 pa_hi;258 u32 len;259};260 261enum {262 OCRDMA_MQE_HDR_EMB_SHIFT = 0,263 OCRDMA_MQE_HDR_EMB_MASK = BIT(0),264 OCRDMA_MQE_HDR_SGE_CNT_SHIFT = 3,265 OCRDMA_MQE_HDR_SGE_CNT_MASK = 0x1F << OCRDMA_MQE_HDR_SGE_CNT_SHIFT,266 OCRDMA_MQE_HDR_SPECIAL_SHIFT = 24,267 OCRDMA_MQE_HDR_SPECIAL_MASK = 0xFF << OCRDMA_MQE_HDR_SPECIAL_SHIFT268};269 270struct ocrdma_mqe_hdr {271 u32 spcl_sge_cnt_emb;272 u32 pyld_len;273 u32 tag_lo;274 u32 tag_hi;275 u32 rsvd3;276};277 278struct ocrdma_mqe_emb_cmd {279 struct ocrdma_mbx_hdr mch;280 u8 pyld[220];281};282 283struct ocrdma_mqe {284 struct ocrdma_mqe_hdr hdr;285 union {286 struct ocrdma_mqe_emb_cmd emb_req;287 struct {288 struct ocrdma_mqe_sge sge[19];289 } nonemb_req;290 u8 cmd[236];291 struct ocrdma_mbx_rsp rsp;292 } u;293};294 295#define OCRDMA_EQ_LEN 4096296#define OCRDMA_MQ_CQ_LEN 256297#define OCRDMA_MQ_LEN 128298 299#define PAGE_SHIFT_4K 12300#define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K)301 302/* Returns number of pages spanned by the data starting at the given addr */303#define PAGES_4K_SPANNED(_address, size) \304 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \305 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))306 307struct ocrdma_delete_q_req {308 struct ocrdma_mbx_hdr req;309 u32 id;310};311 312struct ocrdma_pa {313 u32 lo;314 u32 hi;315};316 317#define MAX_OCRDMA_EQ_PAGES 8318struct ocrdma_create_eq_req {319 struct ocrdma_mbx_hdr req;320 u32 num_pages;321 u32 valid;322 u32 cnt;323 u32 delay;324 u32 rsvd;325 struct ocrdma_pa pa[MAX_OCRDMA_EQ_PAGES];326};327 328enum {329 OCRDMA_CREATE_EQ_VALID = BIT(29),330 OCRDMA_CREATE_EQ_CNT_SHIFT = 26,331 OCRDMA_CREATE_CQ_DELAY_SHIFT = 13,332};333 334struct ocrdma_create_eq_rsp {335 struct ocrdma_mbx_rsp rsp;336 u32 vector_eqid;337};338 339#define OCRDMA_EQ_MINOR_OTHER 0x1340 341struct ocrmda_set_eqd {342 u32 eq_id;343 u32 phase;344 u32 delay_multiplier;345};346 347struct ocrdma_modify_eqd_cmd {348 struct ocrdma_mbx_hdr req;349 u32 num_eq;350 struct ocrmda_set_eqd set_eqd[8];351} __packed;352 353struct ocrdma_modify_eqd_req {354 struct ocrdma_mqe_hdr hdr;355 struct ocrdma_modify_eqd_cmd cmd;356};357 358 359struct ocrdma_modify_eq_delay_rsp {360 struct ocrdma_mbx_rsp hdr;361 u32 rsvd0;362} __packed;363 364enum {365 OCRDMA_MCQE_STATUS_SHIFT = 0,366 OCRDMA_MCQE_STATUS_MASK = 0xFFFF,367 OCRDMA_MCQE_ESTATUS_SHIFT = 16,368 OCRDMA_MCQE_ESTATUS_MASK = 0xFFFF << OCRDMA_MCQE_ESTATUS_SHIFT,369 OCRDMA_MCQE_CONS_SHIFT = 27,370 OCRDMA_MCQE_CONS_MASK = BIT(27),371 OCRDMA_MCQE_CMPL_SHIFT = 28,372 OCRDMA_MCQE_CMPL_MASK = BIT(28),373 OCRDMA_MCQE_AE_SHIFT = 30,374 OCRDMA_MCQE_AE_MASK = BIT(30),375 OCRDMA_MCQE_VALID_SHIFT = 31,376 OCRDMA_MCQE_VALID_MASK = BIT(31)377};378 379struct ocrdma_mcqe {380 u32 status;381 u32 tag_lo;382 u32 tag_hi;383 u32 valid_ae_cmpl_cons;384};385 386enum {387 OCRDMA_AE_MCQE_QPVALID = BIT(31),388 OCRDMA_AE_MCQE_QPID_MASK = 0xFFFF,389 390 OCRDMA_AE_MCQE_CQVALID = BIT(31),391 OCRDMA_AE_MCQE_CQID_MASK = 0xFFFF,392 OCRDMA_AE_MCQE_VALID = BIT(31),393 OCRDMA_AE_MCQE_AE = BIT(30),394 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,395 OCRDMA_AE_MCQE_EVENT_TYPE_MASK =396 0xFF << OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT,397 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT = 8,398 OCRDMA_AE_MCQE_EVENT_CODE_MASK =399 0xFF << OCRDMA_AE_MCQE_EVENT_CODE_SHIFT400};401struct ocrdma_ae_mcqe {402 u32 qpvalid_qpid;403 u32 cqvalid_cqid;404 u32 evt_tag;405 u32 valid_ae_event;406};407 408enum {409 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT = 0,410 OCRDMA_AE_PVID_MCQE_ENABLED_MASK = 0xFF,411 OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,412 OCRDMA_AE_PVID_MCQE_TAG_MASK = 0xFFFF << OCRDMA_AE_PVID_MCQE_TAG_SHIFT413};414 415struct ocrdma_ae_pvid_mcqe {416 u32 tag_enabled;417 u32 event_tag;418 u32 rsvd1;419 u32 rsvd2;420};421 422enum {423 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16,424 OCRDMA_AE_MPA_MCQE_REQ_ID_MASK = 0xFFFF <<425 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT,426 427 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT = 8,428 OCRDMA_AE_MPA_MCQE_EVENT_CODE_MASK = 0xFF <<429 OCRDMA_AE_MPA_MCQE_EVENT_CODE_SHIFT,430 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16,431 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_MASK = 0xFF <<432 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT,433 OCRDMA_AE_MPA_MCQE_EVENT_AE_SHIFT = 30,434 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = BIT(30),435 OCRDMA_AE_MPA_MCQE_EVENT_VALID_SHIFT = 31,436 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = BIT(31)437};438 439struct ocrdma_ae_mpa_mcqe {440 u32 req_id;441 u32 w1;442 u32 w2;443 u32 valid_ae_event;444};445 446enum {447 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_SHIFT = 0,448 OCRDMA_AE_QP_MCQE_NEW_QP_STATE_MASK = 0xFFFF,449 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16,450 OCRDMA_AE_QP_MCQE_QP_ID_MASK = 0xFFFF <<451 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT,452 453 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT = 8,454 OCRDMA_AE_QP_MCQE_EVENT_CODE_MASK = 0xFF <<455 OCRDMA_AE_QP_MCQE_EVENT_CODE_SHIFT,456 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16,457 OCRDMA_AE_QP_MCQE_EVENT_TYPE_MASK = 0xFF <<458 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT,459 OCRDMA_AE_QP_MCQE_EVENT_AE_SHIFT = 30,460 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = BIT(30),461 OCRDMA_AE_QP_MCQE_EVENT_VALID_SHIFT = 31,462 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = BIT(31)463};464 465struct ocrdma_ae_qp_mcqe {466 u32 qp_id_state;467 u32 w1;468 u32 w2;469 u32 valid_ae_event;470};471 472enum ocrdma_async_event_code {473 OCRDMA_ASYNC_LINK_EVE_CODE = 0x01,474 OCRDMA_ASYNC_GRP5_EVE_CODE = 0x05,475 OCRDMA_ASYNC_RDMA_EVE_CODE = 0x14476};477 478enum ocrdma_async_grp5_events {479 OCRDMA_ASYNC_EVENT_QOS_VALUE = 0x01,480 OCRDMA_ASYNC_EVENT_COS_VALUE = 0x02,481 OCRDMA_ASYNC_EVENT_PVID_STATE = 0x03482};483 484enum OCRDMA_ASYNC_EVENT_TYPE {485 OCRDMA_CQ_ERROR = 0x00,486 OCRDMA_CQ_OVERRUN_ERROR = 0x01,487 OCRDMA_CQ_QPCAT_ERROR = 0x02,488 OCRDMA_QP_ACCESS_ERROR = 0x03,489 OCRDMA_QP_COMM_EST_EVENT = 0x04,490 OCRDMA_SQ_DRAINED_EVENT = 0x05,491 OCRDMA_DEVICE_FATAL_EVENT = 0x08,492 OCRDMA_SRQCAT_ERROR = 0x0E,493 OCRDMA_SRQ_LIMIT_EVENT = 0x0F,494 OCRDMA_QP_LAST_WQE_EVENT = 0x10,495 496 OCRDMA_MAX_ASYNC_ERRORS497};498 499struct ocrdma_ae_lnkst_mcqe {500 u32 speed_state_ptn;501 u32 qos_reason_falut;502 u32 evt_tag;503 u32 valid_ae_event;504};505 506enum {507 OCRDMA_AE_LSC_PORT_NUM_MASK = 0x3F,508 OCRDMA_AE_LSC_PT_SHIFT = 0x06,509 OCRDMA_AE_LSC_PT_MASK = (0x03 <<510 OCRDMA_AE_LSC_PT_SHIFT),511 OCRDMA_AE_LSC_LS_SHIFT = 0x08,512 OCRDMA_AE_LSC_LS_MASK = (0xFF <<513 OCRDMA_AE_LSC_LS_SHIFT),514 OCRDMA_AE_LSC_LD_SHIFT = 0x10,515 OCRDMA_AE_LSC_LD_MASK = (0xFF <<516 OCRDMA_AE_LSC_LD_SHIFT),517 OCRDMA_AE_LSC_PPS_SHIFT = 0x18,518 OCRDMA_AE_LSC_PPS_MASK = (0xFF <<519 OCRDMA_AE_LSC_PPS_SHIFT),520 OCRDMA_AE_LSC_PPF_MASK = 0xFF,521 OCRDMA_AE_LSC_ER_SHIFT = 0x08,522 OCRDMA_AE_LSC_ER_MASK = (0xFF <<523 OCRDMA_AE_LSC_ER_SHIFT),524 OCRDMA_AE_LSC_QOS_SHIFT = 0x10,525 OCRDMA_AE_LSC_QOS_MASK = (0xFFFF <<526 OCRDMA_AE_LSC_QOS_SHIFT)527};528 529enum {530 OCRDMA_AE_LSC_PLINK_DOWN = 0x00,531 OCRDMA_AE_LSC_PLINK_UP = 0x01,532 OCRDMA_AE_LSC_LLINK_DOWN = 0x02,533 OCRDMA_AE_LSC_LLINK_MASK = 0x02,534 OCRDMA_AE_LSC_LLINK_UP = 0x03535};536 537/* mailbox command request and responses */538enum {539 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT = 2,540 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = BIT(2),541 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT = 3,542 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = BIT(3),543 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT = 8,544 OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK = 0xFFFFFF <<545 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT,546 547 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16,548 OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK = 0xFFFF <<549 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT,550 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT = 8,551 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK = 0xFF <<552 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT,553 OCRDMA_MBX_QUERY_CFG_L3_TYPE_SHIFT = 3,554 OCRDMA_MBX_QUERY_CFG_L3_TYPE_MASK = 0x18,555 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT = 0,556 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK = 0xFFFF,557 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_SHIFT = 16,558 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_MASK = 0xFFFF <<559 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_SHIFT,560 561 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT = 0,562 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK = 0xFFFF,563 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16,564 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK = 0xFFFF <<565 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT,566 567 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET = 24,568 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK = 0xFF <<569 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET,570 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16,571 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK = 0xFF <<572 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET,573 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET = 0,574 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_MASK = 0xFFFF <<575 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CQES_OFFSET,576 577 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16,578 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK = 0xFFFF <<579 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET,580 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET = 0,581 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_MASK = 0xFFFF <<582 OCRDMA_MBX_QUERY_CFG_MAX_RPIR_QPS_OFFSET,583 584 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16,585 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK = 0xFFFF <<586 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET,587 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET = 0,588 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_MASK = 0xFFFF <<589 OCRDMA_MBX_QUERY_CFG_MAX_DPP_CREDITS_OFFSET,590 591 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET = 0,592 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_MASK = 0xFFFF <<593 OCRDMA_MBX_QUERY_CFG_MAX_DPP_QPS_OFFSET,594 595 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16,596 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_MASK = 0xFFFF <<597 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET,598 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET = 0,599 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK = 0xFFFF <<600 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_OFFSET,601 602 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16,603 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK = 0xFFFF <<604 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET,605 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET = 0,606 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK = 0xFFFF <<607 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_OFFSET,608 609 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16,610 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_MASK = 0xFFFF <<611 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET,612 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET = 0,613 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK = 0xFFFF <<614 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET,615 OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_SHIFT = 0,616 OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_MASK = 0xFFFF,617};618 619struct ocrdma_mbx_query_config {620 struct ocrdma_mqe_hdr hdr;621 struct ocrdma_mbx_rsp rsp;622 u32 qp_srq_cq_ird_ord;623 u32 max_pd_ca_ack_delay;624 u32 max_recv_send_sge;625 u32 max_ird_ord_per_qp;626 u32 max_shared_ird_ord;627 u32 max_mr;628 u32 max_mr_size_hi;629 u32 max_mr_size_lo;630 u32 max_num_mr_pbl;631 u32 max_mw;632 u32 max_fmr;633 u32 max_pages_per_frmr;634 u32 max_mcast_group;635 u32 max_mcast_qp_attach;636 u32 max_total_mcast_qp_attach;637 u32 wqe_rqe_stride_max_dpp_cqs;638 u32 max_srq_rpir_qps;639 u32 max_dpp_pds_credits;640 u32 max_dpp_credits_pds_per_pd;641 u32 max_wqes_rqes_per_q;642 u32 max_cq_cqes_per_cq;643 u32 max_srq_rqe_sge;644 u32 max_wr_rd_sge;645 u32 ird_pgsz_num_pages;646};647 648struct ocrdma_fw_ver_rsp {649 struct ocrdma_mqe_hdr hdr;650 struct ocrdma_mbx_rsp rsp;651 652 u8 running_ver[32];653};654 655struct ocrdma_fw_conf_rsp {656 struct ocrdma_mqe_hdr hdr;657 struct ocrdma_mbx_rsp rsp;658 659 u32 config_num;660 u32 asic_revision;661 u32 phy_port;662 u32 fn_mode;663 struct {664 u32 mode;665 u32 nic_wqid_base;666 u32 nic_wq_tot;667 u32 prot_wqid_base;668 u32 prot_wq_tot;669 u32 prot_rqid_base;670 u32 prot_rqid_tot;671 u32 rsvd[6];672 } ulp[2];673 u32 fn_capabilities;674 u32 rsvd1;675 u32 rsvd2;676 u32 base_eqid;677 u32 max_eq;678 679};680 681enum {682 OCRDMA_FN_MODE_RDMA = 0x4683};684 685enum {686 OCRDMA_IF_TYPE_MASK = 0xFFFF0000,687 OCRDMA_IF_TYPE_SHIFT = 0x10,688 OCRDMA_PHY_TYPE_MASK = 0x0000FFFF,689 OCRDMA_FUTURE_DETAILS_MASK = 0xFFFF0000,690 OCRDMA_FUTURE_DETAILS_SHIFT = 0x10,691 OCRDMA_EX_PHY_DETAILS_MASK = 0x0000FFFF,692 OCRDMA_FSPEED_SUPP_MASK = 0xFFFF0000,693 OCRDMA_FSPEED_SUPP_SHIFT = 0x10,694 OCRDMA_ASPEED_SUPP_MASK = 0x0000FFFF695};696 697struct ocrdma_get_phy_info_rsp {698 struct ocrdma_mqe_hdr hdr;699 struct ocrdma_mbx_rsp rsp;700 701 u32 ityp_ptyp;702 u32 misc_params;703 u32 ftrdtl_exphydtl;704 u32 fspeed_aspeed;705 u32 future_use[2];706};707 708enum {709 OCRDMA_PHY_SPEED_ZERO = 0x0,710 OCRDMA_PHY_SPEED_10MBPS = 0x1,711 OCRDMA_PHY_SPEED_100MBPS = 0x2,712 OCRDMA_PHY_SPEED_1GBPS = 0x4,713 OCRDMA_PHY_SPEED_10GBPS = 0x8,714 OCRDMA_PHY_SPEED_40GBPS = 0x20715};716 717enum {718 OCRDMA_PORT_NUM_MASK = 0x3F,719 OCRDMA_PT_MASK = 0xC0,720 OCRDMA_PT_SHIFT = 0x6,721 OCRDMA_LINK_DUP_MASK = 0x0000FF00,722 OCRDMA_LINK_DUP_SHIFT = 0x8,723 OCRDMA_PHY_PS_MASK = 0x00FF0000,724 OCRDMA_PHY_PS_SHIFT = 0x10,725 OCRDMA_PHY_PFLT_MASK = 0xFF000000,726 OCRDMA_PHY_PFLT_SHIFT = 0x18,727 OCRDMA_QOS_LNKSP_MASK = 0xFFFF0000,728 OCRDMA_QOS_LNKSP_SHIFT = 0x10,729 OCRDMA_LINK_ST_MASK = 0x01,730 OCRDMA_PLFC_MASK = 0x00000400,731 OCRDMA_PLFC_SHIFT = 0x8,732 OCRDMA_PLRFC_MASK = 0x00000200,733 OCRDMA_PLRFC_SHIFT = 0x8,734 OCRDMA_PLTFC_MASK = 0x00000100,735 OCRDMA_PLTFC_SHIFT = 0x8736};737 738struct ocrdma_get_link_speed_rsp {739 struct ocrdma_mqe_hdr hdr;740 struct ocrdma_mbx_rsp rsp;741 742 u32 pflt_pps_ld_pnum;743 u32 qos_lsp;744 u32 res_lnk_st;745};746 747enum {748 OCRDMA_PHYS_LINK_SPEED_ZERO = 0x0,749 OCRDMA_PHYS_LINK_SPEED_10MBPS = 0x1,750 OCRDMA_PHYS_LINK_SPEED_100MBPS = 0x2,751 OCRDMA_PHYS_LINK_SPEED_1GBPS = 0x3,752 OCRDMA_PHYS_LINK_SPEED_10GBPS = 0x4,753 OCRDMA_PHYS_LINK_SPEED_20GBPS = 0x5,754 OCRDMA_PHYS_LINK_SPEED_25GBPS = 0x6,755 OCRDMA_PHYS_LINK_SPEED_40GBPS = 0x7,756 OCRDMA_PHYS_LINK_SPEED_100GBPS = 0x8757};758 759enum {760 OCRDMA_CREATE_CQ_VER2 = 2,761 OCRDMA_CREATE_CQ_VER3 = 3,762 763 OCRDMA_CREATE_CQ_PAGE_CNT_MASK = 0xFFFF,764 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16,765 OCRDMA_CREATE_CQ_PAGE_SIZE_MASK = 0xFF,766 767 OCRDMA_CREATE_CQ_COALESCWM_SHIFT = 12,768 OCRDMA_CREATE_CQ_COALESCWM_MASK = BIT(13) | BIT(12),769 OCRDMA_CREATE_CQ_FLAGS_NODELAY = BIT(14),770 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = BIT(15),771 772 OCRDMA_CREATE_CQ_EQ_ID_MASK = 0xFFFF,773 OCRDMA_CREATE_CQ_CQE_COUNT_MASK = 0xFFFF774};775 776enum {777 OCRDMA_CREATE_CQ_VER0 = 0,778 OCRDMA_CREATE_CQ_DPP = 1,779 OCRDMA_CREATE_CQ_TYPE_SHIFT = 24,780 OCRDMA_CREATE_CQ_EQID_SHIFT = 22,781 782 OCRDMA_CREATE_CQ_CNT_SHIFT = 27,783 OCRDMA_CREATE_CQ_FLAGS_VALID = BIT(29),784 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = BIT(31),785 OCRDMA_CREATE_CQ_DEF_FLAGS = OCRDMA_CREATE_CQ_FLAGS_VALID |786 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE |787 OCRDMA_CREATE_CQ_FLAGS_NODELAY788};789 790struct ocrdma_create_cq_cmd {791 struct ocrdma_mbx_hdr req;792 u32 pgsz_pgcnt;793 u32 ev_cnt_flags;794 u32 eqn;795 u32 pdid_cqecnt;796 u32 rsvd6;797 struct ocrdma_pa pa[OCRDMA_CREATE_CQ_MAX_PAGES];798};799 800struct ocrdma_create_cq {801 struct ocrdma_mqe_hdr hdr;802 struct ocrdma_create_cq_cmd cmd;803};804 805enum {806 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT = 0x10807};808 809enum {810 OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK = 0xFFFF811};812 813struct ocrdma_create_cq_cmd_rsp {814 struct ocrdma_mbx_rsp rsp;815 u32 cq_id;816};817 818struct ocrdma_create_cq_rsp {819 struct ocrdma_mqe_hdr hdr;820 struct ocrdma_create_cq_cmd_rsp rsp;821};822 823enum {824 OCRDMA_CREATE_MQ_V0_CQ_ID_SHIFT = 22,825 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16,826 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16,827 OCRDMA_CREATE_MQ_VALID = BIT(31),828 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = BIT(0)829};830 831struct ocrdma_create_mq_req {832 struct ocrdma_mbx_hdr req;833 u32 cqid_pages;834 u32 async_event_bitmap;835 u32 async_cqid_ringsize;836 u32 valid;837 u32 async_cqid_valid;838 u32 rsvd;839 struct ocrdma_pa pa[8];840};841 842struct ocrdma_create_mq_rsp {843 struct ocrdma_mbx_rsp rsp;844 u32 id;845};846 847enum {848 OCRDMA_DESTROY_CQ_QID_SHIFT = 0,849 OCRDMA_DESTROY_CQ_QID_MASK = 0xFFFF,850 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16,851 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_MASK = 0xFFFF <<852 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT853};854 855struct ocrdma_destroy_cq {856 struct ocrdma_mqe_hdr hdr;857 struct ocrdma_mbx_hdr req;858 859 u32 bypass_flush_qid;860};861 862struct ocrdma_destroy_cq_rsp {863 struct ocrdma_mqe_hdr hdr;864 struct ocrdma_mbx_rsp rsp;865};866 867enum {868 OCRDMA_QPT_GSI = 1,869 OCRDMA_QPT_RC = 2,870 OCRDMA_QPT_UD = 4,871};872 873enum {874 OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT = 0,875 OCRDMA_CREATE_QP_REQ_PD_ID_MASK = 0xFFFF,876 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,877 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT = 19,878 OCRDMA_CREATE_QP_REQ_QPT_SHIFT = 29,879 OCRDMA_CREATE_QP_REQ_QPT_MASK = BIT(31) | BIT(30) | BIT(29),880 881 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT = 0,882 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK = 0xFFFF,883 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16,884 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK = 0xFFFF <<885 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT,886 887 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT = 0,888 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK = 0xFFFF,889 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16,890 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK = 0xFFFF <<891 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT,892 893 OCRDMA_CREATE_QP_REQ_FMR_EN_SHIFT = 0,894 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = BIT(0),895 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_SHIFT = 1,896 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = BIT(1),897 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_SHIFT = 2,898 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = BIT(2),899 OCRDMA_CREATE_QP_REQ_INB_WREN_SHIFT = 3,900 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = BIT(3),901 OCRDMA_CREATE_QP_REQ_INB_RDEN_SHIFT = 4,902 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = BIT(4),903 OCRDMA_CREATE_QP_REQ_USE_SRQ_SHIFT = 5,904 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = BIT(5),905 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_SHIFT = 6,906 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = BIT(6),907 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_SHIFT = 7,908 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = BIT(7),909 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_SHIFT = 8,910 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = BIT(8),911 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16,912 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK = 0xFFFF <<913 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT,914 915 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT = 0,916 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK = 0xFFFF,917 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16,918 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK = 0xFFFF <<919 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT,920 921 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT = 0,922 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK = 0xFFFF,923 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16,924 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK = 0xFFFF <<925 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT,926 927 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT = 0,928 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK = 0xFFFF,929 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16,930 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK = 0xFFFF <<931 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT,932 933 OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT = 0,934 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK = 0xFFFF,935 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16,936 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK = 0xFFFF <<937 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT,938 939 OCRDMA_CREATE_QP_REQ_DPP_CQPID_SHIFT = 0,940 OCRDMA_CREATE_QP_REQ_DPP_CQPID_MASK = 0xFFFF,941 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16,942 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_MASK = 0xFFFF <<943 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT944};945 946enum {947 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16,948 OCRDMA_CREATE_QP_RSP_DPP_PAGE_SHIFT = 1949};950 951#define MAX_OCRDMA_IRD_PAGES 4952 953enum ocrdma_qp_flags {954 OCRDMA_QP_MW_BIND = 1,955 OCRDMA_QP_LKEY0 = (1 << 1),956 OCRDMA_QP_FAST_REG = (1 << 2),957 OCRDMA_QP_INB_RD = (1 << 6),958 OCRDMA_QP_INB_WR = (1 << 7),959};960 961enum ocrdma_qp_state {962 OCRDMA_QPS_RST = 0,963 OCRDMA_QPS_INIT = 1,964 OCRDMA_QPS_RTR = 2,965 OCRDMA_QPS_RTS = 3,966 OCRDMA_QPS_SQE = 4,967 OCRDMA_QPS_SQ_DRAINING = 5,968 OCRDMA_QPS_ERR = 6,969 OCRDMA_QPS_SQD = 7970};971 972struct ocrdma_create_qp_req {973 struct ocrdma_mqe_hdr hdr;974 struct ocrdma_mbx_hdr req;975 976 u32 type_pgsz_pdn;977 u32 max_wqe_rqe;978 u32 max_sge_send_write;979 u32 max_sge_recv_flags;980 u32 max_ord_ird;981 u32 num_wq_rq_pages;982 u32 wqe_rqe_size;983 u32 wq_rq_cqid;984 struct ocrdma_pa wq_addr[MAX_OCRDMA_QP_PAGES];985 struct ocrdma_pa rq_addr[MAX_OCRDMA_QP_PAGES];986 u32 dpp_credits_cqid;987 u32 rpir_lkey;988 struct ocrdma_pa ird_addr[MAX_OCRDMA_IRD_PAGES];989};990 991enum {992 OCRDMA_CREATE_QP_RSP_QP_ID_SHIFT = 0,993 OCRDMA_CREATE_QP_RSP_QP_ID_MASK = 0xFFFF,994 995 OCRDMA_CREATE_QP_RSP_MAX_RQE_SHIFT = 0,996 OCRDMA_CREATE_QP_RSP_MAX_RQE_MASK = 0xFFFF,997 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16,998 OCRDMA_CREATE_QP_RSP_MAX_WQE_MASK = 0xFFFF <<999 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT,1000 1001 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_SHIFT = 0,1002 OCRDMA_CREATE_QP_RSP_MAX_SGE_WRITE_MASK = 0xFFFF,1003 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16,1004 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_MASK = 0xFFFF <<1005 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT,1006 1007 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16,1008 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_MASK = 0xFFFF <<1009 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT,1010 1011 OCRDMA_CREATE_QP_RSP_MAX_IRD_SHIFT = 0,1012 OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK = 0xFFFF,1013 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16,1014 OCRDMA_CREATE_QP_RSP_MAX_ORD_MASK = 0xFFFF <<1015 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT,1016 1017 OCRDMA_CREATE_QP_RSP_RQ_ID_SHIFT = 0,1018 OCRDMA_CREATE_QP_RSP_RQ_ID_MASK = 0xFFFF,1019 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16,1020 OCRDMA_CREATE_QP_RSP_SQ_ID_MASK = 0xFFFF <<1021 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT,1022 1023 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = BIT(0),1024 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT = 1,1025 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK = 0x7FFF <<1026 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT,1027 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16,1028 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK = 0xFFFF <<1029 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT,1030};1031 1032struct ocrdma_create_qp_rsp {1033 struct ocrdma_mqe_hdr hdr;1034 struct ocrdma_mbx_rsp rsp;1035 1036 u32 qp_id;1037 u32 max_wqe_rqe;1038 u32 max_sge_send_write;1039 u32 max_sge_recv;1040 u32 max_ord_ird;1041 u32 sq_rq_id;1042 u32 dpp_response;1043};1044 1045struct ocrdma_destroy_qp {1046 struct ocrdma_mqe_hdr hdr;1047 struct ocrdma_mbx_hdr req;1048 u32 qp_id;1049};1050 1051struct ocrdma_destroy_qp_rsp {1052 struct ocrdma_mqe_hdr hdr;1053 struct ocrdma_mbx_rsp rsp;1054};1055 1056enum {1057 OCRDMA_MODIFY_QP_ID_SHIFT = 0,1058 OCRDMA_MODIFY_QP_ID_MASK = 0xFFFF,1059 1060 OCRDMA_QP_PARA_QPS_VALID = BIT(0),1061 OCRDMA_QP_PARA_SQD_ASYNC_VALID = BIT(1),1062 OCRDMA_QP_PARA_PKEY_VALID = BIT(2),1063 OCRDMA_QP_PARA_QKEY_VALID = BIT(3),1064 OCRDMA_QP_PARA_PMTU_VALID = BIT(4),1065 OCRDMA_QP_PARA_ACK_TO_VALID = BIT(5),1066 OCRDMA_QP_PARA_RETRY_CNT_VALID = BIT(6),1067 OCRDMA_QP_PARA_RRC_VALID = BIT(7),1068 OCRDMA_QP_PARA_RQPSN_VALID = BIT(8),1069 OCRDMA_QP_PARA_MAX_IRD_VALID = BIT(9),1070 OCRDMA_QP_PARA_MAX_ORD_VALID = BIT(10),1071 OCRDMA_QP_PARA_RNT_VALID = BIT(11),1072 OCRDMA_QP_PARA_SQPSN_VALID = BIT(12),1073 OCRDMA_QP_PARA_DST_QPN_VALID = BIT(13),1074 OCRDMA_QP_PARA_MAX_WQE_VALID = BIT(14),1075 OCRDMA_QP_PARA_MAX_RQE_VALID = BIT(15),1076 OCRDMA_QP_PARA_SGE_SEND_VALID = BIT(16),1077 OCRDMA_QP_PARA_SGE_RECV_VALID = BIT(17),1078 OCRDMA_QP_PARA_SGE_WR_VALID = BIT(18),1079 OCRDMA_QP_PARA_INB_RDEN_VALID = BIT(19),1080 OCRDMA_QP_PARA_INB_WREN_VALID = BIT(20),1081 OCRDMA_QP_PARA_FLOW_LBL_VALID = BIT(21),1082 OCRDMA_QP_PARA_BIND_EN_VALID = BIT(22),1083 OCRDMA_QP_PARA_ZLKEY_EN_VALID = BIT(23),1084 OCRDMA_QP_PARA_FMR_EN_VALID = BIT(24),1085 OCRDMA_QP_PARA_INBAT_EN_VALID = BIT(25),1086 OCRDMA_QP_PARA_VLAN_EN_VALID = BIT(26),1087 1088 OCRDMA_MODIFY_QP_FLAGS_RD = BIT(0),1089 OCRDMA_MODIFY_QP_FLAGS_WR = BIT(1),1090 OCRDMA_MODIFY_QP_FLAGS_SEND = BIT(2),1091 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = BIT(3)1092};1093 1094enum {1095 OCRDMA_QP_PARAMS_SRQ_ID_SHIFT = 0,1096 OCRDMA_QP_PARAMS_SRQ_ID_MASK = 0xFFFF,1097 1098 OCRDMA_QP_PARAMS_MAX_RQE_SHIFT = 0,1099 OCRDMA_QP_PARAMS_MAX_RQE_MASK = 0xFFFF,1100 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16,1101 OCRDMA_QP_PARAMS_MAX_WQE_MASK = 0xFFFF <<1102 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT,1103 1104 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_SHIFT = 0,1105 OCRDMA_QP_PARAMS_MAX_SGE_WRITE_MASK = 0xFFFF,1106 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16,1107 OCRDMA_QP_PARAMS_MAX_SGE_SEND_MASK = 0xFFFF <<1108 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT,1109 1110 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = BIT(0),1111 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = BIT(1),1112 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = BIT(2),1113 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = BIT(3),1114 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = BIT(4),1115 OCRDMA_QP_PARAMS_STATE_SHIFT = 5,1116 OCRDMA_QP_PARAMS_STATE_MASK = BIT(5) | BIT(6) | BIT(7),1117 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = BIT(8),1118 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = BIT(9),1119 OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_SHIFT = 11,1120 OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_MASK = BIT(11) | BIT(12) | BIT(13),1121 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16,1122 OCRDMA_QP_PARAMS_MAX_SGE_RECV_MASK = 0xFFFF <<1123 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT,1124 1125 OCRDMA_QP_PARAMS_MAX_IRD_SHIFT = 0,1126 OCRDMA_QP_PARAMS_MAX_IRD_MASK = 0xFFFF,1127 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16,1128 OCRDMA_QP_PARAMS_MAX_ORD_MASK = 0xFFFF <<1129 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT,1130 1131 OCRDMA_QP_PARAMS_RQ_CQID_SHIFT = 0,1132 OCRDMA_QP_PARAMS_RQ_CQID_MASK = 0xFFFF,1133 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16,1134 OCRDMA_QP_PARAMS_WQ_CQID_MASK = 0xFFFF <<1135 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT,1136 1137 OCRDMA_QP_PARAMS_RQ_PSN_SHIFT = 0,1138 OCRDMA_QP_PARAMS_RQ_PSN_MASK = 0xFFFFFF,1139 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT = 24,1140 OCRDMA_QP_PARAMS_HOP_LMT_MASK = 0xFF <<1141 OCRDMA_QP_PARAMS_HOP_LMT_SHIFT,1142 1143 OCRDMA_QP_PARAMS_SQ_PSN_SHIFT = 0,1144 OCRDMA_QP_PARAMS_SQ_PSN_MASK = 0xFFFFFF,1145 OCRDMA_QP_PARAMS_TCLASS_SHIFT = 24,1146 OCRDMA_QP_PARAMS_TCLASS_MASK = 0xFF <<1147 OCRDMA_QP_PARAMS_TCLASS_SHIFT,1148 1149 OCRDMA_QP_PARAMS_DEST_QPN_SHIFT = 0,1150 OCRDMA_QP_PARAMS_DEST_QPN_MASK = 0xFFFFFF,1151 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT = 24,1152 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK = 0x7 <<1153 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT,1154 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT = 27,1155 OCRDMA_QP_PARAMS_ACK_TIMEOUT_MASK = 0x1F <<1156 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT,1157 1158 OCRDMA_QP_PARAMS_PKEY_IDNEX_SHIFT = 0,1159 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK = 0xFFFF,1160 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT = 18,1161 OCRDMA_QP_PARAMS_PATH_MTU_MASK = 0x3FFF <<1162 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT,1163 1164 OCRDMA_QP_PARAMS_FLOW_LABEL_SHIFT = 0,1165 OCRDMA_QP_PARAMS_FLOW_LABEL_MASK = 0xFFFFF,1166 OCRDMA_QP_PARAMS_SL_SHIFT = 20,1167 OCRDMA_QP_PARAMS_SL_MASK = 0xF <<1168 OCRDMA_QP_PARAMS_SL_SHIFT,1169 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT = 24,1170 OCRDMA_QP_PARAMS_RETRY_CNT_MASK = 0x7 <<1171 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT,1172 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT = 27,1173 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK = 0x1F <<1174 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT,1175 1176 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_SHIFT = 0,1177 OCRDMA_QP_PARAMS_DMAC_B4_TO_B5_MASK = 0xFFFF,1178 OCRDMA_QP_PARAMS_VLAN_SHIFT = 16,1179 OCRDMA_QP_PARAMS_VLAN_MASK = 0xFFFF <<1180 OCRDMA_QP_PARAMS_VLAN_SHIFT1181};1182 1183struct ocrdma_qp_params {1184 u32 id;1185 u32 max_wqe_rqe;1186 u32 max_sge_send_write;1187 u32 max_sge_recv_flags;1188 u32 max_ord_ird;1189 u32 wq_rq_cqid;1190 u32 hop_lmt_rq_psn;1191 u32 tclass_sq_psn;1192 u32 ack_to_rnr_rtc_dest_qpn;1193 u32 path_mtu_pkey_indx;1194 u32 rnt_rc_sl_fl;1195 u8 sgid[16];1196 u8 dgid[16];1197 u32 dmac_b0_to_b3;1198 u32 vlan_dmac_b4_to_b5;1199 u32 qkey;1200};1201 1202 1203struct ocrdma_modify_qp {1204 struct ocrdma_mqe_hdr hdr;1205 struct ocrdma_mbx_hdr req;1206 1207 struct ocrdma_qp_params params;1208 u32 flags;1209 u32 rdma_flags;1210 u32 num_outstanding_atomic_rd;1211};1212 1213enum {1214 OCRDMA_MODIFY_QP_RSP_MAX_RQE_SHIFT = 0,1215 OCRDMA_MODIFY_QP_RSP_MAX_RQE_MASK = 0xFFFF,1216 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16,1217 OCRDMA_MODIFY_QP_RSP_MAX_WQE_MASK = 0xFFFF <<1218 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT,1219 1220 OCRDMA_MODIFY_QP_RSP_MAX_IRD_SHIFT = 0,1221 OCRDMA_MODIFY_QP_RSP_MAX_IRD_MASK = 0xFFFF,1222 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16,1223 OCRDMA_MODIFY_QP_RSP_MAX_ORD_MASK = 0xFFFF <<1224 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT1225};1226 1227struct ocrdma_modify_qp_rsp {1228 struct ocrdma_mqe_hdr hdr;1229 struct ocrdma_mbx_rsp rsp;1230 1231 u32 max_wqe_rqe;1232 u32 max_ord_ird;1233};1234 1235struct ocrdma_query_qp {1236 struct ocrdma_mqe_hdr hdr;1237 struct ocrdma_mbx_hdr req;1238 1239#define OCRDMA_QUERY_UP_QP_ID_SHIFT 01240#define OCRDMA_QUERY_UP_QP_ID_MASK 0xFFFFFF1241 u32 qp_id;1242};1243 1244struct ocrdma_query_qp_rsp {1245 struct ocrdma_mqe_hdr hdr;1246 struct ocrdma_mbx_rsp rsp;1247 struct ocrdma_qp_params params;1248 u32 dpp_credits_cqid;1249 u32 rbq_id;1250};1251 1252enum {1253 OCRDMA_CREATE_SRQ_PD_ID_SHIFT = 0,1254 OCRDMA_CREATE_SRQ_PD_ID_MASK = 0xFFFF,1255 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16,1256 OCRDMA_CREATE_SRQ_PG_SZ_MASK = 0x3 <<1257 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT,1258 1259 OCRDMA_CREATE_SRQ_MAX_RQE_SHIFT = 0,1260 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16,1261 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_MASK = 0xFFFF <<1262 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT,1263 1264 OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT = 0,1265 OCRDMA_CREATE_SRQ_RQE_SIZE_MASK = 0xFFFF,1266 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16,1267 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_MASK = 0xFFFF <<1268 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT1269};1270 1271struct ocrdma_create_srq {1272 struct ocrdma_mqe_hdr hdr;1273 struct ocrdma_mbx_hdr req;1274 1275 u32 pgsz_pdid;1276 u32 max_sge_rqe;1277 u32 pages_rqe_sz;1278 struct ocrdma_pa rq_addr[MAX_OCRDMA_SRQ_PAGES];1279};1280 1281enum {1282 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_SHIFT = 0,1283 OCRDMA_CREATE_SRQ_RSP_SRQ_ID_MASK = 0xFFFFFF,1284 1285 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT = 0,1286 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK = 0xFFFF,1287 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16,1288 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK = 0xFFFF <<1289 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT1290};1291 1292struct ocrdma_create_srq_rsp {1293 struct ocrdma_mqe_hdr hdr;1294 struct ocrdma_mbx_rsp rsp;1295 1296 u32 id;1297 u32 max_sge_rqe_allocated;1298};1299 1300enum {1301 OCRDMA_MODIFY_SRQ_ID_SHIFT = 0,1302 OCRDMA_MODIFY_SRQ_ID_MASK = 0xFFFFFF,1303 1304 OCRDMA_MODIFY_SRQ_MAX_RQE_SHIFT = 0,1305 OCRDMA_MODIFY_SRQ_MAX_RQE_MASK = 0xFFFF,1306 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16,1307 OCRDMA_MODIFY_SRQ__LIMIT_MASK = 0xFFFF <<1308 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT1309};1310 1311struct ocrdma_modify_srq {1312 struct ocrdma_mqe_hdr hdr;1313 struct ocrdma_mbx_rsp rep;1314 1315 u32 id;1316 u32 limit_max_rqe;1317};1318 1319enum {1320 OCRDMA_QUERY_SRQ_ID_SHIFT = 0,1321 OCRDMA_QUERY_SRQ_ID_MASK = 0xFFFFFF1322};1323 1324struct ocrdma_query_srq {1325 struct ocrdma_mqe_hdr hdr;1326 struct ocrdma_mbx_rsp req;1327 1328 u32 id;1329};1330 1331enum {1332 OCRDMA_QUERY_SRQ_RSP_PD_ID_SHIFT = 0,1333 OCRDMA_QUERY_SRQ_RSP_PD_ID_MASK = 0xFFFF,1334 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16,1335 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_MASK = 0xFFFF <<1336 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT,1337 1338 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_SHIFT = 0,1339 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK = 0xFFFF,1340 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16,1341 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_MASK = 0xFFFF <<1342 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT1343};1344 1345struct ocrdma_query_srq_rsp {1346 struct ocrdma_mqe_hdr hdr;1347 struct ocrdma_mbx_rsp req;1348 1349 u32 max_rqe_pdid;1350 u32 srq_lmt_max_sge;1351};1352 1353enum {1354 OCRDMA_DESTROY_SRQ_ID_SHIFT = 0,1355 OCRDMA_DESTROY_SRQ_ID_MASK = 0xFFFFFF1356};1357 1358struct ocrdma_destroy_srq {1359 struct ocrdma_mqe_hdr hdr;1360 struct ocrdma_mbx_rsp req;1361 1362 u32 id;1363};1364 1365enum {1366 OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16),1367 OCRDMA_DPP_PAGE_SIZE = 40961368};1369 1370struct ocrdma_alloc_pd {1371 struct ocrdma_mqe_hdr hdr;1372 struct ocrdma_mbx_hdr req;1373 u32 enable_dpp_rsvd;1374};1375 1376enum {1377 OCRDMA_ALLOC_PD_RSP_DPP = BIT(16),1378 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT = 20,1379 OCRDMA_ALLOC_PD_RSP_PDID_MASK = 0xFFFF,1380};1381 1382struct ocrdma_alloc_pd_rsp {1383 struct ocrdma_mqe_hdr hdr;1384 struct ocrdma_mbx_rsp rsp;1385 u32 dpp_page_pdid;1386};1387 1388struct ocrdma_dealloc_pd {1389 struct ocrdma_mqe_hdr hdr;1390 struct ocrdma_mbx_hdr req;1391 u32 id;1392};1393 1394struct ocrdma_dealloc_pd_rsp {1395 struct ocrdma_mqe_hdr hdr;1396 struct ocrdma_mbx_rsp rsp;1397};1398 1399struct ocrdma_alloc_pd_range {1400 struct ocrdma_mqe_hdr hdr;1401 struct ocrdma_mbx_hdr req;1402 u32 enable_dpp_rsvd;1403 u32 pd_count;1404};1405 1406struct ocrdma_alloc_pd_range_rsp {1407 struct ocrdma_mqe_hdr hdr;1408 struct ocrdma_mbx_rsp rsp;1409 u32 dpp_page_pdid;1410 u32 pd_count;1411};1412 1413enum {1414 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK = 0xFFFF,1415};1416 1417struct ocrdma_dealloc_pd_range {1418 struct ocrdma_mqe_hdr hdr;1419 struct ocrdma_mbx_hdr req;1420 u32 start_pd_id;1421 u32 pd_count;1422};1423 1424struct ocrdma_dealloc_pd_range_rsp {1425 struct ocrdma_mqe_hdr hdr;1426 struct ocrdma_mbx_hdr req;1427 u32 rsvd;1428};1429 1430enum {1431 OCRDMA_ADDR_CHECK_ENABLE = 1,1432 OCRDMA_ADDR_CHECK_DISABLE = 01433};1434 1435enum {1436 OCRDMA_ALLOC_LKEY_PD_ID_SHIFT = 0,1437 OCRDMA_ALLOC_LKEY_PD_ID_MASK = 0xFFFF,1438 1439 OCRDMA_ALLOC_LKEY_ADDR_CHECK_SHIFT = 0,1440 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = BIT(0),1441 OCRDMA_ALLOC_LKEY_FMR_SHIFT = 1,1442 OCRDMA_ALLOC_LKEY_FMR_MASK = BIT(1),1443 OCRDMA_ALLOC_LKEY_REMOTE_INV_SHIFT = 2,1444 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = BIT(2),1445 OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT = 3,1446 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = BIT(3),1447 OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT = 4,1448 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = BIT(4),1449 OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT = 5,1450 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = BIT(5),1451 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = BIT(6),1452 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT = 6,1453 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16,1454 OCRDMA_ALLOC_LKEY_PBL_SIZE_MASK = 0xFFFF <<1455 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT1456};1457 1458struct ocrdma_alloc_lkey {1459 struct ocrdma_mqe_hdr hdr;1460 struct ocrdma_mbx_hdr req;1461 1462 u32 pdid;1463 u32 pbl_sz_flags;1464};1465 1466struct ocrdma_alloc_lkey_rsp {1467 struct ocrdma_mqe_hdr hdr;1468 struct ocrdma_mbx_rsp rsp;1469 1470 u32 lrkey;1471 u32 num_pbl_rsvd;1472};1473 1474struct ocrdma_dealloc_lkey {1475 struct ocrdma_mqe_hdr hdr;1476 struct ocrdma_mbx_hdr req;1477 1478 u32 lkey;1479 u32 rsvd_frmr;1480};1481 1482struct ocrdma_dealloc_lkey_rsp {1483 struct ocrdma_mqe_hdr hdr;1484 struct ocrdma_mbx_rsp rsp;1485};1486 1487#define MAX_OCRDMA_NSMR_PBL (u32)221488#define MAX_OCRDMA_PBL_SIZE 655361489#define MAX_OCRDMA_PBL_PER_LKEY 327671490 1491enum {1492 OCRDMA_REG_NSMR_LRKEY_INDEX_SHIFT = 0,1493 OCRDMA_REG_NSMR_LRKEY_INDEX_MASK = 0xFFFFFF,1494 OCRDMA_REG_NSMR_LRKEY_SHIFT = 24,1495 OCRDMA_REG_NSMR_LRKEY_MASK = 0xFF <<1496 OCRDMA_REG_NSMR_LRKEY_SHIFT,1497 1498 OCRDMA_REG_NSMR_PD_ID_SHIFT = 0,1499 OCRDMA_REG_NSMR_PD_ID_MASK = 0xFFFF,1500 OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16,1501 OCRDMA_REG_NSMR_NUM_PBL_MASK = 0xFFFF <<1502 OCRDMA_REG_NSMR_NUM_PBL_SHIFT,1503 1504 OCRDMA_REG_NSMR_PBE_SIZE_SHIFT = 0,1505 OCRDMA_REG_NSMR_PBE_SIZE_MASK = 0xFFFF,1506 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16,1507 OCRDMA_REG_NSMR_HPAGE_SIZE_MASK = 0xFF <<1508 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT,1509 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT = 24,1510 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = BIT(24),1511 OCRDMA_REG_NSMR_ZB_SHIFT = 25,1512 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = BIT(25),1513 OCRDMA_REG_NSMR_REMOTE_INV_SHIFT = 26,1514 OCRDMA_REG_NSMR_REMOTE_INV_MASK = BIT(26),1515 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT = 27,1516 OCRDMA_REG_NSMR_REMOTE_WR_MASK = BIT(27),1517 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT = 28,1518 OCRDMA_REG_NSMR_REMOTE_RD_MASK = BIT(28),1519 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT = 29,1520 OCRDMA_REG_NSMR_LOCAL_WR_MASK = BIT(29),1521 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT = 30,1522 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = BIT(30),1523 OCRDMA_REG_NSMR_LAST_SHIFT = 31,1524 OCRDMA_REG_NSMR_LAST_MASK = BIT(31)1525};1526 1527struct ocrdma_reg_nsmr {1528 struct ocrdma_mqe_hdr hdr;1529 struct ocrdma_mbx_hdr cmd;1530 1531 u32 fr_mr;1532 u32 num_pbl_pdid;1533 u32 flags_hpage_pbe_sz;1534 u32 totlen_low;1535 u32 totlen_high;1536 u32 fbo_low;1537 u32 fbo_high;1538 u32 va_loaddr;1539 u32 va_hiaddr;1540 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];1541};1542 1543enum {1544 OCRDMA_REG_NSMR_CONT_PBL_SHIFT = 0,1545 OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK = 0xFFFF,1546 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16,1547 OCRDMA_REG_NSMR_CONT_NUM_PBL_MASK = 0xFFFF <<1548 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT,1549 1550 OCRDMA_REG_NSMR_CONT_LAST_SHIFT = 31,1551 OCRDMA_REG_NSMR_CONT_LAST_MASK = BIT(31)1552};1553 1554struct ocrdma_reg_nsmr_cont {1555 struct ocrdma_mqe_hdr hdr;1556 struct ocrdma_mbx_hdr cmd;1557 1558 u32 lrkey;1559 u32 num_pbl_offset;1560 u32 last;1561 1562 struct ocrdma_pa pbl[MAX_OCRDMA_NSMR_PBL];1563};1564 1565struct ocrdma_pbe {1566 u32 pa_hi;1567 u32 pa_lo;1568};1569 1570enum {1571 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16,1572 OCRDMA_REG_NSMR_RSP_NUM_PBL_MASK = 0xFFFF00001573};1574struct ocrdma_reg_nsmr_rsp {1575 struct ocrdma_mqe_hdr hdr;1576 struct ocrdma_mbx_rsp rsp;1577 1578 u32 lrkey;1579 u32 num_pbl;1580};1581 1582enum {1583 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_SHIFT = 0,1584 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_INDEX_MASK = 0xFFFFFF,1585 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT = 24,1586 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_MASK = 0xFF <<1587 OCRDMA_REG_NSMR_CONT_RSP_LRKEY_SHIFT,1588 1589 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16,1590 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_MASK = 0xFFFF <<1591 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT1592};1593 1594struct ocrdma_reg_nsmr_cont_rsp {1595 struct ocrdma_mqe_hdr hdr;1596 struct ocrdma_mbx_rsp rsp;1597 1598 u32 lrkey_key_index;1599 u32 num_pbl;1600};1601 1602enum {1603 OCRDMA_ALLOC_MW_PD_ID_SHIFT = 0,1604 OCRDMA_ALLOC_MW_PD_ID_MASK = 0xFFFF1605};1606 1607struct ocrdma_alloc_mw {1608 struct ocrdma_mqe_hdr hdr;1609 struct ocrdma_mbx_hdr req;1610 1611 u32 pdid;1612};1613 1614enum {1615 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_SHIFT = 0,1616 OCRDMA_ALLOC_MW_RSP_LRKEY_INDEX_MASK = 0xFFFFFF1617};1618 1619struct ocrdma_alloc_mw_rsp {1620 struct ocrdma_mqe_hdr hdr;1621 struct ocrdma_mbx_rsp rsp;1622 1623 u32 lrkey_index;1624};1625 1626struct ocrdma_attach_mcast {1627 struct ocrdma_mqe_hdr hdr;1628 struct ocrdma_mbx_hdr req;1629 u32 qp_id;1630 u8 mgid[16];1631 u32 mac_b0_to_b3;1632 u32 vlan_mac_b4_to_b5;1633};1634 1635struct ocrdma_attach_mcast_rsp {1636 struct ocrdma_mqe_hdr hdr;1637 struct ocrdma_mbx_rsp rsp;1638};1639 1640struct ocrdma_detach_mcast {1641 struct ocrdma_mqe_hdr hdr;1642 struct ocrdma_mbx_hdr req;1643 u32 qp_id;1644 u8 mgid[16];1645 u32 mac_b0_to_b3;1646 u32 vlan_mac_b4_to_b5;1647};1648 1649struct ocrdma_detach_mcast_rsp {1650 struct ocrdma_mqe_hdr hdr;1651 struct ocrdma_mbx_rsp rsp;1652};1653 1654enum {1655 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT = 19,1656 OCRDMA_CREATE_AH_NUM_PAGES_MASK = 0xF <<1657 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT,1658 1659 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16,1660 OCRDMA_CREATE_AH_PAGE_SIZE_MASK = 0x7 <<1661 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT,1662 1663 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT = 23,1664 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK = 0x1FF <<1665 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT,1666};1667 1668#define OCRDMA_AH_TBL_PAGES 81669 1670struct ocrdma_create_ah_tbl {1671 struct ocrdma_mqe_hdr hdr;1672 struct ocrdma_mbx_hdr req;1673 1674 u32 ah_conf;1675 struct ocrdma_pa tbl_addr[8];1676};1677 1678struct ocrdma_create_ah_tbl_rsp {1679 struct ocrdma_mqe_hdr hdr;1680 struct ocrdma_mbx_rsp rsp;1681 u32 ahid;1682};1683 1684struct ocrdma_delete_ah_tbl {1685 struct ocrdma_mqe_hdr hdr;1686 struct ocrdma_mbx_hdr req;1687 u32 ahid;1688};1689 1690struct ocrdma_delete_ah_tbl_rsp {1691 struct ocrdma_mqe_hdr hdr;1692 struct ocrdma_mbx_rsp rsp;1693};1694 1695enum {1696 OCRDMA_EQE_VALID_SHIFT = 0,1697 OCRDMA_EQE_VALID_MASK = BIT(0),1698 OCRDMA_EQE_MAJOR_CODE_MASK = 0x0E,1699 OCRDMA_EQE_MAJOR_CODE_SHIFT = 0x01,1700 OCRDMA_EQE_FOR_CQE_MASK = 0xFFFE,1701 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16,1702 OCRDMA_EQE_RESOURCE_ID_MASK = 0xFFFF <<1703 OCRDMA_EQE_RESOURCE_ID_SHIFT,1704};1705 1706enum major_code {1707 OCRDMA_MAJOR_CODE_COMPLETION = 0x00,1708 OCRDMA_MAJOR_CODE_SENTINAL = 0x011709};1710 1711struct ocrdma_eqe {1712 u32 id_valid;1713};1714 1715enum OCRDMA_CQE_STATUS {1716 OCRDMA_CQE_SUCCESS = 0,1717 OCRDMA_CQE_LOC_LEN_ERR,1718 OCRDMA_CQE_LOC_QP_OP_ERR,1719 OCRDMA_CQE_LOC_EEC_OP_ERR,1720 OCRDMA_CQE_LOC_PROT_ERR,1721 OCRDMA_CQE_WR_FLUSH_ERR,1722 OCRDMA_CQE_MW_BIND_ERR,1723 OCRDMA_CQE_BAD_RESP_ERR,1724 OCRDMA_CQE_LOC_ACCESS_ERR,1725 OCRDMA_CQE_REM_INV_REQ_ERR,1726 OCRDMA_CQE_REM_ACCESS_ERR,1727 OCRDMA_CQE_REM_OP_ERR,1728 OCRDMA_CQE_RETRY_EXC_ERR,1729 OCRDMA_CQE_RNR_RETRY_EXC_ERR,1730 OCRDMA_CQE_LOC_RDD_VIOL_ERR,1731 OCRDMA_CQE_REM_INV_RD_REQ_ERR,1732 OCRDMA_CQE_REM_ABORT_ERR,1733 OCRDMA_CQE_INV_EECN_ERR,1734 OCRDMA_CQE_INV_EEC_STATE_ERR,1735 OCRDMA_CQE_FATAL_ERR,1736 OCRDMA_CQE_RESP_TIMEOUT_ERR,1737 OCRDMA_CQE_GENERAL_ERR,1738 1739 OCRDMA_MAX_CQE_ERR1740};1741 1742enum {1743 /* w0 */1744 OCRDMA_CQE_WQEIDX_SHIFT = 0,1745 OCRDMA_CQE_WQEIDX_MASK = 0xFFFF,1746 1747 /* w1 */1748 OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16,1749 OCRDMA_CQE_UD_XFER_LEN_MASK = 0x1FFF,1750 OCRDMA_CQE_PKEY_SHIFT = 0,1751 OCRDMA_CQE_PKEY_MASK = 0xFFFF,1752 OCRDMA_CQE_UD_L3TYPE_SHIFT = 29,1753 OCRDMA_CQE_UD_L3TYPE_MASK = 0x07,1754 1755 /* w2 */1756 OCRDMA_CQE_QPN_SHIFT = 0,1757 OCRDMA_CQE_QPN_MASK = 0x0000FFFF,1758 1759 OCRDMA_CQE_BUFTAG_SHIFT = 16,1760 OCRDMA_CQE_BUFTAG_MASK = 0xFFFF << OCRDMA_CQE_BUFTAG_SHIFT,1761 1762 /* w3 */1763 OCRDMA_CQE_UD_STATUS_SHIFT = 24,1764 OCRDMA_CQE_UD_STATUS_MASK = 0x7 << OCRDMA_CQE_UD_STATUS_SHIFT,1765 OCRDMA_CQE_STATUS_SHIFT = 16,1766 OCRDMA_CQE_STATUS_MASK = 0xFF << OCRDMA_CQE_STATUS_SHIFT,1767 OCRDMA_CQE_VALID = BIT(31),1768 OCRDMA_CQE_INVALIDATE = BIT(30),1769 OCRDMA_CQE_QTYPE = BIT(29),1770 OCRDMA_CQE_IMM = BIT(28),1771 OCRDMA_CQE_WRITE_IMM = BIT(27),1772 OCRDMA_CQE_QTYPE_SQ = 0,1773 OCRDMA_CQE_QTYPE_RQ = 1,1774 OCRDMA_CQE_SRCQP_MASK = 0xFFFFFF1775};1776 1777struct ocrdma_cqe {1778 union {1779 /* w0 to w2 */1780 struct {1781 u32 wqeidx;1782 u32 bytes_xfered;1783 u32 qpn;1784 } wq;1785 struct {1786 u32 lkey_immdt;1787 u32 rxlen;1788 u32 buftag_qpn;1789 } rq;1790 struct {1791 u32 lkey_immdt;1792 u32 rxlen_pkey;1793 u32 buftag_qpn;1794 } ud;1795 struct {1796 u32 word_0;1797 u32 word_1;1798 u32 qpn;1799 } cmn;1800 };1801 u32 flags_status_srcqpn; /* w3 */1802};1803 1804struct ocrdma_sge {1805 u32 addr_hi;1806 u32 addr_lo;1807 u32 lrkey;1808 u32 len;1809};1810 1811enum {1812 OCRDMA_FLAG_SIG = 0x1,1813 OCRDMA_FLAG_INV = 0x2,1814 OCRDMA_FLAG_FENCE_L = 0x4,1815 OCRDMA_FLAG_FENCE_R = 0x8,1816 OCRDMA_FLAG_SOLICIT = 0x10,1817 OCRDMA_FLAG_IMM = 0x20,1818 OCRDMA_FLAG_AH_VLAN_PR = 0x40,1819 1820 /* Stag flags */1821 OCRDMA_LKEY_FLAG_LOCAL_WR = 0x1,1822 OCRDMA_LKEY_FLAG_REMOTE_RD = 0x2,1823 OCRDMA_LKEY_FLAG_REMOTE_WR = 0x4,1824 OCRDMA_LKEY_FLAG_VATO = 0x8,1825};1826 1827enum OCRDMA_WQE_OPCODE {1828 OCRDMA_WRITE = 0x06,1829 OCRDMA_READ = 0x0C,1830 OCRDMA_RESV0 = 0x02,1831 OCRDMA_SEND = 0x00,1832 OCRDMA_CMP_SWP = 0x14,1833 OCRDMA_BIND_MW = 0x10,1834 OCRDMA_FR_MR = 0x11,1835 OCRDMA_RESV1 = 0x0A,1836 OCRDMA_LKEY_INV = 0x15,1837 OCRDMA_FETCH_ADD = 0x13,1838 OCRDMA_POST_RQ = 0x121839};1840 1841enum {1842 OCRDMA_TYPE_INLINE = 0x0,1843 OCRDMA_TYPE_LKEY = 0x1,1844};1845 1846enum {1847 OCRDMA_WQE_OPCODE_SHIFT = 0,1848 OCRDMA_WQE_OPCODE_MASK = 0x0000001F,1849 OCRDMA_WQE_FLAGS_SHIFT = 5,1850 OCRDMA_WQE_TYPE_SHIFT = 16,1851 OCRDMA_WQE_TYPE_MASK = 0x00030000,1852 OCRDMA_WQE_SIZE_SHIFT = 18,1853 OCRDMA_WQE_SIZE_MASK = 0xFF,1854 OCRDMA_WQE_NXT_WQE_SIZE_SHIFT = 25,1855 1856 OCRDMA_WQE_LKEY_FLAGS_SHIFT = 0,1857 OCRDMA_WQE_LKEY_FLAGS_MASK = 0xF1858};1859 1860/* header WQE for all the SQ and RQ operations */1861struct ocrdma_hdr_wqe {1862 u32 cw;1863 union {1864 u32 rsvd_tag;1865 u32 rsvd_lkey_flags;1866 };1867 union {1868 u32 immdt;1869 u32 lkey;1870 };1871 u32 total_len;1872};1873 1874struct ocrdma_ewqe_ud_hdr {1875 u32 rsvd_dest_qpn;1876 u32 qkey;1877 u32 rsvd_ahid;1878 u32 hdr_type;1879};1880 1881/* extended wqe followed by hdr_wqe for Fast Memory register */1882struct ocrdma_ewqe_fr {1883 u32 va_hi;1884 u32 va_lo;1885 u32 fbo_hi;1886 u32 fbo_lo;1887 u32 size_sge;1888 u32 num_sges;1889 u32 rsvd;1890 u32 rsvd2;1891};1892 1893struct ocrdma_eth_basic {1894 u8 dmac[6];1895 u8 smac[6];1896 __be16 eth_type;1897} __packed;1898 1899struct ocrdma_eth_vlan {1900 u8 dmac[6];1901 u8 smac[6];1902 __be16 eth_type;1903 __be16 vlan_tag;1904 __be16 roce_eth_type;1905} __packed;1906 1907struct ocrdma_grh {1908 __be32 tclass_flow;1909 __be32 pdid_hoplimit;1910 u8 sgid[16];1911 u8 dgid[16];1912 u16 rsvd;1913} __packed;1914 1915#define OCRDMA_AV_VALID BIT(7)1916#define OCRDMA_AV_VLAN_VALID BIT(1)1917 1918struct ocrdma_av {1919 struct ocrdma_eth_vlan eth_hdr;1920 struct ocrdma_grh grh;1921 u32 valid;1922} __packed;1923 1924struct ocrdma_rsrc_stats {1925 u32 dpp_pds;1926 u32 non_dpp_pds;1927 u32 rc_dpp_qps;1928 u32 uc_dpp_qps;1929 u32 ud_dpp_qps;1930 u32 rc_non_dpp_qps;1931 u32 rsvd;1932 u32 uc_non_dpp_qps;1933 u32 ud_non_dpp_qps;1934 u32 rsvd1;1935 u32 srqs;1936 u32 rbqs;1937 u32 r64K_nsmr;1938 u32 r64K_to_2M_nsmr;1939 u32 r2M_to_44M_nsmr;1940 u32 r44M_to_1G_nsmr;1941 u32 r1G_to_4G_nsmr;1942 u32 nsmr_count_4G_to_32G;1943 u32 r32G_to_64G_nsmr;1944 u32 r64G_to_128G_nsmr;1945 u32 r128G_to_higher_nsmr;1946 u32 embedded_nsmr;1947 u32 frmr;1948 u32 prefetch_qps;1949 u32 ondemand_qps;1950 u32 phy_mr;1951 u32 mw;1952 u32 rsvd2[7];1953};1954 1955struct ocrdma_db_err_stats {1956 u32 sq_doorbell_errors;1957 u32 cq_doorbell_errors;1958 u32 rq_srq_doorbell_errors;1959 u32 cq_overflow_errors;1960 u32 rsvd[4];1961};1962 1963struct ocrdma_wqe_stats {1964 u32 large_send_rc_wqes_lo;1965 u32 large_send_rc_wqes_hi;1966 u32 large_write_rc_wqes_lo;1967 u32 large_write_rc_wqes_hi;1968 u32 rsvd[4];1969 u32 read_wqes_lo;1970 u32 read_wqes_hi;1971 u32 frmr_wqes_lo;1972 u32 frmr_wqes_hi;1973 u32 mw_bind_wqes_lo;1974 u32 mw_bind_wqes_hi;1975 u32 invalidate_wqes_lo;1976 u32 invalidate_wqes_hi;1977 u32 rsvd1[2];1978 u32 dpp_wqe_drops;1979 u32 rsvd2[5];1980};1981 1982struct ocrdma_tx_stats {1983 u32 send_pkts_lo;1984 u32 send_pkts_hi;1985 u32 write_pkts_lo;1986 u32 write_pkts_hi;1987 u32 read_pkts_lo;1988 u32 read_pkts_hi;1989 u32 read_rsp_pkts_lo;1990 u32 read_rsp_pkts_hi;1991 u32 ack_pkts_lo;1992 u32 ack_pkts_hi;1993 u32 send_bytes_lo;1994 u32 send_bytes_hi;1995 u32 write_bytes_lo;1996 u32 write_bytes_hi;1997 u32 read_req_bytes_lo;1998 u32 read_req_bytes_hi;1999 u32 read_rsp_bytes_lo;2000 u32 read_rsp_bytes_hi;2001 u32 ack_timeouts;2002 u32 rsvd[5];2003};2004 2005 2006struct ocrdma_tx_qp_err_stats {2007 u32 local_length_errors;2008 u32 local_protection_errors;2009 u32 local_qp_operation_errors;2010 u32 retry_count_exceeded_errors;2011 u32 rnr_retry_count_exceeded_errors;2012 u32 rsvd[3];2013};2014 2015struct ocrdma_rx_stats {2016 u32 roce_frame_bytes_lo;2017 u32 roce_frame_bytes_hi;2018 u32 roce_frame_icrc_drops;2019 u32 roce_frame_payload_len_drops;2020 u32 ud_drops;2021 u32 qp1_drops;2022 u32 psn_error_request_packets;2023 u32 psn_error_resp_packets;2024 u32 rnr_nak_timeouts;2025 u32 rnr_nak_receives;2026 u32 roce_frame_rxmt_drops;2027 u32 nak_count_psn_sequence_errors;2028 u32 rc_drop_count_lookup_errors;2029 u32 rq_rnr_naks;2030 u32 srq_rnr_naks;2031 u32 roce_frames_lo;2032 u32 roce_frames_hi;2033 u32 rsvd;2034};2035 2036struct ocrdma_rx_qp_err_stats {2037 u32 nak_invalid_request_errors;2038 u32 nak_remote_operation_errors;2039 u32 nak_count_remote_access_errors;2040 u32 local_length_errors;2041 u32 local_protection_errors;2042 u32 local_qp_operation_errors;2043 u32 rsvd[2];2044};2045 2046struct ocrdma_tx_dbg_stats {2047 u32 data[100];2048};2049 2050struct ocrdma_rx_dbg_stats {2051 u32 data[200];2052};2053 2054struct ocrdma_rdma_stats_req {2055 struct ocrdma_mbx_hdr hdr;2056 u8 reset_stats;2057 u8 rsvd[3];2058} __packed;2059 2060struct ocrdma_rdma_stats_resp {2061 struct ocrdma_mbx_hdr hdr;2062 struct ocrdma_rsrc_stats act_rsrc_stats;2063 struct ocrdma_rsrc_stats th_rsrc_stats;2064 struct ocrdma_db_err_stats db_err_stats;2065 struct ocrdma_wqe_stats wqe_stats;2066 struct ocrdma_tx_stats tx_stats;2067 struct ocrdma_tx_qp_err_stats tx_qp_err_stats;2068 struct ocrdma_rx_stats rx_stats;2069 struct ocrdma_rx_qp_err_stats rx_qp_err_stats;2070 struct ocrdma_tx_dbg_stats tx_dbg_stats;2071 struct ocrdma_rx_dbg_stats rx_dbg_stats;2072} __packed;2073 2074enum {2075 OCRDMA_HBA_ATTRB_EPROM_VER_LO_MASK = 0xFF,2076 OCRDMA_HBA_ATTRB_EPROM_VER_HI_MASK = 0xFF00,2077 OCRDMA_HBA_ATTRB_EPROM_VER_HI_SHIFT = 0x08,2078 OCRDMA_HBA_ATTRB_CDBLEN_MASK = 0xFFFF,2079 OCRDMA_HBA_ATTRB_ASIC_REV_MASK = 0xFF0000,2080 OCRDMA_HBA_ATTRB_ASIC_REV_SHIFT = 0x10,2081 OCRDMA_HBA_ATTRB_GUID0_MASK = 0xFF000000,2082 OCRDMA_HBA_ATTRB_GUID0_SHIFT = 0x18,2083 OCRDMA_HBA_ATTRB_GUID13_MASK = 0xFF,2084 OCRDMA_HBA_ATTRB_GUID14_MASK = 0xFF00,2085 OCRDMA_HBA_ATTRB_GUID14_SHIFT = 0x08,2086 OCRDMA_HBA_ATTRB_GUID15_MASK = 0xFF0000,2087 OCRDMA_HBA_ATTRB_GUID15_SHIFT = 0x10,2088 OCRDMA_HBA_ATTRB_PCNT_MASK = 0xFF000000,2089 OCRDMA_HBA_ATTRB_PCNT_SHIFT = 0x18,2090 OCRDMA_HBA_ATTRB_LDTOUT_MASK = 0xFFFF,2091 OCRDMA_HBA_ATTRB_ISCSI_VER_MASK = 0xFF0000,2092 OCRDMA_HBA_ATTRB_ISCSI_VER_SHIFT = 0x10,2093 OCRDMA_HBA_ATTRB_MFUNC_DEV_MASK = 0xFF000000,2094 OCRDMA_HBA_ATTRB_MFUNC_DEV_SHIFT = 0x18,2095 OCRDMA_HBA_ATTRB_CV_MASK = 0xFF,2096 OCRDMA_HBA_ATTRB_HBA_ST_MASK = 0xFF00,2097 OCRDMA_HBA_ATTRB_HBA_ST_SHIFT = 0x08,2098 OCRDMA_HBA_ATTRB_MAX_DOMS_MASK = 0xFF0000,2099 OCRDMA_HBA_ATTRB_MAX_DOMS_SHIFT = 0x10,2100 OCRDMA_HBA_ATTRB_PTNUM_MASK = 0x3F000000,2101 OCRDMA_HBA_ATTRB_PTNUM_SHIFT = 0x18,2102 OCRDMA_HBA_ATTRB_PT_MASK = 0xC0000000,2103 OCRDMA_HBA_ATTRB_PT_SHIFT = 0x1E,2104 OCRDMA_HBA_ATTRB_ISCSI_FET_MASK = 0xFF,2105 OCRDMA_HBA_ATTRB_ASIC_GEN_MASK = 0xFF00,2106 OCRDMA_HBA_ATTRB_ASIC_GEN_SHIFT = 0x08,2107 OCRDMA_HBA_ATTRB_PCI_VID_MASK = 0xFFFF,2108 OCRDMA_HBA_ATTRB_PCI_DID_MASK = 0xFFFF0000,2109 OCRDMA_HBA_ATTRB_PCI_DID_SHIFT = 0x10,2110 OCRDMA_HBA_ATTRB_PCI_SVID_MASK = 0xFFFF,2111 OCRDMA_HBA_ATTRB_PCI_SSID_MASK = 0xFFFF0000,2112 OCRDMA_HBA_ATTRB_PCI_SSID_SHIFT = 0x10,2113 OCRDMA_HBA_ATTRB_PCI_BUSNUM_MASK = 0xFF,2114 OCRDMA_HBA_ATTRB_PCI_DEVNUM_MASK = 0xFF00,2115 OCRDMA_HBA_ATTRB_PCI_DEVNUM_SHIFT = 0x08,2116 OCRDMA_HBA_ATTRB_PCI_FUNCNUM_MASK = 0xFF0000,2117 OCRDMA_HBA_ATTRB_PCI_FUNCNUM_SHIFT = 0x10,2118 OCRDMA_HBA_ATTRB_IF_TYPE_MASK = 0xFF000000,2119 OCRDMA_HBA_ATTRB_IF_TYPE_SHIFT = 0x18,2120 OCRDMA_HBA_ATTRB_NETFIL_MASK =0xFF2121};2122 2123struct mgmt_hba_attribs {2124 u8 flashrom_version_string[32];2125 u8 manufacturer_name[32];2126 u32 supported_modes;2127 u32 rsvd_eprom_verhi_verlo;2128 u32 mbx_ds_ver;2129 u32 epfw_ds_ver;2130 u8 ncsi_ver_string[12];2131 u32 default_extended_timeout;2132 u8 controller_model_number[32];2133 u8 controller_description[64];2134 u8 controller_serial_number[32];2135 u8 ip_version_string[32];2136 u8 firmware_version_string[32];2137 u8 bios_version_string[32];2138 u8 redboot_version_string[32];2139 u8 driver_version_string[32];2140 u8 fw_on_flash_version_string[32];2141 u32 functionalities_supported;2142 u32 guid0_asicrev_cdblen;2143 u8 generational_guid[12];2144 u32 portcnt_guid15;2145 u32 mfuncdev_iscsi_ldtout;2146 u32 ptpnum_maxdoms_hbast_cv;2147 u32 firmware_post_status;2148 u32 hba_mtu[8];2149 u32 res_asicgen_iscsi_feaures;2150 u32 rsvd1[3];2151};2152 2153struct mgmt_controller_attrib {2154 struct mgmt_hba_attribs hba_attribs;2155 u32 pci_did_vid;2156 u32 pci_ssid_svid;2157 u32 ityp_fnum_devnum_bnum;2158 u32 uid_hi;2159 u32 uid_lo;2160 u32 res_nnetfil;2161 u32 rsvd0[4];2162};2163 2164struct ocrdma_get_ctrl_attribs_rsp {2165 struct ocrdma_mbx_hdr hdr;2166 struct mgmt_controller_attrib ctrl_attribs;2167};2168 2169#define OCRDMA_SUBSYS_DCBX 0x102170 2171enum OCRDMA_DCBX_OPCODE {2172 OCRDMA_CMD_GET_DCBX_CONFIG = 0x012173};2174 2175enum OCRDMA_DCBX_PARAM_TYPE {2176 OCRDMA_PARAMETER_TYPE_ADMIN = 0x00,2177 OCRDMA_PARAMETER_TYPE_OPER = 0x01,2178 OCRDMA_PARAMETER_TYPE_PEER = 0x022179};2180 2181enum OCRDMA_DCBX_PROTO {2182 OCRDMA_PROTO_SELECT_L2 = 0x00,2183 OCRDMA_PROTO_SELECT_L4 = 0x012184};2185 2186enum OCRDMA_DCBX_APP_PARAM {2187 OCRDMA_APP_PARAM_APP_PROTO_MASK = 0xFFFF,2188 OCRDMA_APP_PARAM_PROTO_SEL_MASK = 0xFF,2189 OCRDMA_APP_PARAM_PROTO_SEL_SHIFT = 0x10,2190 OCRDMA_APP_PARAM_VALID_MASK = 0xFF,2191 OCRDMA_APP_PARAM_VALID_SHIFT = 0x182192};2193 2194enum OCRDMA_DCBX_STATE_FLAGS {2195 OCRDMA_STATE_FLAG_ENABLED = 0x01,2196 OCRDMA_STATE_FLAG_ADDVERTISED = 0x02,2197 OCRDMA_STATE_FLAG_WILLING = 0x04,2198 OCRDMA_STATE_FLAG_SYNC = 0x08,2199 OCRDMA_STATE_FLAG_UNSUPPORTED = 0x40000000,2200 OCRDMA_STATE_FLAG_NEG_FAILD = 0x800000002201};2202 2203enum OCRDMA_TCV_AEV_OPV_ST {2204 OCRDMA_DCBX_TC_SUPPORT_MASK = 0xFF,2205 OCRDMA_DCBX_TC_SUPPORT_SHIFT = 0x18,2206 OCRDMA_DCBX_APP_ENTRY_SHIFT = 0x10,2207 OCRDMA_DCBX_OP_PARAM_SHIFT = 0x08,2208 OCRDMA_DCBX_STATE_MASK = 0xFF2209};2210 2211struct ocrdma_app_parameter {2212 u32 valid_proto_app;2213 u32 oui;2214 u32 app_prio[2];2215};2216 2217struct ocrdma_dcbx_cfg {2218 u32 tcv_aev_opv_st;2219 u32 tc_state;2220 u32 pfc_state;2221 u32 qcn_state;2222 u32 appl_state;2223 u32 ll_state;2224 u32 tc_bw[2];2225 u32 tc_prio[8];2226 u32 pfc_prio[2];2227 struct ocrdma_app_parameter app_param[15];2228};2229 2230struct ocrdma_get_dcbx_cfg_req {2231 struct ocrdma_mbx_hdr hdr;2232 u32 param_type;2233} __packed;2234 2235struct ocrdma_get_dcbx_cfg_rsp {2236 struct ocrdma_mbx_rsp hdr;2237 struct ocrdma_dcbx_cfg cfg;2238} __packed;2239 2240#endif /* __OCRDMA_SLI_H__ */2241