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1#ifndef _QIB_KERNEL_H2#define _QIB_KERNEL_H3/*4 * Copyright (c) 2012 - 2017 Intel Corporation. All rights reserved.5 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.6 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.7 *8 * This software is available to you under a choice of one of two9 * licenses. You may choose to be licensed under the terms of the GNU10 * General Public License (GPL) Version 2, available from the file11 * COPYING in the main directory of this source tree, or the12 * OpenIB.org BSD license below:13 *14 * Redistribution and use in source and binary forms, with or15 * without modification, are permitted provided that the following16 * conditions are met:17 *18 * - Redistributions of source code must retain the above19 * copyright notice, this list of conditions and the following20 * disclaimer.21 *22 * - Redistributions in binary form must reproduce the above23 * copyright notice, this list of conditions and the following24 * disclaimer in the documentation and/or other materials25 * provided with the distribution.26 *27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,28 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF29 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND30 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS31 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE34 * SOFTWARE.35 */36 37/*38 * This header file is the base header file for qlogic_ib kernel code39 * qib_user.h serves a similar purpose for user code.40 */41 42#include <linux/interrupt.h>43#include <linux/pci.h>44#include <linux/dma-mapping.h>45#include <linux/mutex.h>46#include <linux/list.h>47#include <linux/scatterlist.h>48#include <linux/slab.h>49#include <linux/io.h>50#include <linux/fs.h>51#include <linux/completion.h>52#include <linux/kref.h>53#include <linux/sched.h>54#include <linux/kthread.h>55#include <linux/xarray.h>56#include <rdma/ib_hdrs.h>57#include <rdma/rdma_vt.h>58 59#include "qib_common.h"60#include "qib_verbs.h"61 62/* only s/w major version of QLogic_IB we can handle */63#define QIB_CHIP_VERS_MAJ 2U64 65/* don't care about this except printing */66#define QIB_CHIP_VERS_MIN 0U67 68/* The Organization Unique Identifier (Mfg code), and its position in GUID */69#define QIB_OUI 0x00117570#define QIB_OUI_LSB 4071 72/*73 * per driver stats, either not device nor port-specific, or74 * summed over all of the devices and ports.75 * They are described by name via ipathfs filesystem, so layout76 * and number of elements can change without breaking compatibility.77 * If members are added or deleted qib_statnames[] in qib_fs.c must78 * change to match.79 */80struct qlogic_ib_stats {81 __u64 sps_ints; /* number of interrupts handled */82 __u64 sps_errints; /* number of error interrupts */83 __u64 sps_txerrs; /* tx-related packet errors */84 __u64 sps_rcverrs; /* non-crc rcv packet errors */85 __u64 sps_hwerrs; /* hardware errors reported (parity, etc.) */86 __u64 sps_nopiobufs; /* no pio bufs avail from kernel */87 __u64 sps_ctxts; /* number of contexts currently open */88 __u64 sps_lenerrs; /* number of kernel packets where RHF != LRH len */89 __u64 sps_buffull;90 __u64 sps_hdrfull;91};92 93extern struct qlogic_ib_stats qib_stats;94extern const struct pci_error_handlers qib_pci_err_handler;95 96#define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ97/*98 * First-cut critierion for "device is active" is99 * two thousand dwords combined Tx, Rx traffic per100 * 5-second interval. SMA packets are 64 dwords,101 * and occur "a few per second", presumably each way.102 */103#define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)104 105/*106 * Below contains all data related to a single context (formerly called port).107 */108 109#ifdef CONFIG_DEBUG_FS110struct qib_opcode_stats_perctx;111#endif112 113struct qib_ctxtdata {114 void **rcvegrbuf;115 dma_addr_t *rcvegrbuf_phys;116 /* rcvhdrq base, needs mmap before useful */117 void *rcvhdrq;118 /* kernel virtual address where hdrqtail is updated */119 void *rcvhdrtail_kvaddr;120 /*121 * temp buffer for expected send setup, allocated at open, instead122 * of each setup call123 */124 void *tid_pg_list;125 /*126 * Shared page for kernel to signal user processes that send buffers127 * need disarming. The process should call QIB_CMD_DISARM_BUFS128 * or QIB_CMD_ACK_EVENT with IPATH_EVENT_DISARM_BUFS set.129 */130 unsigned long *user_event_mask;131 /* when waiting for rcv or pioavail */132 wait_queue_head_t wait;133 /*134 * rcvegr bufs base, physical, must fit135 * in 44 bits so 32 bit programs mmap64 44 bit works)136 */137 dma_addr_t rcvegr_phys;138 /* mmap of hdrq, must fit in 44 bits */139 dma_addr_t rcvhdrq_phys;140 dma_addr_t rcvhdrqtailaddr_phys;141 142 /*143 * number of opens (including slave sub-contexts) on this instance144 * (ignoring forks, dup, etc. for now)145 */146 int cnt;147 /*148 * how much space to leave at start of eager TID entries for149 * protocol use, on each TID150 */151 /* instead of calculating it */152 unsigned ctxt;153 /* local node of context */154 int node_id;155 /* non-zero if ctxt is being shared. */156 u16 subctxt_cnt;157 /* non-zero if ctxt is being shared. */158 u16 subctxt_id;159 /* number of eager TID entries. */160 u16 rcvegrcnt;161 /* index of first eager TID entry. */162 u16 rcvegr_tid_base;163 /* number of pio bufs for this ctxt (all procs, if shared) */164 u32 piocnt;165 /* first pio buffer for this ctxt */166 u32 pio_base;167 /* chip offset of PIO buffers for this ctxt */168 u32 piobufs;169 /* how many alloc_pages() chunks in rcvegrbuf_pages */170 u32 rcvegrbuf_chunks;171 /* how many egrbufs per chunk */172 u16 rcvegrbufs_perchunk;173 /* ilog2 of above */174 u16 rcvegrbufs_perchunk_shift;175 /* order for rcvegrbuf_pages */176 size_t rcvegrbuf_size;177 /* rcvhdrq size (for freeing) */178 size_t rcvhdrq_size;179 /* per-context flags for fileops/intr communication */180 unsigned long flag;181 /* next expected TID to check when looking for free */182 u32 tidcursor;183 /* WAIT_RCV that timed out, no interrupt */184 u32 rcvwait_to;185 /* WAIT_PIO that timed out, no interrupt */186 u32 piowait_to;187 /* WAIT_RCV already happened, no wait */188 u32 rcvnowait;189 /* WAIT_PIO already happened, no wait */190 u32 pionowait;191 /* total number of polled urgent packets */192 u32 urgent;193 /* saved total number of polled urgent packets for poll edge trigger */194 u32 urgent_poll;195 /* pid of process using this ctxt */196 pid_t pid;197 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT];198 /* same size as task_struct .comm[], command that opened context */199 char comm[TASK_COMM_LEN];200 /* pkeys set by this use of this ctxt */201 u16 pkeys[4];202 /* so file ops can get at unit */203 struct qib_devdata *dd;204 /* so funcs that need physical port can get it easily */205 struct qib_pportdata *ppd;206 /* A page of memory for rcvhdrhead, rcvegrhead, rcvegrtail * N */207 void *subctxt_uregbase;208 /* An array of pages for the eager receive buffers * N */209 void *subctxt_rcvegrbuf;210 /* An array of pages for the eager header queue entries * N */211 void *subctxt_rcvhdr_base;212 /* The version of the library which opened this ctxt */213 u32 userversion;214 /* Bitmask of active slaves */215 u32 active_slaves;216 /* Type of packets or conditions we want to poll for */217 u16 poll_type;218 /* receive packet sequence counter */219 u8 seq_cnt;220 u8 redirect_seq_cnt;221 /* ctxt rcvhdrq head offset */222 u32 head;223 /* QPs waiting for context processing */224 struct list_head qp_wait_list;225#ifdef CONFIG_DEBUG_FS226 /* verbs stats per CTX */227 struct qib_opcode_stats_perctx *opstats;228#endif229};230 231struct rvt_sge_state;232 233struct qib_sdma_txreq {234 int flags;235 int sg_count;236 dma_addr_t addr;237 void (*callback)(struct qib_sdma_txreq *, int);238 u16 start_idx; /* sdma private */239 u16 next_descq_idx; /* sdma private */240 struct list_head list; /* sdma private */241};242 243struct qib_sdma_desc {244 __le64 qw[2];245};246 247struct qib_verbs_txreq {248 struct qib_sdma_txreq txreq;249 struct rvt_qp *qp;250 struct rvt_swqe *wqe;251 u32 dwords;252 u16 hdr_dwords;253 u16 hdr_inx;254 struct qib_pio_header *align_buf;255 struct rvt_mregion *mr;256 struct rvt_sge_state *ss;257};258 259#define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1260#define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2261#define QIB_SDMA_TXREQ_F_INTREQ 0x4262#define QIB_SDMA_TXREQ_F_FREEBUF 0x8263#define QIB_SDMA_TXREQ_F_FREEDESC 0x10264 265#define QIB_SDMA_TXREQ_S_OK 0266#define QIB_SDMA_TXREQ_S_SENDERROR 1267#define QIB_SDMA_TXREQ_S_ABORTED 2268#define QIB_SDMA_TXREQ_S_SHUTDOWN 3269 270/*271 * Get/Set IB link-level config parameters for f_get/set_ib_cfg()272 * Mostly for MADs that set or query link parameters, also ipath273 * config interfaces274 */275#define QIB_IB_CFG_LIDLMC 0 /* LID (LS16b) and Mask (MS16b) */276#define QIB_IB_CFG_LWID_ENB 2 /* allowed Link-width */277#define QIB_IB_CFG_LWID 3 /* currently active Link-width */278#define QIB_IB_CFG_SPD_ENB 4 /* allowed Link speeds */279#define QIB_IB_CFG_SPD 5 /* current Link spd */280#define QIB_IB_CFG_RXPOL_ENB 6 /* Auto-RX-polarity enable */281#define QIB_IB_CFG_LREV_ENB 7 /* Auto-Lane-reversal enable */282#define QIB_IB_CFG_LINKLATENCY 8 /* Link Latency (IB1.2 only) */283#define QIB_IB_CFG_HRTBT 9 /* IB heartbeat off/enable/auto; DDR/QDR only */284#define QIB_IB_CFG_OP_VLS 10 /* operational VLs */285#define QIB_IB_CFG_VL_HIGH_CAP 11 /* num of VL high priority weights */286#define QIB_IB_CFG_VL_LOW_CAP 12 /* num of VL low priority weights */287#define QIB_IB_CFG_OVERRUN_THRESH 13 /* IB overrun threshold */288#define QIB_IB_CFG_PHYERR_THRESH 14 /* IB PHY error threshold */289#define QIB_IB_CFG_LINKDEFAULT 15 /* IB link default (sleep/poll) */290#define QIB_IB_CFG_PKEYS 16 /* update partition keys */291#define QIB_IB_CFG_MTU 17 /* update MTU in IBC */292#define QIB_IB_CFG_LSTATE 18 /* update linkcmd and linkinitcmd in IBC */293#define QIB_IB_CFG_VL_HIGH_LIMIT 19294#define QIB_IB_CFG_PMA_TICKS 20 /* PMA sample tick resolution */295#define QIB_IB_CFG_PORT 21 /* switch port we are connected to */296 297/*298 * for CFG_LSTATE: LINKCMD in upper 16 bits, LINKINITCMD in lower 16299 * IB_LINKINITCMD_POLL and SLEEP are also used as set/get values for300 * QIB_IB_CFG_LINKDEFAULT cmd301 */302#define IB_LINKCMD_DOWN (0 << 16)303#define IB_LINKCMD_ARMED (1 << 16)304#define IB_LINKCMD_ACTIVE (2 << 16)305#define IB_LINKINITCMD_NOP 0306#define IB_LINKINITCMD_POLL 1307#define IB_LINKINITCMD_SLEEP 2308#define IB_LINKINITCMD_DISABLE 3309 310/*311 * valid states passed to qib_set_linkstate() user call312 */313#define QIB_IB_LINKDOWN 0314#define QIB_IB_LINKARM 1315#define QIB_IB_LINKACTIVE 2316#define QIB_IB_LINKDOWN_ONLY 3317#define QIB_IB_LINKDOWN_SLEEP 4318#define QIB_IB_LINKDOWN_DISABLE 5319 320/*321 * These 7 values (SDR, DDR, and QDR may be ORed for auto-speed322 * negotiation) are used for the 3rd argument to path_f_set_ib_cfg323 * with cmd QIB_IB_CFG_SPD_ENB, by direct calls or via sysfs. They324 * are also the possible values for qib_link_speed_enabled and active325 * The values were chosen to match values used within the IB spec.326 */327#define QIB_IB_SDR 1328#define QIB_IB_DDR 2329#define QIB_IB_QDR 4330 331#define QIB_DEFAULT_MTU 4096332 333/* max number of IB ports supported per HCA */334#define QIB_MAX_IB_PORTS 2335 336/*337 * Possible IB config parameters for f_get/set_ib_table()338 */339#define QIB_IB_TBL_VL_HIGH_ARB 1 /* Get/set VL high priority weights */340#define QIB_IB_TBL_VL_LOW_ARB 2 /* Get/set VL low priority weights */341 342/*343 * Possible "operations" for f_rcvctrl(ppd, op, ctxt)344 * these are bits so they can be combined, e.g.345 * QIB_RCVCTRL_INTRAVAIL_ENB | QIB_RCVCTRL_CTXT_ENB346 */347#define QIB_RCVCTRL_TAILUPD_ENB 0x01348#define QIB_RCVCTRL_TAILUPD_DIS 0x02349#define QIB_RCVCTRL_CTXT_ENB 0x04350#define QIB_RCVCTRL_CTXT_DIS 0x08351#define QIB_RCVCTRL_INTRAVAIL_ENB 0x10352#define QIB_RCVCTRL_INTRAVAIL_DIS 0x20353#define QIB_RCVCTRL_PKEY_ENB 0x40 /* Note, default is enabled */354#define QIB_RCVCTRL_PKEY_DIS 0x80355#define QIB_RCVCTRL_BP_ENB 0x0100356#define QIB_RCVCTRL_BP_DIS 0x0200357#define QIB_RCVCTRL_TIDFLOW_ENB 0x0400358#define QIB_RCVCTRL_TIDFLOW_DIS 0x0800359 360/*361 * Possible "operations" for f_sendctrl(ppd, op, var)362 * these are bits so they can be combined, e.g.363 * QIB_SENDCTRL_BUFAVAIL_ENB | QIB_SENDCTRL_ENB364 * Some operations (e.g. DISARM, ABORT) are known to365 * be "one-shot", so do not modify shadow.366 */367#define QIB_SENDCTRL_DISARM (0x1000)368#define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM)369 /* available (0x2000) */370#define QIB_SENDCTRL_AVAIL_DIS (0x4000)371#define QIB_SENDCTRL_AVAIL_ENB (0x8000)372#define QIB_SENDCTRL_AVAIL_BLIP (0x10000)373#define QIB_SENDCTRL_SEND_DIS (0x20000)374#define QIB_SENDCTRL_SEND_ENB (0x40000)375#define QIB_SENDCTRL_FLUSH (0x80000)376#define QIB_SENDCTRL_CLEAR (0x100000)377#define QIB_SENDCTRL_DISARM_ALL (0x200000)378 379/*380 * These are the generic indices for requesting per-port381 * counter values via the f_portcntr function. They382 * are always returned as 64 bit values, although most383 * are 32 bit counters.384 */385/* send-related counters */386#define QIBPORTCNTR_PKTSEND 0U387#define QIBPORTCNTR_WORDSEND 1U388#define QIBPORTCNTR_PSXMITDATA 2U389#define QIBPORTCNTR_PSXMITPKTS 3U390#define QIBPORTCNTR_PSXMITWAIT 4U391#define QIBPORTCNTR_SENDSTALL 5U392/* receive-related counters */393#define QIBPORTCNTR_PKTRCV 6U394#define QIBPORTCNTR_PSRCVDATA 7U395#define QIBPORTCNTR_PSRCVPKTS 8U396#define QIBPORTCNTR_RCVEBP 9U397#define QIBPORTCNTR_RCVOVFL 10U398#define QIBPORTCNTR_WORDRCV 11U399/* IB link related error counters */400#define QIBPORTCNTR_RXLOCALPHYERR 12U401#define QIBPORTCNTR_RXVLERR 13U402#define QIBPORTCNTR_ERRICRC 14U403#define QIBPORTCNTR_ERRVCRC 15U404#define QIBPORTCNTR_ERRLPCRC 16U405#define QIBPORTCNTR_BADFORMAT 17U406#define QIBPORTCNTR_ERR_RLEN 18U407#define QIBPORTCNTR_IBSYMBOLERR 19U408#define QIBPORTCNTR_INVALIDRLEN 20U409#define QIBPORTCNTR_UNSUPVL 21U410#define QIBPORTCNTR_EXCESSBUFOVFL 22U411#define QIBPORTCNTR_ERRLINK 23U412#define QIBPORTCNTR_IBLINKDOWN 24U413#define QIBPORTCNTR_IBLINKERRRECOV 25U414#define QIBPORTCNTR_LLI 26U415/* other error counters */416#define QIBPORTCNTR_RXDROPPKT 27U417#define QIBPORTCNTR_VL15PKTDROP 28U418#define QIBPORTCNTR_ERRPKEY 29U419#define QIBPORTCNTR_KHDROVFL 30U420/* sampling counters (these are actually control registers) */421#define QIBPORTCNTR_PSINTERVAL 31U422#define QIBPORTCNTR_PSSTART 32U423#define QIBPORTCNTR_PSSTAT 33U424 425/* how often we check for packet activity for "power on hours (in seconds) */426#define ACTIVITY_TIMER 5427 428#define MAX_NAME_SIZE 64429 430#ifdef CONFIG_INFINIBAND_QIB_DCA431struct qib_irq_notify;432#endif433 434struct qib_msix_entry {435 void *arg;436#ifdef CONFIG_INFINIBAND_QIB_DCA437 int dca;438 int rcv;439 struct qib_irq_notify *notifier;440#endif441 cpumask_var_t mask;442};443 444/* Below is an opaque struct. Each chip (device) can maintain445 * private data needed for its operation, but not germane to the446 * rest of the driver. For convenience, we define another that447 * is chip-specific, per-port448 */449struct qib_chip_specific;450struct qib_chipport_specific;451 452enum qib_sdma_states {453 qib_sdma_state_s00_hw_down,454 qib_sdma_state_s10_hw_start_up_wait,455 qib_sdma_state_s20_idle,456 qib_sdma_state_s30_sw_clean_up_wait,457 qib_sdma_state_s40_hw_clean_up_wait,458 qib_sdma_state_s50_hw_halt_wait,459 qib_sdma_state_s99_running,460};461 462enum qib_sdma_events {463 qib_sdma_event_e00_go_hw_down,464 qib_sdma_event_e10_go_hw_start,465 qib_sdma_event_e20_hw_started,466 qib_sdma_event_e30_go_running,467 qib_sdma_event_e40_sw_cleaned,468 qib_sdma_event_e50_hw_cleaned,469 qib_sdma_event_e60_hw_halted,470 qib_sdma_event_e70_go_idle,471 qib_sdma_event_e7220_err_halted,472 qib_sdma_event_e7322_err_halted,473 qib_sdma_event_e90_timer_tick,474};475 476struct sdma_set_state_action {477 unsigned op_enable:1;478 unsigned op_intenable:1;479 unsigned op_halt:1;480 unsigned op_drain:1;481 unsigned go_s99_running_tofalse:1;482 unsigned go_s99_running_totrue:1;483};484 485struct qib_sdma_state {486 struct kref kref;487 struct completion comp;488 enum qib_sdma_states current_state;489 struct sdma_set_state_action *set_state_action;490 unsigned current_op;491 unsigned go_s99_running;492 unsigned first_sendbuf;493 unsigned last_sendbuf; /* really last +1 */494 /* debugging/devel */495 enum qib_sdma_states previous_state;496 unsigned previous_op;497 enum qib_sdma_events last_event;498};499 500struct xmit_wait {501 struct timer_list timer;502 u64 counter;503 u8 flags;504 struct cache {505 u64 psxmitdata;506 u64 psrcvdata;507 u64 psxmitpkts;508 u64 psrcvpkts;509 u64 psxmitwait;510 } counter_cache;511};512 513/*514 * The structure below encapsulates data relevant to a physical IB Port.515 * Current chips support only one such port, but the separation516 * clarifies things a bit. Note that to conform to IB conventions,517 * port-numbers are one-based. The first or only port is port1.518 */519struct qib_pportdata {520 struct qib_ibport ibport_data;521 522 struct qib_devdata *dd;523 struct qib_chippport_specific *cpspec; /* chip-specific per-port */524 525 /* GUID for this interface, in network order */526 __be64 guid;527 528 /* QIB_POLL, etc. link-state specific flags, per port */529 u32 lflags;530 /* qib_lflags driver is waiting for */531 u32 state_wanted;532 spinlock_t lflags_lock;533 534 /* ref count for each pkey */535 atomic_t pkeyrefs[4];536 537 /*538 * this address is mapped readonly into user processes so they can539 * get status cheaply, whenever they want. One qword of status per port540 */541 u64 *statusp;542 543 /* SendDMA related entries */544 545 /* read mostly */546 struct qib_sdma_desc *sdma_descq;547 struct workqueue_struct *qib_wq;548 struct qib_sdma_state sdma_state;549 dma_addr_t sdma_descq_phys;550 volatile __le64 *sdma_head_dma; /* DMA'ed by chip */551 dma_addr_t sdma_head_phys;552 u16 sdma_descq_cnt;553 554 /* read/write using lock */555 spinlock_t sdma_lock ____cacheline_aligned_in_smp;556 struct list_head sdma_activelist;557 struct list_head sdma_userpending;558 u64 sdma_descq_added;559 u64 sdma_descq_removed;560 u16 sdma_descq_tail;561 u16 sdma_descq_head;562 u8 sdma_generation;563 u8 sdma_intrequest;564 565 struct tasklet_struct sdma_sw_clean_up_task566 ____cacheline_aligned_in_smp;567 568 wait_queue_head_t state_wait; /* for state_wanted */569 570 /* HoL blocking for SMP replies */571 unsigned hol_state;572 struct timer_list hol_timer;573 574 /*575 * Shadow copies of registers; size indicates read access size.576 * Most of them are readonly, but some are write-only register,577 * where we manipulate the bits in the shadow copy, and then write578 * the shadow copy to qlogic_ib.579 *580 * We deliberately make most of these 32 bits, since they have581 * restricted range. For any that we read, we won't to generate 32582 * bit accesses, since Opteron will generate 2 separate 32 bit HT583 * transactions for a 64 bit read, and we want to avoid unnecessary584 * bus transactions.585 */586 587 /* This is the 64 bit group */588 /* last ibcstatus. opaque outside chip-specific code */589 u64 lastibcstat;590 591 /* these are the "32 bit" regs */592 593 /*594 * the following two are 32-bit bitmasks, but {test,clear,set}_bit595 * all expect bit fields to be "unsigned long"596 */597 unsigned long p_rcvctrl; /* shadow per-port rcvctrl */598 unsigned long p_sendctrl; /* shadow per-port sendctrl */599 600 u32 ibmtu; /* The MTU programmed for this unit */601 /*602 * Current max size IB packet (in bytes) including IB headers, that603 * we can send. Changes when ibmtu changes.604 */605 u32 ibmaxlen;606 /*607 * ibmaxlen at init time, limited by chip and by receive buffer608 * size. Not changed after init.609 */610 u32 init_ibmaxlen;611 /* LID programmed for this instance */612 u16 lid;613 /* list of pkeys programmed; 0 if not set */614 u16 pkeys[4];615 /* LID mask control */616 u8 lmc;617 u8 link_width_supported;618 u16 link_speed_supported;619 u8 link_width_enabled;620 u16 link_speed_enabled;621 u8 link_width_active;622 u16 link_speed_active;623 u8 vls_supported;624 u8 vls_operational;625 /* Rx Polarity inversion (compensate for ~tx on partner) */626 u8 rx_pol_inv;627 628 u8 hw_pidx; /* physical port index */629 u32 port; /* IB port number and index into dd->pports - 1 */630 631 u8 delay_mult;632 633 /* used to override LED behavior */634 u8 led_override; /* Substituted for normal value, if non-zero */635 u16 led_override_timeoff; /* delta to next timer event */636 u8 led_override_vals[2]; /* Alternates per blink-frame */637 u8 led_override_phase; /* Just counts, LSB picks from vals[] */638 atomic_t led_override_timer_active;639 /* Used to flash LEDs in override mode */640 struct timer_list led_override_timer;641 struct xmit_wait cong_stats;642 struct timer_list symerr_clear_timer;643 644 /* Synchronize access between driver writes and sysfs reads */645 spinlock_t cc_shadow_lock646 ____cacheline_aligned_in_smp;647 648 /* Shadow copy of the congestion control table */649 struct cc_table_shadow *ccti_entries_shadow;650 651 /* Shadow copy of the congestion control entries */652 struct ib_cc_congestion_setting_attr_shadow *congestion_entries_shadow;653 654 /* List of congestion control table entries */655 struct ib_cc_table_entry_shadow *ccti_entries;656 657 /* 16 congestion entries with each entry corresponding to a SL */658 struct ib_cc_congestion_entry_shadow *congestion_entries;659 660 /* Maximum number of congestion control entries that the agent expects661 * the manager to send.662 */663 u16 cc_supported_table_entries;664 665 /* Total number of congestion control table entries */666 u16 total_cct_entry;667 668 /* Bit map identifying service level */669 u16 cc_sl_control_map;670 671 /* maximum congestion control table index */672 u16 ccti_limit;673 674 /* CA's max number of 64 entry units in the congestion control table */675 u8 cc_max_table_entries;676};677 678/* Observers. Not to be taken lightly, possibly not to ship. */679/*680 * If a diag read or write is to (bottom <= offset <= top),681 * the "hook" is called, allowing, e.g. shadows to be682 * updated in sync with the driver. struct diag_observer683 * is the "visible" part.684 */685struct diag_observer;686 687typedef int (*diag_hook) (struct qib_devdata *dd,688 const struct diag_observer *op,689 u32 offs, u64 *data, u64 mask, int only_32);690 691struct diag_observer {692 diag_hook hook;693 u32 bottom;694 u32 top;695};696 697extern int qib_register_observer(struct qib_devdata *dd,698 const struct diag_observer *op);699 700/* Only declared here, not defined. Private to diags */701struct diag_observer_list_elt;702 703/* device data struct now contains only "general per-device" info.704 * fields related to a physical IB port are in a qib_pportdata struct,705 * described above) while fields only used by a particular chip-type are in706 * a qib_chipdata struct, whose contents are opaque to this file.707 */708struct qib_devdata {709 struct qib_ibdev verbs_dev; /* must be first */710 struct list_head list;711 /* pointers to related structs for this device */712 /* pci access data structure */713 struct pci_dev *pcidev;714 struct cdev *user_cdev;715 struct cdev *diag_cdev;716 struct device *user_device;717 struct device *diag_device;718 719 /* mem-mapped pointer to base of chip regs */720 u64 __iomem *kregbase;721 /* end of mem-mapped chip space excluding sendbuf and user regs */722 u64 __iomem *kregend;723 /* physical address of chip for io_remap, etc. */724 resource_size_t physaddr;725 /* qib_cfgctxts pointers */726 struct qib_ctxtdata **rcd; /* Receive Context Data */727 728 /* qib_pportdata, points to array of (physical) port-specific729 * data structs, indexed by pidx (0..n-1)730 */731 struct qib_pportdata *pport;732 struct qib_chip_specific *cspec; /* chip-specific */733 734 /* kvirt address of 1st 2k pio buffer */735 void __iomem *pio2kbase;736 /* kvirt address of 1st 4k pio buffer */737 void __iomem *pio4kbase;738 /* mem-mapped pointer to base of PIO buffers (if using WC PAT) */739 void __iomem *piobase;740 /* mem-mapped pointer to base of user chip regs (if using WC PAT) */741 u64 __iomem *userbase;742 void __iomem *piovl15base; /* base of VL15 buffers, if not WC */743 /*744 * points to area where PIOavail registers will be DMA'ed.745 * Has to be on a page of it's own, because the page will be746 * mapped into user program space. This copy is *ONLY* ever747 * written by DMA, not by the driver! Need a copy per device748 * when we get to multiple devices749 */750 volatile __le64 *pioavailregs_dma; /* DMA'ed by chip */751 /* physical address where updates occur */752 dma_addr_t pioavailregs_phys;753 754 /* device-specific implementations of functions needed by755 * common code. Contrary to previous consensus, we can't756 * really just point to a device-specific table, because we757 * may need to "bend", e.g. *_f_put_tid758 */759 /* fallback to alternate interrupt type if possible */760 int (*f_intr_fallback)(struct qib_devdata *);761 /* hard reset chip */762 int (*f_reset)(struct qib_devdata *);763 void (*f_quiet_serdes)(struct qib_pportdata *);764 int (*f_bringup_serdes)(struct qib_pportdata *);765 int (*f_early_init)(struct qib_devdata *);766 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);767 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,768 u32, unsigned long);769 void (*f_cleanup)(struct qib_devdata *);770 void (*f_setextled)(struct qib_pportdata *, u32);771 /* fill out chip-specific fields */772 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *);773 /* free irq */774 void (*f_free_irq)(struct qib_devdata *);775 struct qib_message_header *(*f_get_msgheader)776 (struct qib_devdata *, __le32 *);777 void (*f_config_ctxts)(struct qib_devdata *);778 int (*f_get_ib_cfg)(struct qib_pportdata *, int);779 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32);780 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *);781 int (*f_get_ib_table)(struct qib_pportdata *, int, void *);782 int (*f_set_ib_table)(struct qib_pportdata *, int, void *);783 u32 (*f_iblink_state)(u64);784 u8 (*f_ibphys_portstate)(u64);785 void (*f_xgxs_reset)(struct qib_pportdata *);786 /* per chip actions needed for IB Link up/down changes */787 int (*f_ib_updown)(struct qib_pportdata *, int, u64);788 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *);789 /* Read/modify/write of GPIO pins (potentially chip-specific */790 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,791 u32 mask);792 /* Enable writes to config EEPROM (if supported) */793 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);794 /*795 * modify rcvctrl shadow[s] and write to appropriate chip-regs.796 * see above QIB_RCVCTRL_xxx_ENB/DIS for operations.797 * (ctxt == -1) means "all contexts", only meaningful for798 * clearing. Could remove if chip_spec shutdown properly done.799 */800 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op,801 int ctxt);802 /* Read/modify/write sendctrl appropriately for op and port. */803 void (*f_sendctrl)(struct qib_pportdata *, u32 op);804 void (*f_set_intr_state)(struct qib_devdata *, u32);805 void (*f_set_armlaunch)(struct qib_devdata *, u32);806 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);807 int (*f_late_initreg)(struct qib_devdata *);808 int (*f_init_sdma_regs)(struct qib_pportdata *);809 u16 (*f_sdma_gethead)(struct qib_pportdata *);810 int (*f_sdma_busy)(struct qib_pportdata *);811 void (*f_sdma_update_tail)(struct qib_pportdata *, u16);812 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned);813 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned);814 void (*f_sdma_hw_clean_up)(struct qib_pportdata *);815 void (*f_sdma_hw_start_up)(struct qib_pportdata *);816 void (*f_sdma_init_early)(struct qib_pportdata *);817 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);818 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);819 u32 (*f_hdrqempty)(struct qib_ctxtdata *);820 u64 (*f_portcntr)(struct qib_pportdata *, u32);821 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,822 u64 **);823 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,824 char **, u64 **);825 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8);826 void (*f_initvl15_bufs)(struct qib_devdata *);827 void (*f_init_ctxt)(struct qib_ctxtdata *);828 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,829 struct qib_ctxtdata *);830 void (*f_writescratch)(struct qib_devdata *, u32);831 int (*f_tempsense_rd)(struct qib_devdata *, int regnum);832#ifdef CONFIG_INFINIBAND_QIB_DCA833 int (*f_notify_dca)(struct qib_devdata *, unsigned long event);834#endif835 836 char *boardname; /* human readable board info */837 838 /* template for writing TIDs */839 u64 tidtemplate;840 /* value to write to free TIDs */841 u64 tidinvalid;842 843 /* number of registers used for pioavail */844 u32 pioavregs;845 /* device (not port) flags, basically device capabilities */846 u32 flags;847 /* last buffer for user use */848 u32 lastctxt_piobuf;849 850 /* reset value */851 u64 z_int_counter;852 /* percpu intcounter */853 u64 __percpu *int_counter;854 855 /* pio bufs allocated per ctxt */856 u32 pbufsctxt;857 /* if remainder on bufs/ctxt, ctxts < extrabuf get 1 extra */858 u32 ctxts_extrabuf;859 /*860 * number of ctxts configured as max; zero is set to number chip861 * supports, less gives more pio bufs/ctxt, etc.862 */863 u32 cfgctxts;864 /*865 * number of ctxts available for PSM open866 */867 u32 freectxts;868 869 /*870 * hint that we should update pioavailshadow before871 * looking for a PIO buffer872 */873 u32 upd_pio_shadow;874 875 /* internal debugging stats */876 u32 maxpkts_call;877 u32 avgpkts_call;878 u64 nopiobufs;879 880 /* PCI Vendor ID (here for NodeInfo) */881 u16 vendorid;882 /* PCI Device ID (here for NodeInfo) */883 u16 deviceid;884 /* for write combining settings */885 int wc_cookie;886 unsigned long wc_base;887 unsigned long wc_len;888 889 /* shadow copy of struct page *'s for exp tid pages */890 struct page **pageshadow;891 /* shadow copy of dma handles for exp tid pages */892 dma_addr_t *physshadow;893 u64 __iomem *egrtidbase;894 spinlock_t sendctrl_lock; /* protect changes to sendctrl shadow */895 /* around rcd and (user ctxts) ctxt_cnt use (intr vs free) */896 spinlock_t uctxt_lock; /* rcd and user context changes */897 /*898 * per unit status, see also portdata statusp899 * mapped readonly into user processes so they can get unit and900 * IB link status cheaply901 */902 u64 *devstatusp;903 char *freezemsg; /* freeze msg if hw error put chip in freeze */904 u32 freezelen; /* max length of freezemsg */905 /* timer used to prevent stats overflow, error throttling, etc. */906 struct timer_list stats_timer;907 908 /* timer to verify interrupts work, and fallback if possible */909 struct timer_list intrchk_timer;910 unsigned long ureg_align; /* user register alignment */911 912 /*913 * Protects pioavailshadow, pioavailkernel, pio_need_disarm, and914 * pio_writing.915 */916 spinlock_t pioavail_lock;917 /*918 * index of last buffer to optimize search for next919 */920 u32 last_pio;921 /*922 * min kernel pio buffer to optimize search923 */924 u32 min_kernel_pio;925 /*926 * Shadow copies of registers; size indicates read access size.927 * Most of them are readonly, but some are write-only register,928 * where we manipulate the bits in the shadow copy, and then write929 * the shadow copy to qlogic_ib.930 *931 * We deliberately make most of these 32 bits, since they have932 * restricted range. For any that we read, we won't to generate 32933 * bit accesses, since Opteron will generate 2 separate 32 bit HT934 * transactions for a 64 bit read, and we want to avoid unnecessary935 * bus transactions.936 */937 938 /* This is the 64 bit group */939 940 unsigned long pioavailshadow[6];941 /* bitmap of send buffers available for the kernel to use with PIO. */942 unsigned long pioavailkernel[6];943 /* bitmap of send buffers which need to be disarmed. */944 unsigned long pio_need_disarm[3];945 /* bitmap of send buffers which are being written to. */946 unsigned long pio_writing[3];947 /* kr_revision shadow */948 u64 revision;949 /* Base GUID for device (from eeprom, network order) */950 __be64 base_guid;951 952 /*953 * kr_sendpiobufbase value (chip offset of pio buffers), and the954 * base of the 2KB buffer s(user processes only use 2K)955 */956 u64 piobufbase;957 u32 pio2k_bufbase;958 959 /* these are the "32 bit" regs */960 961 /* number of GUIDs in the flash for this interface */962 u32 nguid;963 /*964 * the following two are 32-bit bitmasks, but {test,clear,set}_bit965 * all expect bit fields to be "unsigned long"966 */967 unsigned long rcvctrl; /* shadow per device rcvctrl */968 unsigned long sendctrl; /* shadow per device sendctrl */969 970 /* value we put in kr_rcvhdrcnt */971 u32 rcvhdrcnt;972 /* value we put in kr_rcvhdrsize */973 u32 rcvhdrsize;974 /* value we put in kr_rcvhdrentsize */975 u32 rcvhdrentsize;976 /* kr_ctxtcnt value */977 u32 ctxtcnt;978 /* kr_pagealign value */979 u32 palign;980 /* number of "2KB" PIO buffers */981 u32 piobcnt2k;982 /* size in bytes of "2KB" PIO buffers */983 u32 piosize2k;984 /* max usable size in dwords of a "2KB" PIO buffer before going "4KB" */985 u32 piosize2kmax_dwords;986 /* number of "4KB" PIO buffers */987 u32 piobcnt4k;988 /* size in bytes of "4KB" PIO buffers */989 u32 piosize4k;990 /* kr_rcvegrbase value */991 u32 rcvegrbase;992 /* kr_rcvtidbase value */993 u32 rcvtidbase;994 /* kr_rcvtidcnt value */995 u32 rcvtidcnt;996 /* kr_userregbase */997 u32 uregbase;998 /* shadow the control register contents */999 u32 control;1000 1001 /* chip address space used by 4k pio buffers */1002 u32 align4k;1003 /* size of each rcvegrbuffer */1004 u16 rcvegrbufsize;1005 /* log2 of above */1006 u16 rcvegrbufsize_shift;1007 /* localbus width (1, 2,4,8,16,32) from config space */1008 u32 lbus_width;1009 /* localbus speed in MHz */1010 u32 lbus_speed;1011 int unit; /* unit # of this chip */1012 1013 /* start of CHIP_SPEC move to chipspec, but need code changes */1014 /* low and high portions of MSI capability/vector */1015 u32 msi_lo;1016 /* saved after PCIe init for restore after reset */1017 u32 msi_hi;1018 /* MSI data (vector) saved for restore */1019 u16 msi_data;1020 /* so we can rewrite it after a chip reset */1021 u32 pcibar0;1022 /* so we can rewrite it after a chip reset */1023 u32 pcibar1;1024 u64 rhdrhead_intr_off;1025 1026 /*1027 * ASCII serial number, from flash, large enough for original1028 * all digit strings, and longer QLogic serial number format1029 */1030 u8 serial[16];1031 /* human readable board version */1032 u8 boardversion[96];1033 u8 lbus_info[32]; /* human readable localbus info */1034 /* chip major rev, from qib_revision */1035 u8 majrev;1036 /* chip minor rev, from qib_revision */1037 u8 minrev;1038 1039 /* Misc small ints */1040 /* Number of physical ports available */1041 u8 num_pports;1042 /* Lowest context number which can be used by user processes */1043 u8 first_user_ctxt;1044 u8 n_krcv_queues;1045 u8 qpn_mask;1046 u8 skip_kctxt_mask;1047 1048 u16 rhf_offset; /* offset of RHF within receive header entry */1049 1050 /*1051 * GPIO pins for twsi-connected devices, and device code for eeprom1052 */1053 u8 gpio_sda_num;1054 u8 gpio_scl_num;1055 u8 twsi_eeprom_dev;1056 u8 board_atten;1057 1058 /* Support (including locks) for EEPROM logging of errors and time */1059 /* control access to actual counters, timer */1060 spinlock_t eep_st_lock;1061 /* control high-level access to EEPROM */1062 struct mutex eep_lock;1063 uint64_t traffic_wds;1064 struct qib_diag_client *diag_client;1065 spinlock_t qib_diag_trans_lock; /* protect diag observer ops */1066 struct diag_observer_list_elt *diag_observer_list;1067 1068 u8 psxmitwait_supported;1069 /* cycle length of PS* counters in HW (in picoseconds) */1070 u16 psxmitwait_check_rate;1071 /* high volume overflow errors defered to tasklet */1072 struct tasklet_struct error_tasklet;1073 1074 int assigned_node_id; /* NUMA node closest to HCA */1075};1076 1077/* hol_state values */1078#define QIB_HOL_UP 01079#define QIB_HOL_INIT 11080 1081#define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0)1082#define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1)1083#define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2)1084#define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3)1085#define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4)1086 1087/* operation types for f_txchk_change() */1088#define TXCHK_CHG_TYPE_DIS1 31089#define TXCHK_CHG_TYPE_ENAB1 21090#define TXCHK_CHG_TYPE_KERN 11091#define TXCHK_CHG_TYPE_USER 01092 1093#define QIB_CHASE_TIME msecs_to_jiffies(145)1094#define QIB_CHASE_DIS_TIME msecs_to_jiffies(160)1095 1096/* Private data for file operations */1097struct qib_filedata {1098 struct qib_ctxtdata *rcd;1099 unsigned subctxt;1100 unsigned tidcursor;1101 struct qib_user_sdma_queue *pq;1102 int rec_cpu_num; /* for cpu affinity; -1 if none */1103};1104 1105extern struct xarray qib_dev_table;1106extern struct qib_devdata *qib_lookup(int unit);1107extern u32 qib_cpulist_count;1108extern unsigned long *qib_cpulist;1109extern unsigned qib_cc_table_size;1110 1111int qib_init(struct qib_devdata *, int);1112int init_chip_wc_pat(struct qib_devdata *dd, u32);1113int qib_enable_wc(struct qib_devdata *dd);1114void qib_disable_wc(struct qib_devdata *dd);1115int qib_count_units(int *npresentp, int *nupp);1116int qib_count_active_units(void);1117 1118int qib_cdev_init(int minor, const char *name,1119 const struct file_operations *fops,1120 struct cdev **cdevp, struct device **devp);1121void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp);1122int qib_dev_init(void);1123void qib_dev_cleanup(void);1124 1125int qib_diag_add(struct qib_devdata *);1126void qib_diag_remove(struct qib_devdata *);1127void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64);1128void qib_sdma_update_tail(struct qib_pportdata *, u16); /* hold sdma_lock */1129 1130int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err);1131void qib_bad_intrstatus(struct qib_devdata *);1132void qib_handle_urcv(struct qib_devdata *, u64);1133 1134/* clean up any per-chip chip-specific stuff */1135void qib_chip_cleanup(struct qib_devdata *);1136/* clean up any chip type-specific stuff */1137void qib_chip_done(void);1138 1139/* check to see if we have to force ordering for write combining */1140int qib_unordered_wc(void);1141void qib_pio_copy(void __iomem *to, const void *from, size_t count);1142 1143void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned);1144int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *);1145void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned);1146void qib_cancel_sends(struct qib_pportdata *);1147 1148int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *);1149int qib_setup_eagerbufs(struct qib_ctxtdata *);1150void qib_set_ctxtcnt(struct qib_devdata *);1151int qib_create_ctxts(struct qib_devdata *dd);1152struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32, int);1153int qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8);1154void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *);1155 1156u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *);1157int qib_reset_device(int);1158int qib_wait_linkstate(struct qib_pportdata *, u32, int);1159int qib_set_linkstate(struct qib_pportdata *, u8);1160int qib_set_mtu(struct qib_pportdata *, u16);1161int qib_set_lid(struct qib_pportdata *, u32, u8);1162void qib_hol_down(struct qib_pportdata *);1163void qib_hol_init(struct qib_pportdata *);1164void qib_hol_up(struct qib_pportdata *);1165void qib_hol_event(struct timer_list *);1166void qib_disable_after_error(struct qib_devdata *);1167int qib_set_uevent_bits(struct qib_pportdata *, const int);1168 1169/* for use in system calls, where we want to know device type, etc. */1170#define ctxt_fp(fp) \1171 (((struct qib_filedata *)(fp)->private_data)->rcd)1172#define subctxt_fp(fp) \1173 (((struct qib_filedata *)(fp)->private_data)->subctxt)1174#define tidcursor_fp(fp) \1175 (((struct qib_filedata *)(fp)->private_data)->tidcursor)1176#define user_sdma_queue_fp(fp) \1177 (((struct qib_filedata *)(fp)->private_data)->pq)1178 1179static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd)1180{1181 return ppd->dd;1182}1183 1184static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev)1185{1186 return container_of(dev, struct qib_devdata, verbs_dev);1187}1188 1189static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev)1190{1191 return dd_from_dev(to_idev(ibdev));1192}1193 1194static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp)1195{1196 return container_of(ibp, struct qib_pportdata, ibport_data);1197}1198 1199static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u32 port)1200{1201 struct qib_devdata *dd = dd_from_ibdev(ibdev);1202 u32 pidx = port - 1; /* IB number port from 1, hdw from 0 */1203 1204 WARN_ON(pidx >= dd->num_pports);1205 return &dd->pport[pidx].ibport_data;1206}1207 1208/*1209 * values for dd->flags (_device_ related flags) and1210 */1211#define QIB_HAS_LINK_LATENCY 0x1 /* supports link latency (IB 1.2) */1212#define QIB_INITTED 0x2 /* chip and driver up and initted */1213#define QIB_DOING_RESET 0x4 /* in the middle of doing chip reset */1214#define QIB_PRESENT 0x8 /* chip accesses can be done */1215#define QIB_PIO_FLUSH_WC 0x10 /* Needs Write combining flush for PIO */1216#define QIB_HAS_THRESH_UPDATE 0x401217#define QIB_HAS_SDMA_TIMEOUT 0x801218#define QIB_USE_SPCL_TRIG 0x100 /* SpecialTrigger launch enabled */1219#define QIB_NODMA_RTAIL 0x200 /* rcvhdrtail register DMA enabled */1220#define QIB_HAS_INTX 0x800 /* Supports INTx interrupts */1221#define QIB_HAS_SEND_DMA 0x1000 /* Supports Send DMA */1222#define QIB_HAS_VLSUPP 0x2000 /* Supports multiple VLs; PBC different */1223#define QIB_HAS_HDRSUPP 0x4000 /* Supports header suppression */1224#define QIB_BADINTR 0x8000 /* severe interrupt problems */1225#define QIB_DCA_ENABLED 0x10000 /* Direct Cache Access enabled */1226#define QIB_HAS_QSFP 0x20000 /* device (card instance) has QSFP */1227#define QIB_SHUTDOWN 0x40000 /* device is shutting down */1228 1229/*1230 * values for ppd->lflags (_ib_port_ related flags)1231 */1232#define QIBL_LINKV 0x1 /* IB link state valid */1233#define QIBL_LINKDOWN 0x8 /* IB link is down */1234#define QIBL_LINKINIT 0x10 /* IB link level is up */1235#define QIBL_LINKARMED 0x20 /* IB link is ARMED */1236#define QIBL_LINKACTIVE 0x40 /* IB link is ACTIVE */1237/* leave a gap for more IB-link state */1238#define QIBL_IB_AUTONEG_INPROG 0x1000 /* non-IBTA DDR/QDR neg active */1239#define QIBL_IB_AUTONEG_FAILED 0x2000 /* non-IBTA DDR/QDR neg failed */1240#define QIBL_IB_LINK_DISABLED 0x4000 /* Linkdown-disable forced,1241 * Do not try to bring up */1242#define QIBL_IB_FORCE_NOTIFY 0x8000 /* force notify on next ib change */1243 1244/* IB dword length mask in PBC (lower 11 bits); same for all chips */1245#define QIB_PBC_LENGTH_MASK ((1 << 11) - 1)1246 1247 1248/* ctxt_flag bit offsets */1249 /* waiting for a packet to arrive */1250#define QIB_CTXT_WAITING_RCV 21251 /* master has not finished initializing */1252#define QIB_CTXT_MASTER_UNINIT 41253 /* waiting for an urgent packet to arrive */1254#define QIB_CTXT_WAITING_URG 51255 1256/* free up any allocated data at closes */1257void qib_free_data(struct qib_ctxtdata *dd);1258void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned,1259 u32, struct qib_ctxtdata *);1260struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *,1261 const struct pci_device_id *);1262struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *,1263 const struct pci_device_id *);1264struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *,1265 const struct pci_device_id *);1266void qib_free_devdata(struct qib_devdata *);1267struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra);1268 1269#define QIB_TWSI_NO_DEV 0xFF1270/* Below qib_twsi_ functions must be called with eep_lock held */1271int qib_twsi_reset(struct qib_devdata *dd);1272int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,1273 int len);1274int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,1275 const void *buffer, int len);1276void qib_get_eeprom_info(struct qib_devdata *);1277void qib_dump_lookup_output_queue(struct qib_devdata *);1278void qib_force_pio_avail_update(struct qib_devdata *);1279void qib_clear_symerror_on_linkup(struct timer_list *t);1280 1281/*1282 * Set LED override, only the two LSBs have "public" meaning, but1283 * any non-zero value substitutes them for the Link and LinkTrain1284 * LED states.1285 */1286#define QIB_LED_PHYS 1 /* Physical (linktraining) GREEN LED */1287#define QIB_LED_LOG 2 /* Logical (link) YELLOW LED */1288void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val);1289 1290/* send dma routines */1291int qib_setup_sdma(struct qib_pportdata *);1292void qib_teardown_sdma(struct qib_pportdata *);1293void __qib_sdma_intr(struct qib_pportdata *);1294void qib_sdma_intr(struct qib_pportdata *);1295void qib_user_sdma_send_desc(struct qib_pportdata *dd,1296 struct list_head *pktlist);1297int qib_sdma_verbs_send(struct qib_pportdata *, struct rvt_sge_state *,1298 u32, struct qib_verbs_txreq *);1299/* ppd->sdma_lock should be locked before calling this. */1300int qib_sdma_make_progress(struct qib_pportdata *dd);1301 1302/* must be called under qib_sdma_lock */1303static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd)1304{1305 return ppd->sdma_descq_cnt -1306 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1;1307}1308 1309static inline int __qib_sdma_running(struct qib_pportdata *ppd)1310{1311 return ppd->sdma_state.current_state == qib_sdma_state_s99_running;1312}1313int qib_sdma_running(struct qib_pportdata *);1314void dump_sdma_state(struct qib_pportdata *ppd);1315void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);1316void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);1317 1318/*1319 * number of words used for protocol header if not set by qib_userinit();1320 */1321#define QIB_DFLT_RCVHDRSIZE 91322 1323/*1324 * We need to be able to handle an IB header of at least 24 dwords.1325 * We need the rcvhdrq large enough to handle largest IB header, but1326 * still have room for a 2KB MTU standard IB packet.1327 * Additionally, some processor/memory controller combinations1328 * benefit quite strongly from having the DMA'ed data be cacheline1329 * aligned and a cacheline multiple, so we set the size to 32 dwords1330 * (2 64-byte primary cachelines for pretty much all processors of1331 * interest). The alignment hurts nothing, other than using somewhat1332 * more memory.1333 */1334#define QIB_RCVHDR_ENTSIZE 321335 1336int qib_get_user_pages(unsigned long, size_t, struct page **);1337void qib_release_user_pages(struct page **, size_t);1338int qib_eeprom_read(struct qib_devdata *, u8, void *, int);1339int qib_eeprom_write(struct qib_devdata *, u8, const void *, int);1340u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32);1341void qib_sendbuf_done(struct qib_devdata *, unsigned);1342 1343static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd)1344{1345 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;1346}1347 1348static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd)1349{1350 /*1351 * volatile because it's a DMA target from the chip, routine is1352 * inlined, and don't want register caching or reordering.1353 */1354 return (u32) le64_to_cpu(1355 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr)); /* DMA'ed */1356}1357 1358/*1359 * sysfs interface.1360 */1361 1362extern const struct attribute_group qib_attr_group;1363extern const struct attribute_group *qib_attr_port_groups[];1364 1365int qib_device_create(struct qib_devdata *);1366void qib_device_remove(struct qib_devdata *);1367 1368/* Hook for sysfs read of QSFP */1369extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len);1370 1371int __init qib_init_qibfs(void);1372int __exit qib_exit_qibfs(void);1373 1374int qibfs_add(struct qib_devdata *);1375int qibfs_remove(struct qib_devdata *);1376 1377int qib_pcie_init(struct pci_dev *, const struct pci_device_id *);1378int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,1379 const struct pci_device_id *);1380void qib_pcie_ddcleanup(struct qib_devdata *);1381int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent);1382void qib_free_irq(struct qib_devdata *dd);1383int qib_reinit_intr(struct qib_devdata *dd);1384void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);1385void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);1386/* interrupts for device */1387u64 qib_int_counter(struct qib_devdata *);1388/* interrupt for all devices */1389u64 qib_sps_ints(void);1390 1391/*1392 * dma_addr wrappers - all 0's invalid for hw1393 */1394int qib_map_page(struct pci_dev *d, struct page *p, dma_addr_t *daddr);1395struct pci_dev *qib_get_pci_dev(struct rvt_dev_info *rdi);1396 1397/*1398 * Flush write combining store buffers (if present) and perform a write1399 * barrier.1400 */1401static inline void qib_flush_wc(void)1402{1403#if defined(CONFIG_X86_64)1404 asm volatile("sfence" : : : "memory");1405#else1406 wmb(); /* no reorder around wc flush */1407#endif1408}1409 1410/* global module parameter variables */1411extern unsigned qib_ibmtu;1412extern ushort qib_cfgctxts;1413extern ushort qib_num_cfg_vls;1414extern ushort qib_mini_init; /* If set, do few (ideally 0) writes to chip */1415extern unsigned qib_n_krcv_queues;1416extern unsigned qib_sdma_fetch_arb;1417extern unsigned qib_compat_ddr_negotiate;1418extern int qib_special_trigger;1419extern unsigned qib_numa_aware;1420 1421extern struct mutex qib_mutex;1422 1423/* Number of seconds before our card status check... */1424#define STATUS_TIMEOUT 601425 1426#define QIB_DRV_NAME "ib_qib"1427#define QIB_USER_MINOR_BASE 01428#define QIB_TRACE_MINOR 1271429#define QIB_DIAGPKT_MINOR 1281430#define QIB_DIAG_MINOR_BASE 1291431#define QIB_NMINORS 2551432 1433#define PCI_VENDOR_ID_PATHSCALE 0x1fc11434#define PCI_VENDOR_ID_QLOGIC 0x10771435#define PCI_DEVICE_ID_QLOGIC_IB_6120 0x101436#define PCI_DEVICE_ID_QLOGIC_IB_7220 0x72201437#define PCI_DEVICE_ID_QLOGIC_IB_7322 0x73221438 1439/*1440 * qib_early_err is used (only!) to print early errors before devdata is1441 * allocated, or when dd->pcidev may not be valid, and at the tail end of1442 * cleanup when devdata may have been freed, etc. qib_dev_porterr is1443 * the same as qib_dev_err, but is used when the message really needs1444 * the IB port# to be definitive as to what's happening..1445 * All of these go to the trace log, and the trace log entry is done1446 * first to avoid possible serial port delays from printk.1447 */1448#define qib_early_err(dev, fmt, ...) \1449 dev_err(dev, fmt, ##__VA_ARGS__)1450 1451#define qib_dev_err(dd, fmt, ...) \1452 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \1453 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)1454 1455#define qib_dev_warn(dd, fmt, ...) \1456 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \1457 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)1458 1459#define qib_dev_porterr(dd, port, fmt, ...) \1460 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \1461 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (dd)->unit, (port), \1462 ##__VA_ARGS__)1463 1464#define qib_devinfo(pcidev, fmt, ...) \1465 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__)1466 1467/*1468 * this is used for formatting hw error messages...1469 */1470struct qib_hwerror_msgs {1471 u64 mask;1472 const char *msg;1473 size_t sz;1474};1475 1476#define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b }1477 1478/* in qib_intr.c... */1479void qib_format_hwerrors(u64 hwerrs,1480 const struct qib_hwerror_msgs *hwerrmsgs,1481 size_t nhwerrmsgs, char *msg, size_t lmsg);1482 1483void qib_stop_send_queue(struct rvt_qp *qp);1484void qib_quiesce_qp(struct rvt_qp *qp);1485void qib_flush_qp_waiters(struct rvt_qp *qp);1486int qib_mtu_to_path_mtu(u32 mtu);1487u32 qib_mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu);1488void qib_notify_error_qp(struct rvt_qp *qp);1489int qib_get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp,1490 struct ib_qp_attr *attr);1491 1492#endif /* _QIB_KERNEL_H */1493