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1/*2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.3 *4 * This software is available to you under a choice of one of two5 * licenses. You may choose to be licensed under the terms of the GNU6 * General Public License (GPL) Version 2, available from the file7 * COPYING in the main directory of this source tree, or the8 * OpenIB.org BSD license below:9 *10 * Redistribution and use in source and binary forms, with or11 * without modification, are permitted provided that the following12 * conditions are met:13 *14 * - Redistributions of source code must retain the above15 * copyright notice, this list of conditions and the following16 * disclaimer.17 *18 * - Redistributions in binary form must reproduce the above19 * copyright notice, this list of conditions and the following20 * disclaimer in the documentation and/or other materials21 * provided with the distribution.22 *23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE30 * SOFTWARE.31 */32 33/* This file is mechanically generated from RTL. Any hand-edits will be lost! */34 35#define QIB_6120_Revision_OFFS 0x036#define QIB_6120_Revision_R_Simulator_LSB 0x3F37#define QIB_6120_Revision_R_Simulator_RMASK 0x138#define QIB_6120_Revision_Reserved_LSB 0x2839#define QIB_6120_Revision_Reserved_RMASK 0x7FFFFF40#define QIB_6120_Revision_BoardID_LSB 0x2041#define QIB_6120_Revision_BoardID_RMASK 0xFF42#define QIB_6120_Revision_R_SW_LSB 0x1843#define QIB_6120_Revision_R_SW_RMASK 0xFF44#define QIB_6120_Revision_R_Arch_LSB 0x1045#define QIB_6120_Revision_R_Arch_RMASK 0xFF46#define QIB_6120_Revision_R_ChipRevMajor_LSB 0x847#define QIB_6120_Revision_R_ChipRevMajor_RMASK 0xFF48#define QIB_6120_Revision_R_ChipRevMinor_LSB 0x049#define QIB_6120_Revision_R_ChipRevMinor_RMASK 0xFF50 51#define QIB_6120_Control_OFFS 0x852#define QIB_6120_Control_TxLatency_LSB 0x453#define QIB_6120_Control_TxLatency_RMASK 0x154#define QIB_6120_Control_PCIERetryBufDiagEn_LSB 0x355#define QIB_6120_Control_PCIERetryBufDiagEn_RMASK 0x156#define QIB_6120_Control_LinkEn_LSB 0x257#define QIB_6120_Control_LinkEn_RMASK 0x158#define QIB_6120_Control_FreezeMode_LSB 0x159#define QIB_6120_Control_FreezeMode_RMASK 0x160#define QIB_6120_Control_SyncReset_LSB 0x061#define QIB_6120_Control_SyncReset_RMASK 0x162 63#define QIB_6120_PageAlign_OFFS 0x1064 65#define QIB_6120_PortCnt_OFFS 0x1866 67#define QIB_6120_SendRegBase_OFFS 0x3068 69#define QIB_6120_UserRegBase_OFFS 0x3870 71#define QIB_6120_CntrRegBase_OFFS 0x4072 73#define QIB_6120_Scratch_OFFS 0x4874#define QIB_6120_Scratch_TopHalf_LSB 0x2075#define QIB_6120_Scratch_TopHalf_RMASK 0xFFFFFFFF76#define QIB_6120_Scratch_BottomHalf_LSB 0x077#define QIB_6120_Scratch_BottomHalf_RMASK 0xFFFFFFFF78 79#define QIB_6120_IntBlocked_OFFS 0x6080#define QIB_6120_IntBlocked_ErrorIntBlocked_LSB 0x1F81#define QIB_6120_IntBlocked_ErrorIntBlocked_RMASK 0x182#define QIB_6120_IntBlocked_PioSetIntBlocked_LSB 0x1E83#define QIB_6120_IntBlocked_PioSetIntBlocked_RMASK 0x184#define QIB_6120_IntBlocked_PioBufAvailIntBlocked_LSB 0x1D85#define QIB_6120_IntBlocked_PioBufAvailIntBlocked_RMASK 0x186#define QIB_6120_IntBlocked_assertGPIOIntBlocked_LSB 0x1C87#define QIB_6120_IntBlocked_assertGPIOIntBlocked_RMASK 0x188#define QIB_6120_IntBlocked_Reserved_LSB 0xF89#define QIB_6120_IntBlocked_Reserved_RMASK 0x1FFF90#define QIB_6120_IntBlocked_RcvAvail4IntBlocked_LSB 0x1091#define QIB_6120_IntBlocked_RcvAvail4IntBlocked_RMASK 0x192#define QIB_6120_IntBlocked_RcvAvail3IntBlocked_LSB 0xF93#define QIB_6120_IntBlocked_RcvAvail3IntBlocked_RMASK 0x194#define QIB_6120_IntBlocked_RcvAvail2IntBlocked_LSB 0xE95#define QIB_6120_IntBlocked_RcvAvail2IntBlocked_RMASK 0x196#define QIB_6120_IntBlocked_RcvAvail1IntBlocked_LSB 0xD97#define QIB_6120_IntBlocked_RcvAvail1IntBlocked_RMASK 0x198#define QIB_6120_IntBlocked_RcvAvail0IntBlocked_LSB 0xC99#define QIB_6120_IntBlocked_RcvAvail0IntBlocked_RMASK 0x1100#define QIB_6120_IntBlocked_Reserved1_LSB 0x5101#define QIB_6120_IntBlocked_Reserved1_RMASK 0x7F102#define QIB_6120_IntBlocked_RcvUrg4IntBlocked_LSB 0x4103#define QIB_6120_IntBlocked_RcvUrg4IntBlocked_RMASK 0x1104#define QIB_6120_IntBlocked_RcvUrg3IntBlocked_LSB 0x3105#define QIB_6120_IntBlocked_RcvUrg3IntBlocked_RMASK 0x1106#define QIB_6120_IntBlocked_RcvUrg2IntBlocked_LSB 0x2107#define QIB_6120_IntBlocked_RcvUrg2IntBlocked_RMASK 0x1108#define QIB_6120_IntBlocked_RcvUrg1IntBlocked_LSB 0x1109#define QIB_6120_IntBlocked_RcvUrg1IntBlocked_RMASK 0x1110#define QIB_6120_IntBlocked_RcvUrg0IntBlocked_LSB 0x0111#define QIB_6120_IntBlocked_RcvUrg0IntBlocked_RMASK 0x1112 113#define QIB_6120_IntMask_OFFS 0x68114#define QIB_6120_IntMask_ErrorIntMask_LSB 0x1F115#define QIB_6120_IntMask_ErrorIntMask_RMASK 0x1116#define QIB_6120_IntMask_PioSetIntMask_LSB 0x1E117#define QIB_6120_IntMask_PioSetIntMask_RMASK 0x1118#define QIB_6120_IntMask_PioBufAvailIntMask_LSB 0x1D119#define QIB_6120_IntMask_PioBufAvailIntMask_RMASK 0x1120#define QIB_6120_IntMask_assertGPIOIntMask_LSB 0x1C121#define QIB_6120_IntMask_assertGPIOIntMask_RMASK 0x1122#define QIB_6120_IntMask_Reserved_LSB 0x11123#define QIB_6120_IntMask_Reserved_RMASK 0x7FF124#define QIB_6120_IntMask_RcvAvail4IntMask_LSB 0x10125#define QIB_6120_IntMask_RcvAvail4IntMask_RMASK 0x1126#define QIB_6120_IntMask_RcvAvail3IntMask_LSB 0xF127#define QIB_6120_IntMask_RcvAvail3IntMask_RMASK 0x1128#define QIB_6120_IntMask_RcvAvail2IntMask_LSB 0xE129#define QIB_6120_IntMask_RcvAvail2IntMask_RMASK 0x1130#define QIB_6120_IntMask_RcvAvail1IntMask_LSB 0xD131#define QIB_6120_IntMask_RcvAvail1IntMask_RMASK 0x1132#define QIB_6120_IntMask_RcvAvail0IntMask_LSB 0xC133#define QIB_6120_IntMask_RcvAvail0IntMask_RMASK 0x1134#define QIB_6120_IntMask_Reserved1_LSB 0x5135#define QIB_6120_IntMask_Reserved1_RMASK 0x7F136#define QIB_6120_IntMask_RcvUrg4IntMask_LSB 0x4137#define QIB_6120_IntMask_RcvUrg4IntMask_RMASK 0x1138#define QIB_6120_IntMask_RcvUrg3IntMask_LSB 0x3139#define QIB_6120_IntMask_RcvUrg3IntMask_RMASK 0x1140#define QIB_6120_IntMask_RcvUrg2IntMask_LSB 0x2141#define QIB_6120_IntMask_RcvUrg2IntMask_RMASK 0x1142#define QIB_6120_IntMask_RcvUrg1IntMask_LSB 0x1143#define QIB_6120_IntMask_RcvUrg1IntMask_RMASK 0x1144#define QIB_6120_IntMask_RcvUrg0IntMask_LSB 0x0145#define QIB_6120_IntMask_RcvUrg0IntMask_RMASK 0x1146 147#define QIB_6120_IntStatus_OFFS 0x70148#define QIB_6120_IntStatus_Error_LSB 0x1F149#define QIB_6120_IntStatus_Error_RMASK 0x1150#define QIB_6120_IntStatus_PioSent_LSB 0x1E151#define QIB_6120_IntStatus_PioSent_RMASK 0x1152#define QIB_6120_IntStatus_PioBufAvail_LSB 0x1D153#define QIB_6120_IntStatus_PioBufAvail_RMASK 0x1154#define QIB_6120_IntStatus_assertGPIO_LSB 0x1C155#define QIB_6120_IntStatus_assertGPIO_RMASK 0x1156#define QIB_6120_IntStatus_Reserved_LSB 0xF157#define QIB_6120_IntStatus_Reserved_RMASK 0x1FFF158#define QIB_6120_IntStatus_RcvAvail4_LSB 0x10159#define QIB_6120_IntStatus_RcvAvail4_RMASK 0x1160#define QIB_6120_IntStatus_RcvAvail3_LSB 0xF161#define QIB_6120_IntStatus_RcvAvail3_RMASK 0x1162#define QIB_6120_IntStatus_RcvAvail2_LSB 0xE163#define QIB_6120_IntStatus_RcvAvail2_RMASK 0x1164#define QIB_6120_IntStatus_RcvAvail1_LSB 0xD165#define QIB_6120_IntStatus_RcvAvail1_RMASK 0x1166#define QIB_6120_IntStatus_RcvAvail0_LSB 0xC167#define QIB_6120_IntStatus_RcvAvail0_RMASK 0x1168#define QIB_6120_IntStatus_Reserved1_LSB 0x5169#define QIB_6120_IntStatus_Reserved1_RMASK 0x7F170#define QIB_6120_IntStatus_RcvUrg4_LSB 0x4171#define QIB_6120_IntStatus_RcvUrg4_RMASK 0x1172#define QIB_6120_IntStatus_RcvUrg3_LSB 0x3173#define QIB_6120_IntStatus_RcvUrg3_RMASK 0x1174#define QIB_6120_IntStatus_RcvUrg2_LSB 0x2175#define QIB_6120_IntStatus_RcvUrg2_RMASK 0x1176#define QIB_6120_IntStatus_RcvUrg1_LSB 0x1177#define QIB_6120_IntStatus_RcvUrg1_RMASK 0x1178#define QIB_6120_IntStatus_RcvUrg0_LSB 0x0179#define QIB_6120_IntStatus_RcvUrg0_RMASK 0x1180 181#define QIB_6120_IntClear_OFFS 0x78182#define QIB_6120_IntClear_ErrorIntClear_LSB 0x1F183#define QIB_6120_IntClear_ErrorIntClear_RMASK 0x1184#define QIB_6120_IntClear_PioSetIntClear_LSB 0x1E185#define QIB_6120_IntClear_PioSetIntClear_RMASK 0x1186#define QIB_6120_IntClear_PioBufAvailIntClear_LSB 0x1D187#define QIB_6120_IntClear_PioBufAvailIntClear_RMASK 0x1188#define QIB_6120_IntClear_assertGPIOIntClear_LSB 0x1C189#define QIB_6120_IntClear_assertGPIOIntClear_RMASK 0x1190#define QIB_6120_IntClear_Reserved_LSB 0xF191#define QIB_6120_IntClear_Reserved_RMASK 0x1FFF192#define QIB_6120_IntClear_RcvAvail4IntClear_LSB 0x10193#define QIB_6120_IntClear_RcvAvail4IntClear_RMASK 0x1194#define QIB_6120_IntClear_RcvAvail3IntClear_LSB 0xF195#define QIB_6120_IntClear_RcvAvail3IntClear_RMASK 0x1196#define QIB_6120_IntClear_RcvAvail2IntClear_LSB 0xE197#define QIB_6120_IntClear_RcvAvail2IntClear_RMASK 0x1198#define QIB_6120_IntClear_RcvAvail1IntClear_LSB 0xD199#define QIB_6120_IntClear_RcvAvail1IntClear_RMASK 0x1200#define QIB_6120_IntClear_RcvAvail0IntClear_LSB 0xC201#define QIB_6120_IntClear_RcvAvail0IntClear_RMASK 0x1202#define QIB_6120_IntClear_Reserved1_LSB 0x5203#define QIB_6120_IntClear_Reserved1_RMASK 0x7F204#define QIB_6120_IntClear_RcvUrg4IntClear_LSB 0x4205#define QIB_6120_IntClear_RcvUrg4IntClear_RMASK 0x1206#define QIB_6120_IntClear_RcvUrg3IntClear_LSB 0x3207#define QIB_6120_IntClear_RcvUrg3IntClear_RMASK 0x1208#define QIB_6120_IntClear_RcvUrg2IntClear_LSB 0x2209#define QIB_6120_IntClear_RcvUrg2IntClear_RMASK 0x1210#define QIB_6120_IntClear_RcvUrg1IntClear_LSB 0x1211#define QIB_6120_IntClear_RcvUrg1IntClear_RMASK 0x1212#define QIB_6120_IntClear_RcvUrg0IntClear_LSB 0x0213#define QIB_6120_IntClear_RcvUrg0IntClear_RMASK 0x1214 215#define QIB_6120_ErrMask_OFFS 0x80216#define QIB_6120_ErrMask_Reserved_LSB 0x34217#define QIB_6120_ErrMask_Reserved_RMASK 0xFFF218#define QIB_6120_ErrMask_HardwareErrMask_LSB 0x33219#define QIB_6120_ErrMask_HardwareErrMask_RMASK 0x1220#define QIB_6120_ErrMask_ResetNegatedMask_LSB 0x32221#define QIB_6120_ErrMask_ResetNegatedMask_RMASK 0x1222#define QIB_6120_ErrMask_InvalidAddrErrMask_LSB 0x31223#define QIB_6120_ErrMask_InvalidAddrErrMask_RMASK 0x1224#define QIB_6120_ErrMask_IBStatusChangedMask_LSB 0x30225#define QIB_6120_ErrMask_IBStatusChangedMask_RMASK 0x1226#define QIB_6120_ErrMask_Reserved1_LSB 0x26227#define QIB_6120_ErrMask_Reserved1_RMASK 0x3FF228#define QIB_6120_ErrMask_SendUnsupportedVLErrMask_LSB 0x25229#define QIB_6120_ErrMask_SendUnsupportedVLErrMask_RMASK 0x1230#define QIB_6120_ErrMask_SendUnexpectedPktNumErrMask_LSB 0x24231#define QIB_6120_ErrMask_SendUnexpectedPktNumErrMask_RMASK 0x1232#define QIB_6120_ErrMask_SendPioArmLaunchErrMask_LSB 0x23233#define QIB_6120_ErrMask_SendPioArmLaunchErrMask_RMASK 0x1234#define QIB_6120_ErrMask_SendDroppedDataPktErrMask_LSB 0x22235#define QIB_6120_ErrMask_SendDroppedDataPktErrMask_RMASK 0x1236#define QIB_6120_ErrMask_SendDroppedSmpPktErrMask_LSB 0x21237#define QIB_6120_ErrMask_SendDroppedSmpPktErrMask_RMASK 0x1238#define QIB_6120_ErrMask_SendPktLenErrMask_LSB 0x20239#define QIB_6120_ErrMask_SendPktLenErrMask_RMASK 0x1240#define QIB_6120_ErrMask_SendUnderRunErrMask_LSB 0x1F241#define QIB_6120_ErrMask_SendUnderRunErrMask_RMASK 0x1242#define QIB_6120_ErrMask_SendMaxPktLenErrMask_LSB 0x1E243#define QIB_6120_ErrMask_SendMaxPktLenErrMask_RMASK 0x1244#define QIB_6120_ErrMask_SendMinPktLenErrMask_LSB 0x1D245#define QIB_6120_ErrMask_SendMinPktLenErrMask_RMASK 0x1246#define QIB_6120_ErrMask_Reserved2_LSB 0x12247#define QIB_6120_ErrMask_Reserved2_RMASK 0x7FF248#define QIB_6120_ErrMask_RcvIBLostLinkErrMask_LSB 0x11249#define QIB_6120_ErrMask_RcvIBLostLinkErrMask_RMASK 0x1250#define QIB_6120_ErrMask_RcvHdrErrMask_LSB 0x10251#define QIB_6120_ErrMask_RcvHdrErrMask_RMASK 0x1252#define QIB_6120_ErrMask_RcvHdrLenErrMask_LSB 0xF253#define QIB_6120_ErrMask_RcvHdrLenErrMask_RMASK 0x1254#define QIB_6120_ErrMask_RcvBadTidErrMask_LSB 0xE255#define QIB_6120_ErrMask_RcvBadTidErrMask_RMASK 0x1256#define QIB_6120_ErrMask_RcvHdrFullErrMask_LSB 0xD257#define QIB_6120_ErrMask_RcvHdrFullErrMask_RMASK 0x1258#define QIB_6120_ErrMask_RcvEgrFullErrMask_LSB 0xC259#define QIB_6120_ErrMask_RcvEgrFullErrMask_RMASK 0x1260#define QIB_6120_ErrMask_RcvBadVersionErrMask_LSB 0xB261#define QIB_6120_ErrMask_RcvBadVersionErrMask_RMASK 0x1262#define QIB_6120_ErrMask_RcvIBFlowErrMask_LSB 0xA263#define QIB_6120_ErrMask_RcvIBFlowErrMask_RMASK 0x1264#define QIB_6120_ErrMask_RcvEBPErrMask_LSB 0x9265#define QIB_6120_ErrMask_RcvEBPErrMask_RMASK 0x1266#define QIB_6120_ErrMask_RcvUnsupportedVLErrMask_LSB 0x8267#define QIB_6120_ErrMask_RcvUnsupportedVLErrMask_RMASK 0x1268#define QIB_6120_ErrMask_RcvUnexpectedCharErrMask_LSB 0x7269#define QIB_6120_ErrMask_RcvUnexpectedCharErrMask_RMASK 0x1270#define QIB_6120_ErrMask_RcvShortPktLenErrMask_LSB 0x6271#define QIB_6120_ErrMask_RcvShortPktLenErrMask_RMASK 0x1272#define QIB_6120_ErrMask_RcvLongPktLenErrMask_LSB 0x5273#define QIB_6120_ErrMask_RcvLongPktLenErrMask_RMASK 0x1274#define QIB_6120_ErrMask_RcvMaxPktLenErrMask_LSB 0x4275#define QIB_6120_ErrMask_RcvMaxPktLenErrMask_RMASK 0x1276#define QIB_6120_ErrMask_RcvMinPktLenErrMask_LSB 0x3277#define QIB_6120_ErrMask_RcvMinPktLenErrMask_RMASK 0x1278#define QIB_6120_ErrMask_RcvICRCErrMask_LSB 0x2279#define QIB_6120_ErrMask_RcvICRCErrMask_RMASK 0x1280#define QIB_6120_ErrMask_RcvVCRCErrMask_LSB 0x1281#define QIB_6120_ErrMask_RcvVCRCErrMask_RMASK 0x1282#define QIB_6120_ErrMask_RcvFormatErrMask_LSB 0x0283#define QIB_6120_ErrMask_RcvFormatErrMask_RMASK 0x1284 285#define QIB_6120_ErrStatus_OFFS 0x88286#define QIB_6120_ErrStatus_Reserved_LSB 0x34287#define QIB_6120_ErrStatus_Reserved_RMASK 0xFFF288#define QIB_6120_ErrStatus_HardwareErr_LSB 0x33289#define QIB_6120_ErrStatus_HardwareErr_RMASK 0x1290#define QIB_6120_ErrStatus_ResetNegated_LSB 0x32291#define QIB_6120_ErrStatus_ResetNegated_RMASK 0x1292#define QIB_6120_ErrStatus_InvalidAddrErr_LSB 0x31293#define QIB_6120_ErrStatus_InvalidAddrErr_RMASK 0x1294#define QIB_6120_ErrStatus_IBStatusChanged_LSB 0x30295#define QIB_6120_ErrStatus_IBStatusChanged_RMASK 0x1296#define QIB_6120_ErrStatus_Reserved1_LSB 0x26297#define QIB_6120_ErrStatus_Reserved1_RMASK 0x3FF298#define QIB_6120_ErrStatus_SendUnsupportedVLErr_LSB 0x25299#define QIB_6120_ErrStatus_SendUnsupportedVLErr_RMASK 0x1300#define QIB_6120_ErrStatus_SendUnexpectedPktNumErr_LSB 0x24301#define QIB_6120_ErrStatus_SendUnexpectedPktNumErr_RMASK 0x1302#define QIB_6120_ErrStatus_SendPioArmLaunchErr_LSB 0x23303#define QIB_6120_ErrStatus_SendPioArmLaunchErr_RMASK 0x1304#define QIB_6120_ErrStatus_SendDroppedDataPktErr_LSB 0x22305#define QIB_6120_ErrStatus_SendDroppedDataPktErr_RMASK 0x1306#define QIB_6120_ErrStatus_SendDroppedSmpPktErr_LSB 0x21307#define QIB_6120_ErrStatus_SendDroppedSmpPktErr_RMASK 0x1308#define QIB_6120_ErrStatus_SendPktLenErr_LSB 0x20309#define QIB_6120_ErrStatus_SendPktLenErr_RMASK 0x1310#define QIB_6120_ErrStatus_SendUnderRunErr_LSB 0x1F311#define QIB_6120_ErrStatus_SendUnderRunErr_RMASK 0x1312#define QIB_6120_ErrStatus_SendMaxPktLenErr_LSB 0x1E313#define QIB_6120_ErrStatus_SendMaxPktLenErr_RMASK 0x1314#define QIB_6120_ErrStatus_SendMinPktLenErr_LSB 0x1D315#define QIB_6120_ErrStatus_SendMinPktLenErr_RMASK 0x1316#define QIB_6120_ErrStatus_Reserved2_LSB 0x12317#define QIB_6120_ErrStatus_Reserved2_RMASK 0x7FF318#define QIB_6120_ErrStatus_RcvIBLostLinkErr_LSB 0x11319#define QIB_6120_ErrStatus_RcvIBLostLinkErr_RMASK 0x1320#define QIB_6120_ErrStatus_RcvHdrErr_LSB 0x10321#define QIB_6120_ErrStatus_RcvHdrErr_RMASK 0x1322#define QIB_6120_ErrStatus_RcvHdrLenErr_LSB 0xF323#define QIB_6120_ErrStatus_RcvHdrLenErr_RMASK 0x1324#define QIB_6120_ErrStatus_RcvBadTidErr_LSB 0xE325#define QIB_6120_ErrStatus_RcvBadTidErr_RMASK 0x1326#define QIB_6120_ErrStatus_RcvHdrFullErr_LSB 0xD327#define QIB_6120_ErrStatus_RcvHdrFullErr_RMASK 0x1328#define QIB_6120_ErrStatus_RcvEgrFullErr_LSB 0xC329#define QIB_6120_ErrStatus_RcvEgrFullErr_RMASK 0x1330#define QIB_6120_ErrStatus_RcvBadVersionErr_LSB 0xB331#define QIB_6120_ErrStatus_RcvBadVersionErr_RMASK 0x1332#define QIB_6120_ErrStatus_RcvIBFlowErr_LSB 0xA333#define QIB_6120_ErrStatus_RcvIBFlowErr_RMASK 0x1334#define QIB_6120_ErrStatus_RcvEBPErr_LSB 0x9335#define QIB_6120_ErrStatus_RcvEBPErr_RMASK 0x1336#define QIB_6120_ErrStatus_RcvUnsupportedVLErr_LSB 0x8337#define QIB_6120_ErrStatus_RcvUnsupportedVLErr_RMASK 0x1338#define QIB_6120_ErrStatus_RcvUnexpectedCharErr_LSB 0x7339#define QIB_6120_ErrStatus_RcvUnexpectedCharErr_RMASK 0x1340#define QIB_6120_ErrStatus_RcvShortPktLenErr_LSB 0x6341#define QIB_6120_ErrStatus_RcvShortPktLenErr_RMASK 0x1342#define QIB_6120_ErrStatus_RcvLongPktLenErr_LSB 0x5343#define QIB_6120_ErrStatus_RcvLongPktLenErr_RMASK 0x1344#define QIB_6120_ErrStatus_RcvMaxPktLenErr_LSB 0x4345#define QIB_6120_ErrStatus_RcvMaxPktLenErr_RMASK 0x1346#define QIB_6120_ErrStatus_RcvMinPktLenErr_LSB 0x3347#define QIB_6120_ErrStatus_RcvMinPktLenErr_RMASK 0x1348#define QIB_6120_ErrStatus_RcvICRCErr_LSB 0x2349#define QIB_6120_ErrStatus_RcvICRCErr_RMASK 0x1350#define QIB_6120_ErrStatus_RcvVCRCErr_LSB 0x1351#define QIB_6120_ErrStatus_RcvVCRCErr_RMASK 0x1352#define QIB_6120_ErrStatus_RcvFormatErr_LSB 0x0353#define QIB_6120_ErrStatus_RcvFormatErr_RMASK 0x1354 355#define QIB_6120_ErrClear_OFFS 0x90356#define QIB_6120_ErrClear_Reserved_LSB 0x34357#define QIB_6120_ErrClear_Reserved_RMASK 0xFFF358#define QIB_6120_ErrClear_HardwareErrClear_LSB 0x33359#define QIB_6120_ErrClear_HardwareErrClear_RMASK 0x1360#define QIB_6120_ErrClear_ResetNegatedClear_LSB 0x32361#define QIB_6120_ErrClear_ResetNegatedClear_RMASK 0x1362#define QIB_6120_ErrClear_InvalidAddrErrClear_LSB 0x31363#define QIB_6120_ErrClear_InvalidAddrErrClear_RMASK 0x1364#define QIB_6120_ErrClear_IBStatusChangedClear_LSB 0x30365#define QIB_6120_ErrClear_IBStatusChangedClear_RMASK 0x1366#define QIB_6120_ErrClear_Reserved1_LSB 0x26367#define QIB_6120_ErrClear_Reserved1_RMASK 0x3FF368#define QIB_6120_ErrClear_SendUnsupportedVLErrClear_LSB 0x25369#define QIB_6120_ErrClear_SendUnsupportedVLErrClear_RMASK 0x1370#define QIB_6120_ErrClear_SendUnexpectedPktNumErrClear_LSB 0x24371#define QIB_6120_ErrClear_SendUnexpectedPktNumErrClear_RMASK 0x1372#define QIB_6120_ErrClear_SendPioArmLaunchErrClear_LSB 0x23373#define QIB_6120_ErrClear_SendPioArmLaunchErrClear_RMASK 0x1374#define QIB_6120_ErrClear_SendDroppedDataPktErrClear_LSB 0x22375#define QIB_6120_ErrClear_SendDroppedDataPktErrClear_RMASK 0x1376#define QIB_6120_ErrClear_SendDroppedSmpPktErrClear_LSB 0x21377#define QIB_6120_ErrClear_SendDroppedSmpPktErrClear_RMASK 0x1378#define QIB_6120_ErrClear_SendPktLenErrClear_LSB 0x20379#define QIB_6120_ErrClear_SendPktLenErrClear_RMASK 0x1380#define QIB_6120_ErrClear_SendUnderRunErrClear_LSB 0x1F381#define QIB_6120_ErrClear_SendUnderRunErrClear_RMASK 0x1382#define QIB_6120_ErrClear_SendMaxPktLenErrClear_LSB 0x1E383#define QIB_6120_ErrClear_SendMaxPktLenErrClear_RMASK 0x1384#define QIB_6120_ErrClear_SendMinPktLenErrClear_LSB 0x1D385#define QIB_6120_ErrClear_SendMinPktLenErrClear_RMASK 0x1386#define QIB_6120_ErrClear_Reserved2_LSB 0x12387#define QIB_6120_ErrClear_Reserved2_RMASK 0x7FF388#define QIB_6120_ErrClear_RcvIBLostLinkErrClear_LSB 0x11389#define QIB_6120_ErrClear_RcvIBLostLinkErrClear_RMASK 0x1390#define QIB_6120_ErrClear_RcvHdrErrClear_LSB 0x10391#define QIB_6120_ErrClear_RcvHdrErrClear_RMASK 0x1392#define QIB_6120_ErrClear_RcvHdrLenErrClear_LSB 0xF393#define QIB_6120_ErrClear_RcvHdrLenErrClear_RMASK 0x1394#define QIB_6120_ErrClear_RcvBadTidErrClear_LSB 0xE395#define QIB_6120_ErrClear_RcvBadTidErrClear_RMASK 0x1396#define QIB_6120_ErrClear_RcvHdrFullErrClear_LSB 0xD397#define QIB_6120_ErrClear_RcvHdrFullErrClear_RMASK 0x1398#define QIB_6120_ErrClear_RcvEgrFullErrClear_LSB 0xC399#define QIB_6120_ErrClear_RcvEgrFullErrClear_RMASK 0x1400#define QIB_6120_ErrClear_RcvBadVersionErrClear_LSB 0xB401#define QIB_6120_ErrClear_RcvBadVersionErrClear_RMASK 0x1402#define QIB_6120_ErrClear_RcvIBFlowErrClear_LSB 0xA403#define QIB_6120_ErrClear_RcvIBFlowErrClear_RMASK 0x1404#define QIB_6120_ErrClear_RcvEBPErrClear_LSB 0x9405#define QIB_6120_ErrClear_RcvEBPErrClear_RMASK 0x1406#define QIB_6120_ErrClear_RcvUnsupportedVLErrClear_LSB 0x8407#define QIB_6120_ErrClear_RcvUnsupportedVLErrClear_RMASK 0x1408#define QIB_6120_ErrClear_RcvUnexpectedCharErrClear_LSB 0x7409#define QIB_6120_ErrClear_RcvUnexpectedCharErrClear_RMASK 0x1410#define QIB_6120_ErrClear_RcvShortPktLenErrClear_LSB 0x6411#define QIB_6120_ErrClear_RcvShortPktLenErrClear_RMASK 0x1412#define QIB_6120_ErrClear_RcvLongPktLenErrClear_LSB 0x5413#define QIB_6120_ErrClear_RcvLongPktLenErrClear_RMASK 0x1414#define QIB_6120_ErrClear_RcvMaxPktLenErrClear_LSB 0x4415#define QIB_6120_ErrClear_RcvMaxPktLenErrClear_RMASK 0x1416#define QIB_6120_ErrClear_RcvMinPktLenErrClear_LSB 0x3417#define QIB_6120_ErrClear_RcvMinPktLenErrClear_RMASK 0x1418#define QIB_6120_ErrClear_RcvICRCErrClear_LSB 0x2419#define QIB_6120_ErrClear_RcvICRCErrClear_RMASK 0x1420#define QIB_6120_ErrClear_RcvVCRCErrClear_LSB 0x1421#define QIB_6120_ErrClear_RcvVCRCErrClear_RMASK 0x1422#define QIB_6120_ErrClear_RcvFormatErrClear_LSB 0x0423#define QIB_6120_ErrClear_RcvFormatErrClear_RMASK 0x1424 425#define QIB_6120_HwErrMask_OFFS 0x98426#define QIB_6120_HwErrMask_IBCBusFromSPCParityErrMask_LSB 0x3F427#define QIB_6120_HwErrMask_IBCBusFromSPCParityErrMask_RMASK 0x1428#define QIB_6120_HwErrMask_IBCBusToSPCParityErrMask_LSB 0x3E429#define QIB_6120_HwErrMask_IBCBusToSPCParityErrMask_RMASK 0x1430#define QIB_6120_HwErrMask_Reserved_LSB 0x3D431#define QIB_6120_HwErrMask_Reserved_RMASK 0x1432#define QIB_6120_HwErrMask_IBSerdesPClkNotDetectMask_LSB 0x3C433#define QIB_6120_HwErrMask_IBSerdesPClkNotDetectMask_RMASK 0x1434#define QIB_6120_HwErrMask_PCIESerdesQ0PClkNotDetectMask_LSB 0x3B435#define QIB_6120_HwErrMask_PCIESerdesQ0PClkNotDetectMask_RMASK 0x1436#define QIB_6120_HwErrMask_PCIESerdesQ1PClkNotDetectMask_LSB 0x3A437#define QIB_6120_HwErrMask_PCIESerdesQ1PClkNotDetectMask_RMASK 0x1438#define QIB_6120_HwErrMask_Reserved1_LSB 0x39439#define QIB_6120_HwErrMask_Reserved1_RMASK 0x1440#define QIB_6120_HwErrMask_IBPLLrfSlipMask_LSB 0x38441#define QIB_6120_HwErrMask_IBPLLrfSlipMask_RMASK 0x1442#define QIB_6120_HwErrMask_IBPLLfbSlipMask_LSB 0x37443#define QIB_6120_HwErrMask_IBPLLfbSlipMask_RMASK 0x1444#define QIB_6120_HwErrMask_PowerOnBISTFailedMask_LSB 0x36445#define QIB_6120_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1446#define QIB_6120_HwErrMask_Reserved2_LSB 0x33447#define QIB_6120_HwErrMask_Reserved2_RMASK 0x7448#define QIB_6120_HwErrMask_RXEMemParityErrMask_LSB 0x2C449#define QIB_6120_HwErrMask_RXEMemParityErrMask_RMASK 0x7F450#define QIB_6120_HwErrMask_TXEMemParityErrMask_LSB 0x28451#define QIB_6120_HwErrMask_TXEMemParityErrMask_RMASK 0xF452#define QIB_6120_HwErrMask_Reserved3_LSB 0x22453#define QIB_6120_HwErrMask_Reserved3_RMASK 0x3F454#define QIB_6120_HwErrMask_PCIeBusParityErrMask_LSB 0x1F455#define QIB_6120_HwErrMask_PCIeBusParityErrMask_RMASK 0x7456#define QIB_6120_HwErrMask_PcieCplTimeoutMask_LSB 0x1E457#define QIB_6120_HwErrMask_PcieCplTimeoutMask_RMASK 0x1458#define QIB_6120_HwErrMask_PoisonedTLPMask_LSB 0x1D459#define QIB_6120_HwErrMask_PoisonedTLPMask_RMASK 0x1460#define QIB_6120_HwErrMask_Reserved4_LSB 0x6461#define QIB_6120_HwErrMask_Reserved4_RMASK 0x7FFFFF462#define QIB_6120_HwErrMask_PCIeMemParityErrMask_LSB 0x0463#define QIB_6120_HwErrMask_PCIeMemParityErrMask_RMASK 0x3F464 465#define QIB_6120_HwErrStatus_OFFS 0xA0466#define QIB_6120_HwErrStatus_IBCBusFromSPCParityErr_LSB 0x3F467#define QIB_6120_HwErrStatus_IBCBusFromSPCParityErr_RMASK 0x1468#define QIB_6120_HwErrStatus_IBCBusToSPCParityErr_LSB 0x3E469#define QIB_6120_HwErrStatus_IBCBusToSPCParityErr_RMASK 0x1470#define QIB_6120_HwErrStatus_Reserved_LSB 0x3D471#define QIB_6120_HwErrStatus_Reserved_RMASK 0x1472#define QIB_6120_HwErrStatus_IBSerdesPClkNotDetect_LSB 0x3C473#define QIB_6120_HwErrStatus_IBSerdesPClkNotDetect_RMASK 0x1474#define QIB_6120_HwErrStatus_PCIESerdesQ0PClkNotDetect_LSB 0x3B475#define QIB_6120_HwErrStatus_PCIESerdesQ0PClkNotDetect_RMASK 0x1476#define QIB_6120_HwErrStatus_PCIESerdesQ1PClkNotDetect_LSB 0x3A477#define QIB_6120_HwErrStatus_PCIESerdesQ1PClkNotDetect_RMASK 0x1478#define QIB_6120_HwErrStatus_Reserved1_LSB 0x39479#define QIB_6120_HwErrStatus_Reserved1_RMASK 0x1480#define QIB_6120_HwErrStatus_IBPLLrfSlip_LSB 0x38481#define QIB_6120_HwErrStatus_IBPLLrfSlip_RMASK 0x1482#define QIB_6120_HwErrStatus_IBPLLfbSlip_LSB 0x37483#define QIB_6120_HwErrStatus_IBPLLfbSlip_RMASK 0x1484#define QIB_6120_HwErrStatus_PowerOnBISTFailed_LSB 0x36485#define QIB_6120_HwErrStatus_PowerOnBISTFailed_RMASK 0x1486#define QIB_6120_HwErrStatus_Reserved2_LSB 0x33487#define QIB_6120_HwErrStatus_Reserved2_RMASK 0x7488#define QIB_6120_HwErrStatus_RXEMemParity_LSB 0x2C489#define QIB_6120_HwErrStatus_RXEMemParity_RMASK 0x7F490#define QIB_6120_HwErrStatus_TXEMemParity_LSB 0x28491#define QIB_6120_HwErrStatus_TXEMemParity_RMASK 0xF492#define QIB_6120_HwErrStatus_Reserved3_LSB 0x22493#define QIB_6120_HwErrStatus_Reserved3_RMASK 0x3F494#define QIB_6120_HwErrStatus_PCIeBusParity_LSB 0x1F495#define QIB_6120_HwErrStatus_PCIeBusParity_RMASK 0x7496#define QIB_6120_HwErrStatus_PcieCplTimeout_LSB 0x1E497#define QIB_6120_HwErrStatus_PcieCplTimeout_RMASK 0x1498#define QIB_6120_HwErrStatus_PoisenedTLP_LSB 0x1D499#define QIB_6120_HwErrStatus_PoisenedTLP_RMASK 0x1500#define QIB_6120_HwErrStatus_Reserved4_LSB 0x6501#define QIB_6120_HwErrStatus_Reserved4_RMASK 0x7FFFFF502#define QIB_6120_HwErrStatus_PCIeMemParity_LSB 0x0503#define QIB_6120_HwErrStatus_PCIeMemParity_RMASK 0x3F504 505#define QIB_6120_HwErrClear_OFFS 0xA8506#define QIB_6120_HwErrClear_IBCBusFromSPCParityErrClear_LSB 0x3F507#define QIB_6120_HwErrClear_IBCBusFromSPCParityErrClear_RMASK 0x1508#define QIB_6120_HwErrClear_IBCBusToSPCparityErrClear_LSB 0x3E509#define QIB_6120_HwErrClear_IBCBusToSPCparityErrClear_RMASK 0x1510#define QIB_6120_HwErrClear_Reserved_LSB 0x3D511#define QIB_6120_HwErrClear_Reserved_RMASK 0x1512#define QIB_6120_HwErrClear_IBSerdesPClkNotDetectClear_LSB 0x3C513#define QIB_6120_HwErrClear_IBSerdesPClkNotDetectClear_RMASK 0x1514#define QIB_6120_HwErrClear_PCIESerdesQ0PClkNotDetectClear_LSB 0x3B515#define QIB_6120_HwErrClear_PCIESerdesQ0PClkNotDetectClear_RMASK 0x1516#define QIB_6120_HwErrClear_PCIESerdesQ1PClkNotDetectClear_LSB 0x3A517#define QIB_6120_HwErrClear_PCIESerdesQ1PClkNotDetectClear_RMASK 0x1518#define QIB_6120_HwErrClear_Reserved1_LSB 0x39519#define QIB_6120_HwErrClear_Reserved1_RMASK 0x1520#define QIB_6120_HwErrClear_IBPLLrfSlipClear_LSB 0x38521#define QIB_6120_HwErrClear_IBPLLrfSlipClear_RMASK 0x1522#define QIB_6120_HwErrClear_IBPLLfbSlipClear_LSB 0x37523#define QIB_6120_HwErrClear_IBPLLfbSlipClear_RMASK 0x1524#define QIB_6120_HwErrClear_PowerOnBISTFailedClear_LSB 0x36525#define QIB_6120_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1526#define QIB_6120_HwErrClear_Reserved2_LSB 0x33527#define QIB_6120_HwErrClear_Reserved2_RMASK 0x7528#define QIB_6120_HwErrClear_RXEMemParityClear_LSB 0x2C529#define QIB_6120_HwErrClear_RXEMemParityClear_RMASK 0x7F530#define QIB_6120_HwErrClear_TXEMemParityClear_LSB 0x28531#define QIB_6120_HwErrClear_TXEMemParityClear_RMASK 0xF532#define QIB_6120_HwErrClear_Reserved3_LSB 0x22533#define QIB_6120_HwErrClear_Reserved3_RMASK 0x3F534#define QIB_6120_HwErrClear_PCIeBusParityClr_LSB 0x1F535#define QIB_6120_HwErrClear_PCIeBusParityClr_RMASK 0x7536#define QIB_6120_HwErrClear_PcieCplTimeoutClear_LSB 0x1E537#define QIB_6120_HwErrClear_PcieCplTimeoutClear_RMASK 0x1538#define QIB_6120_HwErrClear_PoisonedTLPClear_LSB 0x1D539#define QIB_6120_HwErrClear_PoisonedTLPClear_RMASK 0x1540#define QIB_6120_HwErrClear_Reserved4_LSB 0x6541#define QIB_6120_HwErrClear_Reserved4_RMASK 0x7FFFFF542#define QIB_6120_HwErrClear_PCIeMemParityClr_LSB 0x0543#define QIB_6120_HwErrClear_PCIeMemParityClr_RMASK 0x3F544 545#define QIB_6120_HwDiagCtrl_OFFS 0xB0546#define QIB_6120_HwDiagCtrl_ForceIBCBusFromSPCParityErr_LSB 0x3F547#define QIB_6120_HwDiagCtrl_ForceIBCBusFromSPCParityErr_RMASK 0x1548#define QIB_6120_HwDiagCtrl_ForceIBCBusToSPCParityErr_LSB 0x3E549#define QIB_6120_HwDiagCtrl_ForceIBCBusToSPCParityErr_RMASK 0x1550#define QIB_6120_HwDiagCtrl_CounterWrEnable_LSB 0x3D551#define QIB_6120_HwDiagCtrl_CounterWrEnable_RMASK 0x1552#define QIB_6120_HwDiagCtrl_CounterDisable_LSB 0x3C553#define QIB_6120_HwDiagCtrl_CounterDisable_RMASK 0x1554#define QIB_6120_HwDiagCtrl_Reserved_LSB 0x33555#define QIB_6120_HwDiagCtrl_Reserved_RMASK 0x1FF556#define QIB_6120_HwDiagCtrl_ForceRxMemParityErr_LSB 0x2C557#define QIB_6120_HwDiagCtrl_ForceRxMemParityErr_RMASK 0x7F558#define QIB_6120_HwDiagCtrl_ForceTxMemparityErr_LSB 0x28559#define QIB_6120_HwDiagCtrl_ForceTxMemparityErr_RMASK 0xF560#define QIB_6120_HwDiagCtrl_Reserved1_LSB 0x23561#define QIB_6120_HwDiagCtrl_Reserved1_RMASK 0x1F562#define QIB_6120_HwDiagCtrl_forcePCIeBusParity_LSB 0x1F563#define QIB_6120_HwDiagCtrl_forcePCIeBusParity_RMASK 0xF564#define QIB_6120_HwDiagCtrl_Reserved2_LSB 0x6565#define QIB_6120_HwDiagCtrl_Reserved2_RMASK 0x1FFFFFF566#define QIB_6120_HwDiagCtrl_forcePCIeMemParity_LSB 0x0567#define QIB_6120_HwDiagCtrl_forcePCIeMemParity_RMASK 0x3F568 569#define QIB_6120_IBCStatus_OFFS 0xC0570#define QIB_6120_IBCStatus_TxCreditOk_LSB 0x1F571#define QIB_6120_IBCStatus_TxCreditOk_RMASK 0x1572#define QIB_6120_IBCStatus_TxReady_LSB 0x1E573#define QIB_6120_IBCStatus_TxReady_RMASK 0x1574#define QIB_6120_IBCStatus_Reserved_LSB 0x7575#define QIB_6120_IBCStatus_Reserved_RMASK 0x7FFFFF576#define QIB_6120_IBCStatus_LinkState_LSB 0x4577#define QIB_6120_IBCStatus_LinkState_RMASK 0x7578#define QIB_6120_IBCStatus_LinkTrainingState_LSB 0x0579#define QIB_6120_IBCStatus_LinkTrainingState_RMASK 0xF580 581#define QIB_6120_IBCCtrl_OFFS 0xC8582#define QIB_6120_IBCCtrl_Loopback_LSB 0x3F583#define QIB_6120_IBCCtrl_Loopback_RMASK 0x1584#define QIB_6120_IBCCtrl_LinkDownDefaultState_LSB 0x3E585#define QIB_6120_IBCCtrl_LinkDownDefaultState_RMASK 0x1586#define QIB_6120_IBCCtrl_Reserved_LSB 0x2B587#define QIB_6120_IBCCtrl_Reserved_RMASK 0x7FFFF588#define QIB_6120_IBCCtrl_CreditScale_LSB 0x28589#define QIB_6120_IBCCtrl_CreditScale_RMASK 0x7590#define QIB_6120_IBCCtrl_OverrunThreshold_LSB 0x24591#define QIB_6120_IBCCtrl_OverrunThreshold_RMASK 0xF592#define QIB_6120_IBCCtrl_PhyerrThreshold_LSB 0x20593#define QIB_6120_IBCCtrl_PhyerrThreshold_RMASK 0xF594#define QIB_6120_IBCCtrl_Reserved1_LSB 0x1F595#define QIB_6120_IBCCtrl_Reserved1_RMASK 0x1596#define QIB_6120_IBCCtrl_MaxPktLen_LSB 0x14597#define QIB_6120_IBCCtrl_MaxPktLen_RMASK 0x7FF598#define QIB_6120_IBCCtrl_LinkCmd_LSB 0x12599#define QIB_6120_IBCCtrl_LinkCmd_RMASK 0x3600#define QIB_6120_IBCCtrl_LinkInitCmd_LSB 0x10601#define QIB_6120_IBCCtrl_LinkInitCmd_RMASK 0x3602#define QIB_6120_IBCCtrl_FlowCtrlWaterMark_LSB 0x8603#define QIB_6120_IBCCtrl_FlowCtrlWaterMark_RMASK 0xFF604#define QIB_6120_IBCCtrl_FlowCtrlPeriod_LSB 0x0605#define QIB_6120_IBCCtrl_FlowCtrlPeriod_RMASK 0xFF606 607#define QIB_6120_EXTStatus_OFFS 0xD0608#define QIB_6120_EXTStatus_GPIOIn_LSB 0x30609#define QIB_6120_EXTStatus_GPIOIn_RMASK 0xFFFF610#define QIB_6120_EXTStatus_Reserved_LSB 0x20611#define QIB_6120_EXTStatus_Reserved_RMASK 0xFFFF612#define QIB_6120_EXTStatus_Reserved1_LSB 0x10613#define QIB_6120_EXTStatus_Reserved1_RMASK 0xFFFF614#define QIB_6120_EXTStatus_MemBISTFoundErr_LSB 0xF615#define QIB_6120_EXTStatus_MemBISTFoundErr_RMASK 0x1616#define QIB_6120_EXTStatus_MemBISTEndTest_LSB 0xE617#define QIB_6120_EXTStatus_MemBISTEndTest_RMASK 0x1618#define QIB_6120_EXTStatus_Reserved2_LSB 0x0619#define QIB_6120_EXTStatus_Reserved2_RMASK 0x3FFF620 621#define QIB_6120_EXTCtrl_OFFS 0xD8622#define QIB_6120_EXTCtrl_GPIOOe_LSB 0x30623#define QIB_6120_EXTCtrl_GPIOOe_RMASK 0xFFFF624#define QIB_6120_EXTCtrl_GPIOInvert_LSB 0x20625#define QIB_6120_EXTCtrl_GPIOInvert_RMASK 0xFFFF626#define QIB_6120_EXTCtrl_Reserved_LSB 0x4627#define QIB_6120_EXTCtrl_Reserved_RMASK 0xFFFFFFF628#define QIB_6120_EXTCtrl_LEDPriPortGreenOn_LSB 0x3629#define QIB_6120_EXTCtrl_LEDPriPortGreenOn_RMASK 0x1630#define QIB_6120_EXTCtrl_LEDPriPortYellowOn_LSB 0x2631#define QIB_6120_EXTCtrl_LEDPriPortYellowOn_RMASK 0x1632#define QIB_6120_EXTCtrl_LEDGblOkGreenOn_LSB 0x1633#define QIB_6120_EXTCtrl_LEDGblOkGreenOn_RMASK 0x1634#define QIB_6120_EXTCtrl_LEDGblErrRedOff_LSB 0x0635#define QIB_6120_EXTCtrl_LEDGblErrRedOff_RMASK 0x1636 637#define QIB_6120_GPIOOut_OFFS 0xE0638 639#define QIB_6120_GPIOMask_OFFS 0xE8640 641#define QIB_6120_GPIOStatus_OFFS 0xF0642 643#define QIB_6120_GPIOClear_OFFS 0xF8644 645#define QIB_6120_RcvCtrl_OFFS 0x100646#define QIB_6120_RcvCtrl_TailUpd_LSB 0x1F647#define QIB_6120_RcvCtrl_TailUpd_RMASK 0x1648#define QIB_6120_RcvCtrl_RcvPartitionKeyDisable_LSB 0x1E649#define QIB_6120_RcvCtrl_RcvPartitionKeyDisable_RMASK 0x1650#define QIB_6120_RcvCtrl_Reserved_LSB 0x15651#define QIB_6120_RcvCtrl_Reserved_RMASK 0x1FF652#define QIB_6120_RcvCtrl_IntrAvail_LSB 0x10653#define QIB_6120_RcvCtrl_IntrAvail_RMASK 0x1F654#define QIB_6120_RcvCtrl_Reserved1_LSB 0x9655#define QIB_6120_RcvCtrl_Reserved1_RMASK 0x7F656#define QIB_6120_RcvCtrl_Reserved2_LSB 0x5657#define QIB_6120_RcvCtrl_Reserved2_RMASK 0xF658#define QIB_6120_RcvCtrl_PortEnable_LSB 0x0659#define QIB_6120_RcvCtrl_PortEnable_RMASK 0x1F660 661#define QIB_6120_RcvBTHQP_OFFS 0x108662#define QIB_6120_RcvBTHQP_BTHQP_Mask_LSB 0x1E663#define QIB_6120_RcvBTHQP_BTHQP_Mask_RMASK 0x3664#define QIB_6120_RcvBTHQP_Reserved_LSB 0x18665#define QIB_6120_RcvBTHQP_Reserved_RMASK 0x3F666#define QIB_6120_RcvBTHQP_RcvBTHQP_LSB 0x0667#define QIB_6120_RcvBTHQP_RcvBTHQP_RMASK 0xFFFFFF668 669#define QIB_6120_RcvHdrSize_OFFS 0x110670 671#define QIB_6120_RcvHdrCnt_OFFS 0x118672 673#define QIB_6120_RcvHdrEntSize_OFFS 0x120674 675#define QIB_6120_RcvTIDBase_OFFS 0x128676 677#define QIB_6120_RcvTIDCnt_OFFS 0x130678 679#define QIB_6120_RcvEgrBase_OFFS 0x138680 681#define QIB_6120_RcvEgrCnt_OFFS 0x140682 683#define QIB_6120_RcvBufBase_OFFS 0x148684 685#define QIB_6120_RcvBufSize_OFFS 0x150686 687#define QIB_6120_RxIntMemBase_OFFS 0x158688 689#define QIB_6120_RxIntMemSize_OFFS 0x160690 691#define QIB_6120_RcvPartitionKey_OFFS 0x168692 693#define QIB_6120_RcvPktLEDCnt_OFFS 0x178694#define QIB_6120_RcvPktLEDCnt_ONperiod_LSB 0x20695#define QIB_6120_RcvPktLEDCnt_ONperiod_RMASK 0xFFFFFFFF696#define QIB_6120_RcvPktLEDCnt_OFFperiod_LSB 0x0697#define QIB_6120_RcvPktLEDCnt_OFFperiod_RMASK 0xFFFFFFFF698 699#define QIB_6120_SendCtrl_OFFS 0x1C0700#define QIB_6120_SendCtrl_Disarm_LSB 0x1F701#define QIB_6120_SendCtrl_Disarm_RMASK 0x1702#define QIB_6120_SendCtrl_Reserved_LSB 0x17703#define QIB_6120_SendCtrl_Reserved_RMASK 0xFF704#define QIB_6120_SendCtrl_DisarmPIOBuf_LSB 0x10705#define QIB_6120_SendCtrl_DisarmPIOBuf_RMASK 0x7F706#define QIB_6120_SendCtrl_Reserved1_LSB 0x4707#define QIB_6120_SendCtrl_Reserved1_RMASK 0xFFF708#define QIB_6120_SendCtrl_PIOEnable_LSB 0x3709#define QIB_6120_SendCtrl_PIOEnable_RMASK 0x1710#define QIB_6120_SendCtrl_PIOBufAvailUpd_LSB 0x2711#define QIB_6120_SendCtrl_PIOBufAvailUpd_RMASK 0x1712#define QIB_6120_SendCtrl_PIOIntBufAvail_LSB 0x1713#define QIB_6120_SendCtrl_PIOIntBufAvail_RMASK 0x1714#define QIB_6120_SendCtrl_Abort_LSB 0x0715#define QIB_6120_SendCtrl_Abort_RMASK 0x1716 717#define QIB_6120_SendPIOBufBase_OFFS 0x1C8718#define QIB_6120_SendPIOBufBase_Reserved_LSB 0x35719#define QIB_6120_SendPIOBufBase_Reserved_RMASK 0x7FF720#define QIB_6120_SendPIOBufBase_BaseAddr_LargePIO_LSB 0x20721#define QIB_6120_SendPIOBufBase_BaseAddr_LargePIO_RMASK 0x1FFFFF722#define QIB_6120_SendPIOBufBase_Reserved1_LSB 0x15723#define QIB_6120_SendPIOBufBase_Reserved1_RMASK 0x7FF724#define QIB_6120_SendPIOBufBase_BaseAddr_SmallPIO_LSB 0x0725#define QIB_6120_SendPIOBufBase_BaseAddr_SmallPIO_RMASK 0x1FFFFF726 727#define QIB_6120_SendPIOSize_OFFS 0x1D0728#define QIB_6120_SendPIOSize_Reserved_LSB 0x2D729#define QIB_6120_SendPIOSize_Reserved_RMASK 0xFFFFF730#define QIB_6120_SendPIOSize_Size_LargePIO_LSB 0x20731#define QIB_6120_SendPIOSize_Size_LargePIO_RMASK 0x1FFF732#define QIB_6120_SendPIOSize_Reserved1_LSB 0xC733#define QIB_6120_SendPIOSize_Reserved1_RMASK 0xFFFFF734#define QIB_6120_SendPIOSize_Size_SmallPIO_LSB 0x0735#define QIB_6120_SendPIOSize_Size_SmallPIO_RMASK 0xFFF736 737#define QIB_6120_SendPIOBufCnt_OFFS 0x1D8738#define QIB_6120_SendPIOBufCnt_Reserved_LSB 0x24739#define QIB_6120_SendPIOBufCnt_Reserved_RMASK 0xFFFFFFF740#define QIB_6120_SendPIOBufCnt_Num_LargePIO_LSB 0x20741#define QIB_6120_SendPIOBufCnt_Num_LargePIO_RMASK 0xF742#define QIB_6120_SendPIOBufCnt_Reserved1_LSB 0x9743#define QIB_6120_SendPIOBufCnt_Reserved1_RMASK 0x7FFFFF744#define QIB_6120_SendPIOBufCnt_Num_SmallPIO_LSB 0x0745#define QIB_6120_SendPIOBufCnt_Num_SmallPIO_RMASK 0x1FF746 747#define QIB_6120_SendPIOAvailAddr_OFFS 0x1E0748#define QIB_6120_SendPIOAvailAddr_SendPIOAvailAddr_LSB 0x6749#define QIB_6120_SendPIOAvailAddr_SendPIOAvailAddr_RMASK 0x3FFFFFFFF750#define QIB_6120_SendPIOAvailAddr_Reserved_LSB 0x0751#define QIB_6120_SendPIOAvailAddr_Reserved_RMASK 0x3F752 753#define QIB_6120_SendBufErr0_OFFS 0x240754#define QIB_6120_SendBufErr0_SendBufErrPIO_63_0_LSB 0x0755#define QIB_6120_SendBufErr0_SendBufErrPIO_63_0_RMASK 0x0756 757#define QIB_6120_RcvHdrAddr0_OFFS 0x280758#define QIB_6120_RcvHdrAddr0_RcvHdrAddr0_LSB 0x2759#define QIB_6120_RcvHdrAddr0_RcvHdrAddr0_RMASK 0x3FFFFFFFFF760#define QIB_6120_RcvHdrAddr0_Reserved_LSB 0x0761#define QIB_6120_RcvHdrAddr0_Reserved_RMASK 0x3762 763#define QIB_6120_RcvHdrTailAddr0_OFFS 0x300764#define QIB_6120_RcvHdrTailAddr0_RcvHdrTailAddr0_LSB 0x2765#define QIB_6120_RcvHdrTailAddr0_RcvHdrTailAddr0_RMASK 0x3FFFFFFFFF766#define QIB_6120_RcvHdrTailAddr0_Reserved_LSB 0x0767#define QIB_6120_RcvHdrTailAddr0_Reserved_RMASK 0x3768 769#define QIB_6120_SerdesCfg0_OFFS 0x3C0770#define QIB_6120_SerdesCfg0_DisableIBTxIdleDetect_LSB 0x3F771#define QIB_6120_SerdesCfg0_DisableIBTxIdleDetect_RMASK 0x1772#define QIB_6120_SerdesCfg0_Reserved_LSB 0x38773#define QIB_6120_SerdesCfg0_Reserved_RMASK 0x7F774#define QIB_6120_SerdesCfg0_RxEqCtl_LSB 0x36775#define QIB_6120_SerdesCfg0_RxEqCtl_RMASK 0x3776#define QIB_6120_SerdesCfg0_TxTermAdj_LSB 0x34777#define QIB_6120_SerdesCfg0_TxTermAdj_RMASK 0x3778#define QIB_6120_SerdesCfg0_RxTermAdj_LSB 0x32779#define QIB_6120_SerdesCfg0_RxTermAdj_RMASK 0x3780#define QIB_6120_SerdesCfg0_TermAdj1_LSB 0x31781#define QIB_6120_SerdesCfg0_TermAdj1_RMASK 0x1782#define QIB_6120_SerdesCfg0_TermAdj0_LSB 0x30783#define QIB_6120_SerdesCfg0_TermAdj0_RMASK 0x1784#define QIB_6120_SerdesCfg0_LPBKA_LSB 0x2F785#define QIB_6120_SerdesCfg0_LPBKA_RMASK 0x1786#define QIB_6120_SerdesCfg0_LPBKB_LSB 0x2E787#define QIB_6120_SerdesCfg0_LPBKB_RMASK 0x1788#define QIB_6120_SerdesCfg0_LPBKC_LSB 0x2D789#define QIB_6120_SerdesCfg0_LPBKC_RMASK 0x1790#define QIB_6120_SerdesCfg0_LPBKD_LSB 0x2C791#define QIB_6120_SerdesCfg0_LPBKD_RMASK 0x1792#define QIB_6120_SerdesCfg0_PW_LSB 0x2B793#define QIB_6120_SerdesCfg0_PW_RMASK 0x1794#define QIB_6120_SerdesCfg0_RefSel_LSB 0x29795#define QIB_6120_SerdesCfg0_RefSel_RMASK 0x3796#define QIB_6120_SerdesCfg0_ParReset_LSB 0x28797#define QIB_6120_SerdesCfg0_ParReset_RMASK 0x1798#define QIB_6120_SerdesCfg0_ParLPBK_LSB 0x27799#define QIB_6120_SerdesCfg0_ParLPBK_RMASK 0x1800#define QIB_6120_SerdesCfg0_OffsetEn_LSB 0x26801#define QIB_6120_SerdesCfg0_OffsetEn_RMASK 0x1802#define QIB_6120_SerdesCfg0_Offset_LSB 0x1E803#define QIB_6120_SerdesCfg0_Offset_RMASK 0xFF804#define QIB_6120_SerdesCfg0_L2PwrDn_LSB 0x1D805#define QIB_6120_SerdesCfg0_L2PwrDn_RMASK 0x1806#define QIB_6120_SerdesCfg0_ResetPLL_LSB 0x1C807#define QIB_6120_SerdesCfg0_ResetPLL_RMASK 0x1808#define QIB_6120_SerdesCfg0_RxTermEnX_LSB 0x18809#define QIB_6120_SerdesCfg0_RxTermEnX_RMASK 0xF810#define QIB_6120_SerdesCfg0_BeaconTxEnX_LSB 0x14811#define QIB_6120_SerdesCfg0_BeaconTxEnX_RMASK 0xF812#define QIB_6120_SerdesCfg0_RxDetEnX_LSB 0x10813#define QIB_6120_SerdesCfg0_RxDetEnX_RMASK 0xF814#define QIB_6120_SerdesCfg0_TxIdeEnX_LSB 0xC815#define QIB_6120_SerdesCfg0_TxIdeEnX_RMASK 0xF816#define QIB_6120_SerdesCfg0_RxIdleEnX_LSB 0x8817#define QIB_6120_SerdesCfg0_RxIdleEnX_RMASK 0xF818#define QIB_6120_SerdesCfg0_L1PwrDnA_LSB 0x7819#define QIB_6120_SerdesCfg0_L1PwrDnA_RMASK 0x1820#define QIB_6120_SerdesCfg0_L1PwrDnB_LSB 0x6821#define QIB_6120_SerdesCfg0_L1PwrDnB_RMASK 0x1822#define QIB_6120_SerdesCfg0_L1PwrDnC_LSB 0x5823#define QIB_6120_SerdesCfg0_L1PwrDnC_RMASK 0x1824#define QIB_6120_SerdesCfg0_L1PwrDnD_LSB 0x4825#define QIB_6120_SerdesCfg0_L1PwrDnD_RMASK 0x1826#define QIB_6120_SerdesCfg0_ResetA_LSB 0x3827#define QIB_6120_SerdesCfg0_ResetA_RMASK 0x1828#define QIB_6120_SerdesCfg0_ResetB_LSB 0x2829#define QIB_6120_SerdesCfg0_ResetB_RMASK 0x1830#define QIB_6120_SerdesCfg0_ResetC_LSB 0x1831#define QIB_6120_SerdesCfg0_ResetC_RMASK 0x1832#define QIB_6120_SerdesCfg0_ResetD_LSB 0x0833#define QIB_6120_SerdesCfg0_ResetD_RMASK 0x1834 835#define QIB_6120_SerdesStat_OFFS 0x3D0836#define QIB_6120_SerdesStat_Reserved_LSB 0xC837#define QIB_6120_SerdesStat_Reserved_RMASK 0xFFFFFFFFFFFFF838#define QIB_6120_SerdesStat_BeaconDetA_LSB 0xB839#define QIB_6120_SerdesStat_BeaconDetA_RMASK 0x1840#define QIB_6120_SerdesStat_BeaconDetB_LSB 0xA841#define QIB_6120_SerdesStat_BeaconDetB_RMASK 0x1842#define QIB_6120_SerdesStat_BeaconDetC_LSB 0x9843#define QIB_6120_SerdesStat_BeaconDetC_RMASK 0x1844#define QIB_6120_SerdesStat_BeaconDetD_LSB 0x8845#define QIB_6120_SerdesStat_BeaconDetD_RMASK 0x1846#define QIB_6120_SerdesStat_RxDetA_LSB 0x7847#define QIB_6120_SerdesStat_RxDetA_RMASK 0x1848#define QIB_6120_SerdesStat_RxDetB_LSB 0x6849#define QIB_6120_SerdesStat_RxDetB_RMASK 0x1850#define QIB_6120_SerdesStat_RxDetC_LSB 0x5851#define QIB_6120_SerdesStat_RxDetC_RMASK 0x1852#define QIB_6120_SerdesStat_RxDetD_LSB 0x4853#define QIB_6120_SerdesStat_RxDetD_RMASK 0x1854#define QIB_6120_SerdesStat_TxIdleDetA_LSB 0x3855#define QIB_6120_SerdesStat_TxIdleDetA_RMASK 0x1856#define QIB_6120_SerdesStat_TxIdleDetB_LSB 0x2857#define QIB_6120_SerdesStat_TxIdleDetB_RMASK 0x1858#define QIB_6120_SerdesStat_TxIdleDetC_LSB 0x1859#define QIB_6120_SerdesStat_TxIdleDetC_RMASK 0x1860#define QIB_6120_SerdesStat_TxIdleDetD_LSB 0x0861#define QIB_6120_SerdesStat_TxIdleDetD_RMASK 0x1862 863#define QIB_6120_XGXSCfg_OFFS 0x3D8864#define QIB_6120_XGXSCfg_ArmLaunchErrorDisable_LSB 0x3F865#define QIB_6120_XGXSCfg_ArmLaunchErrorDisable_RMASK 0x1866#define QIB_6120_XGXSCfg_Reserved_LSB 0x17867#define QIB_6120_XGXSCfg_Reserved_RMASK 0xFFFFFFFFFF868#define QIB_6120_XGXSCfg_polarity_inv_LSB 0x13869#define QIB_6120_XGXSCfg_polarity_inv_RMASK 0xF870#define QIB_6120_XGXSCfg_link_sync_mask_LSB 0x9871#define QIB_6120_XGXSCfg_link_sync_mask_RMASK 0x3FF872#define QIB_6120_XGXSCfg_port_addr_LSB 0x4873#define QIB_6120_XGXSCfg_port_addr_RMASK 0x1F874#define QIB_6120_XGXSCfg_mdd_30_LSB 0x3875#define QIB_6120_XGXSCfg_mdd_30_RMASK 0x1876#define QIB_6120_XGXSCfg_xcv_resetn_LSB 0x2877#define QIB_6120_XGXSCfg_xcv_resetn_RMASK 0x1878#define QIB_6120_XGXSCfg_Reserved1_LSB 0x1879#define QIB_6120_XGXSCfg_Reserved1_RMASK 0x1880#define QIB_6120_XGXSCfg_tx_rx_resetn_LSB 0x0881#define QIB_6120_XGXSCfg_tx_rx_resetn_RMASK 0x1882 883#define QIB_6120_LBIntCnt_OFFS 0x12000884 885#define QIB_6120_LBFlowStallCnt_OFFS 0x12008886 887#define QIB_6120_TxUnsupVLErrCnt_OFFS 0x12018888 889#define QIB_6120_TxDataPktCnt_OFFS 0x12020890 891#define QIB_6120_TxFlowPktCnt_OFFS 0x12028892 893#define QIB_6120_TxDwordCnt_OFFS 0x12030894 895#define QIB_6120_TxLenErrCnt_OFFS 0x12038896 897#define QIB_6120_TxMaxMinLenErrCnt_OFFS 0x12040898 899#define QIB_6120_TxUnderrunCnt_OFFS 0x12048900 901#define QIB_6120_TxFlowStallCnt_OFFS 0x12050902 903#define QIB_6120_TxDroppedPktCnt_OFFS 0x12058904 905#define QIB_6120_RxDroppedPktCnt_OFFS 0x12060906 907#define QIB_6120_RxDataPktCnt_OFFS 0x12068908 909#define QIB_6120_RxFlowPktCnt_OFFS 0x12070910 911#define QIB_6120_RxDwordCnt_OFFS 0x12078912 913#define QIB_6120_RxLenErrCnt_OFFS 0x12080914 915#define QIB_6120_RxMaxMinLenErrCnt_OFFS 0x12088916 917#define QIB_6120_RxICRCErrCnt_OFFS 0x12090918 919#define QIB_6120_RxVCRCErrCnt_OFFS 0x12098920 921#define QIB_6120_RxFlowCtrlErrCnt_OFFS 0x120A0922 923#define QIB_6120_RxBadFormatCnt_OFFS 0x120A8924 925#define QIB_6120_RxLinkProblemCnt_OFFS 0x120B0926 927#define QIB_6120_RxEBPCnt_OFFS 0x120B8928 929#define QIB_6120_RxLPCRCErrCnt_OFFS 0x120C0930 931#define QIB_6120_RxBufOvflCnt_OFFS 0x120C8932 933#define QIB_6120_RxTIDFullErrCnt_OFFS 0x120D0934 935#define QIB_6120_RxTIDValidErrCnt_OFFS 0x120D8936 937#define QIB_6120_RxPKeyMismatchCnt_OFFS 0x120E0938 939#define QIB_6120_RxP0HdrEgrOvflCnt_OFFS 0x120E8940 941#define QIB_6120_IBStatusChangeCnt_OFFS 0x12140942 943#define QIB_6120_IBLinkErrRecoveryCnt_OFFS 0x12148944 945#define QIB_6120_IBLinkDownedCnt_OFFS 0x12150946 947#define QIB_6120_IBSymbolErrCnt_OFFS 0x12158948 949#define QIB_6120_PcieRetryBufDiagQwordCnt_OFFS 0x12170950 951#define QIB_6120_RcvEgrArray0_OFFS 0x14000952 953#define QIB_6120_RcvTIDArray0_OFFS 0x54000954 955#define QIB_6120_PIOLaunchFIFO_OFFS 0x64000956 957#define QIB_6120_SendPIOpbcCache_OFFS 0x64800958 959#define QIB_6120_RcvBuf1_OFFS 0x72000960 961#define QIB_6120_RcvBuf2_OFFS 0x75000962 963#define QIB_6120_RcvFlags_OFFS 0x77000964 965#define QIB_6120_RcvLookupBuf1_OFFS 0x79000966 967#define QIB_6120_RcvDMABuf_OFFS 0x7B000968 969#define QIB_6120_MiscRXEIntMem_OFFS 0x7C000970 971#define QIB_6120_PCIERcvBuf_OFFS 0x80000972 973#define QIB_6120_PCIERetryBuf_OFFS 0x82000974 975#define QIB_6120_PCIERcvBufRdToWrAddr_OFFS 0x84000976 977#define QIB_6120_PIOBuf0_MA_OFFS 0x100000978