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1/*2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.3 *4 *5 * This software is available to you under a choice of one of two6 * licenses. You may choose to be licensed under the terms of the GNU7 * General Public License (GPL) Version 2, available from the file8 * COPYING in the main directory of this source tree, or the9 * OpenIB.org BSD license below:10 *11 * Redistribution and use in source and binary forms, with or12 * without modification, are permitted provided that the following13 * conditions are met:14 *15 * - Redistributions of source code must retain the above16 * copyright notice, this list of conditions and the following17 * disclaimer.18 *19 * - Redistributions in binary form must reproduce the above20 * copyright notice, this list of conditions and the following21 * disclaimer in the documentation and/or other materials22 * provided with the distribution.23 *24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE31 * SOFTWARE.32 *33 */34 35/* This file is mechanically generated from RTL. Any hand-edits will be lost! */36 37#define QIB_7220_Revision_OFFS 0x038#define QIB_7220_Revision_R_Simulator_LSB 0x3F39#define QIB_7220_Revision_R_Simulator_RMASK 0x140#define QIB_7220_Revision_R_Emulation_LSB 0x3E41#define QIB_7220_Revision_R_Emulation_RMASK 0x142#define QIB_7220_Revision_R_Emulation_Revcode_LSB 0x2843#define QIB_7220_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF44#define QIB_7220_Revision_BoardID_LSB 0x2045#define QIB_7220_Revision_BoardID_RMASK 0xFF46#define QIB_7220_Revision_R_SW_LSB 0x1847#define QIB_7220_Revision_R_SW_RMASK 0xFF48#define QIB_7220_Revision_R_Arch_LSB 0x1049#define QIB_7220_Revision_R_Arch_RMASK 0xFF50#define QIB_7220_Revision_R_ChipRevMajor_LSB 0x851#define QIB_7220_Revision_R_ChipRevMajor_RMASK 0xFF52#define QIB_7220_Revision_R_ChipRevMinor_LSB 0x053#define QIB_7220_Revision_R_ChipRevMinor_RMASK 0xFF54 55#define QIB_7220_Control_OFFS 0x856#define QIB_7220_Control_SyncResetExceptPcieIRAMRST_LSB 0x757#define QIB_7220_Control_SyncResetExceptPcieIRAMRST_RMASK 0x158#define QIB_7220_Control_PCIECplQDiagEn_LSB 0x659#define QIB_7220_Control_PCIECplQDiagEn_RMASK 0x160#define QIB_7220_Control_Reserved_LSB 0x561#define QIB_7220_Control_Reserved_RMASK 0x162#define QIB_7220_Control_TxLatency_LSB 0x463#define QIB_7220_Control_TxLatency_RMASK 0x164#define QIB_7220_Control_PCIERetryBufDiagEn_LSB 0x365#define QIB_7220_Control_PCIERetryBufDiagEn_RMASK 0x166#define QIB_7220_Control_LinkEn_LSB 0x267#define QIB_7220_Control_LinkEn_RMASK 0x168#define QIB_7220_Control_FreezeMode_LSB 0x169#define QIB_7220_Control_FreezeMode_RMASK 0x170#define QIB_7220_Control_SyncReset_LSB 0x071#define QIB_7220_Control_SyncReset_RMASK 0x172 73#define QIB_7220_PageAlign_OFFS 0x1074 75#define QIB_7220_PortCnt_OFFS 0x1876 77#define QIB_7220_SendRegBase_OFFS 0x3078 79#define QIB_7220_UserRegBase_OFFS 0x3880 81#define QIB_7220_CntrRegBase_OFFS 0x4082 83#define QIB_7220_Scratch_OFFS 0x4884 85#define QIB_7220_IntMask_OFFS 0x6886#define QIB_7220_IntMask_SDmaIntMask_LSB 0x3F87#define QIB_7220_IntMask_SDmaIntMask_RMASK 0x188#define QIB_7220_IntMask_SDmaDisabledMasked_LSB 0x3E89#define QIB_7220_IntMask_SDmaDisabledMasked_RMASK 0x190#define QIB_7220_IntMask_Reserved_LSB 0x3191#define QIB_7220_IntMask_Reserved_RMASK 0x1FFF92#define QIB_7220_IntMask_RcvUrg16IntMask_LSB 0x3093#define QIB_7220_IntMask_RcvUrg16IntMask_RMASK 0x194#define QIB_7220_IntMask_RcvUrg15IntMask_LSB 0x2F95#define QIB_7220_IntMask_RcvUrg15IntMask_RMASK 0x196#define QIB_7220_IntMask_RcvUrg14IntMask_LSB 0x2E97#define QIB_7220_IntMask_RcvUrg14IntMask_RMASK 0x198#define QIB_7220_IntMask_RcvUrg13IntMask_LSB 0x2D99#define QIB_7220_IntMask_RcvUrg13IntMask_RMASK 0x1100#define QIB_7220_IntMask_RcvUrg12IntMask_LSB 0x2C101#define QIB_7220_IntMask_RcvUrg12IntMask_RMASK 0x1102#define QIB_7220_IntMask_RcvUrg11IntMask_LSB 0x2B103#define QIB_7220_IntMask_RcvUrg11IntMask_RMASK 0x1104#define QIB_7220_IntMask_RcvUrg10IntMask_LSB 0x2A105#define QIB_7220_IntMask_RcvUrg10IntMask_RMASK 0x1106#define QIB_7220_IntMask_RcvUrg9IntMask_LSB 0x29107#define QIB_7220_IntMask_RcvUrg9IntMask_RMASK 0x1108#define QIB_7220_IntMask_RcvUrg8IntMask_LSB 0x28109#define QIB_7220_IntMask_RcvUrg8IntMask_RMASK 0x1110#define QIB_7220_IntMask_RcvUrg7IntMask_LSB 0x27111#define QIB_7220_IntMask_RcvUrg7IntMask_RMASK 0x1112#define QIB_7220_IntMask_RcvUrg6IntMask_LSB 0x26113#define QIB_7220_IntMask_RcvUrg6IntMask_RMASK 0x1114#define QIB_7220_IntMask_RcvUrg5IntMask_LSB 0x25115#define QIB_7220_IntMask_RcvUrg5IntMask_RMASK 0x1116#define QIB_7220_IntMask_RcvUrg4IntMask_LSB 0x24117#define QIB_7220_IntMask_RcvUrg4IntMask_RMASK 0x1118#define QIB_7220_IntMask_RcvUrg3IntMask_LSB 0x23119#define QIB_7220_IntMask_RcvUrg3IntMask_RMASK 0x1120#define QIB_7220_IntMask_RcvUrg2IntMask_LSB 0x22121#define QIB_7220_IntMask_RcvUrg2IntMask_RMASK 0x1122#define QIB_7220_IntMask_RcvUrg1IntMask_LSB 0x21123#define QIB_7220_IntMask_RcvUrg1IntMask_RMASK 0x1124#define QIB_7220_IntMask_RcvUrg0IntMask_LSB 0x20125#define QIB_7220_IntMask_RcvUrg0IntMask_RMASK 0x1126#define QIB_7220_IntMask_ErrorIntMask_LSB 0x1F127#define QIB_7220_IntMask_ErrorIntMask_RMASK 0x1128#define QIB_7220_IntMask_PioSetIntMask_LSB 0x1E129#define QIB_7220_IntMask_PioSetIntMask_RMASK 0x1130#define QIB_7220_IntMask_PioBufAvailIntMask_LSB 0x1D131#define QIB_7220_IntMask_PioBufAvailIntMask_RMASK 0x1132#define QIB_7220_IntMask_assertGPIOIntMask_LSB 0x1C133#define QIB_7220_IntMask_assertGPIOIntMask_RMASK 0x1134#define QIB_7220_IntMask_IBSerdesTrimDoneIntMask_LSB 0x1B135#define QIB_7220_IntMask_IBSerdesTrimDoneIntMask_RMASK 0x1136#define QIB_7220_IntMask_JIntMask_LSB 0x1A137#define QIB_7220_IntMask_JIntMask_RMASK 0x1138#define QIB_7220_IntMask_Reserved1_LSB 0x11139#define QIB_7220_IntMask_Reserved1_RMASK 0x1FF140#define QIB_7220_IntMask_RcvAvail16IntMask_LSB 0x10141#define QIB_7220_IntMask_RcvAvail16IntMask_RMASK 0x1142#define QIB_7220_IntMask_RcvAvail15IntMask_LSB 0xF143#define QIB_7220_IntMask_RcvAvail15IntMask_RMASK 0x1144#define QIB_7220_IntMask_RcvAvail14IntMask_LSB 0xE145#define QIB_7220_IntMask_RcvAvail14IntMask_RMASK 0x1146#define QIB_7220_IntMask_RcvAvail13IntMask_LSB 0xD147#define QIB_7220_IntMask_RcvAvail13IntMask_RMASK 0x1148#define QIB_7220_IntMask_RcvAvail12IntMask_LSB 0xC149#define QIB_7220_IntMask_RcvAvail12IntMask_RMASK 0x1150#define QIB_7220_IntMask_RcvAvail11IntMask_LSB 0xB151#define QIB_7220_IntMask_RcvAvail11IntMask_RMASK 0x1152#define QIB_7220_IntMask_RcvAvail10IntMask_LSB 0xA153#define QIB_7220_IntMask_RcvAvail10IntMask_RMASK 0x1154#define QIB_7220_IntMask_RcvAvail9IntMask_LSB 0x9155#define QIB_7220_IntMask_RcvAvail9IntMask_RMASK 0x1156#define QIB_7220_IntMask_RcvAvail8IntMask_LSB 0x8157#define QIB_7220_IntMask_RcvAvail8IntMask_RMASK 0x1158#define QIB_7220_IntMask_RcvAvail7IntMask_LSB 0x7159#define QIB_7220_IntMask_RcvAvail7IntMask_RMASK 0x1160#define QIB_7220_IntMask_RcvAvail6IntMask_LSB 0x6161#define QIB_7220_IntMask_RcvAvail6IntMask_RMASK 0x1162#define QIB_7220_IntMask_RcvAvail5IntMask_LSB 0x5163#define QIB_7220_IntMask_RcvAvail5IntMask_RMASK 0x1164#define QIB_7220_IntMask_RcvAvail4IntMask_LSB 0x4165#define QIB_7220_IntMask_RcvAvail4IntMask_RMASK 0x1166#define QIB_7220_IntMask_RcvAvail3IntMask_LSB 0x3167#define QIB_7220_IntMask_RcvAvail3IntMask_RMASK 0x1168#define QIB_7220_IntMask_RcvAvail2IntMask_LSB 0x2169#define QIB_7220_IntMask_RcvAvail2IntMask_RMASK 0x1170#define QIB_7220_IntMask_RcvAvail1IntMask_LSB 0x1171#define QIB_7220_IntMask_RcvAvail1IntMask_RMASK 0x1172#define QIB_7220_IntMask_RcvAvail0IntMask_LSB 0x0173#define QIB_7220_IntMask_RcvAvail0IntMask_RMASK 0x1174 175#define QIB_7220_IntStatus_OFFS 0x70176#define QIB_7220_IntStatus_SDmaInt_LSB 0x3F177#define QIB_7220_IntStatus_SDmaInt_RMASK 0x1178#define QIB_7220_IntStatus_SDmaDisabled_LSB 0x3E179#define QIB_7220_IntStatus_SDmaDisabled_RMASK 0x1180#define QIB_7220_IntStatus_Reserved_LSB 0x31181#define QIB_7220_IntStatus_Reserved_RMASK 0x1FFF182#define QIB_7220_IntStatus_RcvUrg16_LSB 0x30183#define QIB_7220_IntStatus_RcvUrg16_RMASK 0x1184#define QIB_7220_IntStatus_RcvUrg15_LSB 0x2F185#define QIB_7220_IntStatus_RcvUrg15_RMASK 0x1186#define QIB_7220_IntStatus_RcvUrg14_LSB 0x2E187#define QIB_7220_IntStatus_RcvUrg14_RMASK 0x1188#define QIB_7220_IntStatus_RcvUrg13_LSB 0x2D189#define QIB_7220_IntStatus_RcvUrg13_RMASK 0x1190#define QIB_7220_IntStatus_RcvUrg12_LSB 0x2C191#define QIB_7220_IntStatus_RcvUrg12_RMASK 0x1192#define QIB_7220_IntStatus_RcvUrg11_LSB 0x2B193#define QIB_7220_IntStatus_RcvUrg11_RMASK 0x1194#define QIB_7220_IntStatus_RcvUrg10_LSB 0x2A195#define QIB_7220_IntStatus_RcvUrg10_RMASK 0x1196#define QIB_7220_IntStatus_RcvUrg9_LSB 0x29197#define QIB_7220_IntStatus_RcvUrg9_RMASK 0x1198#define QIB_7220_IntStatus_RcvUrg8_LSB 0x28199#define QIB_7220_IntStatus_RcvUrg8_RMASK 0x1200#define QIB_7220_IntStatus_RcvUrg7_LSB 0x27201#define QIB_7220_IntStatus_RcvUrg7_RMASK 0x1202#define QIB_7220_IntStatus_RcvUrg6_LSB 0x26203#define QIB_7220_IntStatus_RcvUrg6_RMASK 0x1204#define QIB_7220_IntStatus_RcvUrg5_LSB 0x25205#define QIB_7220_IntStatus_RcvUrg5_RMASK 0x1206#define QIB_7220_IntStatus_RcvUrg4_LSB 0x24207#define QIB_7220_IntStatus_RcvUrg4_RMASK 0x1208#define QIB_7220_IntStatus_RcvUrg3_LSB 0x23209#define QIB_7220_IntStatus_RcvUrg3_RMASK 0x1210#define QIB_7220_IntStatus_RcvUrg2_LSB 0x22211#define QIB_7220_IntStatus_RcvUrg2_RMASK 0x1212#define QIB_7220_IntStatus_RcvUrg1_LSB 0x21213#define QIB_7220_IntStatus_RcvUrg1_RMASK 0x1214#define QIB_7220_IntStatus_RcvUrg0_LSB 0x20215#define QIB_7220_IntStatus_RcvUrg0_RMASK 0x1216#define QIB_7220_IntStatus_Error_LSB 0x1F217#define QIB_7220_IntStatus_Error_RMASK 0x1218#define QIB_7220_IntStatus_PioSent_LSB 0x1E219#define QIB_7220_IntStatus_PioSent_RMASK 0x1220#define QIB_7220_IntStatus_PioBufAvail_LSB 0x1D221#define QIB_7220_IntStatus_PioBufAvail_RMASK 0x1222#define QIB_7220_IntStatus_assertGPIO_LSB 0x1C223#define QIB_7220_IntStatus_assertGPIO_RMASK 0x1224#define QIB_7220_IntStatus_IBSerdesTrimDone_LSB 0x1B225#define QIB_7220_IntStatus_IBSerdesTrimDone_RMASK 0x1226#define QIB_7220_IntStatus_JInt_LSB 0x1A227#define QIB_7220_IntStatus_JInt_RMASK 0x1228#define QIB_7220_IntStatus_Reserved1_LSB 0x11229#define QIB_7220_IntStatus_Reserved1_RMASK 0x1FF230#define QIB_7220_IntStatus_RcvAvail16_LSB 0x10231#define QIB_7220_IntStatus_RcvAvail16_RMASK 0x1232#define QIB_7220_IntStatus_RcvAvail15_LSB 0xF233#define QIB_7220_IntStatus_RcvAvail15_RMASK 0x1234#define QIB_7220_IntStatus_RcvAvail14_LSB 0xE235#define QIB_7220_IntStatus_RcvAvail14_RMASK 0x1236#define QIB_7220_IntStatus_RcvAvail13_LSB 0xD237#define QIB_7220_IntStatus_RcvAvail13_RMASK 0x1238#define QIB_7220_IntStatus_RcvAvail12_LSB 0xC239#define QIB_7220_IntStatus_RcvAvail12_RMASK 0x1240#define QIB_7220_IntStatus_RcvAvail11_LSB 0xB241#define QIB_7220_IntStatus_RcvAvail11_RMASK 0x1242#define QIB_7220_IntStatus_RcvAvail10_LSB 0xA243#define QIB_7220_IntStatus_RcvAvail10_RMASK 0x1244#define QIB_7220_IntStatus_RcvAvail9_LSB 0x9245#define QIB_7220_IntStatus_RcvAvail9_RMASK 0x1246#define QIB_7220_IntStatus_RcvAvail8_LSB 0x8247#define QIB_7220_IntStatus_RcvAvail8_RMASK 0x1248#define QIB_7220_IntStatus_RcvAvail7_LSB 0x7249#define QIB_7220_IntStatus_RcvAvail7_RMASK 0x1250#define QIB_7220_IntStatus_RcvAvail6_LSB 0x6251#define QIB_7220_IntStatus_RcvAvail6_RMASK 0x1252#define QIB_7220_IntStatus_RcvAvail5_LSB 0x5253#define QIB_7220_IntStatus_RcvAvail5_RMASK 0x1254#define QIB_7220_IntStatus_RcvAvail4_LSB 0x4255#define QIB_7220_IntStatus_RcvAvail4_RMASK 0x1256#define QIB_7220_IntStatus_RcvAvail3_LSB 0x3257#define QIB_7220_IntStatus_RcvAvail3_RMASK 0x1258#define QIB_7220_IntStatus_RcvAvail2_LSB 0x2259#define QIB_7220_IntStatus_RcvAvail2_RMASK 0x1260#define QIB_7220_IntStatus_RcvAvail1_LSB 0x1261#define QIB_7220_IntStatus_RcvAvail1_RMASK 0x1262#define QIB_7220_IntStatus_RcvAvail0_LSB 0x0263#define QIB_7220_IntStatus_RcvAvail0_RMASK 0x1264 265#define QIB_7220_IntClear_OFFS 0x78266#define QIB_7220_IntClear_SDmaIntClear_LSB 0x3F267#define QIB_7220_IntClear_SDmaIntClear_RMASK 0x1268#define QIB_7220_IntClear_SDmaDisabledClear_LSB 0x3E269#define QIB_7220_IntClear_SDmaDisabledClear_RMASK 0x1270#define QIB_7220_IntClear_Reserved_LSB 0x31271#define QIB_7220_IntClear_Reserved_RMASK 0x1FFF272#define QIB_7220_IntClear_RcvUrg16IntClear_LSB 0x30273#define QIB_7220_IntClear_RcvUrg16IntClear_RMASK 0x1274#define QIB_7220_IntClear_RcvUrg15IntClear_LSB 0x2F275#define QIB_7220_IntClear_RcvUrg15IntClear_RMASK 0x1276#define QIB_7220_IntClear_RcvUrg14IntClear_LSB 0x2E277#define QIB_7220_IntClear_RcvUrg14IntClear_RMASK 0x1278#define QIB_7220_IntClear_RcvUrg13IntClear_LSB 0x2D279#define QIB_7220_IntClear_RcvUrg13IntClear_RMASK 0x1280#define QIB_7220_IntClear_RcvUrg12IntClear_LSB 0x2C281#define QIB_7220_IntClear_RcvUrg12IntClear_RMASK 0x1282#define QIB_7220_IntClear_RcvUrg11IntClear_LSB 0x2B283#define QIB_7220_IntClear_RcvUrg11IntClear_RMASK 0x1284#define QIB_7220_IntClear_RcvUrg10IntClear_LSB 0x2A285#define QIB_7220_IntClear_RcvUrg10IntClear_RMASK 0x1286#define QIB_7220_IntClear_RcvUrg9IntClear_LSB 0x29287#define QIB_7220_IntClear_RcvUrg9IntClear_RMASK 0x1288#define QIB_7220_IntClear_RcvUrg8IntClear_LSB 0x28289#define QIB_7220_IntClear_RcvUrg8IntClear_RMASK 0x1290#define QIB_7220_IntClear_RcvUrg7IntClear_LSB 0x27291#define QIB_7220_IntClear_RcvUrg7IntClear_RMASK 0x1292#define QIB_7220_IntClear_RcvUrg6IntClear_LSB 0x26293#define QIB_7220_IntClear_RcvUrg6IntClear_RMASK 0x1294#define QIB_7220_IntClear_RcvUrg5IntClear_LSB 0x25295#define QIB_7220_IntClear_RcvUrg5IntClear_RMASK 0x1296#define QIB_7220_IntClear_RcvUrg4IntClear_LSB 0x24297#define QIB_7220_IntClear_RcvUrg4IntClear_RMASK 0x1298#define QIB_7220_IntClear_RcvUrg3IntClear_LSB 0x23299#define QIB_7220_IntClear_RcvUrg3IntClear_RMASK 0x1300#define QIB_7220_IntClear_RcvUrg2IntClear_LSB 0x22301#define QIB_7220_IntClear_RcvUrg2IntClear_RMASK 0x1302#define QIB_7220_IntClear_RcvUrg1IntClear_LSB 0x21303#define QIB_7220_IntClear_RcvUrg1IntClear_RMASK 0x1304#define QIB_7220_IntClear_RcvUrg0IntClear_LSB 0x20305#define QIB_7220_IntClear_RcvUrg0IntClear_RMASK 0x1306#define QIB_7220_IntClear_ErrorIntClear_LSB 0x1F307#define QIB_7220_IntClear_ErrorIntClear_RMASK 0x1308#define QIB_7220_IntClear_PioSetIntClear_LSB 0x1E309#define QIB_7220_IntClear_PioSetIntClear_RMASK 0x1310#define QIB_7220_IntClear_PioBufAvailIntClear_LSB 0x1D311#define QIB_7220_IntClear_PioBufAvailIntClear_RMASK 0x1312#define QIB_7220_IntClear_assertGPIOIntClear_LSB 0x1C313#define QIB_7220_IntClear_assertGPIOIntClear_RMASK 0x1314#define QIB_7220_IntClear_IBSerdesTrimDoneClear_LSB 0x1B315#define QIB_7220_IntClear_IBSerdesTrimDoneClear_RMASK 0x1316#define QIB_7220_IntClear_JIntClear_LSB 0x1A317#define QIB_7220_IntClear_JIntClear_RMASK 0x1318#define QIB_7220_IntClear_Reserved1_LSB 0x11319#define QIB_7220_IntClear_Reserved1_RMASK 0x1FF320#define QIB_7220_IntClear_RcvAvail16IntClear_LSB 0x10321#define QIB_7220_IntClear_RcvAvail16IntClear_RMASK 0x1322#define QIB_7220_IntClear_RcvAvail15IntClear_LSB 0xF323#define QIB_7220_IntClear_RcvAvail15IntClear_RMASK 0x1324#define QIB_7220_IntClear_RcvAvail14IntClear_LSB 0xE325#define QIB_7220_IntClear_RcvAvail14IntClear_RMASK 0x1326#define QIB_7220_IntClear_RcvAvail13IntClear_LSB 0xD327#define QIB_7220_IntClear_RcvAvail13IntClear_RMASK 0x1328#define QIB_7220_IntClear_RcvAvail12IntClear_LSB 0xC329#define QIB_7220_IntClear_RcvAvail12IntClear_RMASK 0x1330#define QIB_7220_IntClear_RcvAvail11IntClear_LSB 0xB331#define QIB_7220_IntClear_RcvAvail11IntClear_RMASK 0x1332#define QIB_7220_IntClear_RcvAvail10IntClear_LSB 0xA333#define QIB_7220_IntClear_RcvAvail10IntClear_RMASK 0x1334#define QIB_7220_IntClear_RcvAvail9IntClear_LSB 0x9335#define QIB_7220_IntClear_RcvAvail9IntClear_RMASK 0x1336#define QIB_7220_IntClear_RcvAvail8IntClear_LSB 0x8337#define QIB_7220_IntClear_RcvAvail8IntClear_RMASK 0x1338#define QIB_7220_IntClear_RcvAvail7IntClear_LSB 0x7339#define QIB_7220_IntClear_RcvAvail7IntClear_RMASK 0x1340#define QIB_7220_IntClear_RcvAvail6IntClear_LSB 0x6341#define QIB_7220_IntClear_RcvAvail6IntClear_RMASK 0x1342#define QIB_7220_IntClear_RcvAvail5IntClear_LSB 0x5343#define QIB_7220_IntClear_RcvAvail5IntClear_RMASK 0x1344#define QIB_7220_IntClear_RcvAvail4IntClear_LSB 0x4345#define QIB_7220_IntClear_RcvAvail4IntClear_RMASK 0x1346#define QIB_7220_IntClear_RcvAvail3IntClear_LSB 0x3347#define QIB_7220_IntClear_RcvAvail3IntClear_RMASK 0x1348#define QIB_7220_IntClear_RcvAvail2IntClear_LSB 0x2349#define QIB_7220_IntClear_RcvAvail2IntClear_RMASK 0x1350#define QIB_7220_IntClear_RcvAvail1IntClear_LSB 0x1351#define QIB_7220_IntClear_RcvAvail1IntClear_RMASK 0x1352#define QIB_7220_IntClear_RcvAvail0IntClear_LSB 0x0353#define QIB_7220_IntClear_RcvAvail0IntClear_RMASK 0x1354 355#define QIB_7220_ErrMask_OFFS 0x80356#define QIB_7220_ErrMask_Reserved_LSB 0x36357#define QIB_7220_ErrMask_Reserved_RMASK 0x3FF358#define QIB_7220_ErrMask_InvalidEEPCmdMask_LSB 0x35359#define QIB_7220_ErrMask_InvalidEEPCmdMask_RMASK 0x1360#define QIB_7220_ErrMask_SDmaDescAddrMisalignErrMask_LSB 0x34361#define QIB_7220_ErrMask_SDmaDescAddrMisalignErrMask_RMASK 0x1362#define QIB_7220_ErrMask_HardwareErrMask_LSB 0x33363#define QIB_7220_ErrMask_HardwareErrMask_RMASK 0x1364#define QIB_7220_ErrMask_ResetNegatedMask_LSB 0x32365#define QIB_7220_ErrMask_ResetNegatedMask_RMASK 0x1366#define QIB_7220_ErrMask_InvalidAddrErrMask_LSB 0x31367#define QIB_7220_ErrMask_InvalidAddrErrMask_RMASK 0x1368#define QIB_7220_ErrMask_IBStatusChangedMask_LSB 0x30369#define QIB_7220_ErrMask_IBStatusChangedMask_RMASK 0x1370#define QIB_7220_ErrMask_SDmaUnexpDataErrMask_LSB 0x2F371#define QIB_7220_ErrMask_SDmaUnexpDataErrMask_RMASK 0x1372#define QIB_7220_ErrMask_SDmaMissingDwErrMask_LSB 0x2E373#define QIB_7220_ErrMask_SDmaMissingDwErrMask_RMASK 0x1374#define QIB_7220_ErrMask_SDmaDwEnErrMask_LSB 0x2D375#define QIB_7220_ErrMask_SDmaDwEnErrMask_RMASK 0x1376#define QIB_7220_ErrMask_SDmaRpyTagErrMask_LSB 0x2C377#define QIB_7220_ErrMask_SDmaRpyTagErrMask_RMASK 0x1378#define QIB_7220_ErrMask_SDma1stDescErrMask_LSB 0x2B379#define QIB_7220_ErrMask_SDma1stDescErrMask_RMASK 0x1380#define QIB_7220_ErrMask_SDmaBaseErrMask_LSB 0x2A381#define QIB_7220_ErrMask_SDmaBaseErrMask_RMASK 0x1382#define QIB_7220_ErrMask_SDmaTailOutOfBoundErrMask_LSB 0x29383#define QIB_7220_ErrMask_SDmaTailOutOfBoundErrMask_RMASK 0x1384#define QIB_7220_ErrMask_SDmaOutOfBoundErrMask_LSB 0x28385#define QIB_7220_ErrMask_SDmaOutOfBoundErrMask_RMASK 0x1386#define QIB_7220_ErrMask_SDmaGenMismatchErrMask_LSB 0x27387#define QIB_7220_ErrMask_SDmaGenMismatchErrMask_RMASK 0x1388#define QIB_7220_ErrMask_SendBufMisuseErrMask_LSB 0x26389#define QIB_7220_ErrMask_SendBufMisuseErrMask_RMASK 0x1390#define QIB_7220_ErrMask_SendUnsupportedVLErrMask_LSB 0x25391#define QIB_7220_ErrMask_SendUnsupportedVLErrMask_RMASK 0x1392#define QIB_7220_ErrMask_SendUnexpectedPktNumErrMask_LSB 0x24393#define QIB_7220_ErrMask_SendUnexpectedPktNumErrMask_RMASK 0x1394#define QIB_7220_ErrMask_SendPioArmLaunchErrMask_LSB 0x23395#define QIB_7220_ErrMask_SendPioArmLaunchErrMask_RMASK 0x1396#define QIB_7220_ErrMask_SendDroppedDataPktErrMask_LSB 0x22397#define QIB_7220_ErrMask_SendDroppedDataPktErrMask_RMASK 0x1398#define QIB_7220_ErrMask_SendDroppedSmpPktErrMask_LSB 0x21399#define QIB_7220_ErrMask_SendDroppedSmpPktErrMask_RMASK 0x1400#define QIB_7220_ErrMask_SendPktLenErrMask_LSB 0x20401#define QIB_7220_ErrMask_SendPktLenErrMask_RMASK 0x1402#define QIB_7220_ErrMask_SendUnderRunErrMask_LSB 0x1F403#define QIB_7220_ErrMask_SendUnderRunErrMask_RMASK 0x1404#define QIB_7220_ErrMask_SendMaxPktLenErrMask_LSB 0x1E405#define QIB_7220_ErrMask_SendMaxPktLenErrMask_RMASK 0x1406#define QIB_7220_ErrMask_SendMinPktLenErrMask_LSB 0x1D407#define QIB_7220_ErrMask_SendMinPktLenErrMask_RMASK 0x1408#define QIB_7220_ErrMask_SDmaDisabledErrMask_LSB 0x1C409#define QIB_7220_ErrMask_SDmaDisabledErrMask_RMASK 0x1410#define QIB_7220_ErrMask_SendSpecialTriggerErrMask_LSB 0x1B411#define QIB_7220_ErrMask_SendSpecialTriggerErrMask_RMASK 0x1412#define QIB_7220_ErrMask_Reserved1_LSB 0x12413#define QIB_7220_ErrMask_Reserved1_RMASK 0x1FF414#define QIB_7220_ErrMask_RcvIBLostLinkErrMask_LSB 0x11415#define QIB_7220_ErrMask_RcvIBLostLinkErrMask_RMASK 0x1416#define QIB_7220_ErrMask_RcvHdrErrMask_LSB 0x10417#define QIB_7220_ErrMask_RcvHdrErrMask_RMASK 0x1418#define QIB_7220_ErrMask_RcvHdrLenErrMask_LSB 0xF419#define QIB_7220_ErrMask_RcvHdrLenErrMask_RMASK 0x1420#define QIB_7220_ErrMask_RcvBadTidErrMask_LSB 0xE421#define QIB_7220_ErrMask_RcvBadTidErrMask_RMASK 0x1422#define QIB_7220_ErrMask_RcvHdrFullErrMask_LSB 0xD423#define QIB_7220_ErrMask_RcvHdrFullErrMask_RMASK 0x1424#define QIB_7220_ErrMask_RcvEgrFullErrMask_LSB 0xC425#define QIB_7220_ErrMask_RcvEgrFullErrMask_RMASK 0x1426#define QIB_7220_ErrMask_RcvBadVersionErrMask_LSB 0xB427#define QIB_7220_ErrMask_RcvBadVersionErrMask_RMASK 0x1428#define QIB_7220_ErrMask_RcvIBFlowErrMask_LSB 0xA429#define QIB_7220_ErrMask_RcvIBFlowErrMask_RMASK 0x1430#define QIB_7220_ErrMask_RcvEBPErrMask_LSB 0x9431#define QIB_7220_ErrMask_RcvEBPErrMask_RMASK 0x1432#define QIB_7220_ErrMask_RcvUnsupportedVLErrMask_LSB 0x8433#define QIB_7220_ErrMask_RcvUnsupportedVLErrMask_RMASK 0x1434#define QIB_7220_ErrMask_RcvUnexpectedCharErrMask_LSB 0x7435#define QIB_7220_ErrMask_RcvUnexpectedCharErrMask_RMASK 0x1436#define QIB_7220_ErrMask_RcvShortPktLenErrMask_LSB 0x6437#define QIB_7220_ErrMask_RcvShortPktLenErrMask_RMASK 0x1438#define QIB_7220_ErrMask_RcvLongPktLenErrMask_LSB 0x5439#define QIB_7220_ErrMask_RcvLongPktLenErrMask_RMASK 0x1440#define QIB_7220_ErrMask_RcvMaxPktLenErrMask_LSB 0x4441#define QIB_7220_ErrMask_RcvMaxPktLenErrMask_RMASK 0x1442#define QIB_7220_ErrMask_RcvMinPktLenErrMask_LSB 0x3443#define QIB_7220_ErrMask_RcvMinPktLenErrMask_RMASK 0x1444#define QIB_7220_ErrMask_RcvICRCErrMask_LSB 0x2445#define QIB_7220_ErrMask_RcvICRCErrMask_RMASK 0x1446#define QIB_7220_ErrMask_RcvVCRCErrMask_LSB 0x1447#define QIB_7220_ErrMask_RcvVCRCErrMask_RMASK 0x1448#define QIB_7220_ErrMask_RcvFormatErrMask_LSB 0x0449#define QIB_7220_ErrMask_RcvFormatErrMask_RMASK 0x1450 451#define QIB_7220_ErrStatus_OFFS 0x88452#define QIB_7220_ErrStatus_Reserved_LSB 0x36453#define QIB_7220_ErrStatus_Reserved_RMASK 0x3FF454#define QIB_7220_ErrStatus_InvalidEEPCmdErr_LSB 0x35455#define QIB_7220_ErrStatus_InvalidEEPCmdErr_RMASK 0x1456#define QIB_7220_ErrStatus_SDmaDescAddrMisalignErr_LSB 0x34457#define QIB_7220_ErrStatus_SDmaDescAddrMisalignErr_RMASK 0x1458#define QIB_7220_ErrStatus_HardwareErr_LSB 0x33459#define QIB_7220_ErrStatus_HardwareErr_RMASK 0x1460#define QIB_7220_ErrStatus_ResetNegated_LSB 0x32461#define QIB_7220_ErrStatus_ResetNegated_RMASK 0x1462#define QIB_7220_ErrStatus_InvalidAddrErr_LSB 0x31463#define QIB_7220_ErrStatus_InvalidAddrErr_RMASK 0x1464#define QIB_7220_ErrStatus_IBStatusChanged_LSB 0x30465#define QIB_7220_ErrStatus_IBStatusChanged_RMASK 0x1466#define QIB_7220_ErrStatus_SDmaUnexpDataErr_LSB 0x2F467#define QIB_7220_ErrStatus_SDmaUnexpDataErr_RMASK 0x1468#define QIB_7220_ErrStatus_SDmaMissingDwErr_LSB 0x2E469#define QIB_7220_ErrStatus_SDmaMissingDwErr_RMASK 0x1470#define QIB_7220_ErrStatus_SDmaDwEnErr_LSB 0x2D471#define QIB_7220_ErrStatus_SDmaDwEnErr_RMASK 0x1472#define QIB_7220_ErrStatus_SDmaRpyTagErr_LSB 0x2C473#define QIB_7220_ErrStatus_SDmaRpyTagErr_RMASK 0x1474#define QIB_7220_ErrStatus_SDma1stDescErr_LSB 0x2B475#define QIB_7220_ErrStatus_SDma1stDescErr_RMASK 0x1476#define QIB_7220_ErrStatus_SDmaBaseErr_LSB 0x2A477#define QIB_7220_ErrStatus_SDmaBaseErr_RMASK 0x1478#define QIB_7220_ErrStatus_SDmaTailOutOfBoundErr_LSB 0x29479#define QIB_7220_ErrStatus_SDmaTailOutOfBoundErr_RMASK 0x1480#define QIB_7220_ErrStatus_SDmaOutOfBoundErr_LSB 0x28481#define QIB_7220_ErrStatus_SDmaOutOfBoundErr_RMASK 0x1482#define QIB_7220_ErrStatus_SDmaGenMismatchErr_LSB 0x27483#define QIB_7220_ErrStatus_SDmaGenMismatchErr_RMASK 0x1484#define QIB_7220_ErrStatus_SendBufMisuseErr_LSB 0x26485#define QIB_7220_ErrStatus_SendBufMisuseErr_RMASK 0x1486#define QIB_7220_ErrStatus_SendUnsupportedVLErr_LSB 0x25487#define QIB_7220_ErrStatus_SendUnsupportedVLErr_RMASK 0x1488#define QIB_7220_ErrStatus_SendUnexpectedPktNumErr_LSB 0x24489#define QIB_7220_ErrStatus_SendUnexpectedPktNumErr_RMASK 0x1490#define QIB_7220_ErrStatus_SendPioArmLaunchErr_LSB 0x23491#define QIB_7220_ErrStatus_SendPioArmLaunchErr_RMASK 0x1492#define QIB_7220_ErrStatus_SendDroppedDataPktErr_LSB 0x22493#define QIB_7220_ErrStatus_SendDroppedDataPktErr_RMASK 0x1494#define QIB_7220_ErrStatus_SendDroppedSmpPktErr_LSB 0x21495#define QIB_7220_ErrStatus_SendDroppedSmpPktErr_RMASK 0x1496#define QIB_7220_ErrStatus_SendPktLenErr_LSB 0x20497#define QIB_7220_ErrStatus_SendPktLenErr_RMASK 0x1498#define QIB_7220_ErrStatus_SendUnderRunErr_LSB 0x1F499#define QIB_7220_ErrStatus_SendUnderRunErr_RMASK 0x1500#define QIB_7220_ErrStatus_SendMaxPktLenErr_LSB 0x1E501#define QIB_7220_ErrStatus_SendMaxPktLenErr_RMASK 0x1502#define QIB_7220_ErrStatus_SendMinPktLenErr_LSB 0x1D503#define QIB_7220_ErrStatus_SendMinPktLenErr_RMASK 0x1504#define QIB_7220_ErrStatus_SDmaDisabledErr_LSB 0x1C505#define QIB_7220_ErrStatus_SDmaDisabledErr_RMASK 0x1506#define QIB_7220_ErrStatus_SendSpecialTriggerErr_LSB 0x1B507#define QIB_7220_ErrStatus_SendSpecialTriggerErr_RMASK 0x1508#define QIB_7220_ErrStatus_Reserved1_LSB 0x12509#define QIB_7220_ErrStatus_Reserved1_RMASK 0x1FF510#define QIB_7220_ErrStatus_RcvIBLostLinkErr_LSB 0x11511#define QIB_7220_ErrStatus_RcvIBLostLinkErr_RMASK 0x1512#define QIB_7220_ErrStatus_RcvHdrErr_LSB 0x10513#define QIB_7220_ErrStatus_RcvHdrErr_RMASK 0x1514#define QIB_7220_ErrStatus_RcvHdrLenErr_LSB 0xF515#define QIB_7220_ErrStatus_RcvHdrLenErr_RMASK 0x1516#define QIB_7220_ErrStatus_RcvBadTidErr_LSB 0xE517#define QIB_7220_ErrStatus_RcvBadTidErr_RMASK 0x1518#define QIB_7220_ErrStatus_RcvHdrFullErr_LSB 0xD519#define QIB_7220_ErrStatus_RcvHdrFullErr_RMASK 0x1520#define QIB_7220_ErrStatus_RcvEgrFullErr_LSB 0xC521#define QIB_7220_ErrStatus_RcvEgrFullErr_RMASK 0x1522#define QIB_7220_ErrStatus_RcvBadVersionErr_LSB 0xB523#define QIB_7220_ErrStatus_RcvBadVersionErr_RMASK 0x1524#define QIB_7220_ErrStatus_RcvIBFlowErr_LSB 0xA525#define QIB_7220_ErrStatus_RcvIBFlowErr_RMASK 0x1526#define QIB_7220_ErrStatus_RcvEBPErr_LSB 0x9527#define QIB_7220_ErrStatus_RcvEBPErr_RMASK 0x1528#define QIB_7220_ErrStatus_RcvUnsupportedVLErr_LSB 0x8529#define QIB_7220_ErrStatus_RcvUnsupportedVLErr_RMASK 0x1530#define QIB_7220_ErrStatus_RcvUnexpectedCharErr_LSB 0x7531#define QIB_7220_ErrStatus_RcvUnexpectedCharErr_RMASK 0x1532#define QIB_7220_ErrStatus_RcvShortPktLenErr_LSB 0x6533#define QIB_7220_ErrStatus_RcvShortPktLenErr_RMASK 0x1534#define QIB_7220_ErrStatus_RcvLongPktLenErr_LSB 0x5535#define QIB_7220_ErrStatus_RcvLongPktLenErr_RMASK 0x1536#define QIB_7220_ErrStatus_RcvMaxPktLenErr_LSB 0x4537#define QIB_7220_ErrStatus_RcvMaxPktLenErr_RMASK 0x1538#define QIB_7220_ErrStatus_RcvMinPktLenErr_LSB 0x3539#define QIB_7220_ErrStatus_RcvMinPktLenErr_RMASK 0x1540#define QIB_7220_ErrStatus_RcvICRCErr_LSB 0x2541#define QIB_7220_ErrStatus_RcvICRCErr_RMASK 0x1542#define QIB_7220_ErrStatus_RcvVCRCErr_LSB 0x1543#define QIB_7220_ErrStatus_RcvVCRCErr_RMASK 0x1544#define QIB_7220_ErrStatus_RcvFormatErr_LSB 0x0545#define QIB_7220_ErrStatus_RcvFormatErr_RMASK 0x1546 547#define QIB_7220_ErrClear_OFFS 0x90548#define QIB_7220_ErrClear_Reserved_LSB 0x36549#define QIB_7220_ErrClear_Reserved_RMASK 0x3FF550#define QIB_7220_ErrClear_InvalidEEPCmdErrClear_LSB 0x35551#define QIB_7220_ErrClear_InvalidEEPCmdErrClear_RMASK 0x1552#define QIB_7220_ErrClear_SDmaDescAddrMisalignErrClear_LSB 0x34553#define QIB_7220_ErrClear_SDmaDescAddrMisalignErrClear_RMASK 0x1554#define QIB_7220_ErrClear_HardwareErrClear_LSB 0x33555#define QIB_7220_ErrClear_HardwareErrClear_RMASK 0x1556#define QIB_7220_ErrClear_ResetNegatedClear_LSB 0x32557#define QIB_7220_ErrClear_ResetNegatedClear_RMASK 0x1558#define QIB_7220_ErrClear_InvalidAddrErrClear_LSB 0x31559#define QIB_7220_ErrClear_InvalidAddrErrClear_RMASK 0x1560#define QIB_7220_ErrClear_IBStatusChangedClear_LSB 0x30561#define QIB_7220_ErrClear_IBStatusChangedClear_RMASK 0x1562#define QIB_7220_ErrClear_SDmaUnexpDataErrClear_LSB 0x2F563#define QIB_7220_ErrClear_SDmaUnexpDataErrClear_RMASK 0x1564#define QIB_7220_ErrClear_SDmaMissingDwErrClear_LSB 0x2E565#define QIB_7220_ErrClear_SDmaMissingDwErrClear_RMASK 0x1566#define QIB_7220_ErrClear_SDmaDwEnErrClear_LSB 0x2D567#define QIB_7220_ErrClear_SDmaDwEnErrClear_RMASK 0x1568#define QIB_7220_ErrClear_SDmaRpyTagErrClear_LSB 0x2C569#define QIB_7220_ErrClear_SDmaRpyTagErrClear_RMASK 0x1570#define QIB_7220_ErrClear_SDma1stDescErrClear_LSB 0x2B571#define QIB_7220_ErrClear_SDma1stDescErrClear_RMASK 0x1572#define QIB_7220_ErrClear_SDmaBaseErrClear_LSB 0x2A573#define QIB_7220_ErrClear_SDmaBaseErrClear_RMASK 0x1574#define QIB_7220_ErrClear_SDmaTailOutOfBoundErrClear_LSB 0x29575#define QIB_7220_ErrClear_SDmaTailOutOfBoundErrClear_RMASK 0x1576#define QIB_7220_ErrClear_SDmaOutOfBoundErrClear_LSB 0x28577#define QIB_7220_ErrClear_SDmaOutOfBoundErrClear_RMASK 0x1578#define QIB_7220_ErrClear_SDmaGenMismatchErrClear_LSB 0x27579#define QIB_7220_ErrClear_SDmaGenMismatchErrClear_RMASK 0x1580#define QIB_7220_ErrClear_SendBufMisuseErrClear_LSB 0x26581#define QIB_7220_ErrClear_SendBufMisuseErrClear_RMASK 0x1582#define QIB_7220_ErrClear_SendUnsupportedVLErrClear_LSB 0x25583#define QIB_7220_ErrClear_SendUnsupportedVLErrClear_RMASK 0x1584#define QIB_7220_ErrClear_SendUnexpectedPktNumErrClear_LSB 0x24585#define QIB_7220_ErrClear_SendUnexpectedPktNumErrClear_RMASK 0x1586#define QIB_7220_ErrClear_SendPioArmLaunchErrClear_LSB 0x23587#define QIB_7220_ErrClear_SendPioArmLaunchErrClear_RMASK 0x1588#define QIB_7220_ErrClear_SendDroppedDataPktErrClear_LSB 0x22589#define QIB_7220_ErrClear_SendDroppedDataPktErrClear_RMASK 0x1590#define QIB_7220_ErrClear_SendDroppedSmpPktErrClear_LSB 0x21591#define QIB_7220_ErrClear_SendDroppedSmpPktErrClear_RMASK 0x1592#define QIB_7220_ErrClear_SendPktLenErrClear_LSB 0x20593#define QIB_7220_ErrClear_SendPktLenErrClear_RMASK 0x1594#define QIB_7220_ErrClear_SendUnderRunErrClear_LSB 0x1F595#define QIB_7220_ErrClear_SendUnderRunErrClear_RMASK 0x1596#define QIB_7220_ErrClear_SendMaxPktLenErrClear_LSB 0x1E597#define QIB_7220_ErrClear_SendMaxPktLenErrClear_RMASK 0x1598#define QIB_7220_ErrClear_SendMinPktLenErrClear_LSB 0x1D599#define QIB_7220_ErrClear_SendMinPktLenErrClear_RMASK 0x1600#define QIB_7220_ErrClear_SDmaDisabledErrClear_LSB 0x1C601#define QIB_7220_ErrClear_SDmaDisabledErrClear_RMASK 0x1602#define QIB_7220_ErrClear_SendSpecialTriggerErrClear_LSB 0x1B603#define QIB_7220_ErrClear_SendSpecialTriggerErrClear_RMASK 0x1604#define QIB_7220_ErrClear_Reserved1_LSB 0x12605#define QIB_7220_ErrClear_Reserved1_RMASK 0x1FF606#define QIB_7220_ErrClear_RcvIBLostLinkErrClear_LSB 0x11607#define QIB_7220_ErrClear_RcvIBLostLinkErrClear_RMASK 0x1608#define QIB_7220_ErrClear_RcvHdrErrClear_LSB 0x10609#define QIB_7220_ErrClear_RcvHdrErrClear_RMASK 0x1610#define QIB_7220_ErrClear_RcvHdrLenErrClear_LSB 0xF611#define QIB_7220_ErrClear_RcvHdrLenErrClear_RMASK 0x1612#define QIB_7220_ErrClear_RcvBadTidErrClear_LSB 0xE613#define QIB_7220_ErrClear_RcvBadTidErrClear_RMASK 0x1614#define QIB_7220_ErrClear_RcvHdrFullErrClear_LSB 0xD615#define QIB_7220_ErrClear_RcvHdrFullErrClear_RMASK 0x1616#define QIB_7220_ErrClear_RcvEgrFullErrClear_LSB 0xC617#define QIB_7220_ErrClear_RcvEgrFullErrClear_RMASK 0x1618#define QIB_7220_ErrClear_RcvBadVersionErrClear_LSB 0xB619#define QIB_7220_ErrClear_RcvBadVersionErrClear_RMASK 0x1620#define QIB_7220_ErrClear_RcvIBFlowErrClear_LSB 0xA621#define QIB_7220_ErrClear_RcvIBFlowErrClear_RMASK 0x1622#define QIB_7220_ErrClear_RcvEBPErrClear_LSB 0x9623#define QIB_7220_ErrClear_RcvEBPErrClear_RMASK 0x1624#define QIB_7220_ErrClear_RcvUnsupportedVLErrClear_LSB 0x8625#define QIB_7220_ErrClear_RcvUnsupportedVLErrClear_RMASK 0x1626#define QIB_7220_ErrClear_RcvUnexpectedCharErrClear_LSB 0x7627#define QIB_7220_ErrClear_RcvUnexpectedCharErrClear_RMASK 0x1628#define QIB_7220_ErrClear_RcvShortPktLenErrClear_LSB 0x6629#define QIB_7220_ErrClear_RcvShortPktLenErrClear_RMASK 0x1630#define QIB_7220_ErrClear_RcvLongPktLenErrClear_LSB 0x5631#define QIB_7220_ErrClear_RcvLongPktLenErrClear_RMASK 0x1632#define QIB_7220_ErrClear_RcvMaxPktLenErrClear_LSB 0x4633#define QIB_7220_ErrClear_RcvMaxPktLenErrClear_RMASK 0x1634#define QIB_7220_ErrClear_RcvMinPktLenErrClear_LSB 0x3635#define QIB_7220_ErrClear_RcvMinPktLenErrClear_RMASK 0x1636#define QIB_7220_ErrClear_RcvICRCErrClear_LSB 0x2637#define QIB_7220_ErrClear_RcvICRCErrClear_RMASK 0x1638#define QIB_7220_ErrClear_RcvVCRCErrClear_LSB 0x1639#define QIB_7220_ErrClear_RcvVCRCErrClear_RMASK 0x1640#define QIB_7220_ErrClear_RcvFormatErrClear_LSB 0x0641#define QIB_7220_ErrClear_RcvFormatErrClear_RMASK 0x1642 643#define QIB_7220_HwErrMask_OFFS 0x98644#define QIB_7220_HwErrMask_IBCBusFromSPCParityErrMask_LSB 0x3F645#define QIB_7220_HwErrMask_IBCBusFromSPCParityErrMask_RMASK 0x1646#define QIB_7220_HwErrMask_IBCBusToSPCParityErrMask_LSB 0x3E647#define QIB_7220_HwErrMask_IBCBusToSPCParityErrMask_RMASK 0x1648#define QIB_7220_HwErrMask_Clk_uC_PLLNotLockedMask_LSB 0x3D649#define QIB_7220_HwErrMask_Clk_uC_PLLNotLockedMask_RMASK 0x1650#define QIB_7220_HwErrMask_IBSerdesPClkNotDetectMask_LSB 0x3C651#define QIB_7220_HwErrMask_IBSerdesPClkNotDetectMask_RMASK 0x1652#define QIB_7220_HwErrMask_PCIESerdesQ3PClkNotDetectMask_LSB 0x3B653#define QIB_7220_HwErrMask_PCIESerdesQ3PClkNotDetectMask_RMASK 0x1654#define QIB_7220_HwErrMask_PCIESerdesQ2PClkNotDetectMask_LSB 0x3A655#define QIB_7220_HwErrMask_PCIESerdesQ2PClkNotDetectMask_RMASK 0x1656#define QIB_7220_HwErrMask_PCIESerdesQ1PClkNotDetectMask_LSB 0x39657#define QIB_7220_HwErrMask_PCIESerdesQ1PClkNotDetectMask_RMASK 0x1658#define QIB_7220_HwErrMask_PCIESerdesQ0PClkNotDetectMask_LSB 0x38659#define QIB_7220_HwErrMask_PCIESerdesQ0PClkNotDetectMask_RMASK 0x1660#define QIB_7220_HwErrMask_Reserved_LSB 0x37661#define QIB_7220_HwErrMask_Reserved_RMASK 0x1662#define QIB_7220_HwErrMask_PowerOnBISTFailedMask_LSB 0x36663#define QIB_7220_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1664#define QIB_7220_HwErrMask_Reserved1_LSB 0x33665#define QIB_7220_HwErrMask_Reserved1_RMASK 0x7666#define QIB_7220_HwErrMask_RXEMemParityErrMask_LSB 0x2C667#define QIB_7220_HwErrMask_RXEMemParityErrMask_RMASK 0x7F668#define QIB_7220_HwErrMask_TXEMemParityErrMask_LSB 0x28669#define QIB_7220_HwErrMask_TXEMemParityErrMask_RMASK 0xF670#define QIB_7220_HwErrMask_DDSRXEQMemoryParityErrMask_LSB 0x27671#define QIB_7220_HwErrMask_DDSRXEQMemoryParityErrMask_RMASK 0x1672#define QIB_7220_HwErrMask_IB_uC_MemoryParityErrMask_LSB 0x26673#define QIB_7220_HwErrMask_IB_uC_MemoryParityErrMask_RMASK 0x1674#define QIB_7220_HwErrMask_PCIEOct1_uC_MemoryParityErrMask_LSB 0x25675#define QIB_7220_HwErrMask_PCIEOct1_uC_MemoryParityErrMask_RMASK 0x1676#define QIB_7220_HwErrMask_PCIEOct0_uC_MemoryParityErrMask_LSB 0x24677#define QIB_7220_HwErrMask_PCIEOct0_uC_MemoryParityErrMask_RMASK 0x1678#define QIB_7220_HwErrMask_Reserved2_LSB 0x22679#define QIB_7220_HwErrMask_Reserved2_RMASK 0x3680#define QIB_7220_HwErrMask_PCIeBusParityErrMask_LSB 0x1F681#define QIB_7220_HwErrMask_PCIeBusParityErrMask_RMASK 0x7682#define QIB_7220_HwErrMask_PcieCplTimeoutMask_LSB 0x1E683#define QIB_7220_HwErrMask_PcieCplTimeoutMask_RMASK 0x1684#define QIB_7220_HwErrMask_PoisonedTLPMask_LSB 0x1D685#define QIB_7220_HwErrMask_PoisonedTLPMask_RMASK 0x1686#define QIB_7220_HwErrMask_SDmaMemReadErrMask_LSB 0x1C687#define QIB_7220_HwErrMask_SDmaMemReadErrMask_RMASK 0x1688#define QIB_7220_HwErrMask_Reserved3_LSB 0x8689#define QIB_7220_HwErrMask_Reserved3_RMASK 0xFFFFF690#define QIB_7220_HwErrMask_PCIeMemParityErrMask_LSB 0x0691#define QIB_7220_HwErrMask_PCIeMemParityErrMask_RMASK 0xFF692 693#define QIB_7220_HwErrStatus_OFFS 0xA0694#define QIB_7220_HwErrStatus_IBCBusFromSPCParityErr_LSB 0x3F695#define QIB_7220_HwErrStatus_IBCBusFromSPCParityErr_RMASK 0x1696#define QIB_7220_HwErrStatus_IBCBusToSPCParityErr_LSB 0x3E697#define QIB_7220_HwErrStatus_IBCBusToSPCParityErr_RMASK 0x1698#define QIB_7220_HwErrStatus_Clk_uC_PLLNotLocked_LSB 0x3D699#define QIB_7220_HwErrStatus_Clk_uC_PLLNotLocked_RMASK 0x1700#define QIB_7220_HwErrStatus_IBSerdesPClkNotDetect_LSB 0x3C701#define QIB_7220_HwErrStatus_IBSerdesPClkNotDetect_RMASK 0x1702#define QIB_7220_HwErrStatus_PCIESerdesQ3PClkNotDetect_LSB 0x3B703#define QIB_7220_HwErrStatus_PCIESerdesQ3PClkNotDetect_RMASK 0x1704#define QIB_7220_HwErrStatus_PCIESerdesQ2PClkNotDetect_LSB 0x3A705#define QIB_7220_HwErrStatus_PCIESerdesQ2PClkNotDetect_RMASK 0x1706#define QIB_7220_HwErrStatus_PCIESerdesQ1PClkNotDetect_LSB 0x39707#define QIB_7220_HwErrStatus_PCIESerdesQ1PClkNotDetect_RMASK 0x1708#define QIB_7220_HwErrStatus_PCIESerdesQ0PClkNotDetect_LSB 0x38709#define QIB_7220_HwErrStatus_PCIESerdesQ0PClkNotDetect_RMASK 0x1710#define QIB_7220_HwErrStatus_Reserved_LSB 0x37711#define QIB_7220_HwErrStatus_Reserved_RMASK 0x1712#define QIB_7220_HwErrStatus_PowerOnBISTFailed_LSB 0x36713#define QIB_7220_HwErrStatus_PowerOnBISTFailed_RMASK 0x1714#define QIB_7220_HwErrStatus_Reserved1_LSB 0x33715#define QIB_7220_HwErrStatus_Reserved1_RMASK 0x7716#define QIB_7220_HwErrStatus_RXEMemParity_LSB 0x2C717#define QIB_7220_HwErrStatus_RXEMemParity_RMASK 0x7F718#define QIB_7220_HwErrStatus_TXEMemParity_LSB 0x28719#define QIB_7220_HwErrStatus_TXEMemParity_RMASK 0xF720#define QIB_7220_HwErrStatus_DDSRXEQMemoryParityErr_LSB 0x27721#define QIB_7220_HwErrStatus_DDSRXEQMemoryParityErr_RMASK 0x1722#define QIB_7220_HwErrStatus_IB_uC_MemoryParityErr_LSB 0x26723#define QIB_7220_HwErrStatus_IB_uC_MemoryParityErr_RMASK 0x1724#define QIB_7220_HwErrStatus_PCIE_uC_Oct1MemoryParityErr_LSB 0x25725#define QIB_7220_HwErrStatus_PCIE_uC_Oct1MemoryParityErr_RMASK 0x1726#define QIB_7220_HwErrStatus_PCIE_uC_Oct0MemoryParityErr_LSB 0x24727#define QIB_7220_HwErrStatus_PCIE_uC_Oct0MemoryParityErr_RMASK 0x1728#define QIB_7220_HwErrStatus_Reserved2_LSB 0x22729#define QIB_7220_HwErrStatus_Reserved2_RMASK 0x3730#define QIB_7220_HwErrStatus_PCIeBusParity_LSB 0x1F731#define QIB_7220_HwErrStatus_PCIeBusParity_RMASK 0x7732#define QIB_7220_HwErrStatus_PcieCplTimeout_LSB 0x1E733#define QIB_7220_HwErrStatus_PcieCplTimeout_RMASK 0x1734#define QIB_7220_HwErrStatus_PoisenedTLP_LSB 0x1D735#define QIB_7220_HwErrStatus_PoisenedTLP_RMASK 0x1736#define QIB_7220_HwErrStatus_SDmaMemReadErr_LSB 0x1C737#define QIB_7220_HwErrStatus_SDmaMemReadErr_RMASK 0x1738#define QIB_7220_HwErrStatus_Reserved3_LSB 0x8739#define QIB_7220_HwErrStatus_Reserved3_RMASK 0xFFFFF740#define QIB_7220_HwErrStatus_PCIeMemParity_LSB 0x0741#define QIB_7220_HwErrStatus_PCIeMemParity_RMASK 0xFF742 743#define QIB_7220_HwErrClear_OFFS 0xA8744#define QIB_7220_HwErrClear_IBCBusFromSPCParityErrClear_LSB 0x3F745#define QIB_7220_HwErrClear_IBCBusFromSPCParityErrClear_RMASK 0x1746#define QIB_7220_HwErrClear_IBCBusToSPCparityErrClear_LSB 0x3E747#define QIB_7220_HwErrClear_IBCBusToSPCparityErrClear_RMASK 0x1748#define QIB_7220_HwErrClear_Clk_uC_PLLNotLockedClear_LSB 0x3D749#define QIB_7220_HwErrClear_Clk_uC_PLLNotLockedClear_RMASK 0x1750#define QIB_7220_HwErrClear_IBSerdesPClkNotDetectClear_LSB 0x3C751#define QIB_7220_HwErrClear_IBSerdesPClkNotDetectClear_RMASK 0x1752#define QIB_7220_HwErrClear_PCIESerdesQ3PClkNotDetectClear_LSB 0x3B753#define QIB_7220_HwErrClear_PCIESerdesQ3PClkNotDetectClear_RMASK 0x1754#define QIB_7220_HwErrClear_PCIESerdesQ2PClkNotDetectClear_LSB 0x3A755#define QIB_7220_HwErrClear_PCIESerdesQ2PClkNotDetectClear_RMASK 0x1756#define QIB_7220_HwErrClear_PCIESerdesQ1PClkNotDetectClear_LSB 0x39757#define QIB_7220_HwErrClear_PCIESerdesQ1PClkNotDetectClear_RMASK 0x1758#define QIB_7220_HwErrClear_PCIESerdesQ0PClkNotDetectClear_LSB 0x38759#define QIB_7220_HwErrClear_PCIESerdesQ0PClkNotDetectClear_RMASK 0x1760#define QIB_7220_HwErrClear_Reserved_LSB 0x37761#define QIB_7220_HwErrClear_Reserved_RMASK 0x1762#define QIB_7220_HwErrClear_PowerOnBISTFailedClear_LSB 0x36763#define QIB_7220_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1764#define QIB_7220_HwErrClear_Reserved1_LSB 0x33765#define QIB_7220_HwErrClear_Reserved1_RMASK 0x7766#define QIB_7220_HwErrClear_RXEMemParityClear_LSB 0x2C767#define QIB_7220_HwErrClear_RXEMemParityClear_RMASK 0x7F768#define QIB_7220_HwErrClear_TXEMemParityClear_LSB 0x28769#define QIB_7220_HwErrClear_TXEMemParityClear_RMASK 0xF770#define QIB_7220_HwErrClear_DDSRXEQMemoryParityErrClear_LSB 0x27771#define QIB_7220_HwErrClear_DDSRXEQMemoryParityErrClear_RMASK 0x1772#define QIB_7220_HwErrClear_IB_uC_MemoryParityErrClear_LSB 0x26773#define QIB_7220_HwErrClear_IB_uC_MemoryParityErrClear_RMASK 0x1774#define QIB_7220_HwErrClear_PCIE_uC_Oct1MemoryParityErrClear_LSB 0x25775#define QIB_7220_HwErrClear_PCIE_uC_Oct1MemoryParityErrClear_RMASK 0x1776#define QIB_7220_HwErrClear_PCIE_uC_Oct0MemoryParityErrClear_LSB 0x24777#define QIB_7220_HwErrClear_PCIE_uC_Oct0MemoryParityErrClear_RMASK 0x1778#define QIB_7220_HwErrClear_Reserved2_LSB 0x22779#define QIB_7220_HwErrClear_Reserved2_RMASK 0x3780#define QIB_7220_HwErrClear_PCIeBusParityClr_LSB 0x1F781#define QIB_7220_HwErrClear_PCIeBusParityClr_RMASK 0x7782#define QIB_7220_HwErrClear_PcieCplTimeoutClear_LSB 0x1E783#define QIB_7220_HwErrClear_PcieCplTimeoutClear_RMASK 0x1784#define QIB_7220_HwErrClear_PoisonedTLPClear_LSB 0x1D785#define QIB_7220_HwErrClear_PoisonedTLPClear_RMASK 0x1786#define QIB_7220_HwErrClear_SDmaMemReadErrClear_LSB 0x1C787#define QIB_7220_HwErrClear_SDmaMemReadErrClear_RMASK 0x1788#define QIB_7220_HwErrClear_Reserved3_LSB 0x8789#define QIB_7220_HwErrClear_Reserved3_RMASK 0xFFFFF790#define QIB_7220_HwErrClear_PCIeMemParityClr_LSB 0x0791#define QIB_7220_HwErrClear_PCIeMemParityClr_RMASK 0xFF792 793#define QIB_7220_HwDiagCtrl_OFFS 0xB0794#define QIB_7220_HwDiagCtrl_ForceIBCBusFromSPCParityErr_LSB 0x3F795#define QIB_7220_HwDiagCtrl_ForceIBCBusFromSPCParityErr_RMASK 0x1796#define QIB_7220_HwDiagCtrl_ForceIBCBusToSPCParityErr_LSB 0x3E797#define QIB_7220_HwDiagCtrl_ForceIBCBusToSPCParityErr_RMASK 0x1798#define QIB_7220_HwDiagCtrl_CounterWrEnable_LSB 0x3D799#define QIB_7220_HwDiagCtrl_CounterWrEnable_RMASK 0x1800#define QIB_7220_HwDiagCtrl_CounterDisable_LSB 0x3C801#define QIB_7220_HwDiagCtrl_CounterDisable_RMASK 0x1802#define QIB_7220_HwDiagCtrl_Reserved_LSB 0x33803#define QIB_7220_HwDiagCtrl_Reserved_RMASK 0x1FF804#define QIB_7220_HwDiagCtrl_ForceRxMemParityErr_LSB 0x2C805#define QIB_7220_HwDiagCtrl_ForceRxMemParityErr_RMASK 0x7F806#define QIB_7220_HwDiagCtrl_ForceTxMemparityErr_LSB 0x28807#define QIB_7220_HwDiagCtrl_ForceTxMemparityErr_RMASK 0xF808#define QIB_7220_HwDiagCtrl_ForceDDSRXEQMemoryParityErr_LSB 0x27809#define QIB_7220_HwDiagCtrl_ForceDDSRXEQMemoryParityErr_RMASK 0x1810#define QIB_7220_HwDiagCtrl_ForceIB_uC_MemoryParityErr_LSB 0x26811#define QIB_7220_HwDiagCtrl_ForceIB_uC_MemoryParityErr_RMASK 0x1812#define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct1MemoryParityErr_LSB 0x25813#define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct1MemoryParityErr_RMASK 0x1814#define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct0MemoryParityErr_LSB 0x24815#define QIB_7220_HwDiagCtrl_ForcePCIE_uC_Oct0MemoryParityErr_RMASK 0x1816#define QIB_7220_HwDiagCtrl_Reserved1_LSB 0x23817#define QIB_7220_HwDiagCtrl_Reserved1_RMASK 0x1818#define QIB_7220_HwDiagCtrl_forcePCIeBusParity_LSB 0x1F819#define QIB_7220_HwDiagCtrl_forcePCIeBusParity_RMASK 0xF820#define QIB_7220_HwDiagCtrl_Reserved2_LSB 0x8821#define QIB_7220_HwDiagCtrl_Reserved2_RMASK 0x7FFFFF822#define QIB_7220_HwDiagCtrl_forcePCIeMemParity_LSB 0x0823#define QIB_7220_HwDiagCtrl_forcePCIeMemParity_RMASK 0xFF824 825#define QIB_7220_REG_0000B8_OFFS 0xB8826 827#define QIB_7220_IBCStatus_OFFS 0xC0828#define QIB_7220_IBCStatus_TxCreditOk_LSB 0x1F829#define QIB_7220_IBCStatus_TxCreditOk_RMASK 0x1830#define QIB_7220_IBCStatus_TxReady_LSB 0x1E831#define QIB_7220_IBCStatus_TxReady_RMASK 0x1832#define QIB_7220_IBCStatus_Reserved_LSB 0xE833#define QIB_7220_IBCStatus_Reserved_RMASK 0xFFFF834#define QIB_7220_IBCStatus_IBTxLaneReversed_LSB 0xD835#define QIB_7220_IBCStatus_IBTxLaneReversed_RMASK 0x1836#define QIB_7220_IBCStatus_IBRxLaneReversed_LSB 0xC837#define QIB_7220_IBCStatus_IBRxLaneReversed_RMASK 0x1838#define QIB_7220_IBCStatus_IB_SERDES_TRIM_DONE_LSB 0xB839#define QIB_7220_IBCStatus_IB_SERDES_TRIM_DONE_RMASK 0x1840#define QIB_7220_IBCStatus_DDS_RXEQ_FAIL_LSB 0xA841#define QIB_7220_IBCStatus_DDS_RXEQ_FAIL_RMASK 0x1842#define QIB_7220_IBCStatus_LinkWidthActive_LSB 0x9843#define QIB_7220_IBCStatus_LinkWidthActive_RMASK 0x1844#define QIB_7220_IBCStatus_LinkSpeedActive_LSB 0x8845#define QIB_7220_IBCStatus_LinkSpeedActive_RMASK 0x1846#define QIB_7220_IBCStatus_LinkState_LSB 0x5847#define QIB_7220_IBCStatus_LinkState_RMASK 0x7848#define QIB_7220_IBCStatus_LinkTrainingState_LSB 0x0849#define QIB_7220_IBCStatus_LinkTrainingState_RMASK 0x1F850 851#define QIB_7220_IBCCtrl_OFFS 0xC8852#define QIB_7220_IBCCtrl_Loopback_LSB 0x3F853#define QIB_7220_IBCCtrl_Loopback_RMASK 0x1854#define QIB_7220_IBCCtrl_LinkDownDefaultState_LSB 0x3E855#define QIB_7220_IBCCtrl_LinkDownDefaultState_RMASK 0x1856#define QIB_7220_IBCCtrl_Reserved_LSB 0x2B857#define QIB_7220_IBCCtrl_Reserved_RMASK 0x7FFFF858#define QIB_7220_IBCCtrl_CreditScale_LSB 0x28859#define QIB_7220_IBCCtrl_CreditScale_RMASK 0x7860#define QIB_7220_IBCCtrl_OverrunThreshold_LSB 0x24861#define QIB_7220_IBCCtrl_OverrunThreshold_RMASK 0xF862#define QIB_7220_IBCCtrl_PhyerrThreshold_LSB 0x20863#define QIB_7220_IBCCtrl_PhyerrThreshold_RMASK 0xF864#define QIB_7220_IBCCtrl_MaxPktLen_LSB 0x15865#define QIB_7220_IBCCtrl_MaxPktLen_RMASK 0x7FF866#define QIB_7220_IBCCtrl_LinkCmd_LSB 0x13867#define QIB_7220_IBCCtrl_LinkCmd_RMASK 0x3868#define QIB_7220_IBCCtrl_LinkInitCmd_LSB 0x10869#define QIB_7220_IBCCtrl_LinkInitCmd_RMASK 0x7870#define QIB_7220_IBCCtrl_FlowCtrlWaterMark_LSB 0x8871#define QIB_7220_IBCCtrl_FlowCtrlWaterMark_RMASK 0xFF872#define QIB_7220_IBCCtrl_FlowCtrlPeriod_LSB 0x0873#define QIB_7220_IBCCtrl_FlowCtrlPeriod_RMASK 0xFF874 875#define QIB_7220_EXTStatus_OFFS 0xD0876#define QIB_7220_EXTStatus_GPIOIn_LSB 0x30877#define QIB_7220_EXTStatus_GPIOIn_RMASK 0xFFFF878#define QIB_7220_EXTStatus_Reserved_LSB 0x20879#define QIB_7220_EXTStatus_Reserved_RMASK 0xFFFF880#define QIB_7220_EXTStatus_Reserved1_LSB 0x10881#define QIB_7220_EXTStatus_Reserved1_RMASK 0xFFFF882#define QIB_7220_EXTStatus_MemBISTDisabled_LSB 0xF883#define QIB_7220_EXTStatus_MemBISTDisabled_RMASK 0x1884#define QIB_7220_EXTStatus_MemBISTEndTest_LSB 0xE885#define QIB_7220_EXTStatus_MemBISTEndTest_RMASK 0x1886#define QIB_7220_EXTStatus_Reserved2_LSB 0x0887#define QIB_7220_EXTStatus_Reserved2_RMASK 0x3FFF888 889#define QIB_7220_EXTCtrl_OFFS 0xD8890#define QIB_7220_EXTCtrl_GPIOOe_LSB 0x30891#define QIB_7220_EXTCtrl_GPIOOe_RMASK 0xFFFF892#define QIB_7220_EXTCtrl_GPIOInvert_LSB 0x20893#define QIB_7220_EXTCtrl_GPIOInvert_RMASK 0xFFFF894#define QIB_7220_EXTCtrl_Reserved_LSB 0x4895#define QIB_7220_EXTCtrl_Reserved_RMASK 0xFFFFFFF896#define QIB_7220_EXTCtrl_LEDPriPortGreenOn_LSB 0x3897#define QIB_7220_EXTCtrl_LEDPriPortGreenOn_RMASK 0x1898#define QIB_7220_EXTCtrl_LEDPriPortYellowOn_LSB 0x2899#define QIB_7220_EXTCtrl_LEDPriPortYellowOn_RMASK 0x1900#define QIB_7220_EXTCtrl_LEDGblOkGreenOn_LSB 0x1901#define QIB_7220_EXTCtrl_LEDGblOkGreenOn_RMASK 0x1902#define QIB_7220_EXTCtrl_LEDGblErrRedOff_LSB 0x0903#define QIB_7220_EXTCtrl_LEDGblErrRedOff_RMASK 0x1904 905#define QIB_7220_GPIOOut_OFFS 0xE0906 907#define QIB_7220_GPIOMask_OFFS 0xE8908 909#define QIB_7220_GPIOStatus_OFFS 0xF0910 911#define QIB_7220_GPIOClear_OFFS 0xF8912 913#define QIB_7220_RcvCtrl_OFFS 0x100914#define QIB_7220_RcvCtrl_Reserved_LSB 0x27915#define QIB_7220_RcvCtrl_Reserved_RMASK 0x1FFFFFF916#define QIB_7220_RcvCtrl_RcvQPMapEnable_LSB 0x26917#define QIB_7220_RcvCtrl_RcvQPMapEnable_RMASK 0x1918#define QIB_7220_RcvCtrl_PortCfg_LSB 0x24919#define QIB_7220_RcvCtrl_PortCfg_RMASK 0x3920#define QIB_7220_RcvCtrl_TailUpd_LSB 0x23921#define QIB_7220_RcvCtrl_TailUpd_RMASK 0x1922#define QIB_7220_RcvCtrl_RcvPartitionKeyDisable_LSB 0x22923#define QIB_7220_RcvCtrl_RcvPartitionKeyDisable_RMASK 0x1924#define QIB_7220_RcvCtrl_IntrAvail_LSB 0x11925#define QIB_7220_RcvCtrl_IntrAvail_RMASK 0x1FFFF926#define QIB_7220_RcvCtrl_PortEnable_LSB 0x0927#define QIB_7220_RcvCtrl_PortEnable_RMASK 0x1FFFF928 929#define QIB_7220_RcvBTHQP_OFFS 0x108930#define QIB_7220_RcvBTHQP_Reserved_LSB 0x18931#define QIB_7220_RcvBTHQP_Reserved_RMASK 0xFF932#define QIB_7220_RcvBTHQP_RcvBTHQP_LSB 0x0933#define QIB_7220_RcvBTHQP_RcvBTHQP_RMASK 0xFFFFFF934 935#define QIB_7220_RcvHdrSize_OFFS 0x110936 937#define QIB_7220_RcvHdrCnt_OFFS 0x118938 939#define QIB_7220_RcvHdrEntSize_OFFS 0x120940 941#define QIB_7220_RcvTIDBase_OFFS 0x128942 943#define QIB_7220_RcvTIDCnt_OFFS 0x130944 945#define QIB_7220_RcvEgrBase_OFFS 0x138946 947#define QIB_7220_RcvEgrCnt_OFFS 0x140948 949#define QIB_7220_RcvBufBase_OFFS 0x148950 951#define QIB_7220_RcvBufSize_OFFS 0x150952 953#define QIB_7220_RxIntMemBase_OFFS 0x158954 955#define QIB_7220_RxIntMemSize_OFFS 0x160956 957#define QIB_7220_RcvPartitionKey_OFFS 0x168958 959#define QIB_7220_RcvQPMulticastPort_OFFS 0x170960#define QIB_7220_RcvQPMulticastPort_Reserved_LSB 0x5961#define QIB_7220_RcvQPMulticastPort_Reserved_RMASK 0x7FFFFFFFFFFFFFF962#define QIB_7220_RcvQPMulticastPort_RcvQpMcPort_LSB 0x0963#define QIB_7220_RcvQPMulticastPort_RcvQpMcPort_RMASK 0x1F964 965#define QIB_7220_RcvPktLEDCnt_OFFS 0x178966#define QIB_7220_RcvPktLEDCnt_ONperiod_LSB 0x20967#define QIB_7220_RcvPktLEDCnt_ONperiod_RMASK 0xFFFFFFFF968#define QIB_7220_RcvPktLEDCnt_OFFperiod_LSB 0x0969#define QIB_7220_RcvPktLEDCnt_OFFperiod_RMASK 0xFFFFFFFF970 971#define QIB_7220_IBCDDRCtrl_OFFS 0x180972#define QIB_7220_IBCDDRCtrl_IB_DLID_MASK_LSB 0x30973#define QIB_7220_IBCDDRCtrl_IB_DLID_MASK_RMASK 0xFFFF974#define QIB_7220_IBCDDRCtrl_IB_DLID_LSB 0x20975#define QIB_7220_IBCDDRCtrl_IB_DLID_RMASK 0xFFFF976#define QIB_7220_IBCDDRCtrl_Reserved_LSB 0x1B977#define QIB_7220_IBCDDRCtrl_Reserved_RMASK 0x1F978#define QIB_7220_IBCDDRCtrl_HRTBT_REQ_LSB 0x1A979#define QIB_7220_IBCDDRCtrl_HRTBT_REQ_RMASK 0x1980#define QIB_7220_IBCDDRCtrl_HRTBT_PORT_LSB 0x12981#define QIB_7220_IBCDDRCtrl_HRTBT_PORT_RMASK 0xFF982#define QIB_7220_IBCDDRCtrl_HRTBT_AUTO_LSB 0x11983#define QIB_7220_IBCDDRCtrl_HRTBT_AUTO_RMASK 0x1984#define QIB_7220_IBCDDRCtrl_HRTBT_ENB_LSB 0x10985#define QIB_7220_IBCDDRCtrl_HRTBT_ENB_RMASK 0x1986#define QIB_7220_IBCDDRCtrl_SD_DDS_LSB 0xC987#define QIB_7220_IBCDDRCtrl_SD_DDS_RMASK 0xF988#define QIB_7220_IBCDDRCtrl_SD_DDSV_LSB 0xB989#define QIB_7220_IBCDDRCtrl_SD_DDSV_RMASK 0x1990#define QIB_7220_IBCDDRCtrl_SD_ADD_ENB_LSB 0xA991#define QIB_7220_IBCDDRCtrl_SD_ADD_ENB_RMASK 0x1992#define QIB_7220_IBCDDRCtrl_SD_RX_EQUAL_ENABLE_LSB 0x9993#define QIB_7220_IBCDDRCtrl_SD_RX_EQUAL_ENABLE_RMASK 0x1994#define QIB_7220_IBCDDRCtrl_IB_LANE_REV_SUPPORTED_LSB 0x8995#define QIB_7220_IBCDDRCtrl_IB_LANE_REV_SUPPORTED_RMASK 0x1996#define QIB_7220_IBCDDRCtrl_IB_POLARITY_REV_SUPP_LSB 0x7997#define QIB_7220_IBCDDRCtrl_IB_POLARITY_REV_SUPP_RMASK 0x1998#define QIB_7220_IBCDDRCtrl_IB_NUM_CHANNELS_LSB 0x5999#define QIB_7220_IBCDDRCtrl_IB_NUM_CHANNELS_RMASK 0x31000#define QIB_7220_IBCDDRCtrl_SD_SPEED_QDR_LSB 0x41001#define QIB_7220_IBCDDRCtrl_SD_SPEED_QDR_RMASK 0x11002#define QIB_7220_IBCDDRCtrl_SD_SPEED_DDR_LSB 0x31003#define QIB_7220_IBCDDRCtrl_SD_SPEED_DDR_RMASK 0x11004#define QIB_7220_IBCDDRCtrl_SD_SPEED_SDR_LSB 0x21005#define QIB_7220_IBCDDRCtrl_SD_SPEED_SDR_RMASK 0x11006#define QIB_7220_IBCDDRCtrl_SD_SPEED_LSB 0x11007#define QIB_7220_IBCDDRCtrl_SD_SPEED_RMASK 0x11008#define QIB_7220_IBCDDRCtrl_IB_ENHANCED_MODE_LSB 0x01009#define QIB_7220_IBCDDRCtrl_IB_ENHANCED_MODE_RMASK 0x11010 1011#define QIB_7220_HRTBT_GUID_OFFS 0x1881012 1013#define QIB_7220_IBCDDRCtrl2_OFFS 0x1A01014#define QIB_7220_IBCDDRCtrl2_IB_BACK_PORCH_LSB 0x51015#define QIB_7220_IBCDDRCtrl2_IB_BACK_PORCH_RMASK 0x1F1016#define QIB_7220_IBCDDRCtrl2_IB_FRONT_PORCH_LSB 0x01017#define QIB_7220_IBCDDRCtrl2_IB_FRONT_PORCH_RMASK 0x1F1018 1019#define QIB_7220_IBCDDRStatus_OFFS 0x1A81020#define QIB_7220_IBCDDRStatus_heartbeat_timed_out_LSB 0x241021#define QIB_7220_IBCDDRStatus_heartbeat_timed_out_RMASK 0x11022#define QIB_7220_IBCDDRStatus_heartbeat_crosstalk_LSB 0x201023#define QIB_7220_IBCDDRStatus_heartbeat_crosstalk_RMASK 0xF1024#define QIB_7220_IBCDDRStatus_RxEqLocalDevice_LSB 0x1E1025#define QIB_7220_IBCDDRStatus_RxEqLocalDevice_RMASK 0x31026#define QIB_7220_IBCDDRStatus_ReqDDSLocalFromRmt_LSB 0x1A1027#define QIB_7220_IBCDDRStatus_ReqDDSLocalFromRmt_RMASK 0xF1028#define QIB_7220_IBCDDRStatus_LinkRoundTripLatency_LSB 0x01029#define QIB_7220_IBCDDRStatus_LinkRoundTripLatency_RMASK 0x3FFFFFF1030 1031#define QIB_7220_JIntReload_OFFS 0x1B01032#define QIB_7220_JIntReload_J_limit_reload_LSB 0x101033#define QIB_7220_JIntReload_J_limit_reload_RMASK 0xFFFF1034#define QIB_7220_JIntReload_J_reload_LSB 0x01035#define QIB_7220_JIntReload_J_reload_RMASK 0xFFFF1036 1037#define QIB_7220_IBNCModeCtrl_OFFS 0x1B81038#define QIB_7220_IBNCModeCtrl_Reserved_LSB 0x1A1039#define QIB_7220_IBNCModeCtrl_Reserved_RMASK 0x3FFFFFFFFF1040#define QIB_7220_IBNCModeCtrl_TSMCode_TS2_LSB 0x111041#define QIB_7220_IBNCModeCtrl_TSMCode_TS2_RMASK 0x1FF1042#define QIB_7220_IBNCModeCtrl_TSMCode_TS1_LSB 0x81043#define QIB_7220_IBNCModeCtrl_TSMCode_TS1_RMASK 0x1FF1044#define QIB_7220_IBNCModeCtrl_Reserved1_LSB 0x31045#define QIB_7220_IBNCModeCtrl_Reserved1_RMASK 0x1F1046#define QIB_7220_IBNCModeCtrl_TSMEnable_ignore_TSM_on_rx_LSB 0x21047#define QIB_7220_IBNCModeCtrl_TSMEnable_ignore_TSM_on_rx_RMASK 0x11048#define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS2_LSB 0x11049#define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS2_RMASK 0x11050#define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS1_LSB 0x01051#define QIB_7220_IBNCModeCtrl_TSMEnable_send_TS1_RMASK 0x11052 1053#define QIB_7220_SendCtrl_OFFS 0x1C01054#define QIB_7220_SendCtrl_Disarm_LSB 0x1F1055#define QIB_7220_SendCtrl_Disarm_RMASK 0x11056#define QIB_7220_SendCtrl_Reserved_LSB 0x1D1057#define QIB_7220_SendCtrl_Reserved_RMASK 0x31058#define QIB_7220_SendCtrl_AvailUpdThld_LSB 0x181059#define QIB_7220_SendCtrl_AvailUpdThld_RMASK 0x1F1060#define QIB_7220_SendCtrl_DisarmPIOBuf_LSB 0x101061#define QIB_7220_SendCtrl_DisarmPIOBuf_RMASK 0xFF1062#define QIB_7220_SendCtrl_Reserved1_LSB 0xD1063#define QIB_7220_SendCtrl_Reserved1_RMASK 0x71064#define QIB_7220_SendCtrl_SDmaHalt_LSB 0xC1065#define QIB_7220_SendCtrl_SDmaHalt_RMASK 0x11066#define QIB_7220_SendCtrl_SDmaEnable_LSB 0xB1067#define QIB_7220_SendCtrl_SDmaEnable_RMASK 0x11068#define QIB_7220_SendCtrl_SDmaSingleDescriptor_LSB 0xA1069#define QIB_7220_SendCtrl_SDmaSingleDescriptor_RMASK 0x11070#define QIB_7220_SendCtrl_SDmaIntEnable_LSB 0x91071#define QIB_7220_SendCtrl_SDmaIntEnable_RMASK 0x11072#define QIB_7220_SendCtrl_Reserved2_LSB 0x51073#define QIB_7220_SendCtrl_Reserved2_RMASK 0xF1074#define QIB_7220_SendCtrl_SSpecialTriggerEn_LSB 0x41075#define QIB_7220_SendCtrl_SSpecialTriggerEn_RMASK 0x11076#define QIB_7220_SendCtrl_SPioEnable_LSB 0x31077#define QIB_7220_SendCtrl_SPioEnable_RMASK 0x11078#define QIB_7220_SendCtrl_SendBufAvailUpd_LSB 0x21079#define QIB_7220_SendCtrl_SendBufAvailUpd_RMASK 0x11080#define QIB_7220_SendCtrl_SendIntBufAvail_LSB 0x11081#define QIB_7220_SendCtrl_SendIntBufAvail_RMASK 0x11082#define QIB_7220_SendCtrl_Abort_LSB 0x01083#define QIB_7220_SendCtrl_Abort_RMASK 0x11084 1085#define QIB_7220_SendBufBase_OFFS 0x1C81086#define QIB_7220_SendBufBase_Reserved_LSB 0x351087#define QIB_7220_SendBufBase_Reserved_RMASK 0x7FF1088#define QIB_7220_SendBufBase_BaseAddr_LargePIO_LSB 0x201089#define QIB_7220_SendBufBase_BaseAddr_LargePIO_RMASK 0x1FFFFF1090#define QIB_7220_SendBufBase_Reserved1_LSB 0x151091#define QIB_7220_SendBufBase_Reserved1_RMASK 0x7FF1092#define QIB_7220_SendBufBase_BaseAddr_SmallPIO_LSB 0x01093#define QIB_7220_SendBufBase_BaseAddr_SmallPIO_RMASK 0x1FFFFF1094 1095#define QIB_7220_SendBufSize_OFFS 0x1D01096#define QIB_7220_SendBufSize_Reserved_LSB 0x2D1097#define QIB_7220_SendBufSize_Reserved_RMASK 0xFFFFF1098#define QIB_7220_SendBufSize_Size_LargePIO_LSB 0x201099#define QIB_7220_SendBufSize_Size_LargePIO_RMASK 0x1FFF1100#define QIB_7220_SendBufSize_Reserved1_LSB 0xC1101#define QIB_7220_SendBufSize_Reserved1_RMASK 0xFFFFF1102#define QIB_7220_SendBufSize_Size_SmallPIO_LSB 0x01103#define QIB_7220_SendBufSize_Size_SmallPIO_RMASK 0xFFF1104 1105#define QIB_7220_SendBufCnt_OFFS 0x1D81106#define QIB_7220_SendBufCnt_Reserved_LSB 0x241107#define QIB_7220_SendBufCnt_Reserved_RMASK 0xFFFFFFF1108#define QIB_7220_SendBufCnt_Num_LargeBuffers_LSB 0x201109#define QIB_7220_SendBufCnt_Num_LargeBuffers_RMASK 0xF1110#define QIB_7220_SendBufCnt_Reserved1_LSB 0x91111#define QIB_7220_SendBufCnt_Reserved1_RMASK 0x7FFFFF1112#define QIB_7220_SendBufCnt_Num_SmallBuffers_LSB 0x01113#define QIB_7220_SendBufCnt_Num_SmallBuffers_RMASK 0x1FF1114 1115#define QIB_7220_SendBufAvailAddr_OFFS 0x1E01116#define QIB_7220_SendBufAvailAddr_SendBufAvailAddr_LSB 0x61117#define QIB_7220_SendBufAvailAddr_SendBufAvailAddr_RMASK 0x3FFFFFFFF1118#define QIB_7220_SendBufAvailAddr_Reserved_LSB 0x01119#define QIB_7220_SendBufAvailAddr_Reserved_RMASK 0x3F1120 1121#define QIB_7220_TxIntMemBase_OFFS 0x1E81122 1123#define QIB_7220_TxIntMemSize_OFFS 0x1F01124 1125#define QIB_7220_SendDmaBase_OFFS 0x1F81126#define QIB_7220_SendDmaBase_Reserved_LSB 0x301127#define QIB_7220_SendDmaBase_Reserved_RMASK 0xFFFF1128#define QIB_7220_SendDmaBase_SendDmaBase_LSB 0x01129#define QIB_7220_SendDmaBase_SendDmaBase_RMASK 0xFFFFFFFFFFFF1130 1131#define QIB_7220_SendDmaLenGen_OFFS 0x2001132#define QIB_7220_SendDmaLenGen_Reserved_LSB 0x131133#define QIB_7220_SendDmaLenGen_Reserved_RMASK 0x1FFFFFFFFFFF1134#define QIB_7220_SendDmaLenGen_Generation_LSB 0x101135#define QIB_7220_SendDmaLenGen_Generation_MSB 0x121136#define QIB_7220_SendDmaLenGen_Generation_RMASK 0x71137#define QIB_7220_SendDmaLenGen_Length_LSB 0x01138#define QIB_7220_SendDmaLenGen_Length_RMASK 0xFFFF1139 1140#define QIB_7220_SendDmaTail_OFFS 0x2081141#define QIB_7220_SendDmaTail_Reserved_LSB 0x101142#define QIB_7220_SendDmaTail_Reserved_RMASK 0xFFFFFFFFFFFF1143#define QIB_7220_SendDmaTail_SendDmaTail_LSB 0x01144#define QIB_7220_SendDmaTail_SendDmaTail_RMASK 0xFFFF1145 1146#define QIB_7220_SendDmaHead_OFFS 0x2101147#define QIB_7220_SendDmaHead_Reserved_LSB 0x301148#define QIB_7220_SendDmaHead_Reserved_RMASK 0xFFFF1149#define QIB_7220_SendDmaHead_InternalSendDmaHead_LSB 0x201150#define QIB_7220_SendDmaHead_InternalSendDmaHead_RMASK 0xFFFF1151#define QIB_7220_SendDmaHead_Reserved1_LSB 0x101152#define QIB_7220_SendDmaHead_Reserved1_RMASK 0xFFFF1153#define QIB_7220_SendDmaHead_SendDmaHead_LSB 0x01154#define QIB_7220_SendDmaHead_SendDmaHead_RMASK 0xFFFF1155 1156#define QIB_7220_SendDmaHeadAddr_OFFS 0x2181157#define QIB_7220_SendDmaHeadAddr_Reserved_LSB 0x301158#define QIB_7220_SendDmaHeadAddr_Reserved_RMASK 0xFFFF1159#define QIB_7220_SendDmaHeadAddr_SendDmaHeadAddr_LSB 0x01160#define QIB_7220_SendDmaHeadAddr_SendDmaHeadAddr_RMASK 0xFFFFFFFFFFFF1161 1162#define QIB_7220_SendDmaBufMask0_OFFS 0x2201163#define QIB_7220_SendDmaBufMask0_BufMask_63_0_LSB 0x01164#define QIB_7220_SendDmaBufMask0_BufMask_63_0_RMASK 0x01165 1166#define QIB_7220_SendDmaStatus_OFFS 0x2381167#define QIB_7220_SendDmaStatus_ScoreBoardDrainInProg_LSB 0x3F1168#define QIB_7220_SendDmaStatus_ScoreBoardDrainInProg_RMASK 0x11169#define QIB_7220_SendDmaStatus_AbortInProg_LSB 0x3E1170#define QIB_7220_SendDmaStatus_AbortInProg_RMASK 0x11171#define QIB_7220_SendDmaStatus_InternalSDmaEnable_LSB 0x3D1172#define QIB_7220_SendDmaStatus_InternalSDmaEnable_RMASK 0x11173#define QIB_7220_SendDmaStatus_ScbDescIndex_13_0_LSB 0x2F1174#define QIB_7220_SendDmaStatus_ScbDescIndex_13_0_RMASK 0x3FFF1175#define QIB_7220_SendDmaStatus_RpyLowAddr_6_0_LSB 0x281176#define QIB_7220_SendDmaStatus_RpyLowAddr_6_0_RMASK 0x7F1177#define QIB_7220_SendDmaStatus_RpyTag_7_0_LSB 0x201178#define QIB_7220_SendDmaStatus_RpyTag_7_0_RMASK 0xFF1179#define QIB_7220_SendDmaStatus_ScbFull_LSB 0x1F1180#define QIB_7220_SendDmaStatus_ScbFull_RMASK 0x11181#define QIB_7220_SendDmaStatus_ScbEmpty_LSB 0x1E1182#define QIB_7220_SendDmaStatus_ScbEmpty_RMASK 0x11183#define QIB_7220_SendDmaStatus_ScbEntryValid_LSB 0x1D1184#define QIB_7220_SendDmaStatus_ScbEntryValid_RMASK 0x11185#define QIB_7220_SendDmaStatus_ScbFetchDescFlag_LSB 0x1C1186#define QIB_7220_SendDmaStatus_ScbFetchDescFlag_RMASK 0x11187#define QIB_7220_SendDmaStatus_SplFifoReadyToGo_LSB 0x1B1188#define QIB_7220_SendDmaStatus_SplFifoReadyToGo_RMASK 0x11189#define QIB_7220_SendDmaStatus_SplFifoDisarmed_LSB 0x1A1190#define QIB_7220_SendDmaStatus_SplFifoDisarmed_RMASK 0x11191#define QIB_7220_SendDmaStatus_SplFifoEmpty_LSB 0x191192#define QIB_7220_SendDmaStatus_SplFifoEmpty_RMASK 0x11193#define QIB_7220_SendDmaStatus_SplFifoFull_LSB 0x181194#define QIB_7220_SendDmaStatus_SplFifoFull_RMASK 0x11195#define QIB_7220_SendDmaStatus_SplFifoBufNum_LSB 0x101196#define QIB_7220_SendDmaStatus_SplFifoBufNum_RMASK 0xFF1197#define QIB_7220_SendDmaStatus_SplFifoDescIndex_LSB 0x01198#define QIB_7220_SendDmaStatus_SplFifoDescIndex_RMASK 0xFFFF1199 1200#define QIB_7220_SendBufErr0_OFFS 0x2401201#define QIB_7220_SendBufErr0_SendBufErr_63_0_LSB 0x01202#define QIB_7220_SendBufErr0_SendBufErr_63_0_RMASK 0x01203 1204#define QIB_7220_RcvHdrAddr0_OFFS 0x2701205#define QIB_7220_RcvHdrAddr0_RcvHdrAddr0_LSB 0x21206#define QIB_7220_RcvHdrAddr0_RcvHdrAddr0_RMASK 0x3FFFFFFFFF1207#define QIB_7220_RcvHdrAddr0_Reserved_LSB 0x01208#define QIB_7220_RcvHdrAddr0_Reserved_RMASK 0x31209 1210#define QIB_7220_RcvHdrTailAddr0_OFFS 0x3001211#define QIB_7220_RcvHdrTailAddr0_RcvHdrTailAddr0_LSB 0x21212#define QIB_7220_RcvHdrTailAddr0_RcvHdrTailAddr0_RMASK 0x3FFFFFFFFF1213#define QIB_7220_RcvHdrTailAddr0_Reserved_LSB 0x01214#define QIB_7220_RcvHdrTailAddr0_Reserved_RMASK 0x31215 1216#define QIB_7220_ibsd_epb_access_ctrl_OFFS 0x3C01217#define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_granted_LSB 0x81218#define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_granted_RMASK 0x11219#define QIB_7220_ibsd_epb_access_ctrl_Reserved_LSB 0x11220#define QIB_7220_ibsd_epb_access_ctrl_Reserved_RMASK 0x7F1221#define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_LSB 0x01222#define QIB_7220_ibsd_epb_access_ctrl_sw_ib_epb_req_RMASK 0x11223 1224#define QIB_7220_ibsd_epb_transaction_reg_OFFS 0x3C81225#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_rdy_LSB 0x1F1226#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_rdy_RMASK 0x11227#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_req_error_LSB 0x1E1228#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_req_error_RMASK 0x11229#define QIB_7220_ibsd_epb_transaction_reg_Reserved_LSB 0x1D1230#define QIB_7220_ibsd_epb_transaction_reg_Reserved_RMASK 0x11231#define QIB_7220_ibsd_epb_transaction_reg_mem_data_parity_LSB 0x1C1232#define QIB_7220_ibsd_epb_transaction_reg_mem_data_parity_RMASK 0x11233#define QIB_7220_ibsd_epb_transaction_reg_Reserved1_LSB 0x1B1234#define QIB_7220_ibsd_epb_transaction_reg_Reserved1_RMASK 0x11235#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_cs_LSB 0x191236#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_cs_RMASK 0x31237#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_read_write_LSB 0x181238#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_read_write_RMASK 0x11239#define QIB_7220_ibsd_epb_transaction_reg_Reserved2_LSB 0x171240#define QIB_7220_ibsd_epb_transaction_reg_Reserved2_RMASK 0x11241#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_address_LSB 0x81242#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_address_RMASK 0x7FFF1243#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_data_LSB 0x01244#define QIB_7220_ibsd_epb_transaction_reg_ib_epb_data_RMASK 0xFF1245 1246#define QIB_7220_XGXSCfg_OFFS 0x3D81247#define QIB_7220_XGXSCfg_sel_link_down_for_fctrl_lane_sync_reset_LSB 0x3F1248#define QIB_7220_XGXSCfg_sel_link_down_for_fctrl_lane_sync_reset_RMASK 0x11249#define QIB_7220_XGXSCfg_Reserved_LSB 0x131250#define QIB_7220_XGXSCfg_Reserved_RMASK 0xFFFFFFFFFFF1251#define QIB_7220_XGXSCfg_link_sync_mask_LSB 0x91252#define QIB_7220_XGXSCfg_link_sync_mask_RMASK 0x3FF1253#define QIB_7220_XGXSCfg_Reserved1_LSB 0x31254#define QIB_7220_XGXSCfg_Reserved1_RMASK 0x3F1255#define QIB_7220_XGXSCfg_xcv_reset_LSB 0x21256#define QIB_7220_XGXSCfg_xcv_reset_RMASK 0x11257#define QIB_7220_XGXSCfg_Reserved2_LSB 0x11258#define QIB_7220_XGXSCfg_Reserved2_RMASK 0x11259#define QIB_7220_XGXSCfg_tx_rx_reset_LSB 0x01260#define QIB_7220_XGXSCfg_tx_rx_reset_RMASK 0x11261 1262#define QIB_7220_IBSerDesCtrl_OFFS 0x3E01263#define QIB_7220_IBSerDesCtrl_Reserved_LSB 0x2D1264#define QIB_7220_IBSerDesCtrl_Reserved_RMASK 0x7FFFF1265#define QIB_7220_IBSerDesCtrl_INT_uC_LSB 0x2C1266#define QIB_7220_IBSerDesCtrl_INT_uC_RMASK 0x11267#define QIB_7220_IBSerDesCtrl_CKSEL_uC_LSB 0x2A1268#define QIB_7220_IBSerDesCtrl_CKSEL_uC_RMASK 0x31269#define QIB_7220_IBSerDesCtrl_PLLN_LSB 0x281270#define QIB_7220_IBSerDesCtrl_PLLN_RMASK 0x31271#define QIB_7220_IBSerDesCtrl_PLLM_LSB 0x251272#define QIB_7220_IBSerDesCtrl_PLLM_RMASK 0x71273#define QIB_7220_IBSerDesCtrl_TXOBPD_LSB 0x241274#define QIB_7220_IBSerDesCtrl_TXOBPD_RMASK 0x11275#define QIB_7220_IBSerDesCtrl_TWC_LSB 0x231276#define QIB_7220_IBSerDesCtrl_TWC_RMASK 0x11277#define QIB_7220_IBSerDesCtrl_RXIDLE_LSB 0x221278#define QIB_7220_IBSerDesCtrl_RXIDLE_RMASK 0x11279#define QIB_7220_IBSerDesCtrl_RXINV_LSB 0x211280#define QIB_7220_IBSerDesCtrl_RXINV_RMASK 0x11281#define QIB_7220_IBSerDesCtrl_TXINV_LSB 0x201282#define QIB_7220_IBSerDesCtrl_TXINV_RMASK 0x11283#define QIB_7220_IBSerDesCtrl_Reserved1_LSB 0x121284#define QIB_7220_IBSerDesCtrl_Reserved1_RMASK 0x3FFF1285#define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForRXEQ_LSB 0xD1286#define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForRXEQ_RMASK 0x1F1287#define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForDDS_LSB 0x81288#define QIB_7220_IBSerDesCtrl_NumSerDesRegsToWrForDDS_RMASK 0x1F1289#define QIB_7220_IBSerDesCtrl_Reserved2_LSB 0x11290#define QIB_7220_IBSerDesCtrl_Reserved2_RMASK 0x7F1291#define QIB_7220_IBSerDesCtrl_ResetIB_uC_Core_LSB 0x01292#define QIB_7220_IBSerDesCtrl_ResetIB_uC_Core_RMASK 0x11293 1294#define QIB_7220_pciesd_epb_access_ctrl_OFFS 0x4001295#define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_granted_LSB 0x81296#define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_granted_RMASK 0x11297#define QIB_7220_pciesd_epb_access_ctrl_Reserved_LSB 0x31298#define QIB_7220_pciesd_epb_access_ctrl_Reserved_RMASK 0x1F1299#define QIB_7220_pciesd_epb_access_ctrl_sw_pcieepb_star_en_LSB 0x11300#define QIB_7220_pciesd_epb_access_ctrl_sw_pcieepb_star_en_RMASK 0x31301#define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_LSB 0x01302#define QIB_7220_pciesd_epb_access_ctrl_sw_pcie_epb_req_RMASK 0x11303 1304#define QIB_7220_pciesd_epb_transaction_reg_OFFS 0x4081305#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_rdy_LSB 0x1F1306#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_rdy_RMASK 0x11307#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_req_error_LSB 0x1E1308#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_req_error_RMASK 0x11309#define QIB_7220_pciesd_epb_transaction_reg_Reserved_LSB 0x1D1310#define QIB_7220_pciesd_epb_transaction_reg_Reserved_RMASK 0x11311#define QIB_7220_pciesd_epb_transaction_reg_mem_data_parity_LSB 0x1C1312#define QIB_7220_pciesd_epb_transaction_reg_mem_data_parity_RMASK 0x11313#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_cs_LSB 0x191314#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_cs_RMASK 0x71315#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_read_write_LSB 0x181316#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_read_write_RMASK 0x11317#define QIB_7220_pciesd_epb_transaction_reg_Reserved1_LSB 0x171318#define QIB_7220_pciesd_epb_transaction_reg_Reserved1_RMASK 0x11319#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_address_LSB 0x81320#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_address_RMASK 0x7FFF1321#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_data_LSB 0x01322#define QIB_7220_pciesd_epb_transaction_reg_pcie_epb_data_RMASK 0xFF1323 1324#define QIB_7220_SerDes_DDSRXEQ0_OFFS 0x5001325#define QIB_7220_SerDes_DDSRXEQ0_reg_addr_LSB 0x41326#define QIB_7220_SerDes_DDSRXEQ0_reg_addr_RMASK 0x3F1327#define QIB_7220_SerDes_DDSRXEQ0_element_num_LSB 0x01328#define QIB_7220_SerDes_DDSRXEQ0_element_num_RMASK 0xF1329 1330#define QIB_7220_LBIntCnt_OFFS 0x130001331 1332#define QIB_7220_LBFlowStallCnt_OFFS 0x130081333 1334#define QIB_7220_TxSDmaDescCnt_OFFS 0x130101335 1336#define QIB_7220_TxUnsupVLErrCnt_OFFS 0x130181337 1338#define QIB_7220_TxDataPktCnt_OFFS 0x130201339 1340#define QIB_7220_TxFlowPktCnt_OFFS 0x130281341 1342#define QIB_7220_TxDwordCnt_OFFS 0x130301343 1344#define QIB_7220_TxLenErrCnt_OFFS 0x130381345 1346#define QIB_7220_TxMaxMinLenErrCnt_OFFS 0x130401347 1348#define QIB_7220_TxUnderrunCnt_OFFS 0x130481349 1350#define QIB_7220_TxFlowStallCnt_OFFS 0x130501351 1352#define QIB_7220_TxDroppedPktCnt_OFFS 0x130581353 1354#define QIB_7220_RxDroppedPktCnt_OFFS 0x130601355 1356#define QIB_7220_RxDataPktCnt_OFFS 0x130681357 1358#define QIB_7220_RxFlowPktCnt_OFFS 0x130701359 1360#define QIB_7220_RxDwordCnt_OFFS 0x130781361 1362#define QIB_7220_RxLenErrCnt_OFFS 0x130801363 1364#define QIB_7220_RxMaxMinLenErrCnt_OFFS 0x130881365 1366#define QIB_7220_RxICRCErrCnt_OFFS 0x130901367 1368#define QIB_7220_RxVCRCErrCnt_OFFS 0x130981369 1370#define QIB_7220_RxFlowCtrlViolCnt_OFFS 0x130A01371 1372#define QIB_7220_RxVersionErrCnt_OFFS 0x130A81373 1374#define QIB_7220_RxLinkMalformCnt_OFFS 0x130B01375 1376#define QIB_7220_RxEBPCnt_OFFS 0x130B81377 1378#define QIB_7220_RxLPCRCErrCnt_OFFS 0x130C01379 1380#define QIB_7220_RxBufOvflCnt_OFFS 0x130C81381 1382#define QIB_7220_RxTIDFullErrCnt_OFFS 0x130D01383 1384#define QIB_7220_RxTIDValidErrCnt_OFFS 0x130D81385 1386#define QIB_7220_RxPKeyMismatchCnt_OFFS 0x130E01387 1388#define QIB_7220_RxP0HdrEgrOvflCnt_OFFS 0x130E81389 1390#define QIB_7220_IBStatusChangeCnt_OFFS 0x131701391 1392#define QIB_7220_IBLinkErrRecoveryCnt_OFFS 0x131781393 1394#define QIB_7220_IBLinkDownedCnt_OFFS 0x131801395 1396#define QIB_7220_IBSymbolErrCnt_OFFS 0x131881397 1398#define QIB_7220_RxVL15DroppedPktCnt_OFFS 0x131901399 1400#define QIB_7220_RxOtherLocalPhyErrCnt_OFFS 0x131981401 1402#define QIB_7220_PcieRetryBufDiagQwordCnt_OFFS 0x131A01403 1404#define QIB_7220_ExcessBufferOvflCnt_OFFS 0x131A81405 1406#define QIB_7220_LocalLinkIntegrityErrCnt_OFFS 0x131B01407 1408#define QIB_7220_RxVlErrCnt_OFFS 0x131B81409 1410#define QIB_7220_RxDlidFltrCnt_OFFS 0x131C01411 1412#define QIB_7220_CNT_0131C8_OFFS 0x131C81413 1414#define QIB_7220_PSStat_OFFS 0x132001415 1416#define QIB_7220_PSStart_OFFS 0x132081417 1418#define QIB_7220_PSInterval_OFFS 0x132101419 1420#define QIB_7220_PSRcvDataCount_OFFS 0x132181421 1422#define QIB_7220_PSRcvPktsCount_OFFS 0x132201423 1424#define QIB_7220_PSXmitDataCount_OFFS 0x132281425 1426#define QIB_7220_PSXmitPktsCount_OFFS 0x132301427 1428#define QIB_7220_PSXmitWaitCount_OFFS 0x132381429 1430#define QIB_7220_CNT_013240_OFFS 0x132401431 1432#define QIB_7220_RcvEgrArray_OFFS 0x140001433 1434#define QIB_7220_MEM_038000_OFFS 0x380001435 1436#define QIB_7220_RcvTIDArray0_OFFS 0x530001437 1438#define QIB_7220_PIOLaunchFIFO_OFFS 0x640001439 1440#define QIB_7220_MEM_064480_OFFS 0x644801441 1442#define QIB_7220_SendPIOpbcCache_OFFS 0x648001443 1444#define QIB_7220_MEM_064C80_OFFS 0x64C801445 1446#define QIB_7220_PreLaunchFIFO_OFFS 0x650001447 1448#define QIB_7220_MEM_065080_OFFS 0x650801449 1450#define QIB_7220_ScoreBoard_OFFS 0x654001451 1452#define QIB_7220_MEM_065440_OFFS 0x654401453 1454#define QIB_7220_DescriptorFIFO_OFFS 0x658001455 1456#define QIB_7220_MEM_065880_OFFS 0x658801457 1458#define QIB_7220_RcvBuf1_OFFS 0x720001459 1460#define QIB_7220_MEM_074800_OFFS 0x748001461 1462#define QIB_7220_RcvBuf2_OFFS 0x750001463 1464#define QIB_7220_MEM_076400_OFFS 0x764001465 1466#define QIB_7220_RcvFlags_OFFS 0x770001467 1468#define QIB_7220_MEM_078400_OFFS 0x784001469 1470#define QIB_7220_RcvLookupBuf1_OFFS 0x790001471 1472#define QIB_7220_MEM_07A400_OFFS 0x7A4001473 1474#define QIB_7220_RcvDMADatBuf_OFFS 0x7B0001475 1476#define QIB_7220_RcvDMAHdrBuf_OFFS 0x7B8001477 1478#define QIB_7220_MiscRXEIntMem_OFFS 0x7C0001479 1480#define QIB_7220_MEM_07D400_OFFS 0x7D4001481 1482#define QIB_7220_PCIERcvBuf_OFFS 0x800001483 1484#define QIB_7220_PCIERetryBuf_OFFS 0x840001485 1486#define QIB_7220_PCIERcvBufRdToWrAddr_OFFS 0x880001487 1488#define QIB_7220_PCIECplBuf_OFFS 0x900001489 1490#define QIB_7220_IBSerDesMappTable_OFFS 0x940001491 1492#define QIB_7220_MEM_095000_OFFS 0x950001493 1494#define QIB_7220_SendBuf0_MA_OFFS 0x1000001495 1496#define QIB_7220_MEM_1A0000_OFFS 0x1A00001497