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1/*2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.3 *4 * This software is available to you under a choice of one of two5 * licenses. You may choose to be licensed under the terms of the GNU6 * General Public License (GPL) Version 2, available from the file7 * COPYING in the main directory of this source tree, or the8 * OpenIB.org BSD license below:9 *10 * Redistribution and use in source and binary forms, with or11 * without modification, are permitted provided that the following12 * conditions are met:13 *14 * - Redistributions of source code must retain the above15 * copyright notice, this list of conditions and the following16 * disclaimer.17 *18 * - Redistributions in binary form must reproduce the above19 * copyright notice, this list of conditions and the following20 * disclaimer in the documentation and/or other materials21 * provided with the distribution.22 *23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE30 * SOFTWARE.31 */32 33/* This file is mechanically generated from RTL. Any hand-edits will be lost! */34 35#define QIB_7322_Revision_OFFS 0x036#define QIB_7322_Revision_DEF 0x000000000201060137#define QIB_7322_Revision_R_Simulator_LSB 0x3F38#define QIB_7322_Revision_R_Simulator_MSB 0x3F39#define QIB_7322_Revision_R_Simulator_RMASK 0x140#define QIB_7322_Revision_R_Emulation_LSB 0x3E41#define QIB_7322_Revision_R_Emulation_MSB 0x3E42#define QIB_7322_Revision_R_Emulation_RMASK 0x143#define QIB_7322_Revision_R_Emulation_Revcode_LSB 0x2844#define QIB_7322_Revision_R_Emulation_Revcode_MSB 0x3D45#define QIB_7322_Revision_R_Emulation_Revcode_RMASK 0x3FFFFF46#define QIB_7322_Revision_BoardID_LSB 0x2047#define QIB_7322_Revision_BoardID_MSB 0x2748#define QIB_7322_Revision_BoardID_RMASK 0xFF49#define QIB_7322_Revision_R_SW_LSB 0x1850#define QIB_7322_Revision_R_SW_MSB 0x1F51#define QIB_7322_Revision_R_SW_RMASK 0xFF52#define QIB_7322_Revision_R_Arch_LSB 0x1053#define QIB_7322_Revision_R_Arch_MSB 0x1754#define QIB_7322_Revision_R_Arch_RMASK 0xFF55#define QIB_7322_Revision_R_ChipRevMajor_LSB 0x856#define QIB_7322_Revision_R_ChipRevMajor_MSB 0xF57#define QIB_7322_Revision_R_ChipRevMajor_RMASK 0xFF58#define QIB_7322_Revision_R_ChipRevMinor_LSB 0x059#define QIB_7322_Revision_R_ChipRevMinor_MSB 0x760#define QIB_7322_Revision_R_ChipRevMinor_RMASK 0xFF61 62#define QIB_7322_Control_OFFS 0x863#define QIB_7322_Control_DEF 0x000000000000000064#define QIB_7322_Control_PCIECplQDiagEn_LSB 0x665#define QIB_7322_Control_PCIECplQDiagEn_MSB 0x666#define QIB_7322_Control_PCIECplQDiagEn_RMASK 0x167#define QIB_7322_Control_PCIEPostQDiagEn_LSB 0x568#define QIB_7322_Control_PCIEPostQDiagEn_MSB 0x569#define QIB_7322_Control_PCIEPostQDiagEn_RMASK 0x170#define QIB_7322_Control_SDmaDescFetchPriorityEn_LSB 0x471#define QIB_7322_Control_SDmaDescFetchPriorityEn_MSB 0x472#define QIB_7322_Control_SDmaDescFetchPriorityEn_RMASK 0x173#define QIB_7322_Control_PCIERetryBufDiagEn_LSB 0x374#define QIB_7322_Control_PCIERetryBufDiagEn_MSB 0x375#define QIB_7322_Control_PCIERetryBufDiagEn_RMASK 0x176#define QIB_7322_Control_FreezeMode_LSB 0x177#define QIB_7322_Control_FreezeMode_MSB 0x178#define QIB_7322_Control_FreezeMode_RMASK 0x179#define QIB_7322_Control_SyncReset_LSB 0x080#define QIB_7322_Control_SyncReset_MSB 0x081#define QIB_7322_Control_SyncReset_RMASK 0x182 83#define QIB_7322_PageAlign_OFFS 0x1084#define QIB_7322_PageAlign_DEF 0x000000000000100085 86#define QIB_7322_ContextCnt_OFFS 0x1887#define QIB_7322_ContextCnt_DEF 0x000000000000001288 89#define QIB_7322_Scratch_OFFS 0x2090#define QIB_7322_Scratch_DEF 0x000000000000000091 92#define QIB_7322_CntrRegBase_OFFS 0x2893#define QIB_7322_CntrRegBase_DEF 0x000000000001100094 95#define QIB_7322_SendRegBase_OFFS 0x3096#define QIB_7322_SendRegBase_DEF 0x000000000000300097 98#define QIB_7322_UserRegBase_OFFS 0x3899#define QIB_7322_UserRegBase_DEF 0x0000000000200000100 101#define QIB_7322_IntMask_OFFS 0x68102#define QIB_7322_IntMask_DEF 0x0000000000000000103#define QIB_7322_IntMask_SDmaIntMask_1_LSB 0x3F104#define QIB_7322_IntMask_SDmaIntMask_1_MSB 0x3F105#define QIB_7322_IntMask_SDmaIntMask_1_RMASK 0x1106#define QIB_7322_IntMask_SDmaIntMask_0_LSB 0x3E107#define QIB_7322_IntMask_SDmaIntMask_0_MSB 0x3E108#define QIB_7322_IntMask_SDmaIntMask_0_RMASK 0x1109#define QIB_7322_IntMask_SDmaProgressIntMask_1_LSB 0x3D110#define QIB_7322_IntMask_SDmaProgressIntMask_1_MSB 0x3D111#define QIB_7322_IntMask_SDmaProgressIntMask_1_RMASK 0x1112#define QIB_7322_IntMask_SDmaProgressIntMask_0_LSB 0x3C113#define QIB_7322_IntMask_SDmaProgressIntMask_0_MSB 0x3C114#define QIB_7322_IntMask_SDmaProgressIntMask_0_RMASK 0x1115#define QIB_7322_IntMask_SDmaIdleIntMask_1_LSB 0x3B116#define QIB_7322_IntMask_SDmaIdleIntMask_1_MSB 0x3B117#define QIB_7322_IntMask_SDmaIdleIntMask_1_RMASK 0x1118#define QIB_7322_IntMask_SDmaIdleIntMask_0_LSB 0x3A119#define QIB_7322_IntMask_SDmaIdleIntMask_0_MSB 0x3A120#define QIB_7322_IntMask_SDmaIdleIntMask_0_RMASK 0x1121#define QIB_7322_IntMask_SDmaCleanupDoneMask_1_LSB 0x39122#define QIB_7322_IntMask_SDmaCleanupDoneMask_1_MSB 0x39123#define QIB_7322_IntMask_SDmaCleanupDoneMask_1_RMASK 0x1124#define QIB_7322_IntMask_SDmaCleanupDoneMask_0_LSB 0x38125#define QIB_7322_IntMask_SDmaCleanupDoneMask_0_MSB 0x38126#define QIB_7322_IntMask_SDmaCleanupDoneMask_0_RMASK 0x1127#define QIB_7322_IntMask_RcvUrg17IntMask_LSB 0x31128#define QIB_7322_IntMask_RcvUrg17IntMask_MSB 0x31129#define QIB_7322_IntMask_RcvUrg17IntMask_RMASK 0x1130#define QIB_7322_IntMask_RcvUrg16IntMask_LSB 0x30131#define QIB_7322_IntMask_RcvUrg16IntMask_MSB 0x30132#define QIB_7322_IntMask_RcvUrg16IntMask_RMASK 0x1133#define QIB_7322_IntMask_RcvUrg15IntMask_LSB 0x2F134#define QIB_7322_IntMask_RcvUrg15IntMask_MSB 0x2F135#define QIB_7322_IntMask_RcvUrg15IntMask_RMASK 0x1136#define QIB_7322_IntMask_RcvUrg14IntMask_LSB 0x2E137#define QIB_7322_IntMask_RcvUrg14IntMask_MSB 0x2E138#define QIB_7322_IntMask_RcvUrg14IntMask_RMASK 0x1139#define QIB_7322_IntMask_RcvUrg13IntMask_LSB 0x2D140#define QIB_7322_IntMask_RcvUrg13IntMask_MSB 0x2D141#define QIB_7322_IntMask_RcvUrg13IntMask_RMASK 0x1142#define QIB_7322_IntMask_RcvUrg12IntMask_LSB 0x2C143#define QIB_7322_IntMask_RcvUrg12IntMask_MSB 0x2C144#define QIB_7322_IntMask_RcvUrg12IntMask_RMASK 0x1145#define QIB_7322_IntMask_RcvUrg11IntMask_LSB 0x2B146#define QIB_7322_IntMask_RcvUrg11IntMask_MSB 0x2B147#define QIB_7322_IntMask_RcvUrg11IntMask_RMASK 0x1148#define QIB_7322_IntMask_RcvUrg10IntMask_LSB 0x2A149#define QIB_7322_IntMask_RcvUrg10IntMask_MSB 0x2A150#define QIB_7322_IntMask_RcvUrg10IntMask_RMASK 0x1151#define QIB_7322_IntMask_RcvUrg9IntMask_LSB 0x29152#define QIB_7322_IntMask_RcvUrg9IntMask_MSB 0x29153#define QIB_7322_IntMask_RcvUrg9IntMask_RMASK 0x1154#define QIB_7322_IntMask_RcvUrg8IntMask_LSB 0x28155#define QIB_7322_IntMask_RcvUrg8IntMask_MSB 0x28156#define QIB_7322_IntMask_RcvUrg8IntMask_RMASK 0x1157#define QIB_7322_IntMask_RcvUrg7IntMask_LSB 0x27158#define QIB_7322_IntMask_RcvUrg7IntMask_MSB 0x27159#define QIB_7322_IntMask_RcvUrg7IntMask_RMASK 0x1160#define QIB_7322_IntMask_RcvUrg6IntMask_LSB 0x26161#define QIB_7322_IntMask_RcvUrg6IntMask_MSB 0x26162#define QIB_7322_IntMask_RcvUrg6IntMask_RMASK 0x1163#define QIB_7322_IntMask_RcvUrg5IntMask_LSB 0x25164#define QIB_7322_IntMask_RcvUrg5IntMask_MSB 0x25165#define QIB_7322_IntMask_RcvUrg5IntMask_RMASK 0x1166#define QIB_7322_IntMask_RcvUrg4IntMask_LSB 0x24167#define QIB_7322_IntMask_RcvUrg4IntMask_MSB 0x24168#define QIB_7322_IntMask_RcvUrg4IntMask_RMASK 0x1169#define QIB_7322_IntMask_RcvUrg3IntMask_LSB 0x23170#define QIB_7322_IntMask_RcvUrg3IntMask_MSB 0x23171#define QIB_7322_IntMask_RcvUrg3IntMask_RMASK 0x1172#define QIB_7322_IntMask_RcvUrg2IntMask_LSB 0x22173#define QIB_7322_IntMask_RcvUrg2IntMask_MSB 0x22174#define QIB_7322_IntMask_RcvUrg2IntMask_RMASK 0x1175#define QIB_7322_IntMask_RcvUrg1IntMask_LSB 0x21176#define QIB_7322_IntMask_RcvUrg1IntMask_MSB 0x21177#define QIB_7322_IntMask_RcvUrg1IntMask_RMASK 0x1178#define QIB_7322_IntMask_RcvUrg0IntMask_LSB 0x20179#define QIB_7322_IntMask_RcvUrg0IntMask_MSB 0x20180#define QIB_7322_IntMask_RcvUrg0IntMask_RMASK 0x1181#define QIB_7322_IntMask_ErrIntMask_1_LSB 0x1F182#define QIB_7322_IntMask_ErrIntMask_1_MSB 0x1F183#define QIB_7322_IntMask_ErrIntMask_1_RMASK 0x1184#define QIB_7322_IntMask_ErrIntMask_0_LSB 0x1E185#define QIB_7322_IntMask_ErrIntMask_0_MSB 0x1E186#define QIB_7322_IntMask_ErrIntMask_0_RMASK 0x1187#define QIB_7322_IntMask_ErrIntMask_LSB 0x1D188#define QIB_7322_IntMask_ErrIntMask_MSB 0x1D189#define QIB_7322_IntMask_ErrIntMask_RMASK 0x1190#define QIB_7322_IntMask_AssertGPIOIntMask_LSB 0x1C191#define QIB_7322_IntMask_AssertGPIOIntMask_MSB 0x1C192#define QIB_7322_IntMask_AssertGPIOIntMask_RMASK 0x1193#define QIB_7322_IntMask_SendDoneIntMask_1_LSB 0x19194#define QIB_7322_IntMask_SendDoneIntMask_1_MSB 0x19195#define QIB_7322_IntMask_SendDoneIntMask_1_RMASK 0x1196#define QIB_7322_IntMask_SendDoneIntMask_0_LSB 0x18197#define QIB_7322_IntMask_SendDoneIntMask_0_MSB 0x18198#define QIB_7322_IntMask_SendDoneIntMask_0_RMASK 0x1199#define QIB_7322_IntMask_SendBufAvailIntMask_LSB 0x17200#define QIB_7322_IntMask_SendBufAvailIntMask_MSB 0x17201#define QIB_7322_IntMask_SendBufAvailIntMask_RMASK 0x1202#define QIB_7322_IntMask_RcvAvail17IntMask_LSB 0x11203#define QIB_7322_IntMask_RcvAvail17IntMask_MSB 0x11204#define QIB_7322_IntMask_RcvAvail17IntMask_RMASK 0x1205#define QIB_7322_IntMask_RcvAvail16IntMask_LSB 0x10206#define QIB_7322_IntMask_RcvAvail16IntMask_MSB 0x10207#define QIB_7322_IntMask_RcvAvail16IntMask_RMASK 0x1208#define QIB_7322_IntMask_RcvAvail15IntMask_LSB 0xF209#define QIB_7322_IntMask_RcvAvail15IntMask_MSB 0xF210#define QIB_7322_IntMask_RcvAvail15IntMask_RMASK 0x1211#define QIB_7322_IntMask_RcvAvail14IntMask_LSB 0xE212#define QIB_7322_IntMask_RcvAvail14IntMask_MSB 0xE213#define QIB_7322_IntMask_RcvAvail14IntMask_RMASK 0x1214#define QIB_7322_IntMask_RcvAvail13IntMask_LSB 0xD215#define QIB_7322_IntMask_RcvAvail13IntMask_MSB 0xD216#define QIB_7322_IntMask_RcvAvail13IntMask_RMASK 0x1217#define QIB_7322_IntMask_RcvAvail12IntMask_LSB 0xC218#define QIB_7322_IntMask_RcvAvail12IntMask_MSB 0xC219#define QIB_7322_IntMask_RcvAvail12IntMask_RMASK 0x1220#define QIB_7322_IntMask_RcvAvail11IntMask_LSB 0xB221#define QIB_7322_IntMask_RcvAvail11IntMask_MSB 0xB222#define QIB_7322_IntMask_RcvAvail11IntMask_RMASK 0x1223#define QIB_7322_IntMask_RcvAvail10IntMask_LSB 0xA224#define QIB_7322_IntMask_RcvAvail10IntMask_MSB 0xA225#define QIB_7322_IntMask_RcvAvail10IntMask_RMASK 0x1226#define QIB_7322_IntMask_RcvAvail9IntMask_LSB 0x9227#define QIB_7322_IntMask_RcvAvail9IntMask_MSB 0x9228#define QIB_7322_IntMask_RcvAvail9IntMask_RMASK 0x1229#define QIB_7322_IntMask_RcvAvail8IntMask_LSB 0x8230#define QIB_7322_IntMask_RcvAvail8IntMask_MSB 0x8231#define QIB_7322_IntMask_RcvAvail8IntMask_RMASK 0x1232#define QIB_7322_IntMask_RcvAvail7IntMask_LSB 0x7233#define QIB_7322_IntMask_RcvAvail7IntMask_MSB 0x7234#define QIB_7322_IntMask_RcvAvail7IntMask_RMASK 0x1235#define QIB_7322_IntMask_RcvAvail6IntMask_LSB 0x6236#define QIB_7322_IntMask_RcvAvail6IntMask_MSB 0x6237#define QIB_7322_IntMask_RcvAvail6IntMask_RMASK 0x1238#define QIB_7322_IntMask_RcvAvail5IntMask_LSB 0x5239#define QIB_7322_IntMask_RcvAvail5IntMask_MSB 0x5240#define QIB_7322_IntMask_RcvAvail5IntMask_RMASK 0x1241#define QIB_7322_IntMask_RcvAvail4IntMask_LSB 0x4242#define QIB_7322_IntMask_RcvAvail4IntMask_MSB 0x4243#define QIB_7322_IntMask_RcvAvail4IntMask_RMASK 0x1244#define QIB_7322_IntMask_RcvAvail3IntMask_LSB 0x3245#define QIB_7322_IntMask_RcvAvail3IntMask_MSB 0x3246#define QIB_7322_IntMask_RcvAvail3IntMask_RMASK 0x1247#define QIB_7322_IntMask_RcvAvail2IntMask_LSB 0x2248#define QIB_7322_IntMask_RcvAvail2IntMask_MSB 0x2249#define QIB_7322_IntMask_RcvAvail2IntMask_RMASK 0x1250#define QIB_7322_IntMask_RcvAvail1IntMask_LSB 0x1251#define QIB_7322_IntMask_RcvAvail1IntMask_MSB 0x1252#define QIB_7322_IntMask_RcvAvail1IntMask_RMASK 0x1253#define QIB_7322_IntMask_RcvAvail0IntMask_LSB 0x0254#define QIB_7322_IntMask_RcvAvail0IntMask_MSB 0x0255#define QIB_7322_IntMask_RcvAvail0IntMask_RMASK 0x1256 257#define QIB_7322_IntStatus_OFFS 0x70258#define QIB_7322_IntStatus_DEF 0x0000000000000000259#define QIB_7322_IntStatus_SDmaInt_1_LSB 0x3F260#define QIB_7322_IntStatus_SDmaInt_1_MSB 0x3F261#define QIB_7322_IntStatus_SDmaInt_1_RMASK 0x1262#define QIB_7322_IntStatus_SDmaInt_0_LSB 0x3E263#define QIB_7322_IntStatus_SDmaInt_0_MSB 0x3E264#define QIB_7322_IntStatus_SDmaInt_0_RMASK 0x1265#define QIB_7322_IntStatus_SDmaProgressInt_1_LSB 0x3D266#define QIB_7322_IntStatus_SDmaProgressInt_1_MSB 0x3D267#define QIB_7322_IntStatus_SDmaProgressInt_1_RMASK 0x1268#define QIB_7322_IntStatus_SDmaProgressInt_0_LSB 0x3C269#define QIB_7322_IntStatus_SDmaProgressInt_0_MSB 0x3C270#define QIB_7322_IntStatus_SDmaProgressInt_0_RMASK 0x1271#define QIB_7322_IntStatus_SDmaIdleInt_1_LSB 0x3B272#define QIB_7322_IntStatus_SDmaIdleInt_1_MSB 0x3B273#define QIB_7322_IntStatus_SDmaIdleInt_1_RMASK 0x1274#define QIB_7322_IntStatus_SDmaIdleInt_0_LSB 0x3A275#define QIB_7322_IntStatus_SDmaIdleInt_0_MSB 0x3A276#define QIB_7322_IntStatus_SDmaIdleInt_0_RMASK 0x1277#define QIB_7322_IntStatus_SDmaCleanupDone_1_LSB 0x39278#define QIB_7322_IntStatus_SDmaCleanupDone_1_MSB 0x39279#define QIB_7322_IntStatus_SDmaCleanupDone_1_RMASK 0x1280#define QIB_7322_IntStatus_SDmaCleanupDone_0_LSB 0x38281#define QIB_7322_IntStatus_SDmaCleanupDone_0_MSB 0x38282#define QIB_7322_IntStatus_SDmaCleanupDone_0_RMASK 0x1283#define QIB_7322_IntStatus_RcvUrg17_LSB 0x31284#define QIB_7322_IntStatus_RcvUrg17_MSB 0x31285#define QIB_7322_IntStatus_RcvUrg17_RMASK 0x1286#define QIB_7322_IntStatus_RcvUrg16_LSB 0x30287#define QIB_7322_IntStatus_RcvUrg16_MSB 0x30288#define QIB_7322_IntStatus_RcvUrg16_RMASK 0x1289#define QIB_7322_IntStatus_RcvUrg15_LSB 0x2F290#define QIB_7322_IntStatus_RcvUrg15_MSB 0x2F291#define QIB_7322_IntStatus_RcvUrg15_RMASK 0x1292#define QIB_7322_IntStatus_RcvUrg14_LSB 0x2E293#define QIB_7322_IntStatus_RcvUrg14_MSB 0x2E294#define QIB_7322_IntStatus_RcvUrg14_RMASK 0x1295#define QIB_7322_IntStatus_RcvUrg13_LSB 0x2D296#define QIB_7322_IntStatus_RcvUrg13_MSB 0x2D297#define QIB_7322_IntStatus_RcvUrg13_RMASK 0x1298#define QIB_7322_IntStatus_RcvUrg12_LSB 0x2C299#define QIB_7322_IntStatus_RcvUrg12_MSB 0x2C300#define QIB_7322_IntStatus_RcvUrg12_RMASK 0x1301#define QIB_7322_IntStatus_RcvUrg11_LSB 0x2B302#define QIB_7322_IntStatus_RcvUrg11_MSB 0x2B303#define QIB_7322_IntStatus_RcvUrg11_RMASK 0x1304#define QIB_7322_IntStatus_RcvUrg10_LSB 0x2A305#define QIB_7322_IntStatus_RcvUrg10_MSB 0x2A306#define QIB_7322_IntStatus_RcvUrg10_RMASK 0x1307#define QIB_7322_IntStatus_RcvUrg9_LSB 0x29308#define QIB_7322_IntStatus_RcvUrg9_MSB 0x29309#define QIB_7322_IntStatus_RcvUrg9_RMASK 0x1310#define QIB_7322_IntStatus_RcvUrg8_LSB 0x28311#define QIB_7322_IntStatus_RcvUrg8_MSB 0x28312#define QIB_7322_IntStatus_RcvUrg8_RMASK 0x1313#define QIB_7322_IntStatus_RcvUrg7_LSB 0x27314#define QIB_7322_IntStatus_RcvUrg7_MSB 0x27315#define QIB_7322_IntStatus_RcvUrg7_RMASK 0x1316#define QIB_7322_IntStatus_RcvUrg6_LSB 0x26317#define QIB_7322_IntStatus_RcvUrg6_MSB 0x26318#define QIB_7322_IntStatus_RcvUrg6_RMASK 0x1319#define QIB_7322_IntStatus_RcvUrg5_LSB 0x25320#define QIB_7322_IntStatus_RcvUrg5_MSB 0x25321#define QIB_7322_IntStatus_RcvUrg5_RMASK 0x1322#define QIB_7322_IntStatus_RcvUrg4_LSB 0x24323#define QIB_7322_IntStatus_RcvUrg4_MSB 0x24324#define QIB_7322_IntStatus_RcvUrg4_RMASK 0x1325#define QIB_7322_IntStatus_RcvUrg3_LSB 0x23326#define QIB_7322_IntStatus_RcvUrg3_MSB 0x23327#define QIB_7322_IntStatus_RcvUrg3_RMASK 0x1328#define QIB_7322_IntStatus_RcvUrg2_LSB 0x22329#define QIB_7322_IntStatus_RcvUrg2_MSB 0x22330#define QIB_7322_IntStatus_RcvUrg2_RMASK 0x1331#define QIB_7322_IntStatus_RcvUrg1_LSB 0x21332#define QIB_7322_IntStatus_RcvUrg1_MSB 0x21333#define QIB_7322_IntStatus_RcvUrg1_RMASK 0x1334#define QIB_7322_IntStatus_RcvUrg0_LSB 0x20335#define QIB_7322_IntStatus_RcvUrg0_MSB 0x20336#define QIB_7322_IntStatus_RcvUrg0_RMASK 0x1337#define QIB_7322_IntStatus_Err_1_LSB 0x1F338#define QIB_7322_IntStatus_Err_1_MSB 0x1F339#define QIB_7322_IntStatus_Err_1_RMASK 0x1340#define QIB_7322_IntStatus_Err_0_LSB 0x1E341#define QIB_7322_IntStatus_Err_0_MSB 0x1E342#define QIB_7322_IntStatus_Err_0_RMASK 0x1343#define QIB_7322_IntStatus_Err_LSB 0x1D344#define QIB_7322_IntStatus_Err_MSB 0x1D345#define QIB_7322_IntStatus_Err_RMASK 0x1346#define QIB_7322_IntStatus_AssertGPIO_LSB 0x1C347#define QIB_7322_IntStatus_AssertGPIO_MSB 0x1C348#define QIB_7322_IntStatus_AssertGPIO_RMASK 0x1349#define QIB_7322_IntStatus_SendDone_1_LSB 0x19350#define QIB_7322_IntStatus_SendDone_1_MSB 0x19351#define QIB_7322_IntStatus_SendDone_1_RMASK 0x1352#define QIB_7322_IntStatus_SendDone_0_LSB 0x18353#define QIB_7322_IntStatus_SendDone_0_MSB 0x18354#define QIB_7322_IntStatus_SendDone_0_RMASK 0x1355#define QIB_7322_IntStatus_SendBufAvail_LSB 0x17356#define QIB_7322_IntStatus_SendBufAvail_MSB 0x17357#define QIB_7322_IntStatus_SendBufAvail_RMASK 0x1358#define QIB_7322_IntStatus_RcvAvail17_LSB 0x11359#define QIB_7322_IntStatus_RcvAvail17_MSB 0x11360#define QIB_7322_IntStatus_RcvAvail17_RMASK 0x1361#define QIB_7322_IntStatus_RcvAvail16_LSB 0x10362#define QIB_7322_IntStatus_RcvAvail16_MSB 0x10363#define QIB_7322_IntStatus_RcvAvail16_RMASK 0x1364#define QIB_7322_IntStatus_RcvAvail15_LSB 0xF365#define QIB_7322_IntStatus_RcvAvail15_MSB 0xF366#define QIB_7322_IntStatus_RcvAvail15_RMASK 0x1367#define QIB_7322_IntStatus_RcvAvail14_LSB 0xE368#define QIB_7322_IntStatus_RcvAvail14_MSB 0xE369#define QIB_7322_IntStatus_RcvAvail14_RMASK 0x1370#define QIB_7322_IntStatus_RcvAvail13_LSB 0xD371#define QIB_7322_IntStatus_RcvAvail13_MSB 0xD372#define QIB_7322_IntStatus_RcvAvail13_RMASK 0x1373#define QIB_7322_IntStatus_RcvAvail12_LSB 0xC374#define QIB_7322_IntStatus_RcvAvail12_MSB 0xC375#define QIB_7322_IntStatus_RcvAvail12_RMASK 0x1376#define QIB_7322_IntStatus_RcvAvail11_LSB 0xB377#define QIB_7322_IntStatus_RcvAvail11_MSB 0xB378#define QIB_7322_IntStatus_RcvAvail11_RMASK 0x1379#define QIB_7322_IntStatus_RcvAvail10_LSB 0xA380#define QIB_7322_IntStatus_RcvAvail10_MSB 0xA381#define QIB_7322_IntStatus_RcvAvail10_RMASK 0x1382#define QIB_7322_IntStatus_RcvAvail9_LSB 0x9383#define QIB_7322_IntStatus_RcvAvail9_MSB 0x9384#define QIB_7322_IntStatus_RcvAvail9_RMASK 0x1385#define QIB_7322_IntStatus_RcvAvail8_LSB 0x8386#define QIB_7322_IntStatus_RcvAvail8_MSB 0x8387#define QIB_7322_IntStatus_RcvAvail8_RMASK 0x1388#define QIB_7322_IntStatus_RcvAvail7_LSB 0x7389#define QIB_7322_IntStatus_RcvAvail7_MSB 0x7390#define QIB_7322_IntStatus_RcvAvail7_RMASK 0x1391#define QIB_7322_IntStatus_RcvAvail6_LSB 0x6392#define QIB_7322_IntStatus_RcvAvail6_MSB 0x6393#define QIB_7322_IntStatus_RcvAvail6_RMASK 0x1394#define QIB_7322_IntStatus_RcvAvail5_LSB 0x5395#define QIB_7322_IntStatus_RcvAvail5_MSB 0x5396#define QIB_7322_IntStatus_RcvAvail5_RMASK 0x1397#define QIB_7322_IntStatus_RcvAvail4_LSB 0x4398#define QIB_7322_IntStatus_RcvAvail4_MSB 0x4399#define QIB_7322_IntStatus_RcvAvail4_RMASK 0x1400#define QIB_7322_IntStatus_RcvAvail3_LSB 0x3401#define QIB_7322_IntStatus_RcvAvail3_MSB 0x3402#define QIB_7322_IntStatus_RcvAvail3_RMASK 0x1403#define QIB_7322_IntStatus_RcvAvail2_LSB 0x2404#define QIB_7322_IntStatus_RcvAvail2_MSB 0x2405#define QIB_7322_IntStatus_RcvAvail2_RMASK 0x1406#define QIB_7322_IntStatus_RcvAvail1_LSB 0x1407#define QIB_7322_IntStatus_RcvAvail1_MSB 0x1408#define QIB_7322_IntStatus_RcvAvail1_RMASK 0x1409#define QIB_7322_IntStatus_RcvAvail0_LSB 0x0410#define QIB_7322_IntStatus_RcvAvail0_MSB 0x0411#define QIB_7322_IntStatus_RcvAvail0_RMASK 0x1412 413#define QIB_7322_IntClear_OFFS 0x78414#define QIB_7322_IntClear_DEF 0x0000000000000000415#define QIB_7322_IntClear_SDmaIntClear_1_LSB 0x3F416#define QIB_7322_IntClear_SDmaIntClear_1_MSB 0x3F417#define QIB_7322_IntClear_SDmaIntClear_1_RMASK 0x1418#define QIB_7322_IntClear_SDmaIntClear_0_LSB 0x3E419#define QIB_7322_IntClear_SDmaIntClear_0_MSB 0x3E420#define QIB_7322_IntClear_SDmaIntClear_0_RMASK 0x1421#define QIB_7322_IntClear_SDmaProgressIntClear_1_LSB 0x3D422#define QIB_7322_IntClear_SDmaProgressIntClear_1_MSB 0x3D423#define QIB_7322_IntClear_SDmaProgressIntClear_1_RMASK 0x1424#define QIB_7322_IntClear_SDmaProgressIntClear_0_LSB 0x3C425#define QIB_7322_IntClear_SDmaProgressIntClear_0_MSB 0x3C426#define QIB_7322_IntClear_SDmaProgressIntClear_0_RMASK 0x1427#define QIB_7322_IntClear_SDmaIdleIntClear_1_LSB 0x3B428#define QIB_7322_IntClear_SDmaIdleIntClear_1_MSB 0x3B429#define QIB_7322_IntClear_SDmaIdleIntClear_1_RMASK 0x1430#define QIB_7322_IntClear_SDmaIdleIntClear_0_LSB 0x3A431#define QIB_7322_IntClear_SDmaIdleIntClear_0_MSB 0x3A432#define QIB_7322_IntClear_SDmaIdleIntClear_0_RMASK 0x1433#define QIB_7322_IntClear_SDmaCleanupDoneClear_1_LSB 0x39434#define QIB_7322_IntClear_SDmaCleanupDoneClear_1_MSB 0x39435#define QIB_7322_IntClear_SDmaCleanupDoneClear_1_RMASK 0x1436#define QIB_7322_IntClear_SDmaCleanupDoneClear_0_LSB 0x38437#define QIB_7322_IntClear_SDmaCleanupDoneClear_0_MSB 0x38438#define QIB_7322_IntClear_SDmaCleanupDoneClear_0_RMASK 0x1439#define QIB_7322_IntClear_RcvUrg17IntClear_LSB 0x31440#define QIB_7322_IntClear_RcvUrg17IntClear_MSB 0x31441#define QIB_7322_IntClear_RcvUrg17IntClear_RMASK 0x1442#define QIB_7322_IntClear_RcvUrg16IntClear_LSB 0x30443#define QIB_7322_IntClear_RcvUrg16IntClear_MSB 0x30444#define QIB_7322_IntClear_RcvUrg16IntClear_RMASK 0x1445#define QIB_7322_IntClear_RcvUrg15IntClear_LSB 0x2F446#define QIB_7322_IntClear_RcvUrg15IntClear_MSB 0x2F447#define QIB_7322_IntClear_RcvUrg15IntClear_RMASK 0x1448#define QIB_7322_IntClear_RcvUrg14IntClear_LSB 0x2E449#define QIB_7322_IntClear_RcvUrg14IntClear_MSB 0x2E450#define QIB_7322_IntClear_RcvUrg14IntClear_RMASK 0x1451#define QIB_7322_IntClear_RcvUrg13IntClear_LSB 0x2D452#define QIB_7322_IntClear_RcvUrg13IntClear_MSB 0x2D453#define QIB_7322_IntClear_RcvUrg13IntClear_RMASK 0x1454#define QIB_7322_IntClear_RcvUrg12IntClear_LSB 0x2C455#define QIB_7322_IntClear_RcvUrg12IntClear_MSB 0x2C456#define QIB_7322_IntClear_RcvUrg12IntClear_RMASK 0x1457#define QIB_7322_IntClear_RcvUrg11IntClear_LSB 0x2B458#define QIB_7322_IntClear_RcvUrg11IntClear_MSB 0x2B459#define QIB_7322_IntClear_RcvUrg11IntClear_RMASK 0x1460#define QIB_7322_IntClear_RcvUrg10IntClear_LSB 0x2A461#define QIB_7322_IntClear_RcvUrg10IntClear_MSB 0x2A462#define QIB_7322_IntClear_RcvUrg10IntClear_RMASK 0x1463#define QIB_7322_IntClear_RcvUrg9IntClear_LSB 0x29464#define QIB_7322_IntClear_RcvUrg9IntClear_MSB 0x29465#define QIB_7322_IntClear_RcvUrg9IntClear_RMASK 0x1466#define QIB_7322_IntClear_RcvUrg8IntClear_LSB 0x28467#define QIB_7322_IntClear_RcvUrg8IntClear_MSB 0x28468#define QIB_7322_IntClear_RcvUrg8IntClear_RMASK 0x1469#define QIB_7322_IntClear_RcvUrg7IntClear_LSB 0x27470#define QIB_7322_IntClear_RcvUrg7IntClear_MSB 0x27471#define QIB_7322_IntClear_RcvUrg7IntClear_RMASK 0x1472#define QIB_7322_IntClear_RcvUrg6IntClear_LSB 0x26473#define QIB_7322_IntClear_RcvUrg6IntClear_MSB 0x26474#define QIB_7322_IntClear_RcvUrg6IntClear_RMASK 0x1475#define QIB_7322_IntClear_RcvUrg5IntClear_LSB 0x25476#define QIB_7322_IntClear_RcvUrg5IntClear_MSB 0x25477#define QIB_7322_IntClear_RcvUrg5IntClear_RMASK 0x1478#define QIB_7322_IntClear_RcvUrg4IntClear_LSB 0x24479#define QIB_7322_IntClear_RcvUrg4IntClear_MSB 0x24480#define QIB_7322_IntClear_RcvUrg4IntClear_RMASK 0x1481#define QIB_7322_IntClear_RcvUrg3IntClear_LSB 0x23482#define QIB_7322_IntClear_RcvUrg3IntClear_MSB 0x23483#define QIB_7322_IntClear_RcvUrg3IntClear_RMASK 0x1484#define QIB_7322_IntClear_RcvUrg2IntClear_LSB 0x22485#define QIB_7322_IntClear_RcvUrg2IntClear_MSB 0x22486#define QIB_7322_IntClear_RcvUrg2IntClear_RMASK 0x1487#define QIB_7322_IntClear_RcvUrg1IntClear_LSB 0x21488#define QIB_7322_IntClear_RcvUrg1IntClear_MSB 0x21489#define QIB_7322_IntClear_RcvUrg1IntClear_RMASK 0x1490#define QIB_7322_IntClear_RcvUrg0IntClear_LSB 0x20491#define QIB_7322_IntClear_RcvUrg0IntClear_MSB 0x20492#define QIB_7322_IntClear_RcvUrg0IntClear_RMASK 0x1493#define QIB_7322_IntClear_ErrIntClear_1_LSB 0x1F494#define QIB_7322_IntClear_ErrIntClear_1_MSB 0x1F495#define QIB_7322_IntClear_ErrIntClear_1_RMASK 0x1496#define QIB_7322_IntClear_ErrIntClear_0_LSB 0x1E497#define QIB_7322_IntClear_ErrIntClear_0_MSB 0x1E498#define QIB_7322_IntClear_ErrIntClear_0_RMASK 0x1499#define QIB_7322_IntClear_ErrIntClear_LSB 0x1D500#define QIB_7322_IntClear_ErrIntClear_MSB 0x1D501#define QIB_7322_IntClear_ErrIntClear_RMASK 0x1502#define QIB_7322_IntClear_AssertGPIOIntClear_LSB 0x1C503#define QIB_7322_IntClear_AssertGPIOIntClear_MSB 0x1C504#define QIB_7322_IntClear_AssertGPIOIntClear_RMASK 0x1505#define QIB_7322_IntClear_SendDoneIntClear_1_LSB 0x19506#define QIB_7322_IntClear_SendDoneIntClear_1_MSB 0x19507#define QIB_7322_IntClear_SendDoneIntClear_1_RMASK 0x1508#define QIB_7322_IntClear_SendDoneIntClear_0_LSB 0x18509#define QIB_7322_IntClear_SendDoneIntClear_0_MSB 0x18510#define QIB_7322_IntClear_SendDoneIntClear_0_RMASK 0x1511#define QIB_7322_IntClear_SendBufAvailIntClear_LSB 0x17512#define QIB_7322_IntClear_SendBufAvailIntClear_MSB 0x17513#define QIB_7322_IntClear_SendBufAvailIntClear_RMASK 0x1514#define QIB_7322_IntClear_RcvAvail17IntClear_LSB 0x11515#define QIB_7322_IntClear_RcvAvail17IntClear_MSB 0x11516#define QIB_7322_IntClear_RcvAvail17IntClear_RMASK 0x1517#define QIB_7322_IntClear_RcvAvail16IntClear_LSB 0x10518#define QIB_7322_IntClear_RcvAvail16IntClear_MSB 0x10519#define QIB_7322_IntClear_RcvAvail16IntClear_RMASK 0x1520#define QIB_7322_IntClear_RcvAvail15IntClear_LSB 0xF521#define QIB_7322_IntClear_RcvAvail15IntClear_MSB 0xF522#define QIB_7322_IntClear_RcvAvail15IntClear_RMASK 0x1523#define QIB_7322_IntClear_RcvAvail14IntClear_LSB 0xE524#define QIB_7322_IntClear_RcvAvail14IntClear_MSB 0xE525#define QIB_7322_IntClear_RcvAvail14IntClear_RMASK 0x1526#define QIB_7322_IntClear_RcvAvail13IntClear_LSB 0xD527#define QIB_7322_IntClear_RcvAvail13IntClear_MSB 0xD528#define QIB_7322_IntClear_RcvAvail13IntClear_RMASK 0x1529#define QIB_7322_IntClear_RcvAvail12IntClear_LSB 0xC530#define QIB_7322_IntClear_RcvAvail12IntClear_MSB 0xC531#define QIB_7322_IntClear_RcvAvail12IntClear_RMASK 0x1532#define QIB_7322_IntClear_RcvAvail11IntClear_LSB 0xB533#define QIB_7322_IntClear_RcvAvail11IntClear_MSB 0xB534#define QIB_7322_IntClear_RcvAvail11IntClear_RMASK 0x1535#define QIB_7322_IntClear_RcvAvail10IntClear_LSB 0xA536#define QIB_7322_IntClear_RcvAvail10IntClear_MSB 0xA537#define QIB_7322_IntClear_RcvAvail10IntClear_RMASK 0x1538#define QIB_7322_IntClear_RcvAvail9IntClear_LSB 0x9539#define QIB_7322_IntClear_RcvAvail9IntClear_MSB 0x9540#define QIB_7322_IntClear_RcvAvail9IntClear_RMASK 0x1541#define QIB_7322_IntClear_RcvAvail8IntClear_LSB 0x8542#define QIB_7322_IntClear_RcvAvail8IntClear_MSB 0x8543#define QIB_7322_IntClear_RcvAvail8IntClear_RMASK 0x1544#define QIB_7322_IntClear_RcvAvail7IntClear_LSB 0x7545#define QIB_7322_IntClear_RcvAvail7IntClear_MSB 0x7546#define QIB_7322_IntClear_RcvAvail7IntClear_RMASK 0x1547#define QIB_7322_IntClear_RcvAvail6IntClear_LSB 0x6548#define QIB_7322_IntClear_RcvAvail6IntClear_MSB 0x6549#define QIB_7322_IntClear_RcvAvail6IntClear_RMASK 0x1550#define QIB_7322_IntClear_RcvAvail5IntClear_LSB 0x5551#define QIB_7322_IntClear_RcvAvail5IntClear_MSB 0x5552#define QIB_7322_IntClear_RcvAvail5IntClear_RMASK 0x1553#define QIB_7322_IntClear_RcvAvail4IntClear_LSB 0x4554#define QIB_7322_IntClear_RcvAvail4IntClear_MSB 0x4555#define QIB_7322_IntClear_RcvAvail4IntClear_RMASK 0x1556#define QIB_7322_IntClear_RcvAvail3IntClear_LSB 0x3557#define QIB_7322_IntClear_RcvAvail3IntClear_MSB 0x3558#define QIB_7322_IntClear_RcvAvail3IntClear_RMASK 0x1559#define QIB_7322_IntClear_RcvAvail2IntClear_LSB 0x2560#define QIB_7322_IntClear_RcvAvail2IntClear_MSB 0x2561#define QIB_7322_IntClear_RcvAvail2IntClear_RMASK 0x1562#define QIB_7322_IntClear_RcvAvail1IntClear_LSB 0x1563#define QIB_7322_IntClear_RcvAvail1IntClear_MSB 0x1564#define QIB_7322_IntClear_RcvAvail1IntClear_RMASK 0x1565#define QIB_7322_IntClear_RcvAvail0IntClear_LSB 0x0566#define QIB_7322_IntClear_RcvAvail0IntClear_MSB 0x0567#define QIB_7322_IntClear_RcvAvail0IntClear_RMASK 0x1568 569#define QIB_7322_ErrMask_OFFS 0x80570#define QIB_7322_ErrMask_DEF 0x0000000000000000571#define QIB_7322_ErrMask_ResetNegatedMask_LSB 0x3F572#define QIB_7322_ErrMask_ResetNegatedMask_MSB 0x3F573#define QIB_7322_ErrMask_ResetNegatedMask_RMASK 0x1574#define QIB_7322_ErrMask_HardwareErrMask_LSB 0x3E575#define QIB_7322_ErrMask_HardwareErrMask_MSB 0x3E576#define QIB_7322_ErrMask_HardwareErrMask_RMASK 0x1577#define QIB_7322_ErrMask_InvalidAddrErrMask_LSB 0x3D578#define QIB_7322_ErrMask_InvalidAddrErrMask_MSB 0x3D579#define QIB_7322_ErrMask_InvalidAddrErrMask_RMASK 0x1580#define QIB_7322_ErrMask_SDmaVL15ErrMask_LSB 0x38581#define QIB_7322_ErrMask_SDmaVL15ErrMask_MSB 0x38582#define QIB_7322_ErrMask_SDmaVL15ErrMask_RMASK 0x1583#define QIB_7322_ErrMask_SBufVL15MisUseErrMask_LSB 0x37584#define QIB_7322_ErrMask_SBufVL15MisUseErrMask_MSB 0x37585#define QIB_7322_ErrMask_SBufVL15MisUseErrMask_RMASK 0x1586#define QIB_7322_ErrMask_InvalidEEPCmdMask_LSB 0x35587#define QIB_7322_ErrMask_InvalidEEPCmdMask_MSB 0x35588#define QIB_7322_ErrMask_InvalidEEPCmdMask_RMASK 0x1589#define QIB_7322_ErrMask_RcvContextShareErrMask_LSB 0x34590#define QIB_7322_ErrMask_RcvContextShareErrMask_MSB 0x34591#define QIB_7322_ErrMask_RcvContextShareErrMask_RMASK 0x1592#define QIB_7322_ErrMask_SendVLMismatchErrMask_LSB 0x24593#define QIB_7322_ErrMask_SendVLMismatchErrMask_MSB 0x24594#define QIB_7322_ErrMask_SendVLMismatchErrMask_RMASK 0x1595#define QIB_7322_ErrMask_SendArmLaunchErrMask_LSB 0x23596#define QIB_7322_ErrMask_SendArmLaunchErrMask_MSB 0x23597#define QIB_7322_ErrMask_SendArmLaunchErrMask_RMASK 0x1598#define QIB_7322_ErrMask_SendSpecialTriggerErrMask_LSB 0x1B599#define QIB_7322_ErrMask_SendSpecialTriggerErrMask_MSB 0x1B600#define QIB_7322_ErrMask_SendSpecialTriggerErrMask_RMASK 0x1601#define QIB_7322_ErrMask_SDmaWrongPortErrMask_LSB 0x1A602#define QIB_7322_ErrMask_SDmaWrongPortErrMask_MSB 0x1A603#define QIB_7322_ErrMask_SDmaWrongPortErrMask_RMASK 0x1604#define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_LSB 0x19605#define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_MSB 0x19606#define QIB_7322_ErrMask_SDmaBufMaskDuplicateErrMask_RMASK 0x1607#define QIB_7322_ErrMask_RcvHdrFullErrMask_LSB 0xD608#define QIB_7322_ErrMask_RcvHdrFullErrMask_MSB 0xD609#define QIB_7322_ErrMask_RcvHdrFullErrMask_RMASK 0x1610#define QIB_7322_ErrMask_RcvEgrFullErrMask_LSB 0xC611#define QIB_7322_ErrMask_RcvEgrFullErrMask_MSB 0xC612#define QIB_7322_ErrMask_RcvEgrFullErrMask_RMASK 0x1613 614#define QIB_7322_ErrStatus_OFFS 0x88615#define QIB_7322_ErrStatus_DEF 0x0000000000000000616#define QIB_7322_ErrStatus_ResetNegated_LSB 0x3F617#define QIB_7322_ErrStatus_ResetNegated_MSB 0x3F618#define QIB_7322_ErrStatus_ResetNegated_RMASK 0x1619#define QIB_7322_ErrStatus_HardwareErr_LSB 0x3E620#define QIB_7322_ErrStatus_HardwareErr_MSB 0x3E621#define QIB_7322_ErrStatus_HardwareErr_RMASK 0x1622#define QIB_7322_ErrStatus_InvalidAddrErr_LSB 0x3D623#define QIB_7322_ErrStatus_InvalidAddrErr_MSB 0x3D624#define QIB_7322_ErrStatus_InvalidAddrErr_RMASK 0x1625#define QIB_7322_ErrStatus_SDmaVL15Err_LSB 0x38626#define QIB_7322_ErrStatus_SDmaVL15Err_MSB 0x38627#define QIB_7322_ErrStatus_SDmaVL15Err_RMASK 0x1628#define QIB_7322_ErrStatus_SBufVL15MisUseErr_LSB 0x37629#define QIB_7322_ErrStatus_SBufVL15MisUseErr_MSB 0x37630#define QIB_7322_ErrStatus_SBufVL15MisUseErr_RMASK 0x1631#define QIB_7322_ErrStatus_InvalidEEPCmdErr_LSB 0x35632#define QIB_7322_ErrStatus_InvalidEEPCmdErr_MSB 0x35633#define QIB_7322_ErrStatus_InvalidEEPCmdErr_RMASK 0x1634#define QIB_7322_ErrStatus_RcvContextShareErr_LSB 0x34635#define QIB_7322_ErrStatus_RcvContextShareErr_MSB 0x34636#define QIB_7322_ErrStatus_RcvContextShareErr_RMASK 0x1637#define QIB_7322_ErrStatus_SendVLMismatchErr_LSB 0x24638#define QIB_7322_ErrStatus_SendVLMismatchErr_MSB 0x24639#define QIB_7322_ErrStatus_SendVLMismatchErr_RMASK 0x1640#define QIB_7322_ErrStatus_SendArmLaunchErr_LSB 0x23641#define QIB_7322_ErrStatus_SendArmLaunchErr_MSB 0x23642#define QIB_7322_ErrStatus_SendArmLaunchErr_RMASK 0x1643#define QIB_7322_ErrStatus_SendSpecialTriggerErr_LSB 0x1B644#define QIB_7322_ErrStatus_SendSpecialTriggerErr_MSB 0x1B645#define QIB_7322_ErrStatus_SendSpecialTriggerErr_RMASK 0x1646#define QIB_7322_ErrStatus_SDmaWrongPortErr_LSB 0x1A647#define QIB_7322_ErrStatus_SDmaWrongPortErr_MSB 0x1A648#define QIB_7322_ErrStatus_SDmaWrongPortErr_RMASK 0x1649#define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_LSB 0x19650#define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_MSB 0x19651#define QIB_7322_ErrStatus_SDmaBufMaskDuplicateErr_RMASK 0x1652#define QIB_7322_ErrStatus_RcvHdrFullErr_LSB 0xD653#define QIB_7322_ErrStatus_RcvHdrFullErr_MSB 0xD654#define QIB_7322_ErrStatus_RcvHdrFullErr_RMASK 0x1655#define QIB_7322_ErrStatus_RcvEgrFullErr_LSB 0xC656#define QIB_7322_ErrStatus_RcvEgrFullErr_MSB 0xC657#define QIB_7322_ErrStatus_RcvEgrFullErr_RMASK 0x1658 659#define QIB_7322_ErrClear_OFFS 0x90660#define QIB_7322_ErrClear_DEF 0x0000000000000000661#define QIB_7322_ErrClear_ResetNegatedClear_LSB 0x3F662#define QIB_7322_ErrClear_ResetNegatedClear_MSB 0x3F663#define QIB_7322_ErrClear_ResetNegatedClear_RMASK 0x1664#define QIB_7322_ErrClear_HardwareErrClear_LSB 0x3E665#define QIB_7322_ErrClear_HardwareErrClear_MSB 0x3E666#define QIB_7322_ErrClear_HardwareErrClear_RMASK 0x1667#define QIB_7322_ErrClear_InvalidAddrErrClear_LSB 0x3D668#define QIB_7322_ErrClear_InvalidAddrErrClear_MSB 0x3D669#define QIB_7322_ErrClear_InvalidAddrErrClear_RMASK 0x1670#define QIB_7322_ErrClear_SDmaVL15ErrClear_LSB 0x38671#define QIB_7322_ErrClear_SDmaVL15ErrClear_MSB 0x38672#define QIB_7322_ErrClear_SDmaVL15ErrClear_RMASK 0x1673#define QIB_7322_ErrClear_SBufVL15MisUseErrClear_LSB 0x37674#define QIB_7322_ErrClear_SBufVL15MisUseErrClear_MSB 0x37675#define QIB_7322_ErrClear_SBufVL15MisUseErrClear_RMASK 0x1676#define QIB_7322_ErrClear_InvalidEEPCmdErrClear_LSB 0x35677#define QIB_7322_ErrClear_InvalidEEPCmdErrClear_MSB 0x35678#define QIB_7322_ErrClear_InvalidEEPCmdErrClear_RMASK 0x1679#define QIB_7322_ErrClear_RcvContextShareErrClear_LSB 0x34680#define QIB_7322_ErrClear_RcvContextShareErrClear_MSB 0x34681#define QIB_7322_ErrClear_RcvContextShareErrClear_RMASK 0x1682#define QIB_7322_ErrClear_SendVLMismatchErrMask_LSB 0x24683#define QIB_7322_ErrClear_SendVLMismatchErrMask_MSB 0x24684#define QIB_7322_ErrClear_SendVLMismatchErrMask_RMASK 0x1685#define QIB_7322_ErrClear_SendArmLaunchErrClear_LSB 0x23686#define QIB_7322_ErrClear_SendArmLaunchErrClear_MSB 0x23687#define QIB_7322_ErrClear_SendArmLaunchErrClear_RMASK 0x1688#define QIB_7322_ErrClear_SendSpecialTriggerErrClear_LSB 0x1B689#define QIB_7322_ErrClear_SendSpecialTriggerErrClear_MSB 0x1B690#define QIB_7322_ErrClear_SendSpecialTriggerErrClear_RMASK 0x1691#define QIB_7322_ErrClear_SDmaWrongPortErrClear_LSB 0x1A692#define QIB_7322_ErrClear_SDmaWrongPortErrClear_MSB 0x1A693#define QIB_7322_ErrClear_SDmaWrongPortErrClear_RMASK 0x1694#define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_LSB 0x19695#define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_MSB 0x19696#define QIB_7322_ErrClear_SDmaBufMaskDuplicateErrClear_RMASK 0x1697#define QIB_7322_ErrClear_RcvHdrFullErrClear_LSB 0xD698#define QIB_7322_ErrClear_RcvHdrFullErrClear_MSB 0xD699#define QIB_7322_ErrClear_RcvHdrFullErrClear_RMASK 0x1700#define QIB_7322_ErrClear_RcvEgrFullErrClear_LSB 0xC701#define QIB_7322_ErrClear_RcvEgrFullErrClear_MSB 0xC702#define QIB_7322_ErrClear_RcvEgrFullErrClear_RMASK 0x1703 704#define QIB_7322_HwErrMask_OFFS 0x98705#define QIB_7322_HwErrMask_DEF 0x0000000000000000706#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_LSB 0x3F707#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_MSB 0x3F708#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_1_RMASK 0x1709#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_LSB 0x3E710#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_MSB 0x3E711#define QIB_7322_HwErrMask_IBSerdesPClkNotDetectMask_0_RMASK 0x1712#define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_LSB 0x37713#define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_MSB 0x37714#define QIB_7322_HwErrMask_PCIESerdesPClkNotDetectMask_RMASK 0x1715#define QIB_7322_HwErrMask_PowerOnBISTFailedMask_LSB 0x36716#define QIB_7322_HwErrMask_PowerOnBISTFailedMask_MSB 0x36717#define QIB_7322_HwErrMask_PowerOnBISTFailedMask_RMASK 0x1718#define QIB_7322_HwErrMask_TempsenseTholdReachedMask_LSB 0x35719#define QIB_7322_HwErrMask_TempsenseTholdReachedMask_MSB 0x35720#define QIB_7322_HwErrMask_TempsenseTholdReachedMask_RMASK 0x1721#define QIB_7322_HwErrMask_MemoryErrMask_LSB 0x30722#define QIB_7322_HwErrMask_MemoryErrMask_MSB 0x30723#define QIB_7322_HwErrMask_MemoryErrMask_RMASK 0x1724#define QIB_7322_HwErrMask_pcie_phy_txParityErr_LSB 0x22725#define QIB_7322_HwErrMask_pcie_phy_txParityErr_MSB 0x22726#define QIB_7322_HwErrMask_pcie_phy_txParityErr_RMASK 0x1727#define QIB_7322_HwErrMask_PCIeBusParityErrMask_LSB 0x1F728#define QIB_7322_HwErrMask_PCIeBusParityErrMask_MSB 0x21729#define QIB_7322_HwErrMask_PCIeBusParityErrMask_RMASK 0x7730#define QIB_7322_HwErrMask_PcieCplTimeoutMask_LSB 0x1E731#define QIB_7322_HwErrMask_PcieCplTimeoutMask_MSB 0x1E732#define QIB_7322_HwErrMask_PcieCplTimeoutMask_RMASK 0x1733#define QIB_7322_HwErrMask_PciePoisonedTLPMask_LSB 0x1D734#define QIB_7322_HwErrMask_PciePoisonedTLPMask_MSB 0x1D735#define QIB_7322_HwErrMask_PciePoisonedTLPMask_RMASK 0x1736#define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_LSB 0x1C737#define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_MSB 0x1C738#define QIB_7322_HwErrMask_SDmaMemReadErrMask_1_RMASK 0x1739#define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_LSB 0x1B740#define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_MSB 0x1B741#define QIB_7322_HwErrMask_SDmaMemReadErrMask_0_RMASK 0x1742#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_LSB 0xF743#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_MSB 0xF744#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_1_RMASK 0x1745#define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_LSB 0xE746#define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_MSB 0xE747#define QIB_7322_HwErrMask_IBCBusToSPCParityErrMask_1_RMASK 0x1748#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_LSB 0xD749#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_MSB 0xD750#define QIB_7322_HwErrMask_IBCBusFromSPCParityErrMask_0_RMASK 0x1751#define QIB_7322_HwErrMask_statusValidNoEopMask_LSB 0xC752#define QIB_7322_HwErrMask_statusValidNoEopMask_MSB 0xC753#define QIB_7322_HwErrMask_statusValidNoEopMask_RMASK 0x1754#define QIB_7322_HwErrMask_LATriggeredMask_LSB 0xB755#define QIB_7322_HwErrMask_LATriggeredMask_MSB 0xB756#define QIB_7322_HwErrMask_LATriggeredMask_RMASK 0x1757 758#define QIB_7322_HwErrStatus_OFFS 0xA0759#define QIB_7322_HwErrStatus_DEF 0x0000000000000000760#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_LSB 0x3F761#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_MSB 0x3F762#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_1_RMASK 0x1763#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_LSB 0x3E764#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_MSB 0x3E765#define QIB_7322_HwErrStatus_IBSerdesPClkNotDetect_0_RMASK 0x1766#define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_LSB 0x37767#define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_MSB 0x37768#define QIB_7322_HwErrStatus_PCIESerdesPClkNotDetect_RMASK 0x1769#define QIB_7322_HwErrStatus_PowerOnBISTFailed_LSB 0x36770#define QIB_7322_HwErrStatus_PowerOnBISTFailed_MSB 0x36771#define QIB_7322_HwErrStatus_PowerOnBISTFailed_RMASK 0x1772#define QIB_7322_HwErrStatus_TempsenseTholdReached_LSB 0x35773#define QIB_7322_HwErrStatus_TempsenseTholdReached_MSB 0x35774#define QIB_7322_HwErrStatus_TempsenseTholdReached_RMASK 0x1775#define QIB_7322_HwErrStatus_MemoryErr_LSB 0x30776#define QIB_7322_HwErrStatus_MemoryErr_MSB 0x30777#define QIB_7322_HwErrStatus_MemoryErr_RMASK 0x1778#define QIB_7322_HwErrStatus_pcie_phy_txParityErr_LSB 0x22779#define QIB_7322_HwErrStatus_pcie_phy_txParityErr_MSB 0x22780#define QIB_7322_HwErrStatus_pcie_phy_txParityErr_RMASK 0x1781#define QIB_7322_HwErrStatus_PCIeBusParity_LSB 0x1F782#define QIB_7322_HwErrStatus_PCIeBusParity_MSB 0x21783#define QIB_7322_HwErrStatus_PCIeBusParity_RMASK 0x7784#define QIB_7322_HwErrStatus_PcieCplTimeout_LSB 0x1E785#define QIB_7322_HwErrStatus_PcieCplTimeout_MSB 0x1E786#define QIB_7322_HwErrStatus_PcieCplTimeout_RMASK 0x1787#define QIB_7322_HwErrStatus_PciePoisonedTLP_LSB 0x1D788#define QIB_7322_HwErrStatus_PciePoisonedTLP_MSB 0x1D789#define QIB_7322_HwErrStatus_PciePoisonedTLP_RMASK 0x1790#define QIB_7322_HwErrStatus_SDmaMemReadErr_1_LSB 0x1C791#define QIB_7322_HwErrStatus_SDmaMemReadErr_1_MSB 0x1C792#define QIB_7322_HwErrStatus_SDmaMemReadErr_1_RMASK 0x1793#define QIB_7322_HwErrStatus_SDmaMemReadErr_0_LSB 0x1B794#define QIB_7322_HwErrStatus_SDmaMemReadErr_0_MSB 0x1B795#define QIB_7322_HwErrStatus_SDmaMemReadErr_0_RMASK 0x1796#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_LSB 0xF797#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_MSB 0xF798#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_1_RMASK 0x1799#define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_LSB 0xE800#define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_MSB 0xE801#define QIB_7322_HwErrStatus_IBCBusToSPCParityErr_1_RMASK 0x1802#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_LSB 0xD803#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_MSB 0xD804#define QIB_7322_HwErrStatus_IBCBusFromSPCParityErr_0_RMASK 0x1805#define QIB_7322_HwErrStatus_statusValidNoEop_LSB 0xC806#define QIB_7322_HwErrStatus_statusValidNoEop_MSB 0xC807#define QIB_7322_HwErrStatus_statusValidNoEop_RMASK 0x1808#define QIB_7322_HwErrStatus_LATriggered_LSB 0xB809#define QIB_7322_HwErrStatus_LATriggered_MSB 0xB810#define QIB_7322_HwErrStatus_LATriggered_RMASK 0x1811 812#define QIB_7322_HwErrClear_OFFS 0xA8813#define QIB_7322_HwErrClear_DEF 0x0000000000000000814#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_LSB 0x3F815#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_MSB 0x3F816#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_1_RMASK 0x1817#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_LSB 0x3E818#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_MSB 0x3E819#define QIB_7322_HwErrClear_IBSerdesPClkNotDetectClear_0_RMASK 0x1820#define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_LSB 0x37821#define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_MSB 0x37822#define QIB_7322_HwErrClear_PCIESerdesPClkNotDetectClear_RMASK 0x1823#define QIB_7322_HwErrClear_PowerOnBISTFailedClear_LSB 0x36824#define QIB_7322_HwErrClear_PowerOnBISTFailedClear_MSB 0x36825#define QIB_7322_HwErrClear_PowerOnBISTFailedClear_RMASK 0x1826#define QIB_7322_HwErrClear_TempsenseTholdReachedClear_LSB 0x35827#define QIB_7322_HwErrClear_TempsenseTholdReachedClear_MSB 0x35828#define QIB_7322_HwErrClear_TempsenseTholdReachedClear_RMASK 0x1829#define QIB_7322_HwErrClear_MemoryErrClear_LSB 0x30830#define QIB_7322_HwErrClear_MemoryErrClear_MSB 0x30831#define QIB_7322_HwErrClear_MemoryErrClear_RMASK 0x1832#define QIB_7322_HwErrClear_pcie_phy_txParityErr_LSB 0x22833#define QIB_7322_HwErrClear_pcie_phy_txParityErr_MSB 0x22834#define QIB_7322_HwErrClear_pcie_phy_txParityErr_RMASK 0x1835#define QIB_7322_HwErrClear_PCIeBusParityClear_LSB 0x1F836#define QIB_7322_HwErrClear_PCIeBusParityClear_MSB 0x21837#define QIB_7322_HwErrClear_PCIeBusParityClear_RMASK 0x7838#define QIB_7322_HwErrClear_PcieCplTimeoutClear_LSB 0x1E839#define QIB_7322_HwErrClear_PcieCplTimeoutClear_MSB 0x1E840#define QIB_7322_HwErrClear_PcieCplTimeoutClear_RMASK 0x1841#define QIB_7322_HwErrClear_PciePoisonedTLPClear_LSB 0x1D842#define QIB_7322_HwErrClear_PciePoisonedTLPClear_MSB 0x1D843#define QIB_7322_HwErrClear_PciePoisonedTLPClear_RMASK 0x1844#define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_LSB 0x1C845#define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_MSB 0x1C846#define QIB_7322_HwErrClear_SDmaMemReadErrClear_1_RMASK 0x1847#define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_LSB 0x1B848#define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_MSB 0x1B849#define QIB_7322_HwErrClear_SDmaMemReadErrClear_0_RMASK 0x1850#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_LSB 0xF851#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_MSB 0xF852#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_1_RMASK 0x1853#define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_LSB 0xE854#define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_MSB 0xE855#define QIB_7322_HwErrClear_IBCBusToSPCParityErrClear_1_RMASK 0x1856#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_LSB 0xD857#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_MSB 0xD858#define QIB_7322_HwErrClear_IBCBusFromSPCParityErrClear_0_RMASK 0x1859#define QIB_7322_HwErrClear_statusValidNoEopClear_LSB 0xC860#define QIB_7322_HwErrClear_statusValidNoEopClear_MSB 0xC861#define QIB_7322_HwErrClear_statusValidNoEopClear_RMASK 0x1862#define QIB_7322_HwErrClear_LATriggeredClear_LSB 0xB863#define QIB_7322_HwErrClear_LATriggeredClear_MSB 0xB864#define QIB_7322_HwErrClear_LATriggeredClear_RMASK 0x1865 866#define QIB_7322_HwDiagCtrl_OFFS 0xB0867#define QIB_7322_HwDiagCtrl_DEF 0x0000000000000000868#define QIB_7322_HwDiagCtrl_Diagnostic_LSB 0x3F869#define QIB_7322_HwDiagCtrl_Diagnostic_MSB 0x3F870#define QIB_7322_HwDiagCtrl_Diagnostic_RMASK 0x1871#define QIB_7322_HwDiagCtrl_CounterWrEnable_LSB 0x3D872#define QIB_7322_HwDiagCtrl_CounterWrEnable_MSB 0x3D873#define QIB_7322_HwDiagCtrl_CounterWrEnable_RMASK 0x1874#define QIB_7322_HwDiagCtrl_CounterDisable_LSB 0x3C875#define QIB_7322_HwDiagCtrl_CounterDisable_MSB 0x3C876#define QIB_7322_HwDiagCtrl_CounterDisable_RMASK 0x1877#define QIB_7322_HwDiagCtrl_forcePCIeBusParity_LSB 0x1F878#define QIB_7322_HwDiagCtrl_forcePCIeBusParity_MSB 0x22879#define QIB_7322_HwDiagCtrl_forcePCIeBusParity_RMASK 0xF880#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_LSB 0xF881#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_MSB 0xF882#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_1_RMASK 0x1883#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_LSB 0xE884#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_MSB 0xE885#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_1_RMASK 0x1886#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_LSB 0xD887#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_MSB 0xD888#define QIB_7322_HwDiagCtrl_ForceIBCBusFromSPCParityErr_0_RMASK 0x1889#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_LSB 0xC890#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_MSB 0xC891#define QIB_7322_HwDiagCtrl_ForceIBCBusToSPCParityErr_0_RMASK 0x1892 893#define QIB_7322_EXTStatus_OFFS 0xC0894#define QIB_7322_EXTStatus_DEF 0x000000000000X000895#define QIB_7322_EXTStatus_GPIOIn_LSB 0x30896#define QIB_7322_EXTStatus_GPIOIn_MSB 0x3F897#define QIB_7322_EXTStatus_GPIOIn_RMASK 0xFFFF898#define QIB_7322_EXTStatus_MemBISTDisabled_LSB 0xF899#define QIB_7322_EXTStatus_MemBISTDisabled_MSB 0xF900#define QIB_7322_EXTStatus_MemBISTDisabled_RMASK 0x1901#define QIB_7322_EXTStatus_MemBISTEndTest_LSB 0xE902#define QIB_7322_EXTStatus_MemBISTEndTest_MSB 0xE903#define QIB_7322_EXTStatus_MemBISTEndTest_RMASK 0x1904 905#define QIB_7322_EXTCtrl_OFFS 0xC8906#define QIB_7322_EXTCtrl_DEF 0x0000000000000000907#define QIB_7322_EXTCtrl_GPIOOe_LSB 0x30908#define QIB_7322_EXTCtrl_GPIOOe_MSB 0x3F909#define QIB_7322_EXTCtrl_GPIOOe_RMASK 0xFFFF910#define QIB_7322_EXTCtrl_GPIOInvert_LSB 0x20911#define QIB_7322_EXTCtrl_GPIOInvert_MSB 0x2F912#define QIB_7322_EXTCtrl_GPIOInvert_RMASK 0xFFFF913#define QIB_7322_EXTCtrl_LEDPort1GreenOn_LSB 0x3914#define QIB_7322_EXTCtrl_LEDPort1GreenOn_MSB 0x3915#define QIB_7322_EXTCtrl_LEDPort1GreenOn_RMASK 0x1916#define QIB_7322_EXTCtrl_LEDPort1YellowOn_LSB 0x2917#define QIB_7322_EXTCtrl_LEDPort1YellowOn_MSB 0x2918#define QIB_7322_EXTCtrl_LEDPort1YellowOn_RMASK 0x1919#define QIB_7322_EXTCtrl_LEDPort0GreenOn_LSB 0x1920#define QIB_7322_EXTCtrl_LEDPort0GreenOn_MSB 0x1921#define QIB_7322_EXTCtrl_LEDPort0GreenOn_RMASK 0x1922#define QIB_7322_EXTCtrl_LEDPort0YellowOn_LSB 0x0923#define QIB_7322_EXTCtrl_LEDPort0YellowOn_MSB 0x0924#define QIB_7322_EXTCtrl_LEDPort0YellowOn_RMASK 0x1925 926#define QIB_7322_GPIOOut_OFFS 0xE0927#define QIB_7322_GPIOOut_DEF 0x0000000000000000928 929#define QIB_7322_GPIOMask_OFFS 0xE8930#define QIB_7322_GPIOMask_DEF 0x0000000000000000931 932#define QIB_7322_GPIOStatus_OFFS 0xF0933#define QIB_7322_GPIOStatus_DEF 0x0000000000000000934 935#define QIB_7322_GPIOClear_OFFS 0xF8936#define QIB_7322_GPIOClear_DEF 0x0000000000000000937 938#define QIB_7322_RcvCtrl_OFFS 0x100939#define QIB_7322_RcvCtrl_DEF 0x0000000000000000940#define QIB_7322_RcvCtrl_TidReDirect_LSB 0x30941#define QIB_7322_RcvCtrl_TidReDirect_MSB 0x3F942#define QIB_7322_RcvCtrl_TidReDirect_RMASK 0xFFFF943#define QIB_7322_RcvCtrl_TailUpd_LSB 0x2F944#define QIB_7322_RcvCtrl_TailUpd_MSB 0x2F945#define QIB_7322_RcvCtrl_TailUpd_RMASK 0x1946#define QIB_7322_RcvCtrl_XrcTypeCode_LSB 0x2C947#define QIB_7322_RcvCtrl_XrcTypeCode_MSB 0x2E948#define QIB_7322_RcvCtrl_XrcTypeCode_RMASK 0x7949#define QIB_7322_RcvCtrl_TidFlowEnable_LSB 0x2B950#define QIB_7322_RcvCtrl_TidFlowEnable_MSB 0x2B951#define QIB_7322_RcvCtrl_TidFlowEnable_RMASK 0x1952#define QIB_7322_RcvCtrl_ContextCfg_LSB 0x29953#define QIB_7322_RcvCtrl_ContextCfg_MSB 0x2A954#define QIB_7322_RcvCtrl_ContextCfg_RMASK 0x3955#define QIB_7322_RcvCtrl_IntrAvail_LSB 0x14956#define QIB_7322_RcvCtrl_IntrAvail_MSB 0x25957#define QIB_7322_RcvCtrl_IntrAvail_RMASK 0x3FFFF958#define QIB_7322_RcvCtrl_dontDropRHQFull_LSB 0x0959#define QIB_7322_RcvCtrl_dontDropRHQFull_MSB 0x11960#define QIB_7322_RcvCtrl_dontDropRHQFull_RMASK 0x3FFFF961 962#define QIB_7322_RcvHdrSize_OFFS 0x110963#define QIB_7322_RcvHdrSize_DEF 0x0000000000000000964 965#define QIB_7322_RcvHdrCnt_OFFS 0x118966#define QIB_7322_RcvHdrCnt_DEF 0x0000000000000000967 968#define QIB_7322_RcvHdrEntSize_OFFS 0x120969#define QIB_7322_RcvHdrEntSize_DEF 0x0000000000000000970 971#define QIB_7322_RcvTIDBase_OFFS 0x128972#define QIB_7322_RcvTIDBase_DEF 0x0000000000050000973 974#define QIB_7322_RcvTIDCnt_OFFS 0x130975#define QIB_7322_RcvTIDCnt_DEF 0x0000000000000200976 977#define QIB_7322_RcvEgrBase_OFFS 0x138978#define QIB_7322_RcvEgrBase_DEF 0x0000000000014000979 980#define QIB_7322_RcvEgrCnt_OFFS 0x140981#define QIB_7322_RcvEgrCnt_DEF 0x0000000000001000982 983#define QIB_7322_RcvBufBase_OFFS 0x148984#define QIB_7322_RcvBufBase_DEF 0x0000000000080000985 986#define QIB_7322_RcvBufSize_OFFS 0x150987#define QIB_7322_RcvBufSize_DEF 0x0000000000005000988 989#define QIB_7322_RxIntMemBase_OFFS 0x158990#define QIB_7322_RxIntMemBase_DEF 0x0000000000077000991 992#define QIB_7322_RxIntMemSize_OFFS 0x160993#define QIB_7322_RxIntMemSize_DEF 0x0000000000007000994 995#define QIB_7322_feature_mask_OFFS 0x190996#define QIB_7322_feature_mask_DEF 0x00000000000000XX997 998#define QIB_7322_active_feature_mask_OFFS 0x198999#define QIB_7322_active_feature_mask_DEF 0x00000000000000XX1000#define QIB_7322_active_feature_mask_Port1_QDR_Enabled_LSB 0x51001#define QIB_7322_active_feature_mask_Port1_QDR_Enabled_MSB 0x51002#define QIB_7322_active_feature_mask_Port1_QDR_Enabled_RMASK 0x11003#define QIB_7322_active_feature_mask_Port1_DDR_Enabled_LSB 0x41004#define QIB_7322_active_feature_mask_Port1_DDR_Enabled_MSB 0x41005#define QIB_7322_active_feature_mask_Port1_DDR_Enabled_RMASK 0x11006#define QIB_7322_active_feature_mask_Port1_SDR_Enabled_LSB 0x31007#define QIB_7322_active_feature_mask_Port1_SDR_Enabled_MSB 0x31008#define QIB_7322_active_feature_mask_Port1_SDR_Enabled_RMASK 0x11009#define QIB_7322_active_feature_mask_Port0_QDR_Enabled_LSB 0x21010#define QIB_7322_active_feature_mask_Port0_QDR_Enabled_MSB 0x21011#define QIB_7322_active_feature_mask_Port0_QDR_Enabled_RMASK 0x11012#define QIB_7322_active_feature_mask_Port0_DDR_Enabled_LSB 0x11013#define QIB_7322_active_feature_mask_Port0_DDR_Enabled_MSB 0x11014#define QIB_7322_active_feature_mask_Port0_DDR_Enabled_RMASK 0x11015#define QIB_7322_active_feature_mask_Port0_SDR_Enabled_LSB 0x01016#define QIB_7322_active_feature_mask_Port0_SDR_Enabled_MSB 0x01017#define QIB_7322_active_feature_mask_Port0_SDR_Enabled_RMASK 0x11018 1019#define QIB_7322_SendCtrl_OFFS 0x1C01020#define QIB_7322_SendCtrl_DEF 0x00000000000000001021#define QIB_7322_SendCtrl_Disarm_LSB 0x1F1022#define QIB_7322_SendCtrl_Disarm_MSB 0x1F1023#define QIB_7322_SendCtrl_Disarm_RMASK 0x11024#define QIB_7322_SendCtrl_SendBufAvailPad64Byte_LSB 0x1D1025#define QIB_7322_SendCtrl_SendBufAvailPad64Byte_MSB 0x1D1026#define QIB_7322_SendCtrl_SendBufAvailPad64Byte_RMASK 0x11027#define QIB_7322_SendCtrl_AvailUpdThld_LSB 0x181028#define QIB_7322_SendCtrl_AvailUpdThld_MSB 0x1C1029#define QIB_7322_SendCtrl_AvailUpdThld_RMASK 0x1F1030#define QIB_7322_SendCtrl_DisarmSendBuf_LSB 0x101031#define QIB_7322_SendCtrl_DisarmSendBuf_MSB 0x171032#define QIB_7322_SendCtrl_DisarmSendBuf_RMASK 0xFF1033#define QIB_7322_SendCtrl_SpecialTriggerEn_LSB 0x41034#define QIB_7322_SendCtrl_SpecialTriggerEn_MSB 0x41035#define QIB_7322_SendCtrl_SpecialTriggerEn_RMASK 0x11036#define QIB_7322_SendCtrl_SendBufAvailUpd_LSB 0x21037#define QIB_7322_SendCtrl_SendBufAvailUpd_MSB 0x21038#define QIB_7322_SendCtrl_SendBufAvailUpd_RMASK 0x11039#define QIB_7322_SendCtrl_SendIntBufAvail_LSB 0x11040#define QIB_7322_SendCtrl_SendIntBufAvail_MSB 0x11041#define QIB_7322_SendCtrl_SendIntBufAvail_RMASK 0x11042 1043#define QIB_7322_SendBufBase_OFFS 0x1C81044#define QIB_7322_SendBufBase_DEF 0x00180000001000001045#define QIB_7322_SendBufBase_BaseAddr_LargePIO_LSB 0x201046#define QIB_7322_SendBufBase_BaseAddr_LargePIO_MSB 0x341047#define QIB_7322_SendBufBase_BaseAddr_LargePIO_RMASK 0x1FFFFF1048#define QIB_7322_SendBufBase_BaseAddr_SmallPIO_LSB 0x01049#define QIB_7322_SendBufBase_BaseAddr_SmallPIO_MSB 0x141050#define QIB_7322_SendBufBase_BaseAddr_SmallPIO_RMASK 0x1FFFFF1051 1052#define QIB_7322_SendBufSize_OFFS 0x1D01053#define QIB_7322_SendBufSize_DEF 0x00001080000008801054#define QIB_7322_SendBufSize_Size_LargePIO_LSB 0x201055#define QIB_7322_SendBufSize_Size_LargePIO_MSB 0x2C1056#define QIB_7322_SendBufSize_Size_LargePIO_RMASK 0x1FFF1057#define QIB_7322_SendBufSize_Size_SmallPIO_LSB 0x01058#define QIB_7322_SendBufSize_Size_SmallPIO_MSB 0xB1059#define QIB_7322_SendBufSize_Size_SmallPIO_RMASK 0xFFF1060 1061#define QIB_7322_SendBufCnt_OFFS 0x1D81062#define QIB_7322_SendBufCnt_DEF 0x00000020000000801063#define QIB_7322_SendBufCnt_Num_LargeBuffers_LSB 0x201064#define QIB_7322_SendBufCnt_Num_LargeBuffers_MSB 0x251065#define QIB_7322_SendBufCnt_Num_LargeBuffers_RMASK 0x3F1066#define QIB_7322_SendBufCnt_Num_SmallBuffers_LSB 0x01067#define QIB_7322_SendBufCnt_Num_SmallBuffers_MSB 0x81068#define QIB_7322_SendBufCnt_Num_SmallBuffers_RMASK 0x1FF1069 1070#define QIB_7322_SendBufAvailAddr_OFFS 0x1E01071#define QIB_7322_SendBufAvailAddr_DEF 0x00000000000000001072#define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_LSB 0x61073#define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_MSB 0x271074#define QIB_7322_SendBufAvailAddr_SendBufAvailAddr_RMASK 0x3FFFFFFFF1075 1076#define QIB_7322_SendBufErr0_OFFS 0x2401077#define QIB_7322_SendBufErr0_DEF 0x00000000000000001078#define QIB_7322_SendBufErr0_SendBufErr_63_0_LSB 0x01079#define QIB_7322_SendBufErr0_SendBufErr_63_0_MSB 0x3F1080#define QIB_7322_SendBufErr0_SendBufErr_63_0_RMASK 0x01081 1082#define QIB_7322_AvailUpdCount_OFFS 0x2681083#define QIB_7322_AvailUpdCount_DEF 0x00000000000000001084#define QIB_7322_AvailUpdCount_AvailUpdCount_LSB 0x01085#define QIB_7322_AvailUpdCount_AvailUpdCount_MSB 0x41086#define QIB_7322_AvailUpdCount_AvailUpdCount_RMASK 0x1F1087 1088#define QIB_7322_RcvHdrAddr0_OFFS 0x2801089#define QIB_7322_RcvHdrAddr0_DEF 0x00000000000000001090#define QIB_7322_RcvHdrAddr0_RcvHdrAddr_LSB 0x21091#define QIB_7322_RcvHdrAddr0_RcvHdrAddr_MSB 0x271092#define QIB_7322_RcvHdrAddr0_RcvHdrAddr_RMASK 0x3FFFFFFFFF1093 1094#define QIB_7322_RcvHdrTailAddr0_OFFS 0x3401095#define QIB_7322_RcvHdrTailAddr0_DEF 0x00000000000000001096#define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_LSB 0x21097#define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_MSB 0x271098#define QIB_7322_RcvHdrTailAddr0_RcvHdrTailAddr_RMASK 0x3FFFFFFFFF1099 1100#define QIB_7322_ahb_access_ctrl_OFFS 0x4601101#define QIB_7322_ahb_access_ctrl_DEF 0x00000000000000001102#define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_LSB 0x11103#define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_MSB 0x21104#define QIB_7322_ahb_access_ctrl_sw_sel_ahb_trgt_RMASK 0x31105#define QIB_7322_ahb_access_ctrl_sw_ahb_sel_LSB 0x01106#define QIB_7322_ahb_access_ctrl_sw_ahb_sel_MSB 0x01107#define QIB_7322_ahb_access_ctrl_sw_ahb_sel_RMASK 0x11108 1109#define QIB_7322_ahb_transaction_reg_OFFS 0x4681110#define QIB_7322_ahb_transaction_reg_DEF 0x00000000800000001111#define QIB_7322_ahb_transaction_reg_ahb_data_LSB 0x201112#define QIB_7322_ahb_transaction_reg_ahb_data_MSB 0x3F1113#define QIB_7322_ahb_transaction_reg_ahb_data_RMASK 0xFFFFFFFF1114#define QIB_7322_ahb_transaction_reg_ahb_rdy_LSB 0x1F1115#define QIB_7322_ahb_transaction_reg_ahb_rdy_MSB 0x1F1116#define QIB_7322_ahb_transaction_reg_ahb_rdy_RMASK 0x11117#define QIB_7322_ahb_transaction_reg_ahb_req_err_LSB 0x1E1118#define QIB_7322_ahb_transaction_reg_ahb_req_err_MSB 0x1E1119#define QIB_7322_ahb_transaction_reg_ahb_req_err_RMASK 0x11120#define QIB_7322_ahb_transaction_reg_write_not_read_LSB 0x1B1121#define QIB_7322_ahb_transaction_reg_write_not_read_MSB 0x1B1122#define QIB_7322_ahb_transaction_reg_write_not_read_RMASK 0x11123#define QIB_7322_ahb_transaction_reg_ahb_address_LSB 0x101124#define QIB_7322_ahb_transaction_reg_ahb_address_MSB 0x1A1125#define QIB_7322_ahb_transaction_reg_ahb_address_RMASK 0x7FF1126 1127#define QIB_7322_SPC_JTAG_ACCESS_REG_OFFS 0x4701128#define QIB_7322_SPC_JTAG_ACCESS_REG_DEF 0x00000000000000011129#define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_LSB 0xA1130#define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_MSB 0xA1131#define QIB_7322_SPC_JTAG_ACCESS_REG_SPC_JTAG_ACCESS_EN_RMASK 0x11132#define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_LSB 0x51133#define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_MSB 0x91134#define QIB_7322_SPC_JTAG_ACCESS_REG_bist_en_RMASK 0x1F1135#define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_LSB 0x31136#define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_MSB 0x41137#define QIB_7322_SPC_JTAG_ACCESS_REG_opcode_RMASK 0x31138#define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_LSB 0x21139#define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_MSB 0x21140#define QIB_7322_SPC_JTAG_ACCESS_REG_tdi_RMASK 0x11141#define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_LSB 0x11142#define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_MSB 0x11143#define QIB_7322_SPC_JTAG_ACCESS_REG_tdo_RMASK 0x11144#define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_LSB 0x01145#define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_MSB 0x01146#define QIB_7322_SPC_JTAG_ACCESS_REG_rdy_RMASK 0x11147 1148#define QIB_7322_SendCheckMask0_OFFS 0x4C01149#define QIB_7322_SendCheckMask0_DEF 0x00000000000000001150#define QIB_7322_SendCheckMask0_SendCheckMask_63_32_LSB 0x01151#define QIB_7322_SendCheckMask0_SendCheckMask_63_32_MSB 0x3F1152#define QIB_7322_SendCheckMask0_SendCheckMask_63_32_RMASK 0x01153 1154#define QIB_7322_SendGRHCheckMask0_OFFS 0x4E01155#define QIB_7322_SendGRHCheckMask0_DEF 0x00000000000000001156#define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_LSB 0x01157#define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_MSB 0x3F1158#define QIB_7322_SendGRHCheckMask0_SendGRHCheckMask_63_32_RMASK 0x01159 1160#define QIB_7322_SendIBPacketMask0_OFFS 0x5001161#define QIB_7322_SendIBPacketMask0_DEF 0x00000000000000001162#define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_LSB 0x01163#define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_MSB 0x3F1164#define QIB_7322_SendIBPacketMask0_SendIBPacketMask_63_32_RMASK 0x01165 1166#define QIB_7322_IntRedirect0_OFFS 0x5401167#define QIB_7322_IntRedirect0_DEF 0x00000000000000001168#define QIB_7322_IntRedirect0_vec11_LSB 0x371169#define QIB_7322_IntRedirect0_vec11_MSB 0x3B1170#define QIB_7322_IntRedirect0_vec11_RMASK 0x1F1171#define QIB_7322_IntRedirect0_vec10_LSB 0x321172#define QIB_7322_IntRedirect0_vec10_MSB 0x361173#define QIB_7322_IntRedirect0_vec10_RMASK 0x1F1174#define QIB_7322_IntRedirect0_vec9_LSB 0x2D1175#define QIB_7322_IntRedirect0_vec9_MSB 0x311176#define QIB_7322_IntRedirect0_vec9_RMASK 0x1F1177#define QIB_7322_IntRedirect0_vec8_LSB 0x281178#define QIB_7322_IntRedirect0_vec8_MSB 0x2C1179#define QIB_7322_IntRedirect0_vec8_RMASK 0x1F1180#define QIB_7322_IntRedirect0_vec7_LSB 0x231181#define QIB_7322_IntRedirect0_vec7_MSB 0x271182#define QIB_7322_IntRedirect0_vec7_RMASK 0x1F1183#define QIB_7322_IntRedirect0_vec6_LSB 0x1E1184#define QIB_7322_IntRedirect0_vec6_MSB 0x221185#define QIB_7322_IntRedirect0_vec6_RMASK 0x1F1186#define QIB_7322_IntRedirect0_vec5_LSB 0x191187#define QIB_7322_IntRedirect0_vec5_MSB 0x1D1188#define QIB_7322_IntRedirect0_vec5_RMASK 0x1F1189#define QIB_7322_IntRedirect0_vec4_LSB 0x141190#define QIB_7322_IntRedirect0_vec4_MSB 0x181191#define QIB_7322_IntRedirect0_vec4_RMASK 0x1F1192#define QIB_7322_IntRedirect0_vec3_LSB 0xF1193#define QIB_7322_IntRedirect0_vec3_MSB 0x131194#define QIB_7322_IntRedirect0_vec3_RMASK 0x1F1195#define QIB_7322_IntRedirect0_vec2_LSB 0xA1196#define QIB_7322_IntRedirect0_vec2_MSB 0xE1197#define QIB_7322_IntRedirect0_vec2_RMASK 0x1F1198#define QIB_7322_IntRedirect0_vec1_LSB 0x51199#define QIB_7322_IntRedirect0_vec1_MSB 0x91200#define QIB_7322_IntRedirect0_vec1_RMASK 0x1F1201#define QIB_7322_IntRedirect0_vec0_LSB 0x01202#define QIB_7322_IntRedirect0_vec0_MSB 0x41203#define QIB_7322_IntRedirect0_vec0_RMASK 0x1F1204 1205#define QIB_7322_Int_Granted_OFFS 0x5701206#define QIB_7322_Int_Granted_DEF 0x00000000000000001207 1208#define QIB_7322_vec_clr_without_int_OFFS 0x5781209#define QIB_7322_vec_clr_without_int_DEF 0x00000000000000001210 1211#define QIB_7322_DCACtrlA_OFFS 0x5801212#define QIB_7322_DCACtrlA_DEF 0x00000000000000001213#define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_LSB 0x41214#define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_MSB 0x41215#define QIB_7322_DCACtrlA_SendDMAHead1DCAEnable_RMASK 0x11216#define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_LSB 0x31217#define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_MSB 0x31218#define QIB_7322_DCACtrlA_SendDMAHead0DCAEnable_RMASK 0x11219#define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_LSB 0x21220#define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_MSB 0x21221#define QIB_7322_DCACtrlA_RcvTailUpdDCAEnable_RMASK 0x11222#define QIB_7322_DCACtrlA_EagerDCAEnable_LSB 0x11223#define QIB_7322_DCACtrlA_EagerDCAEnable_MSB 0x11224#define QIB_7322_DCACtrlA_EagerDCAEnable_RMASK 0x11225#define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_LSB 0x01226#define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_MSB 0x01227#define QIB_7322_DCACtrlA_RcvHdrqDCAEnable_RMASK 0x11228 1229#define QIB_7322_DCACtrlB_OFFS 0x5881230#define QIB_7322_DCACtrlB_DEF 0x00000000000000001231#define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_LSB 0x361232#define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_MSB 0x3B1233#define QIB_7322_DCACtrlB_RcvHdrq3DCAXfrCnt_RMASK 0x3F1234#define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_LSB 0x2E1235#define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_MSB 0x351236#define QIB_7322_DCACtrlB_RcvHdrq3DCAOPH_RMASK 0xFF1237#define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_LSB 0x281238#define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_MSB 0x2D1239#define QIB_7322_DCACtrlB_RcvHdrq2DCAXfrCnt_RMASK 0x3F1240#define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_LSB 0x201241#define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_MSB 0x271242#define QIB_7322_DCACtrlB_RcvHdrq2DCAOPH_RMASK 0xFF1243#define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_LSB 0x161244#define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_MSB 0x1B1245#define QIB_7322_DCACtrlB_RcvHdrq1DCAXfrCnt_RMASK 0x3F1246#define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_LSB 0xE1247#define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_MSB 0x151248#define QIB_7322_DCACtrlB_RcvHdrq1DCAOPH_RMASK 0xFF1249#define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_LSB 0x81250#define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_MSB 0xD1251#define QIB_7322_DCACtrlB_RcvHdrq0DCAXfrCnt_RMASK 0x3F1252#define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_LSB 0x01253#define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_MSB 0x71254#define QIB_7322_DCACtrlB_RcvHdrq0DCAOPH_RMASK 0xFF1255 1256#define QIB_7322_DCACtrlC_OFFS 0x5901257#define QIB_7322_DCACtrlC_DEF 0x00000000000000001258#define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_LSB 0x361259#define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_MSB 0x3B1260#define QIB_7322_DCACtrlC_RcvHdrq7DCAXfrCnt_RMASK 0x3F1261#define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_LSB 0x2E1262#define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_MSB 0x351263#define QIB_7322_DCACtrlC_RcvHdrq7DCAOPH_RMASK 0xFF1264#define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_LSB 0x281265#define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_MSB 0x2D1266#define QIB_7322_DCACtrlC_RcvHdrq6DCAXfrCnt_RMASK 0x3F1267#define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_LSB 0x201268#define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_MSB 0x271269#define QIB_7322_DCACtrlC_RcvHdrq6DCAOPH_RMASK 0xFF1270#define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_LSB 0x161271#define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_MSB 0x1B1272#define QIB_7322_DCACtrlC_RcvHdrq5DCAXfrCnt_RMASK 0x3F1273#define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_LSB 0xE1274#define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_MSB 0x151275#define QIB_7322_DCACtrlC_RcvHdrq5DCAOPH_RMASK 0xFF1276#define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_LSB 0x81277#define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_MSB 0xD1278#define QIB_7322_DCACtrlC_RcvHdrq4DCAXfrCnt_RMASK 0x3F1279#define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_LSB 0x01280#define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_MSB 0x71281#define QIB_7322_DCACtrlC_RcvHdrq4DCAOPH_RMASK 0xFF1282 1283#define QIB_7322_DCACtrlD_OFFS 0x5981284#define QIB_7322_DCACtrlD_DEF 0x00000000000000001285#define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_LSB 0x361286#define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_MSB 0x3B1287#define QIB_7322_DCACtrlD_RcvHdrq11DCAXfrCnt_RMASK 0x3F1288#define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_LSB 0x2E1289#define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_MSB 0x351290#define QIB_7322_DCACtrlD_RcvHdrq11DCAOPH_RMASK 0xFF1291#define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_LSB 0x281292#define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_MSB 0x2D1293#define QIB_7322_DCACtrlD_RcvHdrq10DCAXfrCnt_RMASK 0x3F1294#define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_LSB 0x201295#define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_MSB 0x271296#define QIB_7322_DCACtrlD_RcvHdrq10DCAOPH_RMASK 0xFF1297#define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_LSB 0x161298#define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_MSB 0x1B1299#define QIB_7322_DCACtrlD_RcvHdrq9DCAXfrCnt_RMASK 0x3F1300#define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_LSB 0xE1301#define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_MSB 0x151302#define QIB_7322_DCACtrlD_RcvHdrq9DCAOPH_RMASK 0xFF1303#define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_LSB 0x81304#define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_MSB 0xD1305#define QIB_7322_DCACtrlD_RcvHdrq8DCAXfrCnt_RMASK 0x3F1306#define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_LSB 0x01307#define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_MSB 0x71308#define QIB_7322_DCACtrlD_RcvHdrq8DCAOPH_RMASK 0xFF1309 1310#define QIB_7322_DCACtrlE_OFFS 0x5A01311#define QIB_7322_DCACtrlE_DEF 0x00000000000000001312#define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_LSB 0x361313#define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_MSB 0x3B1314#define QIB_7322_DCACtrlE_RcvHdrq15DCAXfrCnt_RMASK 0x3F1315#define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_LSB 0x2E1316#define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_MSB 0x351317#define QIB_7322_DCACtrlE_RcvHdrq15DCAOPH_RMASK 0xFF1318#define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_LSB 0x281319#define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_MSB 0x2D1320#define QIB_7322_DCACtrlE_RcvHdrq14DCAXfrCnt_RMASK 0x3F1321#define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_LSB 0x201322#define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_MSB 0x271323#define QIB_7322_DCACtrlE_RcvHdrq14DCAOPH_RMASK 0xFF1324#define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_LSB 0x161325#define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_MSB 0x1B1326#define QIB_7322_DCACtrlE_RcvHdrq13DCAXfrCnt_RMASK 0x3F1327#define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_LSB 0xE1328#define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_MSB 0x151329#define QIB_7322_DCACtrlE_RcvHdrq13DCAOPH_RMASK 0xFF1330#define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_LSB 0x81331#define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_MSB 0xD1332#define QIB_7322_DCACtrlE_RcvHdrq12DCAXfrCnt_RMASK 0x3F1333#define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_LSB 0x01334#define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_MSB 0x71335#define QIB_7322_DCACtrlE_RcvHdrq12DCAOPH_RMASK 0xFF1336 1337#define QIB_7322_DCACtrlF_OFFS 0x5A81338#define QIB_7322_DCACtrlF_DEF 0x00000000000000001339#define QIB_7322_DCACtrlF_SendDma1DCAOPH_LSB 0x281340#define QIB_7322_DCACtrlF_SendDma1DCAOPH_MSB 0x2F1341#define QIB_7322_DCACtrlF_SendDma1DCAOPH_RMASK 0xFF1342#define QIB_7322_DCACtrlF_SendDma0DCAOPH_LSB 0x201343#define QIB_7322_DCACtrlF_SendDma0DCAOPH_MSB 0x271344#define QIB_7322_DCACtrlF_SendDma0DCAOPH_RMASK 0xFF1345#define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_LSB 0x161346#define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_MSB 0x1B1347#define QIB_7322_DCACtrlF_RcvHdrq17DCAXfrCnt_RMASK 0x3F1348#define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_LSB 0xE1349#define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_MSB 0x151350#define QIB_7322_DCACtrlF_RcvHdrq17DCAOPH_RMASK 0xFF1351#define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_LSB 0x81352#define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_MSB 0xD1353#define QIB_7322_DCACtrlF_RcvHdrq16DCAXfrCnt_RMASK 0x3F1354#define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_LSB 0x01355#define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_MSB 0x71356#define QIB_7322_DCACtrlF_RcvHdrq16DCAOPH_RMASK 0xFF1357 1358#define QIB_7322_RcvAvailTimeOut0_OFFS 0xC001359#define QIB_7322_RcvAvailTimeOut0_DEF 0x00000000000000001360#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_LSB 0x101361#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_MSB 0x1F1362#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOCount_RMASK 0xFFFF1363#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_LSB 0x01364#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_MSB 0xF1365#define QIB_7322_RcvAvailTimeOut0_RcvAvailTOReload_RMASK 0xFFFF1366 1367#define QIB_7322_CntrRegBase_0_OFFS 0x10281368#define QIB_7322_CntrRegBase_0_DEF 0x00000000000120001369 1370#define QIB_7322_ErrMask_0_OFFS 0x10801371#define QIB_7322_ErrMask_0_DEF 0x00000000000000001372#define QIB_7322_ErrMask_0_IBStatusChangedMask_LSB 0x3A1373#define QIB_7322_ErrMask_0_IBStatusChangedMask_MSB 0x3A1374#define QIB_7322_ErrMask_0_IBStatusChangedMask_RMASK 0x11375#define QIB_7322_ErrMask_0_SHeadersErrMask_LSB 0x391376#define QIB_7322_ErrMask_0_SHeadersErrMask_MSB 0x391377#define QIB_7322_ErrMask_0_SHeadersErrMask_RMASK 0x11378#define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_LSB 0x361379#define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_MSB 0x361380#define QIB_7322_ErrMask_0_VL15BufMisuseErrMask_RMASK 0x11381#define QIB_7322_ErrMask_0_SDmaHaltErrMask_LSB 0x311382#define QIB_7322_ErrMask_0_SDmaHaltErrMask_MSB 0x311383#define QIB_7322_ErrMask_0_SDmaHaltErrMask_RMASK 0x11384#define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_LSB 0x301385#define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_MSB 0x301386#define QIB_7322_ErrMask_0_SDmaDescAddrMisalignErrMask_RMASK 0x11387#define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_LSB 0x2F1388#define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_MSB 0x2F1389#define QIB_7322_ErrMask_0_SDmaUnexpDataErrMask_RMASK 0x11390#define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_LSB 0x2E1391#define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_MSB 0x2E1392#define QIB_7322_ErrMask_0_SDmaMissingDwErrMask_RMASK 0x11393#define QIB_7322_ErrMask_0_SDmaDwEnErrMask_LSB 0x2D1394#define QIB_7322_ErrMask_0_SDmaDwEnErrMask_MSB 0x2D1395#define QIB_7322_ErrMask_0_SDmaDwEnErrMask_RMASK 0x11396#define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_LSB 0x2C1397#define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_MSB 0x2C1398#define QIB_7322_ErrMask_0_SDmaRpyTagErrMask_RMASK 0x11399#define QIB_7322_ErrMask_0_SDma1stDescErrMask_LSB 0x2B1400#define QIB_7322_ErrMask_0_SDma1stDescErrMask_MSB 0x2B1401#define QIB_7322_ErrMask_0_SDma1stDescErrMask_RMASK 0x11402#define QIB_7322_ErrMask_0_SDmaBaseErrMask_LSB 0x2A1403#define QIB_7322_ErrMask_0_SDmaBaseErrMask_MSB 0x2A1404#define QIB_7322_ErrMask_0_SDmaBaseErrMask_RMASK 0x11405#define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_LSB 0x291406#define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_MSB 0x291407#define QIB_7322_ErrMask_0_SDmaTailOutOfBoundErrMask_RMASK 0x11408#define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_LSB 0x281409#define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_MSB 0x281410#define QIB_7322_ErrMask_0_SDmaOutOfBoundErrMask_RMASK 0x11411#define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_LSB 0x271412#define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_MSB 0x271413#define QIB_7322_ErrMask_0_SDmaGenMismatchErrMask_RMASK 0x11414#define QIB_7322_ErrMask_0_SendBufMisuseErrMask_LSB 0x261415#define QIB_7322_ErrMask_0_SendBufMisuseErrMask_MSB 0x261416#define QIB_7322_ErrMask_0_SendBufMisuseErrMask_RMASK 0x11417#define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_LSB 0x251418#define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_MSB 0x251419#define QIB_7322_ErrMask_0_SendUnsupportedVLErrMask_RMASK 0x11420#define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_LSB 0x241421#define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_MSB 0x241422#define QIB_7322_ErrMask_0_SendUnexpectedPktNumErrMask_RMASK 0x11423#define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_LSB 0x221424#define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_MSB 0x221425#define QIB_7322_ErrMask_0_SendDroppedDataPktErrMask_RMASK 0x11426#define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_LSB 0x211427#define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_MSB 0x211428#define QIB_7322_ErrMask_0_SendDroppedSmpPktErrMask_RMASK 0x11429#define QIB_7322_ErrMask_0_SendPktLenErrMask_LSB 0x201430#define QIB_7322_ErrMask_0_SendPktLenErrMask_MSB 0x201431#define QIB_7322_ErrMask_0_SendPktLenErrMask_RMASK 0x11432#define QIB_7322_ErrMask_0_SendUnderRunErrMask_LSB 0x1F1433#define QIB_7322_ErrMask_0_SendUnderRunErrMask_MSB 0x1F1434#define QIB_7322_ErrMask_0_SendUnderRunErrMask_RMASK 0x11435#define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_LSB 0x1E1436#define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_MSB 0x1E1437#define QIB_7322_ErrMask_0_SendMaxPktLenErrMask_RMASK 0x11438#define QIB_7322_ErrMask_0_SendMinPktLenErrMask_LSB 0x1D1439#define QIB_7322_ErrMask_0_SendMinPktLenErrMask_MSB 0x1D1440#define QIB_7322_ErrMask_0_SendMinPktLenErrMask_RMASK 0x11441#define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_LSB 0x111442#define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_MSB 0x111443#define QIB_7322_ErrMask_0_RcvIBLostLinkErrMask_RMASK 0x11444#define QIB_7322_ErrMask_0_RcvHdrErrMask_LSB 0x101445#define QIB_7322_ErrMask_0_RcvHdrErrMask_MSB 0x101446#define QIB_7322_ErrMask_0_RcvHdrErrMask_RMASK 0x11447#define QIB_7322_ErrMask_0_RcvHdrLenErrMask_LSB 0xF1448#define QIB_7322_ErrMask_0_RcvHdrLenErrMask_MSB 0xF1449#define QIB_7322_ErrMask_0_RcvHdrLenErrMask_RMASK 0x11450#define QIB_7322_ErrMask_0_RcvBadTidErrMask_LSB 0xE1451#define QIB_7322_ErrMask_0_RcvBadTidErrMask_MSB 0xE1452#define QIB_7322_ErrMask_0_RcvBadTidErrMask_RMASK 0x11453#define QIB_7322_ErrMask_0_RcvBadVersionErrMask_LSB 0xB1454#define QIB_7322_ErrMask_0_RcvBadVersionErrMask_MSB 0xB1455#define QIB_7322_ErrMask_0_RcvBadVersionErrMask_RMASK 0x11456#define QIB_7322_ErrMask_0_RcvIBFlowErrMask_LSB 0xA1457#define QIB_7322_ErrMask_0_RcvIBFlowErrMask_MSB 0xA1458#define QIB_7322_ErrMask_0_RcvIBFlowErrMask_RMASK 0x11459#define QIB_7322_ErrMask_0_RcvEBPErrMask_LSB 0x91460#define QIB_7322_ErrMask_0_RcvEBPErrMask_MSB 0x91461#define QIB_7322_ErrMask_0_RcvEBPErrMask_RMASK 0x11462#define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_LSB 0x81463#define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_MSB 0x81464#define QIB_7322_ErrMask_0_RcvUnsupportedVLErrMask_RMASK 0x11465#define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_LSB 0x71466#define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_MSB 0x71467#define QIB_7322_ErrMask_0_RcvUnexpectedCharErrMask_RMASK 0x11468#define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_LSB 0x61469#define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_MSB 0x61470#define QIB_7322_ErrMask_0_RcvShortPktLenErrMask_RMASK 0x11471#define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_LSB 0x51472#define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_MSB 0x51473#define QIB_7322_ErrMask_0_RcvLongPktLenErrMask_RMASK 0x11474#define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_LSB 0x41475#define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_MSB 0x41476#define QIB_7322_ErrMask_0_RcvMaxPktLenErrMask_RMASK 0x11477#define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_LSB 0x31478#define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_MSB 0x31479#define QIB_7322_ErrMask_0_RcvMinPktLenErrMask_RMASK 0x11480#define QIB_7322_ErrMask_0_RcvICRCErrMask_LSB 0x21481#define QIB_7322_ErrMask_0_RcvICRCErrMask_MSB 0x21482#define QIB_7322_ErrMask_0_RcvICRCErrMask_RMASK 0x11483#define QIB_7322_ErrMask_0_RcvVCRCErrMask_LSB 0x11484#define QIB_7322_ErrMask_0_RcvVCRCErrMask_MSB 0x11485#define QIB_7322_ErrMask_0_RcvVCRCErrMask_RMASK 0x11486#define QIB_7322_ErrMask_0_RcvFormatErrMask_LSB 0x01487#define QIB_7322_ErrMask_0_RcvFormatErrMask_MSB 0x01488#define QIB_7322_ErrMask_0_RcvFormatErrMask_RMASK 0x11489 1490#define QIB_7322_ErrStatus_0_OFFS 0x10881491#define QIB_7322_ErrStatus_0_DEF 0x00000000000000001492#define QIB_7322_ErrStatus_0_IBStatusChanged_LSB 0x3A1493#define QIB_7322_ErrStatus_0_IBStatusChanged_MSB 0x3A1494#define QIB_7322_ErrStatus_0_IBStatusChanged_RMASK 0x11495#define QIB_7322_ErrStatus_0_SHeadersErr_LSB 0x391496#define QIB_7322_ErrStatus_0_SHeadersErr_MSB 0x391497#define QIB_7322_ErrStatus_0_SHeadersErr_RMASK 0x11498#define QIB_7322_ErrStatus_0_VL15BufMisuseErr_LSB 0x361499#define QIB_7322_ErrStatus_0_VL15BufMisuseErr_MSB 0x361500#define QIB_7322_ErrStatus_0_VL15BufMisuseErr_RMASK 0x11501#define QIB_7322_ErrStatus_0_SDmaHaltErr_LSB 0x311502#define QIB_7322_ErrStatus_0_SDmaHaltErr_MSB 0x311503#define QIB_7322_ErrStatus_0_SDmaHaltErr_RMASK 0x11504#define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_LSB 0x301505#define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_MSB 0x301506#define QIB_7322_ErrStatus_0_SDmaDescAddrMisalignErr_RMASK 0x11507#define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_LSB 0x2F1508#define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_MSB 0x2F1509#define QIB_7322_ErrStatus_0_SDmaUnexpDataErr_RMASK 0x11510#define QIB_7322_ErrStatus_0_SDmaMissingDwErr_LSB 0x2E1511#define QIB_7322_ErrStatus_0_SDmaMissingDwErr_MSB 0x2E1512#define QIB_7322_ErrStatus_0_SDmaMissingDwErr_RMASK 0x11513#define QIB_7322_ErrStatus_0_SDmaDwEnErr_LSB 0x2D1514#define QIB_7322_ErrStatus_0_SDmaDwEnErr_MSB 0x2D1515#define QIB_7322_ErrStatus_0_SDmaDwEnErr_RMASK 0x11516#define QIB_7322_ErrStatus_0_SDmaRpyTagErr_LSB 0x2C1517#define QIB_7322_ErrStatus_0_SDmaRpyTagErr_MSB 0x2C1518#define QIB_7322_ErrStatus_0_SDmaRpyTagErr_RMASK 0x11519#define QIB_7322_ErrStatus_0_SDma1stDescErr_LSB 0x2B1520#define QIB_7322_ErrStatus_0_SDma1stDescErr_MSB 0x2B1521#define QIB_7322_ErrStatus_0_SDma1stDescErr_RMASK 0x11522#define QIB_7322_ErrStatus_0_SDmaBaseErr_LSB 0x2A1523#define QIB_7322_ErrStatus_0_SDmaBaseErr_MSB 0x2A1524#define QIB_7322_ErrStatus_0_SDmaBaseErr_RMASK 0x11525#define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_LSB 0x291526#define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_MSB 0x291527#define QIB_7322_ErrStatus_0_SDmaTailOutOfBoundErr_RMASK 0x11528#define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_LSB 0x281529#define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_MSB 0x281530#define QIB_7322_ErrStatus_0_SDmaOutOfBoundErr_RMASK 0x11531#define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_LSB 0x271532#define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_MSB 0x271533#define QIB_7322_ErrStatus_0_SDmaGenMismatchErr_RMASK 0x11534#define QIB_7322_ErrStatus_0_SendBufMisuseErr_LSB 0x261535#define QIB_7322_ErrStatus_0_SendBufMisuseErr_MSB 0x261536#define QIB_7322_ErrStatus_0_SendBufMisuseErr_RMASK 0x11537#define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_LSB 0x251538#define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_MSB 0x251539#define QIB_7322_ErrStatus_0_SendUnsupportedVLErr_RMASK 0x11540#define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_LSB 0x241541#define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_MSB 0x241542#define QIB_7322_ErrStatus_0_SendUnexpectedPktNumErr_RMASK 0x11543#define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_LSB 0x221544#define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_MSB 0x221545#define QIB_7322_ErrStatus_0_SendDroppedDataPktErr_RMASK 0x11546#define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_LSB 0x211547#define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_MSB 0x211548#define QIB_7322_ErrStatus_0_SendDroppedSmpPktErr_RMASK 0x11549#define QIB_7322_ErrStatus_0_SendPktLenErr_LSB 0x201550#define QIB_7322_ErrStatus_0_SendPktLenErr_MSB 0x201551#define QIB_7322_ErrStatus_0_SendPktLenErr_RMASK 0x11552#define QIB_7322_ErrStatus_0_SendUnderRunErr_LSB 0x1F1553#define QIB_7322_ErrStatus_0_SendUnderRunErr_MSB 0x1F1554#define QIB_7322_ErrStatus_0_SendUnderRunErr_RMASK 0x11555#define QIB_7322_ErrStatus_0_SendMaxPktLenErr_LSB 0x1E1556#define QIB_7322_ErrStatus_0_SendMaxPktLenErr_MSB 0x1E1557#define QIB_7322_ErrStatus_0_SendMaxPktLenErr_RMASK 0x11558#define QIB_7322_ErrStatus_0_SendMinPktLenErr_LSB 0x1D1559#define QIB_7322_ErrStatus_0_SendMinPktLenErr_MSB 0x1D1560#define QIB_7322_ErrStatus_0_SendMinPktLenErr_RMASK 0x11561#define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_LSB 0x111562#define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_MSB 0x111563#define QIB_7322_ErrStatus_0_RcvIBLostLinkErr_RMASK 0x11564#define QIB_7322_ErrStatus_0_RcvHdrErr_LSB 0x101565#define QIB_7322_ErrStatus_0_RcvHdrErr_MSB 0x101566#define QIB_7322_ErrStatus_0_RcvHdrErr_RMASK 0x11567#define QIB_7322_ErrStatus_0_RcvHdrLenErr_LSB 0xF1568#define QIB_7322_ErrStatus_0_RcvHdrLenErr_MSB 0xF1569#define QIB_7322_ErrStatus_0_RcvHdrLenErr_RMASK 0x11570#define QIB_7322_ErrStatus_0_RcvBadTidErr_LSB 0xE1571#define QIB_7322_ErrStatus_0_RcvBadTidErr_MSB 0xE1572#define QIB_7322_ErrStatus_0_RcvBadTidErr_RMASK 0x11573#define QIB_7322_ErrStatus_0_RcvBadVersionErr_LSB 0xB1574#define QIB_7322_ErrStatus_0_RcvBadVersionErr_MSB 0xB1575#define QIB_7322_ErrStatus_0_RcvBadVersionErr_RMASK 0x11576#define QIB_7322_ErrStatus_0_RcvIBFlowErr_LSB 0xA1577#define QIB_7322_ErrStatus_0_RcvIBFlowErr_MSB 0xA1578#define QIB_7322_ErrStatus_0_RcvIBFlowErr_RMASK 0x11579#define QIB_7322_ErrStatus_0_RcvEBPErr_LSB 0x91580#define QIB_7322_ErrStatus_0_RcvEBPErr_MSB 0x91581#define QIB_7322_ErrStatus_0_RcvEBPErr_RMASK 0x11582#define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_LSB 0x81583#define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_MSB 0x81584#define QIB_7322_ErrStatus_0_RcvUnsupportedVLErr_RMASK 0x11585#define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_LSB 0x71586#define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_MSB 0x71587#define QIB_7322_ErrStatus_0_RcvUnexpectedCharErr_RMASK 0x11588#define QIB_7322_ErrStatus_0_RcvShortPktLenErr_LSB 0x61589#define QIB_7322_ErrStatus_0_RcvShortPktLenErr_MSB 0x61590#define QIB_7322_ErrStatus_0_RcvShortPktLenErr_RMASK 0x11591#define QIB_7322_ErrStatus_0_RcvLongPktLenErr_LSB 0x51592#define QIB_7322_ErrStatus_0_RcvLongPktLenErr_MSB 0x51593#define QIB_7322_ErrStatus_0_RcvLongPktLenErr_RMASK 0x11594#define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_LSB 0x41595#define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_MSB 0x41596#define QIB_7322_ErrStatus_0_RcvMaxPktLenErr_RMASK 0x11597#define QIB_7322_ErrStatus_0_RcvMinPktLenErr_LSB 0x31598#define QIB_7322_ErrStatus_0_RcvMinPktLenErr_MSB 0x31599#define QIB_7322_ErrStatus_0_RcvMinPktLenErr_RMASK 0x11600#define QIB_7322_ErrStatus_0_RcvICRCErr_LSB 0x21601#define QIB_7322_ErrStatus_0_RcvICRCErr_MSB 0x21602#define QIB_7322_ErrStatus_0_RcvICRCErr_RMASK 0x11603#define QIB_7322_ErrStatus_0_RcvVCRCErr_LSB 0x11604#define QIB_7322_ErrStatus_0_RcvVCRCErr_MSB 0x11605#define QIB_7322_ErrStatus_0_RcvVCRCErr_RMASK 0x11606#define QIB_7322_ErrStatus_0_RcvFormatErr_LSB 0x01607#define QIB_7322_ErrStatus_0_RcvFormatErr_MSB 0x01608#define QIB_7322_ErrStatus_0_RcvFormatErr_RMASK 0x11609 1610#define QIB_7322_ErrClear_0_OFFS 0x10901611#define QIB_7322_ErrClear_0_DEF 0x00000000000000001612#define QIB_7322_ErrClear_0_IBStatusChangedClear_LSB 0x3A1613#define QIB_7322_ErrClear_0_IBStatusChangedClear_MSB 0x3A1614#define QIB_7322_ErrClear_0_IBStatusChangedClear_RMASK 0x11615#define QIB_7322_ErrClear_0_SHeadersErrClear_LSB 0x391616#define QIB_7322_ErrClear_0_SHeadersErrClear_MSB 0x391617#define QIB_7322_ErrClear_0_SHeadersErrClear_RMASK 0x11618#define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_LSB 0x361619#define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_MSB 0x361620#define QIB_7322_ErrClear_0_VL15BufMisuseErrClear_RMASK 0x11621#define QIB_7322_ErrClear_0_SDmaHaltErrClear_LSB 0x311622#define QIB_7322_ErrClear_0_SDmaHaltErrClear_MSB 0x311623#define QIB_7322_ErrClear_0_SDmaHaltErrClear_RMASK 0x11624#define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_LSB 0x301625#define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_MSB 0x301626#define QIB_7322_ErrClear_0_SDmaDescAddrMisalignErrClear_RMASK 0x11627#define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_LSB 0x2F1628#define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_MSB 0x2F1629#define QIB_7322_ErrClear_0_SDmaUnexpDataErrClear_RMASK 0x11630#define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_LSB 0x2E1631#define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_MSB 0x2E1632#define QIB_7322_ErrClear_0_SDmaMissingDwErrClear_RMASK 0x11633#define QIB_7322_ErrClear_0_SDmaDwEnErrClear_LSB 0x2D1634#define QIB_7322_ErrClear_0_SDmaDwEnErrClear_MSB 0x2D1635#define QIB_7322_ErrClear_0_SDmaDwEnErrClear_RMASK 0x11636#define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_LSB 0x2C1637#define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_MSB 0x2C1638#define QIB_7322_ErrClear_0_SDmaRpyTagErrClear_RMASK 0x11639#define QIB_7322_ErrClear_0_SDma1stDescErrClear_LSB 0x2B1640#define QIB_7322_ErrClear_0_SDma1stDescErrClear_MSB 0x2B1641#define QIB_7322_ErrClear_0_SDma1stDescErrClear_RMASK 0x11642#define QIB_7322_ErrClear_0_SDmaBaseErrClear_LSB 0x2A1643#define QIB_7322_ErrClear_0_SDmaBaseErrClear_MSB 0x2A1644#define QIB_7322_ErrClear_0_SDmaBaseErrClear_RMASK 0x11645#define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_LSB 0x291646#define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_MSB 0x291647#define QIB_7322_ErrClear_0_SDmaTailOutOfBoundErrClear_RMASK 0x11648#define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_LSB 0x281649#define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_MSB 0x281650#define QIB_7322_ErrClear_0_SDmaOutOfBoundErrClear_RMASK 0x11651#define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_LSB 0x271652#define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_MSB 0x271653#define QIB_7322_ErrClear_0_SDmaGenMismatchErrClear_RMASK 0x11654#define QIB_7322_ErrClear_0_SendBufMisuseErrClear_LSB 0x261655#define QIB_7322_ErrClear_0_SendBufMisuseErrClear_MSB 0x261656#define QIB_7322_ErrClear_0_SendBufMisuseErrClear_RMASK 0x11657#define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_LSB 0x251658#define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_MSB 0x251659#define QIB_7322_ErrClear_0_SendUnsupportedVLErrClear_RMASK 0x11660#define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_LSB 0x241661#define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_MSB 0x241662#define QIB_7322_ErrClear_0_SendUnexpectedPktNumErrClear_RMASK 0x11663#define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_LSB 0x221664#define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_MSB 0x221665#define QIB_7322_ErrClear_0_SendDroppedDataPktErrClear_RMASK 0x11666#define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_LSB 0x211667#define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_MSB 0x211668#define QIB_7322_ErrClear_0_SendDroppedSmpPktErrClear_RMASK 0x11669#define QIB_7322_ErrClear_0_SendPktLenErrClear_LSB 0x201670#define QIB_7322_ErrClear_0_SendPktLenErrClear_MSB 0x201671#define QIB_7322_ErrClear_0_SendPktLenErrClear_RMASK 0x11672#define QIB_7322_ErrClear_0_SendUnderRunErrClear_LSB 0x1F1673#define QIB_7322_ErrClear_0_SendUnderRunErrClear_MSB 0x1F1674#define QIB_7322_ErrClear_0_SendUnderRunErrClear_RMASK 0x11675#define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_LSB 0x1E1676#define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_MSB 0x1E1677#define QIB_7322_ErrClear_0_SendMaxPktLenErrClear_RMASK 0x11678#define QIB_7322_ErrClear_0_SendMinPktLenErrClear_LSB 0x1D1679#define QIB_7322_ErrClear_0_SendMinPktLenErrClear_MSB 0x1D1680#define QIB_7322_ErrClear_0_SendMinPktLenErrClear_RMASK 0x11681#define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_LSB 0x111682#define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_MSB 0x111683#define QIB_7322_ErrClear_0_RcvIBLostLinkErrClear_RMASK 0x11684#define QIB_7322_ErrClear_0_RcvHdrErrClear_LSB 0x101685#define QIB_7322_ErrClear_0_RcvHdrErrClear_MSB 0x101686#define QIB_7322_ErrClear_0_RcvHdrErrClear_RMASK 0x11687#define QIB_7322_ErrClear_0_RcvHdrLenErrClear_LSB 0xF1688#define QIB_7322_ErrClear_0_RcvHdrLenErrClear_MSB 0xF1689#define QIB_7322_ErrClear_0_RcvHdrLenErrClear_RMASK 0x11690#define QIB_7322_ErrClear_0_RcvBadTidErrClear_LSB 0xE1691#define QIB_7322_ErrClear_0_RcvBadTidErrClear_MSB 0xE1692#define QIB_7322_ErrClear_0_RcvBadTidErrClear_RMASK 0x11693#define QIB_7322_ErrClear_0_RcvBadVersionErrClear_LSB 0xB1694#define QIB_7322_ErrClear_0_RcvBadVersionErrClear_MSB 0xB1695#define QIB_7322_ErrClear_0_RcvBadVersionErrClear_RMASK 0x11696#define QIB_7322_ErrClear_0_RcvIBFlowErrClear_LSB 0xA1697#define QIB_7322_ErrClear_0_RcvIBFlowErrClear_MSB 0xA1698#define QIB_7322_ErrClear_0_RcvIBFlowErrClear_RMASK 0x11699#define QIB_7322_ErrClear_0_RcvEBPErrClear_LSB 0x91700#define QIB_7322_ErrClear_0_RcvEBPErrClear_MSB 0x91701#define QIB_7322_ErrClear_0_RcvEBPErrClear_RMASK 0x11702#define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_LSB 0x81703#define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_MSB 0x81704#define QIB_7322_ErrClear_0_RcvUnsupportedVLErrClear_RMASK 0x11705#define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_LSB 0x71706#define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_MSB 0x71707#define QIB_7322_ErrClear_0_RcvUnexpectedCharErrClear_RMASK 0x11708#define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_LSB 0x61709#define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_MSB 0x61710#define QIB_7322_ErrClear_0_RcvShortPktLenErrClear_RMASK 0x11711#define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_LSB 0x51712#define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_MSB 0x51713#define QIB_7322_ErrClear_0_RcvLongPktLenErrClear_RMASK 0x11714#define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_LSB 0x41715#define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_MSB 0x41716#define QIB_7322_ErrClear_0_RcvMaxPktLenErrClear_RMASK 0x11717#define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_LSB 0x31718#define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_MSB 0x31719#define QIB_7322_ErrClear_0_RcvMinPktLenErrClear_RMASK 0x11720#define QIB_7322_ErrClear_0_RcvICRCErrClear_LSB 0x21721#define QIB_7322_ErrClear_0_RcvICRCErrClear_MSB 0x21722#define QIB_7322_ErrClear_0_RcvICRCErrClear_RMASK 0x11723#define QIB_7322_ErrClear_0_RcvVCRCErrClear_LSB 0x11724#define QIB_7322_ErrClear_0_RcvVCRCErrClear_MSB 0x11725#define QIB_7322_ErrClear_0_RcvVCRCErrClear_RMASK 0x11726#define QIB_7322_ErrClear_0_RcvFormatErrClear_LSB 0x01727#define QIB_7322_ErrClear_0_RcvFormatErrClear_MSB 0x01728#define QIB_7322_ErrClear_0_RcvFormatErrClear_RMASK 0x11729 1730#define QIB_7322_TXEStatus_0_OFFS 0x10B81731#define QIB_7322_TXEStatus_0_DEF 0x0000000XC00080FF1732#define QIB_7322_TXEStatus_0_TXE_IBC_Idle_LSB 0x1F1733#define QIB_7322_TXEStatus_0_TXE_IBC_Idle_MSB 0x1F1734#define QIB_7322_TXEStatus_0_TXE_IBC_Idle_RMASK 0x11735#define QIB_7322_TXEStatus_0_RmFifoEmpty_LSB 0x1E1736#define QIB_7322_TXEStatus_0_RmFifoEmpty_MSB 0x1E1737#define QIB_7322_TXEStatus_0_RmFifoEmpty_RMASK 0x11738#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_LSB 0xF1739#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_MSB 0xF1740#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL15_RMASK 0x11741#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_LSB 0x71742#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_MSB 0x71743#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL7_RMASK 0x11744#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_LSB 0x61745#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_MSB 0x61746#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL6_RMASK 0x11747#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_LSB 0x51748#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_MSB 0x51749#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL5_RMASK 0x11750#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_LSB 0x41751#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_MSB 0x41752#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL4_RMASK 0x11753#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_LSB 0x31754#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_MSB 0x31755#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL3_RMASK 0x11756#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_LSB 0x21757#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_MSB 0x21758#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL2_RMASK 0x11759#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_LSB 0x11760#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_MSB 0x11761#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL1_RMASK 0x11762#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_LSB 0x01763#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_MSB 0x01764#define QIB_7322_TXEStatus_0_LaFifoEmpty_VL0_RMASK 0x11765 1766#define QIB_7322_RcvCtrl_0_OFFS 0x11001767#define QIB_7322_RcvCtrl_0_DEF 0x00000000000000001768#define QIB_7322_RcvCtrl_0_RcvResetCredit_LSB 0x2A1769#define QIB_7322_RcvCtrl_0_RcvResetCredit_MSB 0x2A1770#define QIB_7322_RcvCtrl_0_RcvResetCredit_RMASK 0x11771#define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_LSB 0x291772#define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_MSB 0x291773#define QIB_7322_RcvCtrl_0_RcvPartitionKeyDisable_RMASK 0x11774#define QIB_7322_RcvCtrl_0_RcvQPMapEnable_LSB 0x281775#define QIB_7322_RcvCtrl_0_RcvQPMapEnable_MSB 0x281776#define QIB_7322_RcvCtrl_0_RcvQPMapEnable_RMASK 0x11777#define QIB_7322_RcvCtrl_0_RcvIBPortEnable_LSB 0x271778#define QIB_7322_RcvCtrl_0_RcvIBPortEnable_MSB 0x271779#define QIB_7322_RcvCtrl_0_RcvIBPortEnable_RMASK 0x11780#define QIB_7322_RcvCtrl_0_ContextEnableUser_LSB 0x21781#define QIB_7322_RcvCtrl_0_ContextEnableUser_MSB 0x111782#define QIB_7322_RcvCtrl_0_ContextEnableUser_RMASK 0xFFFF1783#define QIB_7322_RcvCtrl_0_ContextEnableKernel_LSB 0x01784#define QIB_7322_RcvCtrl_0_ContextEnableKernel_MSB 0x01785#define QIB_7322_RcvCtrl_0_ContextEnableKernel_RMASK 0x11786 1787#define QIB_7322_RcvBTHQP_0_OFFS 0x11081788#define QIB_7322_RcvBTHQP_0_DEF 0x00000000000000001789#define QIB_7322_RcvBTHQP_0_RcvBTHQP_LSB 0x01790#define QIB_7322_RcvBTHQP_0_RcvBTHQP_MSB 0x171791#define QIB_7322_RcvBTHQP_0_RcvBTHQP_RMASK 0xFFFFFF1792 1793#define QIB_7322_RcvQPMapTableA_0_OFFS 0x11101794#define QIB_7322_RcvQPMapTableA_0_DEF 0x00000000000000001795#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_LSB 0x191796#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_MSB 0x1D1797#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext5_RMASK 0x1F1798#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_LSB 0x141799#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_MSB 0x181800#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext4_RMASK 0x1F1801#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_LSB 0xF1802#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_MSB 0x131803#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext3_RMASK 0x1F1804#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_LSB 0xA1805#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_MSB 0xE1806#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext2_RMASK 0x1F1807#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_LSB 0x51808#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_MSB 0x91809#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext1_RMASK 0x1F1810#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_LSB 0x01811#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_MSB 0x41812#define QIB_7322_RcvQPMapTableA_0_RcvQPMapContext0_RMASK 0x1F1813 1814#define QIB_7322_RcvQPMapTableB_0_OFFS 0x11181815#define QIB_7322_RcvQPMapTableB_0_DEF 0x00000000000000001816#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_LSB 0x191817#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_MSB 0x1D1818#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext11_RMASK 0x1F1819#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_LSB 0x141820#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_MSB 0x181821#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext10_RMASK 0x1F1822#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_LSB 0xF1823#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_MSB 0x131824#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext9_RMASK 0x1F1825#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_LSB 0xA1826#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_MSB 0xE1827#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext8_RMASK 0x1F1828#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_LSB 0x51829#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_MSB 0x91830#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext7_RMASK 0x1F1831#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_LSB 0x01832#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_MSB 0x41833#define QIB_7322_RcvQPMapTableB_0_RcvQPMapContext6_RMASK 0x1F1834 1835#define QIB_7322_RcvQPMapTableC_0_OFFS 0x11201836#define QIB_7322_RcvQPMapTableC_0_DEF 0x00000000000000001837#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_LSB 0x191838#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_MSB 0x1D1839#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext17_RMASK 0x1F1840#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_LSB 0x141841#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_MSB 0x181842#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext16_RMASK 0x1F1843#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_LSB 0xF1844#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_MSB 0x131845#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext15_RMASK 0x1F1846#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_LSB 0xA1847#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_MSB 0xE1848#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext14_RMASK 0x1F1849#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_LSB 0x51850#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_MSB 0x91851#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext13_RMASK 0x1F1852#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_LSB 0x01853#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_MSB 0x41854#define QIB_7322_RcvQPMapTableC_0_RcvQPMapContext12_RMASK 0x1F1855 1856#define QIB_7322_RcvQPMapTableD_0_OFFS 0x11281857#define QIB_7322_RcvQPMapTableD_0_DEF 0x00000000000000001858#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_LSB 0x191859#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_MSB 0x1D1860#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext23_RMASK 0x1F1861#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_LSB 0x141862#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_MSB 0x181863#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext22_RMASK 0x1F1864#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_LSB 0xF1865#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_MSB 0x131866#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext21_RMASK 0x1F1867#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_LSB 0xA1868#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_MSB 0xE1869#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext20_RMASK 0x1F1870#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_LSB 0x51871#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_MSB 0x91872#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext19_RMASK 0x1F1873#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_LSB 0x01874#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_MSB 0x41875#define QIB_7322_RcvQPMapTableD_0_RcvQPMapContext18_RMASK 0x1F1876 1877#define QIB_7322_RcvQPMapTableE_0_OFFS 0x11301878#define QIB_7322_RcvQPMapTableE_0_DEF 0x00000000000000001879#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_LSB 0x191880#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_MSB 0x1D1881#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext29_RMASK 0x1F1882#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_LSB 0x141883#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_MSB 0x181884#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext28_RMASK 0x1F1885#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_LSB 0xF1886#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_MSB 0x131887#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext27_RMASK 0x1F1888#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_LSB 0xA1889#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_MSB 0xE1890#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext26_RMASK 0x1F1891#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_LSB 0x51892#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_MSB 0x91893#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext25_RMASK 0x1F1894#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_LSB 0x01895#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_MSB 0x41896#define QIB_7322_RcvQPMapTableE_0_RcvQPMapContext24_RMASK 0x1F1897 1898#define QIB_7322_RcvQPMapTableF_0_OFFS 0x11381899#define QIB_7322_RcvQPMapTableF_0_DEF 0x00000000000000001900#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_LSB 0x51901#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_MSB 0x91902#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext31_RMASK 0x1F1903#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_LSB 0x01904#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_MSB 0x41905#define QIB_7322_RcvQPMapTableF_0_RcvQPMapContext30_RMASK 0x1F1906 1907#define QIB_7322_PSStat_0_OFFS 0x11401908#define QIB_7322_PSStat_0_DEF 0x00000000000000001909 1910#define QIB_7322_PSStart_0_OFFS 0x11481911#define QIB_7322_PSStart_0_DEF 0x00000000000000001912 1913#define QIB_7322_PSInterval_0_OFFS 0x11501914#define QIB_7322_PSInterval_0_DEF 0x00000000000000001915 1916#define QIB_7322_RcvStatus_0_OFFS 0x11601917#define QIB_7322_RcvStatus_0_DEF 0x00000000000000001918#define QIB_7322_RcvStatus_0_DmaeqBlockingContext_LSB 0x11919#define QIB_7322_RcvStatus_0_DmaeqBlockingContext_MSB 0x51920#define QIB_7322_RcvStatus_0_DmaeqBlockingContext_RMASK 0x1F1921#define QIB_7322_RcvStatus_0_RxPktInProgress_LSB 0x01922#define QIB_7322_RcvStatus_0_RxPktInProgress_MSB 0x01923#define QIB_7322_RcvStatus_0_RxPktInProgress_RMASK 0x11924 1925#define QIB_7322_RcvPartitionKey_0_OFFS 0x11681926#define QIB_7322_RcvPartitionKey_0_DEF 0x00000000000000001927 1928#define QIB_7322_RcvQPMulticastContext_0_OFFS 0x11701929#define QIB_7322_RcvQPMulticastContext_0_DEF 0x00000000000000001930#define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_LSB 0x01931#define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_MSB 0x41932#define QIB_7322_RcvQPMulticastContext_0_RcvQpMcContext_RMASK 0x1F1933 1934#define QIB_7322_RcvPktLEDCnt_0_OFFS 0x11781935#define QIB_7322_RcvPktLEDCnt_0_DEF 0x00000000000000001936#define QIB_7322_RcvPktLEDCnt_0_ONperiod_LSB 0x201937#define QIB_7322_RcvPktLEDCnt_0_ONperiod_MSB 0x3F1938#define QIB_7322_RcvPktLEDCnt_0_ONperiod_RMASK 0xFFFFFFFF1939#define QIB_7322_RcvPktLEDCnt_0_OFFperiod_LSB 0x01940#define QIB_7322_RcvPktLEDCnt_0_OFFperiod_MSB 0x1F1941#define QIB_7322_RcvPktLEDCnt_0_OFFperiod_RMASK 0xFFFFFFFF1942 1943#define QIB_7322_SendDmaIdleCnt_0_OFFS 0x11801944#define QIB_7322_SendDmaIdleCnt_0_DEF 0x00000000000000001945#define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_LSB 0x01946#define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_MSB 0xF1947#define QIB_7322_SendDmaIdleCnt_0_SendDmaIdleCnt_RMASK 0xFFFF1948 1949#define QIB_7322_SendDmaReloadCnt_0_OFFS 0x11881950#define QIB_7322_SendDmaReloadCnt_0_DEF 0x00000000000000001951#define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_LSB 0x01952#define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_MSB 0xF1953#define QIB_7322_SendDmaReloadCnt_0_SendDmaReloadCnt_RMASK 0xFFFF1954 1955#define QIB_7322_SendDmaDescCnt_0_OFFS 0x11901956#define QIB_7322_SendDmaDescCnt_0_DEF 0x00000000000000001957#define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_LSB 0x01958#define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_MSB 0xF1959#define QIB_7322_SendDmaDescCnt_0_SendDmaDescCnt_RMASK 0xFFFF1960 1961#define QIB_7322_SendCtrl_0_OFFS 0x11C01962#define QIB_7322_SendCtrl_0_DEF 0x00000000000000001963#define QIB_7322_SendCtrl_0_IBVLArbiterEn_LSB 0xF1964#define QIB_7322_SendCtrl_0_IBVLArbiterEn_MSB 0xF1965#define QIB_7322_SendCtrl_0_IBVLArbiterEn_RMASK 0x11966#define QIB_7322_SendCtrl_0_TxeDrainRmFifo_LSB 0xE1967#define QIB_7322_SendCtrl_0_TxeDrainRmFifo_MSB 0xE1968#define QIB_7322_SendCtrl_0_TxeDrainRmFifo_RMASK 0x11969#define QIB_7322_SendCtrl_0_TxeDrainLaFifo_LSB 0xD1970#define QIB_7322_SendCtrl_0_TxeDrainLaFifo_MSB 0xD1971#define QIB_7322_SendCtrl_0_TxeDrainLaFifo_RMASK 0x11972#define QIB_7322_SendCtrl_0_SDmaHalt_LSB 0xC1973#define QIB_7322_SendCtrl_0_SDmaHalt_MSB 0xC1974#define QIB_7322_SendCtrl_0_SDmaHalt_RMASK 0x11975#define QIB_7322_SendCtrl_0_SDmaEnable_LSB 0xB1976#define QIB_7322_SendCtrl_0_SDmaEnable_MSB 0xB1977#define QIB_7322_SendCtrl_0_SDmaEnable_RMASK 0x11978#define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_LSB 0xA1979#define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_MSB 0xA1980#define QIB_7322_SendCtrl_0_SDmaSingleDescriptor_RMASK 0x11981#define QIB_7322_SendCtrl_0_SDmaIntEnable_LSB 0x91982#define QIB_7322_SendCtrl_0_SDmaIntEnable_MSB 0x91983#define QIB_7322_SendCtrl_0_SDmaIntEnable_RMASK 0x11984#define QIB_7322_SendCtrl_0_SDmaCleanup_LSB 0x81985#define QIB_7322_SendCtrl_0_SDmaCleanup_MSB 0x81986#define QIB_7322_SendCtrl_0_SDmaCleanup_RMASK 0x11987#define QIB_7322_SendCtrl_0_ForceCreditUpToDate_LSB 0x71988#define QIB_7322_SendCtrl_0_ForceCreditUpToDate_MSB 0x71989#define QIB_7322_SendCtrl_0_ForceCreditUpToDate_RMASK 0x11990#define QIB_7322_SendCtrl_0_SendEnable_LSB 0x31991#define QIB_7322_SendCtrl_0_SendEnable_MSB 0x31992#define QIB_7322_SendCtrl_0_SendEnable_RMASK 0x11993#define QIB_7322_SendCtrl_0_TxeBypassIbc_LSB 0x11994#define QIB_7322_SendCtrl_0_TxeBypassIbc_MSB 0x11995#define QIB_7322_SendCtrl_0_TxeBypassIbc_RMASK 0x11996#define QIB_7322_SendCtrl_0_TxeAbortIbc_LSB 0x01997#define QIB_7322_SendCtrl_0_TxeAbortIbc_MSB 0x01998#define QIB_7322_SendCtrl_0_TxeAbortIbc_RMASK 0x11999 2000#define QIB_7322_SendDmaBase_0_OFFS 0x11F82001#define QIB_7322_SendDmaBase_0_DEF 0x00000000000000002002#define QIB_7322_SendDmaBase_0_SendDmaBase_LSB 0x02003#define QIB_7322_SendDmaBase_0_SendDmaBase_MSB 0x2F2004#define QIB_7322_SendDmaBase_0_SendDmaBase_RMASK 0xFFFFFFFFFFFF2005 2006#define QIB_7322_SendDmaLenGen_0_OFFS 0x12002007#define QIB_7322_SendDmaLenGen_0_DEF 0x00000000000000002008#define QIB_7322_SendDmaLenGen_0_Generation_LSB 0x102009#define QIB_7322_SendDmaLenGen_0_Generation_MSB 0x122010#define QIB_7322_SendDmaLenGen_0_Generation_RMASK 0x72011#define QIB_7322_SendDmaLenGen_0_Length_LSB 0x02012#define QIB_7322_SendDmaLenGen_0_Length_MSB 0xF2013#define QIB_7322_SendDmaLenGen_0_Length_RMASK 0xFFFF2014 2015#define QIB_7322_SendDmaTail_0_OFFS 0x12082016#define QIB_7322_SendDmaTail_0_DEF 0x00000000000000002017#define QIB_7322_SendDmaTail_0_SendDmaTail_LSB 0x02018#define QIB_7322_SendDmaTail_0_SendDmaTail_MSB 0xF2019#define QIB_7322_SendDmaTail_0_SendDmaTail_RMASK 0xFFFF2020 2021#define QIB_7322_SendDmaHead_0_OFFS 0x12102022#define QIB_7322_SendDmaHead_0_DEF 0x00000000000000002023#define QIB_7322_SendDmaHead_0_InternalSendDmaHead_LSB 0x202024#define QIB_7322_SendDmaHead_0_InternalSendDmaHead_MSB 0x2F2025#define QIB_7322_SendDmaHead_0_InternalSendDmaHead_RMASK 0xFFFF2026#define QIB_7322_SendDmaHead_0_SendDmaHead_LSB 0x02027#define QIB_7322_SendDmaHead_0_SendDmaHead_MSB 0xF2028#define QIB_7322_SendDmaHead_0_SendDmaHead_RMASK 0xFFFF2029 2030#define QIB_7322_SendDmaHeadAddr_0_OFFS 0x12182031#define QIB_7322_SendDmaHeadAddr_0_DEF 0x00000000000000002032#define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_LSB 0x02033#define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_MSB 0x2F2034#define QIB_7322_SendDmaHeadAddr_0_SendDmaHeadAddr_RMASK 0xFFFFFFFFFFFF2035 2036#define QIB_7322_SendDmaBufMask0_0_OFFS 0x12202037#define QIB_7322_SendDmaBufMask0_0_DEF 0x00000000000000002038#define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_LSB 0x02039#define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_MSB 0x3F2040#define QIB_7322_SendDmaBufMask0_0_BufMask_63_0_RMASK 0x02041 2042#define QIB_7322_SendDmaStatus_0_OFFS 0x12382043#define QIB_7322_SendDmaStatus_0_DEF 0x00000000420000002044#define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_LSB 0x3F2045#define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_MSB 0x3F2046#define QIB_7322_SendDmaStatus_0_ScoreBoardDrainInProg_RMASK 0x12047#define QIB_7322_SendDmaStatus_0_HaltInProg_LSB 0x3E2048#define QIB_7322_SendDmaStatus_0_HaltInProg_MSB 0x3E2049#define QIB_7322_SendDmaStatus_0_HaltInProg_RMASK 0x12050#define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_LSB 0x3D2051#define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_MSB 0x3D2052#define QIB_7322_SendDmaStatus_0_InternalSDmaHalt_RMASK 0x12053#define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_LSB 0x2F2054#define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_MSB 0x3C2055#define QIB_7322_SendDmaStatus_0_ScbDescIndex_13_0_RMASK 0x3FFF2056#define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_LSB 0x282057#define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_MSB 0x2E2058#define QIB_7322_SendDmaStatus_0_RpyLowAddr_6_0_RMASK 0x7F2059#define QIB_7322_SendDmaStatus_0_RpyTag_7_0_LSB 0x202060#define QIB_7322_SendDmaStatus_0_RpyTag_7_0_MSB 0x272061#define QIB_7322_SendDmaStatus_0_RpyTag_7_0_RMASK 0xFF2062#define QIB_7322_SendDmaStatus_0_ScbFull_LSB 0x1F2063#define QIB_7322_SendDmaStatus_0_ScbFull_MSB 0x1F2064#define QIB_7322_SendDmaStatus_0_ScbFull_RMASK 0x12065#define QIB_7322_SendDmaStatus_0_ScbEmpty_LSB 0x1E2066#define QIB_7322_SendDmaStatus_0_ScbEmpty_MSB 0x1E2067#define QIB_7322_SendDmaStatus_0_ScbEmpty_RMASK 0x12068#define QIB_7322_SendDmaStatus_0_ScbEntryValid_LSB 0x1D2069#define QIB_7322_SendDmaStatus_0_ScbEntryValid_MSB 0x1D2070#define QIB_7322_SendDmaStatus_0_ScbEntryValid_RMASK 0x12071#define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_LSB 0x1C2072#define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_MSB 0x1C2073#define QIB_7322_SendDmaStatus_0_ScbFetchDescFlag_RMASK 0x12074#define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_LSB 0x1B2075#define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_MSB 0x1B2076#define QIB_7322_SendDmaStatus_0_SplFifoReadyToGo_RMASK 0x12077#define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_LSB 0x1A2078#define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_MSB 0x1A2079#define QIB_7322_SendDmaStatus_0_SplFifoDisarmed_RMASK 0x12080#define QIB_7322_SendDmaStatus_0_SplFifoEmpty_LSB 0x192081#define QIB_7322_SendDmaStatus_0_SplFifoEmpty_MSB 0x192082#define QIB_7322_SendDmaStatus_0_SplFifoEmpty_RMASK 0x12083#define QIB_7322_SendDmaStatus_0_SplFifoFull_LSB 0x182084#define QIB_7322_SendDmaStatus_0_SplFifoFull_MSB 0x182085#define QIB_7322_SendDmaStatus_0_SplFifoFull_RMASK 0x12086#define QIB_7322_SendDmaStatus_0_SplFifoBufNum_LSB 0x102087#define QIB_7322_SendDmaStatus_0_SplFifoBufNum_MSB 0x172088#define QIB_7322_SendDmaStatus_0_SplFifoBufNum_RMASK 0xFF2089#define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_LSB 0x02090#define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_MSB 0xF2091#define QIB_7322_SendDmaStatus_0_SplFifoDescIndex_RMASK 0xFFFF2092 2093#define QIB_7322_SendDmaPriorityThld_0_OFFS 0x12582094#define QIB_7322_SendDmaPriorityThld_0_DEF 0x00000000000000002095#define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_LSB 0x02096#define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_MSB 0x32097#define QIB_7322_SendDmaPriorityThld_0_PriorityThreshold_RMASK 0xF2098 2099#define QIB_7322_SendHdrErrSymptom_0_OFFS 0x12602100#define QIB_7322_SendHdrErrSymptom_0_DEF 0x00000000000000002101#define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_LSB 0x62102#define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_MSB 0x62103#define QIB_7322_SendHdrErrSymptom_0_NonKeyPacket_RMASK 0x12104#define QIB_7322_SendHdrErrSymptom_0_GRHFail_LSB 0x52105#define QIB_7322_SendHdrErrSymptom_0_GRHFail_MSB 0x52106#define QIB_7322_SendHdrErrSymptom_0_GRHFail_RMASK 0x12107#define QIB_7322_SendHdrErrSymptom_0_PkeyFail_LSB 0x42108#define QIB_7322_SendHdrErrSymptom_0_PkeyFail_MSB 0x42109#define QIB_7322_SendHdrErrSymptom_0_PkeyFail_RMASK 0x12110#define QIB_7322_SendHdrErrSymptom_0_QPFail_LSB 0x32111#define QIB_7322_SendHdrErrSymptom_0_QPFail_MSB 0x32112#define QIB_7322_SendHdrErrSymptom_0_QPFail_RMASK 0x12113#define QIB_7322_SendHdrErrSymptom_0_SLIDFail_LSB 0x22114#define QIB_7322_SendHdrErrSymptom_0_SLIDFail_MSB 0x22115#define QIB_7322_SendHdrErrSymptom_0_SLIDFail_RMASK 0x12116#define QIB_7322_SendHdrErrSymptom_0_RawIPV6_LSB 0x12117#define QIB_7322_SendHdrErrSymptom_0_RawIPV6_MSB 0x12118#define QIB_7322_SendHdrErrSymptom_0_RawIPV6_RMASK 0x12119#define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_LSB 0x02120#define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_MSB 0x02121#define QIB_7322_SendHdrErrSymptom_0_PacketTooSmall_RMASK 0x12122 2123#define QIB_7322_RxCreditVL0_0_OFFS 0x12802124#define QIB_7322_RxCreditVL0_0_DEF 0x00000000000000002125#define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_LSB 0x102126#define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_MSB 0x1B2127#define QIB_7322_RxCreditVL0_0_RxBufrConsumedVL_RMASK 0xFFF2128#define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_LSB 0x02129#define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_MSB 0xB2130#define QIB_7322_RxCreditVL0_0_RxMaxCreditVL_RMASK 0xFFF2131 2132#define QIB_7322_SendDmaBufUsed0_0_OFFS 0x14802133#define QIB_7322_SendDmaBufUsed0_0_DEF 0x00000000000000002134#define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_LSB 0x02135#define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_MSB 0x3F2136#define QIB_7322_SendDmaBufUsed0_0_BufUsed_63_0_RMASK 0x02137 2138#define QIB_7322_SendCheckControl_0_OFFS 0x14A82139#define QIB_7322_SendCheckControl_0_DEF 0x00000000000000002140#define QIB_7322_SendCheckControl_0_PKey_En_LSB 0x42141#define QIB_7322_SendCheckControl_0_PKey_En_MSB 0x42142#define QIB_7322_SendCheckControl_0_PKey_En_RMASK 0x12143#define QIB_7322_SendCheckControl_0_BTHQP_En_LSB 0x32144#define QIB_7322_SendCheckControl_0_BTHQP_En_MSB 0x32145#define QIB_7322_SendCheckControl_0_BTHQP_En_RMASK 0x12146#define QIB_7322_SendCheckControl_0_SLID_En_LSB 0x22147#define QIB_7322_SendCheckControl_0_SLID_En_MSB 0x22148#define QIB_7322_SendCheckControl_0_SLID_En_RMASK 0x12149#define QIB_7322_SendCheckControl_0_RawIPV6_En_LSB 0x12150#define QIB_7322_SendCheckControl_0_RawIPV6_En_MSB 0x12151#define QIB_7322_SendCheckControl_0_RawIPV6_En_RMASK 0x12152#define QIB_7322_SendCheckControl_0_PacketTooSmall_En_LSB 0x02153#define QIB_7322_SendCheckControl_0_PacketTooSmall_En_MSB 0x02154#define QIB_7322_SendCheckControl_0_PacketTooSmall_En_RMASK 0x12155 2156#define QIB_7322_SendIBSLIDMask_0_OFFS 0x14B02157#define QIB_7322_SendIBSLIDMask_0_DEF 0x00000000000000002158#define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_LSB 0x02159#define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_MSB 0xF2160#define QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK 0xFFFF2161 2162#define QIB_7322_SendIBSLIDAssign_0_OFFS 0x14B82163#define QIB_7322_SendIBSLIDAssign_0_DEF 0x00000000000000002164#define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_LSB 0x02165#define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_MSB 0xF2166#define QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK 0xFFFF2167 2168#define QIB_7322_IBCStatusA_0_OFFS 0x15402169#define QIB_7322_IBCStatusA_0_DEF 0x0000000000000X022170#define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_LSB 0x272171#define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_MSB 0x272172#define QIB_7322_IBCStatusA_0_TxCreditOk_VL7_RMASK 0x12173#define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_LSB 0x262174#define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_MSB 0x262175#define QIB_7322_IBCStatusA_0_TxCreditOk_VL6_RMASK 0x12176#define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_LSB 0x252177#define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_MSB 0x252178#define QIB_7322_IBCStatusA_0_TxCreditOk_VL5_RMASK 0x12179#define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_LSB 0x242180#define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_MSB 0x242181#define QIB_7322_IBCStatusA_0_TxCreditOk_VL4_RMASK 0x12182#define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_LSB 0x232183#define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_MSB 0x232184#define QIB_7322_IBCStatusA_0_TxCreditOk_VL3_RMASK 0x12185#define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_LSB 0x222186#define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_MSB 0x222187#define QIB_7322_IBCStatusA_0_TxCreditOk_VL2_RMASK 0x12188#define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_LSB 0x212189#define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_MSB 0x212190#define QIB_7322_IBCStatusA_0_TxCreditOk_VL1_RMASK 0x12191#define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_LSB 0x202192#define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_MSB 0x202193#define QIB_7322_IBCStatusA_0_TxCreditOk_VL0_RMASK 0x12194#define QIB_7322_IBCStatusA_0_TxReady_LSB 0x1E2195#define QIB_7322_IBCStatusA_0_TxReady_MSB 0x1E2196#define QIB_7322_IBCStatusA_0_TxReady_RMASK 0x12197#define QIB_7322_IBCStatusA_0_LinkSpeedQDR_LSB 0x1D2198#define QIB_7322_IBCStatusA_0_LinkSpeedQDR_MSB 0x1D2199#define QIB_7322_IBCStatusA_0_LinkSpeedQDR_RMASK 0x12200#define QIB_7322_IBCStatusA_0_ScrambleCapRemote_LSB 0xF2201#define QIB_7322_IBCStatusA_0_ScrambleCapRemote_MSB 0xF2202#define QIB_7322_IBCStatusA_0_ScrambleCapRemote_RMASK 0x12203#define QIB_7322_IBCStatusA_0_ScrambleEn_LSB 0xE2204#define QIB_7322_IBCStatusA_0_ScrambleEn_MSB 0xE2205#define QIB_7322_IBCStatusA_0_ScrambleEn_RMASK 0x12206#define QIB_7322_IBCStatusA_0_IBTxLaneReversed_LSB 0xD2207#define QIB_7322_IBCStatusA_0_IBTxLaneReversed_MSB 0xD2208#define QIB_7322_IBCStatusA_0_IBTxLaneReversed_RMASK 0x12209#define QIB_7322_IBCStatusA_0_IBRxLaneReversed_LSB 0xC2210#define QIB_7322_IBCStatusA_0_IBRxLaneReversed_MSB 0xC2211#define QIB_7322_IBCStatusA_0_IBRxLaneReversed_RMASK 0x12212#define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_LSB 0xA2213#define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_MSB 0xA2214#define QIB_7322_IBCStatusA_0_DDS_RXEQ_FAIL_RMASK 0x12215#define QIB_7322_IBCStatusA_0_LinkWidthActive_LSB 0x92216#define QIB_7322_IBCStatusA_0_LinkWidthActive_MSB 0x92217#define QIB_7322_IBCStatusA_0_LinkWidthActive_RMASK 0x12218#define QIB_7322_IBCStatusA_0_LinkSpeedActive_LSB 0x82219#define QIB_7322_IBCStatusA_0_LinkSpeedActive_MSB 0x82220#define QIB_7322_IBCStatusA_0_LinkSpeedActive_RMASK 0x12221#define QIB_7322_IBCStatusA_0_LinkState_LSB 0x52222#define QIB_7322_IBCStatusA_0_LinkState_MSB 0x72223#define QIB_7322_IBCStatusA_0_LinkState_RMASK 0x72224#define QIB_7322_IBCStatusA_0_LinkTrainingState_LSB 0x02225#define QIB_7322_IBCStatusA_0_LinkTrainingState_MSB 0x42226#define QIB_7322_IBCStatusA_0_LinkTrainingState_RMASK 0x1F2227 2228#define QIB_7322_IBCStatusB_0_OFFS 0x15482229#define QIB_7322_IBCStatusB_0_DEF 0x00000000XXXXXXXX2230#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_LSB 0x272231#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_MSB 0x272232#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_debug_RMASK 0x12233#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_LSB 0x262234#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_MSB 0x262235#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_reached_threshold_RMASK 0x12236#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_LSB 0x252237#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_MSB 0x252238#define QIB_7322_IBCStatusB_0_ibsd_adaptation_timer_started_RMASK 0x12239#define QIB_7322_IBCStatusB_0_heartbeat_timed_out_LSB 0x242240#define QIB_7322_IBCStatusB_0_heartbeat_timed_out_MSB 0x242241#define QIB_7322_IBCStatusB_0_heartbeat_timed_out_RMASK 0x12242#define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_LSB 0x202243#define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_MSB 0x232244#define QIB_7322_IBCStatusB_0_heartbeat_crosstalk_RMASK 0xF2245#define QIB_7322_IBCStatusB_0_RxEqLocalDevice_LSB 0x1E2246#define QIB_7322_IBCStatusB_0_RxEqLocalDevice_MSB 0x1F2247#define QIB_7322_IBCStatusB_0_RxEqLocalDevice_RMASK 0x32248#define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_LSB 0x1A2249#define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_MSB 0x1D2250#define QIB_7322_IBCStatusB_0_ReqDDSLocalFromRmt_RMASK 0xF2251#define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_LSB 0x02252#define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_MSB 0x192253#define QIB_7322_IBCStatusB_0_LinkRoundTripLatency_RMASK 0x3FFFFFF2254 2255#define QIB_7322_IBCCtrlA_0_OFFS 0x15602256#define QIB_7322_IBCCtrlA_0_DEF 0x00000000000000002257#define QIB_7322_IBCCtrlA_0_Loopback_LSB 0x3F2258#define QIB_7322_IBCCtrlA_0_Loopback_MSB 0x3F2259#define QIB_7322_IBCCtrlA_0_Loopback_RMASK 0x12260#define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_LSB 0x3E2261#define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_MSB 0x3E2262#define QIB_7322_IBCCtrlA_0_LinkDownDefaultState_RMASK 0x12263#define QIB_7322_IBCCtrlA_0_IBLinkEn_LSB 0x3D2264#define QIB_7322_IBCCtrlA_0_IBLinkEn_MSB 0x3D2265#define QIB_7322_IBCCtrlA_0_IBLinkEn_RMASK 0x12266#define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_LSB 0x3C2267#define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_MSB 0x3C2268#define QIB_7322_IBCCtrlA_0_IBStatIntReductionEn_RMASK 0x12269#define QIB_7322_IBCCtrlA_0_NumVLane_LSB 0x302270#define QIB_7322_IBCCtrlA_0_NumVLane_MSB 0x322271#define QIB_7322_IBCCtrlA_0_NumVLane_RMASK 0x72272#define QIB_7322_IBCCtrlA_0_OverrunThreshold_LSB 0x242273#define QIB_7322_IBCCtrlA_0_OverrunThreshold_MSB 0x272274#define QIB_7322_IBCCtrlA_0_OverrunThreshold_RMASK 0xF2275#define QIB_7322_IBCCtrlA_0_PhyerrThreshold_LSB 0x202276#define QIB_7322_IBCCtrlA_0_PhyerrThreshold_MSB 0x232277#define QIB_7322_IBCCtrlA_0_PhyerrThreshold_RMASK 0xF2278#define QIB_7322_IBCCtrlA_0_MaxPktLen_LSB 0x152279#define QIB_7322_IBCCtrlA_0_MaxPktLen_MSB 0x1F2280#define QIB_7322_IBCCtrlA_0_MaxPktLen_RMASK 0x7FF2281#define QIB_7322_IBCCtrlA_0_LinkCmd_LSB 0x132282#define QIB_7322_IBCCtrlA_0_LinkCmd_MSB 0x142283#define QIB_7322_IBCCtrlA_0_LinkCmd_RMASK 0x32284#define QIB_7322_IBCCtrlA_0_LinkInitCmd_LSB 0x102285#define QIB_7322_IBCCtrlA_0_LinkInitCmd_MSB 0x122286#define QIB_7322_IBCCtrlA_0_LinkInitCmd_RMASK 0x72287#define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_LSB 0x82288#define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_MSB 0xF2289#define QIB_7322_IBCCtrlA_0_FlowCtrlWaterMark_RMASK 0xFF2290#define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_LSB 0x02291#define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_MSB 0x72292#define QIB_7322_IBCCtrlA_0_FlowCtrlPeriod_RMASK 0xFF2293 2294#define QIB_7322_IBCCtrlB_0_OFFS 0x15682295#define QIB_7322_IBCCtrlB_0_DEF 0x00000000000305FF2296#define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_LSB 0x302297#define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_MSB 0x3F2298#define QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK 0xFFFF2299#define QIB_7322_IBCCtrlB_0_IB_DLID_LSB 0x202300#define QIB_7322_IBCCtrlB_0_IB_DLID_MSB 0x2F2301#define QIB_7322_IBCCtrlB_0_IB_DLID_RMASK 0xFFFF2302#define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_LSB 0x1B2303#define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_MSB 0x1B2304#define QIB_7322_IBCCtrlB_0_IB_ENABLE_FILT_DPKT_RMASK 0x12305#define QIB_7322_IBCCtrlB_0_HRTBT_REQ_LSB 0x1A2306#define QIB_7322_IBCCtrlB_0_HRTBT_REQ_MSB 0x1A2307#define QIB_7322_IBCCtrlB_0_HRTBT_REQ_RMASK 0x12308#define QIB_7322_IBCCtrlB_0_HRTBT_PORT_LSB 0x122309#define QIB_7322_IBCCtrlB_0_HRTBT_PORT_MSB 0x192310#define QIB_7322_IBCCtrlB_0_HRTBT_PORT_RMASK 0xFF2311#define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_LSB 0x112312#define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_MSB 0x112313#define QIB_7322_IBCCtrlB_0_HRTBT_AUTO_RMASK 0x12314#define QIB_7322_IBCCtrlB_0_HRTBT_ENB_LSB 0x102315#define QIB_7322_IBCCtrlB_0_HRTBT_ENB_MSB 0x102316#define QIB_7322_IBCCtrlB_0_HRTBT_ENB_RMASK 0x12317#define QIB_7322_IBCCtrlB_0_SD_DDS_LSB 0xC2318#define QIB_7322_IBCCtrlB_0_SD_DDS_MSB 0xF2319#define QIB_7322_IBCCtrlB_0_SD_DDS_RMASK 0xF2320#define QIB_7322_IBCCtrlB_0_SD_DDSV_LSB 0xB2321#define QIB_7322_IBCCtrlB_0_SD_DDSV_MSB 0xB2322#define QIB_7322_IBCCtrlB_0_SD_DDSV_RMASK 0x12323#define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_LSB 0xA2324#define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_MSB 0xA2325#define QIB_7322_IBCCtrlB_0_SD_ADD_ENB_RMASK 0x12326#define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_LSB 0x92327#define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_MSB 0x92328#define QIB_7322_IBCCtrlB_0_SD_RX_EQUAL_ENABLE_RMASK 0x12329#define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_LSB 0x82330#define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_MSB 0x82331#define QIB_7322_IBCCtrlB_0_IB_LANE_REV_SUPPORTED_RMASK 0x12332#define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_LSB 0x72333#define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_MSB 0x72334#define QIB_7322_IBCCtrlB_0_IB_POLARITY_REV_SUPP_RMASK 0x12335#define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_LSB 0x52336#define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_MSB 0x62337#define QIB_7322_IBCCtrlB_0_IB_NUM_CHANNELS_RMASK 0x32338#define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_LSB 0x42339#define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_MSB 0x42340#define QIB_7322_IBCCtrlB_0_SD_SPEED_QDR_RMASK 0x12341#define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_LSB 0x32342#define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_MSB 0x32343#define QIB_7322_IBCCtrlB_0_SD_SPEED_DDR_RMASK 0x12344#define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_LSB 0x22345#define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_MSB 0x22346#define QIB_7322_IBCCtrlB_0_SD_SPEED_SDR_RMASK 0x12347#define QIB_7322_IBCCtrlB_0_SD_SPEED_LSB 0x12348#define QIB_7322_IBCCtrlB_0_SD_SPEED_MSB 0x12349#define QIB_7322_IBCCtrlB_0_SD_SPEED_RMASK 0x12350#define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_LSB 0x02351#define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_MSB 0x02352#define QIB_7322_IBCCtrlB_0_IB_ENHANCED_MODE_RMASK 0x12353 2354#define QIB_7322_IBCCtrlC_0_OFFS 0x15702355#define QIB_7322_IBCCtrlC_0_DEF 0x00000000000003012356#define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_LSB 0x52357#define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_MSB 0x92358#define QIB_7322_IBCCtrlC_0_IB_BACK_PORCH_RMASK 0x1F2359#define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_LSB 0x02360#define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_MSB 0x42361#define QIB_7322_IBCCtrlC_0_IB_FRONT_PORCH_RMASK 0x1F2362 2363#define QIB_7322_HRTBT_GUID_0_OFFS 0x15882364#define QIB_7322_HRTBT_GUID_0_DEF 0x00000000000000002365 2366#define QIB_7322_IB_SDTEST_IF_TX_0_OFFS 0x15902367#define QIB_7322_IB_SDTEST_IF_TX_0_DEF 0x00000000000000002368#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_LSB 0x302369#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_MSB 0x3F2370#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_RX_CFG_RMASK 0xFFFF2371#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_LSB 0x202372#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_MSB 0x2F2373#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_TX_CFG_RMASK 0xFFFF2374#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_LSB 0xD2375#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_MSB 0xF2376#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_SPEED_RMASK 0x72377#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_LSB 0xB2378#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_MSB 0xC2379#define QIB_7322_IB_SDTEST_IF_TX_0_TS_TX_OPCODE_RMASK 0x32380#define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_LSB 0x42381#define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_MSB 0x42382#define QIB_7322_IB_SDTEST_IF_TX_0_CREDIT_CHANGE_RMASK 0x12383#define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_LSB 0x22384#define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_MSB 0x32385#define QIB_7322_IB_SDTEST_IF_TX_0_VL_CAP_RMASK 0x32386#define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_LSB 0x12387#define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_MSB 0x12388#define QIB_7322_IB_SDTEST_IF_TX_0_TS_3_TX_VALID_RMASK 0x12389#define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_LSB 0x02390#define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_MSB 0x02391#define QIB_7322_IB_SDTEST_IF_TX_0_TS_T_TX_VALID_RMASK 0x12392 2393#define QIB_7322_IB_SDTEST_IF_RX_0_OFFS 0x15982394#define QIB_7322_IB_SDTEST_IF_RX_0_DEF 0x00000000000000002395#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_LSB 0x302396#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_MSB 0x3F2397#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_RX_CFG_RMASK 0xFFFF2398#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_LSB 0x202399#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_MSB 0x2F2400#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_TX_CFG_RMASK 0xFFFF2401#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_LSB 0x182402#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_MSB 0x1F2403#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_B_RMASK 0xFF2404#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_LSB 0x102405#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_MSB 0x172406#define QIB_7322_IB_SDTEST_IF_RX_0_TS_RX_A_RMASK 0xFF2407#define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_LSB 0x12408#define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_MSB 0x12409#define QIB_7322_IB_SDTEST_IF_RX_0_TS_3_RX_VALID_RMASK 0x12410#define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_LSB 0x02411#define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_MSB 0x02412#define QIB_7322_IB_SDTEST_IF_RX_0_TS_T_RX_VALID_RMASK 0x12413 2414#define QIB_7322_IBNCModeCtrl_0_OFFS 0x15B82415#define QIB_7322_IBNCModeCtrl_0_DEF 0x00000000000000002416#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_LSB 0x222417#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_MSB 0x222418#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteForce_RMASK 0x12419#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_LSB 0x212420#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_MSB 0x212421#define QIB_7322_IBNCModeCtrl_0_ScrambleCapRemoteMask_RMASK 0x12422#define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_LSB 0x202423#define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_MSB 0x202424#define QIB_7322_IBNCModeCtrl_0_ScrambleCapLocal_RMASK 0x12425#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_LSB 0x112426#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_MSB 0x192427#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS2_RMASK 0x1FF2428#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_LSB 0x82429#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_MSB 0x102430#define QIB_7322_IBNCModeCtrl_0_TSMCode_TS1_RMASK 0x1FF2431#define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_LSB 0x22432#define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_MSB 0x22433#define QIB_7322_IBNCModeCtrl_0_TSMEnable_ignore_TSM_on_rx_RMASK 0x12434#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_LSB 0x12435#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_MSB 0x12436#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS2_RMASK 0x12437#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_LSB 0x02438#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_MSB 0x02439#define QIB_7322_IBNCModeCtrl_0_TSMEnable_send_TS1_RMASK 0x12440 2441#define QIB_7322_IBSerdesStatus_0_OFFS 0x15D02442#define QIB_7322_IBSerdesStatus_0_DEF 0x00000000000000002443 2444#define QIB_7322_IBPCSConfig_0_OFFS 0x15D82445#define QIB_7322_IBPCSConfig_0_DEF 0x00000000000000072446#define QIB_7322_IBPCSConfig_0_link_sync_mask_LSB 0x92447#define QIB_7322_IBPCSConfig_0_link_sync_mask_MSB 0x122448#define QIB_7322_IBPCSConfig_0_link_sync_mask_RMASK 0x3FF2449#define QIB_7322_IBPCSConfig_0_xcv_rreset_LSB 0x22450#define QIB_7322_IBPCSConfig_0_xcv_rreset_MSB 0x22451#define QIB_7322_IBPCSConfig_0_xcv_rreset_RMASK 0x12452#define QIB_7322_IBPCSConfig_0_xcv_treset_LSB 0x12453#define QIB_7322_IBPCSConfig_0_xcv_treset_MSB 0x12454#define QIB_7322_IBPCSConfig_0_xcv_treset_RMASK 0x12455#define QIB_7322_IBPCSConfig_0_tx_rx_reset_LSB 0x02456#define QIB_7322_IBPCSConfig_0_tx_rx_reset_MSB 0x02457#define QIB_7322_IBPCSConfig_0_tx_rx_reset_RMASK 0x12458 2459#define QIB_7322_IBSerdesCtrl_0_OFFS 0x15E02460#define QIB_7322_IBSerdesCtrl_0_DEF 0x0000000000FFA00F2461#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_LSB 0x1A2462#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_MSB 0x1A2463#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_QDR_RMASK 0x12464#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_LSB 0x192465#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_MSB 0x192466#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_DDR_RMASK 0x12467#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_LSB 0x182468#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_MSB 0x182469#define QIB_7322_IBSerdesCtrl_0_DISABLE_RXLATOFF_SDR_RMASK 0x12470#define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_LSB 0x142471#define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_MSB 0x172472#define QIB_7322_IBSerdesCtrl_0_CHANNEL_RESET_N_RMASK 0xF2473#define QIB_7322_IBSerdesCtrl_0_CGMODE_LSB 0x102474#define QIB_7322_IBSerdesCtrl_0_CGMODE_MSB 0x132475#define QIB_7322_IBSerdesCtrl_0_CGMODE_RMASK 0xF2476#define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_LSB 0xF2477#define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_MSB 0xF2478#define QIB_7322_IBSerdesCtrl_0_IB_LAT_MODE_RMASK 0x12479#define QIB_7322_IBSerdesCtrl_0_RXLOSEN_LSB 0xD2480#define QIB_7322_IBSerdesCtrl_0_RXLOSEN_MSB 0xD2481#define QIB_7322_IBSerdesCtrl_0_RXLOSEN_RMASK 0x12482#define QIB_7322_IBSerdesCtrl_0_LPEN_LSB 0xC2483#define QIB_7322_IBSerdesCtrl_0_LPEN_MSB 0xC2484#define QIB_7322_IBSerdesCtrl_0_LPEN_RMASK 0x12485#define QIB_7322_IBSerdesCtrl_0_PLLPD_LSB 0xB2486#define QIB_7322_IBSerdesCtrl_0_PLLPD_MSB 0xB2487#define QIB_7322_IBSerdesCtrl_0_PLLPD_RMASK 0x12488#define QIB_7322_IBSerdesCtrl_0_TXPD_LSB 0xA2489#define QIB_7322_IBSerdesCtrl_0_TXPD_MSB 0xA2490#define QIB_7322_IBSerdesCtrl_0_TXPD_RMASK 0x12491#define QIB_7322_IBSerdesCtrl_0_RXPD_LSB 0x92492#define QIB_7322_IBSerdesCtrl_0_RXPD_MSB 0x92493#define QIB_7322_IBSerdesCtrl_0_RXPD_RMASK 0x12494#define QIB_7322_IBSerdesCtrl_0_TXIDLE_LSB 0x82495#define QIB_7322_IBSerdesCtrl_0_TXIDLE_MSB 0x82496#define QIB_7322_IBSerdesCtrl_0_TXIDLE_RMASK 0x12497#define QIB_7322_IBSerdesCtrl_0_CMODE_LSB 0x02498#define QIB_7322_IBSerdesCtrl_0_CMODE_MSB 0x62499#define QIB_7322_IBSerdesCtrl_0_CMODE_RMASK 0x7F2500 2501#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_OFFS 0x16002502#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_DEF 0x00000000000000002503#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_LSB 0x1F2504#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_MSB 0x1F2505#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_tx_override_deemphasis_select_RMASK 0x12506#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_LSB 0x1E2507#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_MSB 0x1E2508#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_reset_tx_deemphasis_override_RMASK 0x12509#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_LSB 0xE2510#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_MSB 0x112511#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txampcntl_d2a_RMASK 0xF2512#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_LSB 0x92513#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_MSB 0xD2514#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txc0_ena_RMASK 0x1F2515#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_LSB 0x52516#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_MSB 0x82517#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcp1_ena_RMASK 0xF2518#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_LSB 0x32519#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_MSB 0x42520#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_xtra_emph0_RMASK 0x32521#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_LSB 0x02522#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_MSB 0x22523#define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_txcn1_ena_RMASK 0x72524 2525#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_OFFS 0x16402526#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_DEF 0x00000000000000002527#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_LSB 0x272528#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_MSB 0x272529#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch3_RMASK 0x12530#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_LSB 0x262531#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_MSB 0x262532#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch2_RMASK 0x12533#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_LSB 0x252534#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_MSB 0x252535#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch1_RMASK 0x12536#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_LSB 0x242537#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_MSB 0x242538#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenagain_sdr_ch0_RMASK 0x12539#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_LSB 0x232540#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_MSB 0x232541#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch3_RMASK 0x12542#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_LSB 0x222543#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_MSB 0x222544#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch2_RMASK 0x12545#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_LSB 0x212546#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_MSB 0x212547#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch1_RMASK 0x12548#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_LSB 0x202549#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_MSB 0x202550#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenale_sdr_ch0_RMASK 0x12551#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_LSB 0x182552#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_MSB 0x1F2553#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch3_RMASK 0xFF2554#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_LSB 0x102555#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_MSB 0x172556#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch2_RMASK 0xFF2557#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_LSB 0x82558#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_MSB 0xF2559#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch1_RMASK 0xFF2560#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_LSB 0x02561#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_MSB 0x72562#define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_static_disable_rxenadfe_sdr_ch0_RMASK 0xFF2563 2564#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_OFFS 0x16482565#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_DEF 0x00000000000000002566#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_LSB 0x272567#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_MSB 0x272568#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch3_RMASK 0x12569#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_LSB 0x262570#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_MSB 0x262571#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch2_RMASK 0x12572#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_LSB 0x252573#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_MSB 0x252574#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch1_RMASK 0x12575#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_LSB 0x242576#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_MSB 0x242577#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenagain_sdr_ch0_RMASK 0x12578#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_LSB 0x232579#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_MSB 0x232580#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch3_RMASK 0x12581#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_LSB 0x222582#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_MSB 0x222583#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch2_RMASK 0x12584#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_LSB 0x212585#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_MSB 0x212586#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch1_RMASK 0x12587#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_LSB 0x202588#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_MSB 0x202589#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenale_sdr_ch0_RMASK 0x12590#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_LSB 0x182591#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_MSB 0x1F2592#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch3_RMASK 0xFF2593#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_LSB 0x102594#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_MSB 0x172595#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch2_RMASK 0xFF2596#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_LSB 0x82597#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_MSB 0xF2598#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch1_RMASK 0xFF2599#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_LSB 0x02600#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_MSB 0x72601#define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_dyn_disable_rxenadfe_sdr_ch0_RMASK 0xFF2602 2603#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_OFFS 0x16502604#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_DEF 0x00000000000000002605#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_LSB 0x272606#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_MSB 0x272607#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch3_RMASK 0x12608#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_LSB 0x262609#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_MSB 0x262610#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch2_RMASK 0x12611#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_LSB 0x252612#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_MSB 0x252613#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch1_RMASK 0x12614#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_LSB 0x242615#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_MSB 0x242616#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenagain_ddr_ch0_RMASK 0x12617#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_LSB 0x232618#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_MSB 0x232619#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch3_RMASK 0x12620#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_LSB 0x222621#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_MSB 0x222622#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch2_RMASK 0x12623#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_LSB 0x212624#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_MSB 0x212625#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch1_RMASK 0x12626#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_LSB 0x202627#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_MSB 0x202628#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenale_ddr_ch0_RMASK 0x12629#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_LSB 0x182630#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_MSB 0x1F2631#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch3_RMASK 0xFF2632#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_LSB 0x102633#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_MSB 0x172634#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch2_RMASK 0xFF2635#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_LSB 0x82636#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_MSB 0xF2637#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch1_RMASK 0xFF2638#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_LSB 0x02639#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_MSB 0x72640#define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_static_disable_rxenadfe_ddr_ch0_RMASK 0xFF2641 2642#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_OFFS 0x16582643#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_DEF 0x00000000000000002644#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_LSB 0x272645#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_MSB 0x272646#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch3_RMASK 0x12647#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_LSB 0x262648#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_MSB 0x262649#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch2_RMASK 0x12650#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_LSB 0x252651#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_MSB 0x252652#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch1_RMASK 0x12653#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_LSB 0x242654#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_MSB 0x242655#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenagain_ddr_ch0_RMASK 0x12656#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_LSB 0x232657#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_MSB 0x232658#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch3_RMASK 0x12659#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_LSB 0x222660#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_MSB 0x222661#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch2_RMASK 0x12662#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_LSB 0x212663#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_MSB 0x212664#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch1_RMASK 0x12665#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_LSB 0x202666#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_MSB 0x202667#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenale_ddr_ch0_RMASK 0x12668#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_LSB 0x182669#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_MSB 0x1F2670#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch3_RMASK 0xFF2671#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_LSB 0x102672#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_MSB 0x172673#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch2_RMASK 0xFF2674#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_LSB 0x82675#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_MSB 0xF2676#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch1_RMASK 0xFF2677#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_LSB 0x02678#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_MSB 0x72679#define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_dyn_disable_rxenadfe_ddr_ch0_RMASK 0xFF2680 2681#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_OFFS 0x16602682#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_DEF 0x00000000000000002683#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_LSB 0x272684#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_MSB 0x272685#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch3_RMASK 0x12686#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_LSB 0x262687#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_MSB 0x262688#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch2_RMASK 0x12689#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_LSB 0x252690#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_MSB 0x252691#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch1_RMASK 0x12692#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_LSB 0x242693#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_MSB 0x242694#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenagain_qdr_ch0_RMASK 0x12695#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_LSB 0x232696#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_MSB 0x232697#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch3_RMASK 0x12698#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_LSB 0x222699#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_MSB 0x222700#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch2_RMASK 0x12701#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_LSB 0x212702#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_MSB 0x212703#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch1_RMASK 0x12704#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_LSB 0x202705#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_MSB 0x202706#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenale_qdr_ch0_RMASK 0x12707#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_LSB 0x182708#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_MSB 0x1F2709#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch3_RMASK 0xFF2710#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_LSB 0x102711#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_MSB 0x172712#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch2_RMASK 0xFF2713#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_LSB 0x82714#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_MSB 0xF2715#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch1_RMASK 0xFF2716#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_LSB 0x02717#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_MSB 0x72718#define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_static_disable_rxenadfe_qdr_ch0_RMASK 0xFF2719 2720#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_OFFS 0x16682721#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_DEF 0x00000000000000002722#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_LSB 0x272723#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_MSB 0x272724#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch3_RMASK 0x12725#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_LSB 0x262726#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_MSB 0x262727#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch2_RMASK 0x12728#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_LSB 0x252729#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_MSB 0x252730#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch1_RMASK 0x12731#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_LSB 0x242732#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_MSB 0x242733#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenagain_qdr_ch0_RMASK 0x12734#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_LSB 0x232735#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_MSB 0x232736#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch3_RMASK 0x12737#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_LSB 0x222738#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_MSB 0x222739#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch2_RMASK 0x12740#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_LSB 0x212741#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_MSB 0x212742#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch1_RMASK 0x12743#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_LSB 0x202744#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_MSB 0x202745#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenale_qdr_ch0_RMASK 0x12746#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_LSB 0x182747#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_MSB 0x1F2748#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch3_RMASK 0xFF2749#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_LSB 0x102750#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_MSB 0x172751#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch2_RMASK 0xFF2752#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_LSB 0x82753#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_MSB 0xF2754#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch1_RMASK 0xFF2755#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_LSB 0x02756#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_MSB 0x72757#define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_dyn_disable_rxenadfe_qdr_ch0_RMASK 0xFF2758 2759#define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_OFFS 0x16702760#define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_DEF 0x00000000000000002761 2762#define QIB_7322_HighPriorityLimit_0_OFFS 0x1BC02763#define QIB_7322_HighPriorityLimit_0_DEF 0x00000000000000002764#define QIB_7322_HighPriorityLimit_0_Limit_LSB 0x02765#define QIB_7322_HighPriorityLimit_0_Limit_MSB 0x72766#define QIB_7322_HighPriorityLimit_0_Limit_RMASK 0xFF2767 2768#define QIB_7322_LowPriority0_0_OFFS 0x1C002769#define QIB_7322_LowPriority0_0_DEF 0x00000000000000002770#define QIB_7322_LowPriority0_0_VirtualLane_LSB 0x102771#define QIB_7322_LowPriority0_0_VirtualLane_MSB 0x122772#define QIB_7322_LowPriority0_0_VirtualLane_RMASK 0x72773#define QIB_7322_LowPriority0_0_Weight_LSB 0x02774#define QIB_7322_LowPriority0_0_Weight_MSB 0x72775#define QIB_7322_LowPriority0_0_Weight_RMASK 0xFF2776 2777#define QIB_7322_HighPriority0_0_OFFS 0x1E002778#define QIB_7322_HighPriority0_0_DEF 0x00000000000000002779#define QIB_7322_HighPriority0_0_VirtualLane_LSB 0x102780#define QIB_7322_HighPriority0_0_VirtualLane_MSB 0x122781#define QIB_7322_HighPriority0_0_VirtualLane_RMASK 0x72782#define QIB_7322_HighPriority0_0_Weight_LSB 0x02783#define QIB_7322_HighPriority0_0_Weight_MSB 0x72784#define QIB_7322_HighPriority0_0_Weight_RMASK 0xFF2785 2786#define QIB_7322_CntrRegBase_1_OFFS 0x20282787#define QIB_7322_CntrRegBase_1_DEF 0x00000000000130002788 2789#define QIB_7322_RcvQPMulticastContext_1_OFFS 0x21702790 2791#define QIB_7322_SendCtrl_1_OFFS 0x21C02792 2793#define QIB_7322_SendBufAvail0_OFFS 0x30002794#define QIB_7322_SendBufAvail0_DEF 0x00000000000000002795#define QIB_7322_SendBufAvail0_SendBuf_31_0_LSB 0x02796#define QIB_7322_SendBufAvail0_SendBuf_31_0_MSB 0x3F2797#define QIB_7322_SendBufAvail0_SendBuf_31_0_RMASK 0x02798 2799#define QIB_7322_MsixTable_OFFS 0x80002800#define QIB_7322_MsixTable_DEF 0x00000000000000002801 2802#define QIB_7322_MsixPba_OFFS 0x90002803#define QIB_7322_MsixPba_DEF 0x00000000000000002804 2805#define QIB_7322_LAMemory_OFFS 0xA0002806#define QIB_7322_LAMemory_DEF 0x00000000000000002807 2808#define QIB_7322_LBIntCnt_OFFS 0x110002809#define QIB_7322_LBIntCnt_DEF 0x00000000000000002810 2811#define QIB_7322_LBFlowStallCnt_OFFS 0x110082812#define QIB_7322_LBFlowStallCnt_DEF 0x00000000000000002813 2814#define QIB_7322_RxTIDFullErrCnt_OFFS 0x110D02815#define QIB_7322_RxTIDFullErrCnt_DEF 0x00000000000000002816 2817#define QIB_7322_RxTIDValidErrCnt_OFFS 0x110D82818#define QIB_7322_RxTIDValidErrCnt_DEF 0x00000000000000002819 2820#define QIB_7322_RxP0HdrEgrOvflCnt_OFFS 0x110E82821#define QIB_7322_RxP0HdrEgrOvflCnt_DEF 0x00000000000000002822 2823#define QIB_7322_PcieRetryBufDiagQwordCnt_OFFS 0x111A02824#define QIB_7322_PcieRetryBufDiagQwordCnt_DEF 0x00000000000000002825 2826#define QIB_7322_RxTidFlowDropCnt_OFFS 0x111E02827#define QIB_7322_RxTidFlowDropCnt_DEF 0x00000000000000002828 2829#define QIB_7322_LBIntCnt_0_OFFS 0x120002830#define QIB_7322_LBIntCnt_0_DEF 0x00000000000000002831 2832#define QIB_7322_TxCreditUpToDateTimeOut_0_OFFS 0x120082833#define QIB_7322_TxCreditUpToDateTimeOut_0_DEF 0x00000000000000002834 2835#define QIB_7322_TxSDmaDescCnt_0_OFFS 0x120102836#define QIB_7322_TxSDmaDescCnt_0_DEF 0x00000000000000002837 2838#define QIB_7322_TxUnsupVLErrCnt_0_OFFS 0x120182839#define QIB_7322_TxUnsupVLErrCnt_0_DEF 0x00000000000000002840 2841#define QIB_7322_TxDataPktCnt_0_OFFS 0x120202842#define QIB_7322_TxDataPktCnt_0_DEF 0x00000000000000002843 2844#define QIB_7322_TxFlowPktCnt_0_OFFS 0x120282845#define QIB_7322_TxFlowPktCnt_0_DEF 0x00000000000000002846 2847#define QIB_7322_TxDwordCnt_0_OFFS 0x120302848#define QIB_7322_TxDwordCnt_0_DEF 0x00000000000000002849 2850#define QIB_7322_TxLenErrCnt_0_OFFS 0x120382851#define QIB_7322_TxLenErrCnt_0_DEF 0x00000000000000002852 2853#define QIB_7322_TxMaxMinLenErrCnt_0_OFFS 0x120402854#define QIB_7322_TxMaxMinLenErrCnt_0_DEF 0x00000000000000002855 2856#define QIB_7322_TxUnderrunCnt_0_OFFS 0x120482857#define QIB_7322_TxUnderrunCnt_0_DEF 0x00000000000000002858 2859#define QIB_7322_TxFlowStallCnt_0_OFFS 0x120502860#define QIB_7322_TxFlowStallCnt_0_DEF 0x00000000000000002861 2862#define QIB_7322_TxDroppedPktCnt_0_OFFS 0x120582863#define QIB_7322_TxDroppedPktCnt_0_DEF 0x00000000000000002864 2865#define QIB_7322_RxDroppedPktCnt_0_OFFS 0x120602866#define QIB_7322_RxDroppedPktCnt_0_DEF 0x00000000000000002867 2868#define QIB_7322_RxDataPktCnt_0_OFFS 0x120682869#define QIB_7322_RxDataPktCnt_0_DEF 0x00000000000000002870 2871#define QIB_7322_RxFlowPktCnt_0_OFFS 0x120702872#define QIB_7322_RxFlowPktCnt_0_DEF 0x00000000000000002873 2874#define QIB_7322_RxDwordCnt_0_OFFS 0x120782875#define QIB_7322_RxDwordCnt_0_DEF 0x00000000000000002876 2877#define QIB_7322_RxLenErrCnt_0_OFFS 0x120802878#define QIB_7322_RxLenErrCnt_0_DEF 0x00000000000000002879 2880#define QIB_7322_RxMaxMinLenErrCnt_0_OFFS 0x120882881#define QIB_7322_RxMaxMinLenErrCnt_0_DEF 0x00000000000000002882 2883#define QIB_7322_RxICRCErrCnt_0_OFFS 0x120902884#define QIB_7322_RxICRCErrCnt_0_DEF 0x00000000000000002885 2886#define QIB_7322_RxVCRCErrCnt_0_OFFS 0x120982887#define QIB_7322_RxVCRCErrCnt_0_DEF 0x00000000000000002888 2889#define QIB_7322_RxFlowCtrlViolCnt_0_OFFS 0x120A02890#define QIB_7322_RxFlowCtrlViolCnt_0_DEF 0x00000000000000002891 2892#define QIB_7322_RxVersionErrCnt_0_OFFS 0x120A82893#define QIB_7322_RxVersionErrCnt_0_DEF 0x00000000000000002894 2895#define QIB_7322_RxLinkMalformCnt_0_OFFS 0x120B02896#define QIB_7322_RxLinkMalformCnt_0_DEF 0x00000000000000002897 2898#define QIB_7322_RxEBPCnt_0_OFFS 0x120B82899#define QIB_7322_RxEBPCnt_0_DEF 0x00000000000000002900 2901#define QIB_7322_RxLPCRCErrCnt_0_OFFS 0x120C02902#define QIB_7322_RxLPCRCErrCnt_0_DEF 0x00000000000000002903 2904#define QIB_7322_RxBufOvflCnt_0_OFFS 0x120C82905#define QIB_7322_RxBufOvflCnt_0_DEF 0x00000000000000002906 2907#define QIB_7322_RxLenTruncateCnt_0_OFFS 0x120D02908#define QIB_7322_RxLenTruncateCnt_0_DEF 0x00000000000000002909 2910#define QIB_7322_RxPKeyMismatchCnt_0_OFFS 0x120E02911#define QIB_7322_RxPKeyMismatchCnt_0_DEF 0x00000000000000002912 2913#define QIB_7322_IBLinkDownedCnt_0_OFFS 0x121802914#define QIB_7322_IBLinkDownedCnt_0_DEF 0x00000000000000002915 2916#define QIB_7322_IBSymbolErrCnt_0_OFFS 0x121882917#define QIB_7322_IBSymbolErrCnt_0_DEF 0x00000000000000002918 2919#define QIB_7322_IBStatusChangeCnt_0_OFFS 0x121902920#define QIB_7322_IBStatusChangeCnt_0_DEF 0x00000000000000002921 2922#define QIB_7322_IBLinkErrRecoveryCnt_0_OFFS 0x121982923#define QIB_7322_IBLinkErrRecoveryCnt_0_DEF 0x00000000000000002924 2925#define QIB_7322_ExcessBufferOvflCnt_0_OFFS 0x121A82926#define QIB_7322_ExcessBufferOvflCnt_0_DEF 0x00000000000000002927 2928#define QIB_7322_LocalLinkIntegrityErrCnt_0_OFFS 0x121B02929#define QIB_7322_LocalLinkIntegrityErrCnt_0_DEF 0x00000000000000002930 2931#define QIB_7322_RxVlErrCnt_0_OFFS 0x121B82932#define QIB_7322_RxVlErrCnt_0_DEF 0x00000000000000002933 2934#define QIB_7322_RxDlidFltrCnt_0_OFFS 0x121C02935#define QIB_7322_RxDlidFltrCnt_0_DEF 0x00000000000000002936 2937#define QIB_7322_RxVL15DroppedPktCnt_0_OFFS 0x121C82938#define QIB_7322_RxVL15DroppedPktCnt_0_DEF 0x00000000000000002939 2940#define QIB_7322_RxOtherLocalPhyErrCnt_0_OFFS 0x121D02941#define QIB_7322_RxOtherLocalPhyErrCnt_0_DEF 0x00000000000000002942 2943#define QIB_7322_RxQPInvalidContextCnt_0_OFFS 0x121D82944#define QIB_7322_RxQPInvalidContextCnt_0_DEF 0x00000000000000002945 2946#define QIB_7322_TxHeadersErrCnt_0_OFFS 0x121F82947#define QIB_7322_TxHeadersErrCnt_0_DEF 0x00000000000000002948 2949#define QIB_7322_PSRcvDataCount_0_OFFS 0x122182950#define QIB_7322_PSRcvDataCount_0_DEF 0x00000000000000002951 2952#define QIB_7322_PSRcvPktsCount_0_OFFS 0x122202953#define QIB_7322_PSRcvPktsCount_0_DEF 0x00000000000000002954 2955#define QIB_7322_PSXmitDataCount_0_OFFS 0x122282956#define QIB_7322_PSXmitDataCount_0_DEF 0x00000000000000002957 2958#define QIB_7322_PSXmitPktsCount_0_OFFS 0x122302959#define QIB_7322_PSXmitPktsCount_0_DEF 0x00000000000000002960 2961#define QIB_7322_PSXmitWaitCount_0_OFFS 0x122382962#define QIB_7322_PSXmitWaitCount_0_DEF 0x00000000000000002963 2964#define QIB_7322_LBIntCnt_1_OFFS 0x130002965#define QIB_7322_LBIntCnt_1_DEF 0x00000000000000002966 2967#define QIB_7322_TxCreditUpToDateTimeOut_1_OFFS 0x130082968#define QIB_7322_TxCreditUpToDateTimeOut_1_DEF 0x00000000000000002969 2970#define QIB_7322_TxSDmaDescCnt_1_OFFS 0x130102971#define QIB_7322_TxSDmaDescCnt_1_DEF 0x00000000000000002972 2973#define QIB_7322_TxUnsupVLErrCnt_1_OFFS 0x130182974#define QIB_7322_TxUnsupVLErrCnt_1_DEF 0x00000000000000002975 2976#define QIB_7322_TxDataPktCnt_1_OFFS 0x130202977#define QIB_7322_TxDataPktCnt_1_DEF 0x00000000000000002978 2979#define QIB_7322_TxFlowPktCnt_1_OFFS 0x130282980#define QIB_7322_TxFlowPktCnt_1_DEF 0x00000000000000002981 2982#define QIB_7322_TxDwordCnt_1_OFFS 0x130302983#define QIB_7322_TxDwordCnt_1_DEF 0x00000000000000002984 2985#define QIB_7322_TxLenErrCnt_1_OFFS 0x130382986#define QIB_7322_TxLenErrCnt_1_DEF 0x00000000000000002987 2988#define QIB_7322_TxMaxMinLenErrCnt_1_OFFS 0x130402989#define QIB_7322_TxMaxMinLenErrCnt_1_DEF 0x00000000000000002990 2991#define QIB_7322_TxUnderrunCnt_1_OFFS 0x130482992#define QIB_7322_TxUnderrunCnt_1_DEF 0x00000000000000002993 2994#define QIB_7322_TxFlowStallCnt_1_OFFS 0x130502995#define QIB_7322_TxFlowStallCnt_1_DEF 0x00000000000000002996 2997#define QIB_7322_TxDroppedPktCnt_1_OFFS 0x130582998#define QIB_7322_TxDroppedPktCnt_1_DEF 0x00000000000000002999 3000#define QIB_7322_RxDroppedPktCnt_1_OFFS 0x130603001#define QIB_7322_RxDroppedPktCnt_1_DEF 0x00000000000000003002 3003#define QIB_7322_RxDataPktCnt_1_OFFS 0x130683004#define QIB_7322_RxDataPktCnt_1_DEF 0x00000000000000003005 3006#define QIB_7322_RxFlowPktCnt_1_OFFS 0x130703007#define QIB_7322_RxFlowPktCnt_1_DEF 0x00000000000000003008 3009#define QIB_7322_RxDwordCnt_1_OFFS 0x130783010#define QIB_7322_RxDwordCnt_1_DEF 0x00000000000000003011 3012#define QIB_7322_RxLenErrCnt_1_OFFS 0x130803013#define QIB_7322_RxLenErrCnt_1_DEF 0x00000000000000003014 3015#define QIB_7322_RxMaxMinLenErrCnt_1_OFFS 0x130883016#define QIB_7322_RxMaxMinLenErrCnt_1_DEF 0x00000000000000003017 3018#define QIB_7322_RxICRCErrCnt_1_OFFS 0x130903019#define QIB_7322_RxICRCErrCnt_1_DEF 0x00000000000000003020 3021#define QIB_7322_RxVCRCErrCnt_1_OFFS 0x130983022#define QIB_7322_RxVCRCErrCnt_1_DEF 0x00000000000000003023 3024#define QIB_7322_RxFlowCtrlViolCnt_1_OFFS 0x130A03025#define QIB_7322_RxFlowCtrlViolCnt_1_DEF 0x00000000000000003026 3027#define QIB_7322_RxVersionErrCnt_1_OFFS 0x130A83028#define QIB_7322_RxVersionErrCnt_1_DEF 0x00000000000000003029 3030#define QIB_7322_RxLinkMalformCnt_1_OFFS 0x130B03031#define QIB_7322_RxLinkMalformCnt_1_DEF 0x00000000000000003032 3033#define QIB_7322_RxEBPCnt_1_OFFS 0x130B83034#define QIB_7322_RxEBPCnt_1_DEF 0x00000000000000003035 3036#define QIB_7322_RxLPCRCErrCnt_1_OFFS 0x130C03037#define QIB_7322_RxLPCRCErrCnt_1_DEF 0x00000000000000003038 3039#define QIB_7322_RxBufOvflCnt_1_OFFS 0x130C83040#define QIB_7322_RxBufOvflCnt_1_DEF 0x00000000000000003041 3042#define QIB_7322_RxLenTruncateCnt_1_OFFS 0x130D03043#define QIB_7322_RxLenTruncateCnt_1_DEF 0x00000000000000003044 3045#define QIB_7322_RxPKeyMismatchCnt_1_OFFS 0x130E03046#define QIB_7322_RxPKeyMismatchCnt_1_DEF 0x00000000000000003047 3048#define QIB_7322_IBLinkDownedCnt_1_OFFS 0x131803049#define QIB_7322_IBLinkDownedCnt_1_DEF 0x00000000000000003050 3051#define QIB_7322_IBSymbolErrCnt_1_OFFS 0x131883052#define QIB_7322_IBSymbolErrCnt_1_DEF 0x00000000000000003053 3054#define QIB_7322_IBStatusChangeCnt_1_OFFS 0x131903055#define QIB_7322_IBStatusChangeCnt_1_DEF 0x00000000000000003056 3057#define QIB_7322_IBLinkErrRecoveryCnt_1_OFFS 0x131983058#define QIB_7322_IBLinkErrRecoveryCnt_1_DEF 0x00000000000000003059 3060#define QIB_7322_ExcessBufferOvflCnt_1_OFFS 0x131A83061#define QIB_7322_ExcessBufferOvflCnt_1_DEF 0x00000000000000003062 3063#define QIB_7322_LocalLinkIntegrityErrCnt_1_OFFS 0x131B03064#define QIB_7322_LocalLinkIntegrityErrCnt_1_DEF 0x00000000000000003065 3066#define QIB_7322_RxVlErrCnt_1_OFFS 0x131B83067#define QIB_7322_RxVlErrCnt_1_DEF 0x00000000000000003068 3069#define QIB_7322_RxDlidFltrCnt_1_OFFS 0x131C03070#define QIB_7322_RxDlidFltrCnt_1_DEF 0x00000000000000003071 3072#define QIB_7322_RxVL15DroppedPktCnt_1_OFFS 0x131C83073#define QIB_7322_RxVL15DroppedPktCnt_1_DEF 0x00000000000000003074 3075#define QIB_7322_RxOtherLocalPhyErrCnt_1_OFFS 0x131D03076#define QIB_7322_RxOtherLocalPhyErrCnt_1_DEF 0x00000000000000003077 3078#define QIB_7322_RxQPInvalidContextCnt_1_OFFS 0x131D83079#define QIB_7322_RxQPInvalidContextCnt_1_DEF 0x00000000000000003080 3081#define QIB_7322_TxHeadersErrCnt_1_OFFS 0x131F83082#define QIB_7322_TxHeadersErrCnt_1_DEF 0x00000000000000003083 3084#define QIB_7322_PSRcvDataCount_1_OFFS 0x132183085#define QIB_7322_PSRcvDataCount_1_DEF 0x00000000000000003086 3087#define QIB_7322_PSRcvPktsCount_1_OFFS 0x132203088#define QIB_7322_PSRcvPktsCount_1_DEF 0x00000000000000003089 3090#define QIB_7322_PSXmitDataCount_1_OFFS 0x132283091#define QIB_7322_PSXmitDataCount_1_DEF 0x00000000000000003092 3093#define QIB_7322_PSXmitPktsCount_1_OFFS 0x132303094#define QIB_7322_PSXmitPktsCount_1_DEF 0x00000000000000003095 3096#define QIB_7322_PSXmitWaitCount_1_OFFS 0x132383097#define QIB_7322_PSXmitWaitCount_1_DEF 0x00000000000000003098 3099#define QIB_7322_RcvEgrArray_OFFS 0x140003100#define QIB_7322_RcvEgrArray_DEF 0x00000000000000003101#define QIB_7322_RcvEgrArray_RT_BufSize_LSB 0x253102#define QIB_7322_RcvEgrArray_RT_BufSize_MSB 0x273103#define QIB_7322_RcvEgrArray_RT_BufSize_RMASK 0x73104#define QIB_7322_RcvEgrArray_RT_Addr_LSB 0x03105#define QIB_7322_RcvEgrArray_RT_Addr_MSB 0x243106#define QIB_7322_RcvEgrArray_RT_Addr_RMASK 0x1FFFFFFFFF3107 3108#define QIB_7322_RcvTIDArray0_OFFS 0x500003109#define QIB_7322_RcvTIDArray0_DEF 0x00000000000000003110#define QIB_7322_RcvTIDArray0_RT_BufSize_LSB 0x253111#define QIB_7322_RcvTIDArray0_RT_BufSize_MSB 0x273112#define QIB_7322_RcvTIDArray0_RT_BufSize_RMASK 0x73113#define QIB_7322_RcvTIDArray0_RT_Addr_LSB 0x03114#define QIB_7322_RcvTIDArray0_RT_Addr_MSB 0x243115#define QIB_7322_RcvTIDArray0_RT_Addr_RMASK 0x1FFFFFFFFF3116 3117#define QIB_7322_IBSD_DDS_MAP_TABLE_0_OFFS 0xD00003118#define QIB_7322_IBSD_DDS_MAP_TABLE_0_DEF 0x00000000000000003119 3120#define QIB_7322_RcvHdrTail0_OFFS 0x2000003121#define QIB_7322_RcvHdrTail0_DEF 0x00000000000000003122 3123#define QIB_7322_RcvHdrHead0_OFFS 0x2000083124#define QIB_7322_RcvHdrHead0_DEF 0x00000000000000003125#define QIB_7322_RcvHdrHead0_counter_LSB 0x203126#define QIB_7322_RcvHdrHead0_counter_MSB 0x2F3127#define QIB_7322_RcvHdrHead0_counter_RMASK 0xFFFF3128#define QIB_7322_RcvHdrHead0_RcvHeadPointer_LSB 0x03129#define QIB_7322_RcvHdrHead0_RcvHeadPointer_MSB 0x1F3130#define QIB_7322_RcvHdrHead0_RcvHeadPointer_RMASK 0xFFFFFFFF3131 3132#define QIB_7322_RcvEgrIndexTail0_OFFS 0x2000103133#define QIB_7322_RcvEgrIndexTail0_DEF 0x00000000000000003134 3135#define QIB_7322_RcvEgrIndexHead0_OFFS 0x2000183136#define QIB_7322_RcvEgrIndexHead0_DEF 0x00000000000000003137 3138#define QIB_7322_RcvTIDFlowTable0_OFFS 0x2010003139#define QIB_7322_RcvTIDFlowTable0_DEF 0x00000000000000003140#define QIB_7322_RcvTIDFlowTable0_GenMismatch_LSB 0x1C3141#define QIB_7322_RcvTIDFlowTable0_GenMismatch_MSB 0x1C3142#define QIB_7322_RcvTIDFlowTable0_GenMismatch_RMASK 0x13143#define QIB_7322_RcvTIDFlowTable0_SeqMismatch_LSB 0x1B3144#define QIB_7322_RcvTIDFlowTable0_SeqMismatch_MSB 0x1B3145#define QIB_7322_RcvTIDFlowTable0_SeqMismatch_RMASK 0x13146#define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_LSB 0x163147#define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_MSB 0x163148#define QIB_7322_RcvTIDFlowTable0_KeepOnGenErr_RMASK 0x13149#define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_LSB 0x153150#define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_MSB 0x153151#define QIB_7322_RcvTIDFlowTable0_KeepAfterSeqErr_RMASK 0x13152#define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_LSB 0x143153#define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_MSB 0x143154#define QIB_7322_RcvTIDFlowTable0_HdrSuppEnabled_RMASK 0x13155#define QIB_7322_RcvTIDFlowTable0_FlowValid_LSB 0x133156#define QIB_7322_RcvTIDFlowTable0_FlowValid_MSB 0x133157#define QIB_7322_RcvTIDFlowTable0_FlowValid_RMASK 0x13158#define QIB_7322_RcvTIDFlowTable0_GenVal_LSB 0xB3159#define QIB_7322_RcvTIDFlowTable0_GenVal_MSB 0x123160#define QIB_7322_RcvTIDFlowTable0_GenVal_RMASK 0xFF3161#define QIB_7322_RcvTIDFlowTable0_SeqNum_LSB 0x03162#define QIB_7322_RcvTIDFlowTable0_SeqNum_MSB 0xA3163#define QIB_7322_RcvTIDFlowTable0_SeqNum_RMASK 0x7FF3164