1237 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * see notice in hfc_multi.c4 */5 6#define DEBUG_HFCMULTI_FIFO 0x000100007#define DEBUG_HFCMULTI_CRC 0x000200008#define DEBUG_HFCMULTI_INIT 0x000400009#define DEBUG_HFCMULTI_PLXSD 0x0008000010#define DEBUG_HFCMULTI_MODE 0x0010000011#define DEBUG_HFCMULTI_MSG 0x0020000012#define DEBUG_HFCMULTI_STATE 0x0040000013#define DEBUG_HFCMULTI_FILL 0x0080000014#define DEBUG_HFCMULTI_SYNC 0x0100000015#define DEBUG_HFCMULTI_DTMF 0x0200000016#define DEBUG_HFCMULTI_LOCK 0x8000000017 18#define PCI_ENA_REGIO 0x0119#define PCI_ENA_MEMIO 0x0220 21#define XHFC_IRQ 4 /* SIU_IRQ2 */22#define XHFC_MEMBASE 0xFE00000023#define XHFC_MEMSIZE 0x0000100024#define XHFC_OFFSET 0x0000100025#define PA_XHFC_A0 0x0020 /* PA10 */26#define PB_XHFC_IRQ1 0x00000100 /* PB23 */27#define PB_XHFC_IRQ2 0x00000200 /* PB22 */28#define PB_XHFC_IRQ3 0x00000400 /* PB21 */29#define PB_XHFC_IRQ4 0x00000800 /* PB20 */30 31/*32 * NOTE: some registers are assigned multiple times due to different modes33 * also registers are assigned differen for HFC-4s/8s and HFC-E134 */35 36/*37 #define MAX_FRAME_SIZE 204838*/39 40struct hfc_chan {41 struct dchannel *dch; /* link if channel is a D-channel */42 struct bchannel *bch; /* link if channel is a B-channel */43 int port; /* the interface port this */44 /* channel is associated with */45 int nt_timer; /* -1 if off, 0 if elapsed, >0 if running */46 int los, ais, slip_tx, slip_rx, rdi; /* current alarms */47 int jitter;48 u_long cfg; /* port configuration */49 int sync; /* sync state (used by E1) */50 u_int protocol; /* current protocol */51 int slot_tx; /* current pcm slot */52 int bank_tx; /* current pcm bank */53 int slot_rx;54 int bank_rx;55 int conf; /* conference setting of TX slot */56 int txpending; /* if there is currently data in */57 /* the FIFO 0=no, 1=yes, 2=splloop */58 int Zfill; /* rx-fifo level on last hfcmulti_tx */59 int rx_off; /* set to turn fifo receive off */60 int coeff_count; /* curren coeff block */61 s32 *coeff; /* memory pointer to 8 coeff blocks */62};63 64 65struct hfcm_hw {66 u_char r_ctrl;67 u_char r_irq_ctrl;68 u_char r_cirm;69 u_char r_ram_sz;70 u_char r_pcm_md0;71 u_char r_irqmsk_misc;72 u_char r_dtmf;73 u_char r_st_sync;74 u_char r_sci_msk;75 u_char r_tx0, r_tx1;76 u_char a_st_ctrl0[8];77 u_char r_bert_wd_md;78 timer_t timer;79};80 81 82/* for each stack these flags are used (cfg) */83#define HFC_CFG_NONCAP_TX 1 /* S/T TX interface has less capacity */84#define HFC_CFG_DIS_ECHANNEL 2 /* disable E-channel processing */85#define HFC_CFG_REG_ECHANNEL 3 /* register E-channel */86#define HFC_CFG_OPTICAL 4 /* the E1 interface is optical */87#define HFC_CFG_REPORT_LOS 5 /* the card should report loss of signal */88#define HFC_CFG_REPORT_AIS 6 /* the card should report alarm ind. sign. */89#define HFC_CFG_REPORT_SLIP 7 /* the card should report bit slips */90#define HFC_CFG_REPORT_RDI 8 /* the card should report remote alarm */91#define HFC_CFG_DTMF 9 /* enable DTMF-detection */92#define HFC_CFG_CRC4 10 /* disable CRC-4 Multiframe mode, */93/* use double frame instead. */94 95#define HFC_TYPE_E1 1 /* controller is HFC-E1 */96#define HFC_TYPE_4S 4 /* controller is HFC-4S */97#define HFC_TYPE_8S 8 /* controller is HFC-8S */98#define HFC_TYPE_XHFC 5 /* controller is XHFC */99 100#define HFC_CHIP_EXRAM_128 0 /* external ram 128k */101#define HFC_CHIP_EXRAM_512 1 /* external ram 256k */102#define HFC_CHIP_REVISION0 2 /* old fifo handling */103#define HFC_CHIP_PCM_SLAVE 3 /* PCM is slave */104#define HFC_CHIP_PCM_MASTER 4 /* PCM is master */105#define HFC_CHIP_RX_SYNC 5 /* disable pll sync for pcm */106#define HFC_CHIP_DTMF 6 /* DTMF decoding is enabled */107#define HFC_CHIP_CONF 7 /* conference handling is enabled */108#define HFC_CHIP_ULAW 8 /* ULAW mode */109#define HFC_CHIP_CLOCK2 9 /* double clock mode */110#define HFC_CHIP_E1CLOCK_GET 10 /* always get clock from E1 interface */111#define HFC_CHIP_E1CLOCK_PUT 11 /* always put clock from E1 interface */112#define HFC_CHIP_WATCHDOG 12 /* whether we should send signals */113/* to the watchdog */114#define HFC_CHIP_B410P 13 /* whether we have a b410p with echocan in */115/* hw */116#define HFC_CHIP_PLXSD 14 /* whether we have a Speech-Design PLX */117#define HFC_CHIP_EMBSD 15 /* whether we have a SD Embedded board */118 119#define HFC_IO_MODE_PCIMEM 0x00 /* normal memory mapped IO */120#define HFC_IO_MODE_REGIO 0x01 /* PCI io access */121#define HFC_IO_MODE_PLXSD 0x02 /* access HFC via PLX9030 */122#define HFC_IO_MODE_EMBSD 0x03 /* direct access */123 124/* table entry in the PCI devices list */125struct hm_map {126 char *vendor_name;127 char *card_name;128 int type;129 int ports;130 int clock2;131 int leds;132 int opticalsupport;133 int dip_type;134 int io_mode;135 int irq;136};137 138struct hfc_multi {139 struct list_head list;140 struct hm_map *mtyp;141 int id;142 int pcm; /* id of pcm bus */143 int ctype; /* controller type */144 int ports;145 146 u_int irq; /* irq used by card */147 u_int irqcnt;148 struct pci_dev *pci_dev;149 int io_mode; /* selects mode */150#ifdef HFC_REGISTER_DEBUG151 void (*HFC_outb)(struct hfc_multi *hc, u_char reg,152 u_char val, const char *function, int line);153 void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg,154 u_char val, const char *function, int line);155 u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg,156 const char *function, int line);157 u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg,158 const char *function, int line);159 u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg,160 const char *function, int line);161 u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg,162 const char *function, int line);163 void (*HFC_wait)(struct hfc_multi *hc,164 const char *function, int line);165 void (*HFC_wait_nodebug)(struct hfc_multi *hc,166 const char *function, int line);167#else168 void (*HFC_outb)(struct hfc_multi *hc, u_char reg,169 u_char val);170 void (*HFC_outb_nodebug)(struct hfc_multi *hc, u_char reg,171 u_char val);172 u_char (*HFC_inb)(struct hfc_multi *hc, u_char reg);173 u_char (*HFC_inb_nodebug)(struct hfc_multi *hc, u_char reg);174 u_short (*HFC_inw)(struct hfc_multi *hc, u_char reg);175 u_short (*HFC_inw_nodebug)(struct hfc_multi *hc, u_char reg);176 void (*HFC_wait)(struct hfc_multi *hc);177 void (*HFC_wait_nodebug)(struct hfc_multi *hc);178#endif179 void (*read_fifo)(struct hfc_multi *hc, u_char *data,180 int len);181 void (*write_fifo)(struct hfc_multi *hc, u_char *data,182 int len);183 u_long pci_origmembase, plx_origmembase;184 void __iomem *pci_membase; /* PCI memory */185 void __iomem *plx_membase; /* PLX memory */186 u_long xhfc_origmembase;187 u_char *xhfc_membase;188 u_long *xhfc_memaddr, *xhfc_memdata;189#ifdef CONFIG_MISDN_HFCMULTI_8xx190 struct immap *immap;191#endif192 u_long pb_irqmsk; /* Portbit mask to check the IRQ line */193 u_long pci_iobase; /* PCI IO */194 struct hfcm_hw hw; /* remember data of write-only-registers */195 196 u_long chip; /* chip configuration */197 int masterclk; /* port that provides master clock -1=off */198 unsigned char silence;/* silence byte */199 unsigned char silence_data[128];/* silence block */200 int dtmf; /* flag that dtmf is currently in process */201 int Flen; /* F-buffer size */202 int Zlen; /* Z-buffer size (must be int for calculation)*/203 int max_trans; /* maximum transparent fifo fill */204 int Zmin; /* Z-buffer offset */205 int DTMFbase; /* base address of DTMF coefficients */206 207 u_int slots; /* number of PCM slots */208 u_int leds; /* type of leds */209 u_long ledstate; /* save last state of leds */210 int opticalsupport; /* has the e1 board */211 /* an optical Interface */212 213 u_int bmask[32]; /* bitmask of bchannels for port */214 u_char dnum[32]; /* array of used dchannel numbers for port */215 u_char created[32]; /* what port is created */216 u_int activity_tx; /* if there is data TX / RX */217 u_int activity_rx; /* bitmask according to port number */218 /* (will be cleared after */219 /* showing led-states) */220 u_int flash[8]; /* counter for flashing 8 leds on activity */221 222 u_long wdcount; /* every 500 ms we need to */223 /* send the watchdog a signal */224 u_char wdbyte; /* watchdog toggle byte */225 int e1_state; /* keep track of last state */226 int e1_getclock; /* if sync is retrieved from interface */227 int syncronized; /* keep track of existing sync interface */228 int e1_resync; /* resync jobs */229 230 spinlock_t lock; /* the lock */231 232 struct mISDNclock *iclock; /* isdn clock support */233 int iclock_on;234 235 /*236 * the channel index is counted from 0, regardless where the channel237 * is located on the hfc-channel.238 * the bch->channel is equvalent to the hfc-channel239 */240 struct hfc_chan chan[32];241 signed char slot_owner[256]; /* owner channel of slot */242};243 244/* PLX GPIOs */245#define PLX_GPIO4_DIR_BIT 13246#define PLX_GPIO4_BIT 14247#define PLX_GPIO5_DIR_BIT 16248#define PLX_GPIO5_BIT 17249#define PLX_GPIO6_DIR_BIT 19250#define PLX_GPIO6_BIT 20251#define PLX_GPIO7_DIR_BIT 22252#define PLX_GPIO7_BIT 23253#define PLX_GPIO8_DIR_BIT 25254#define PLX_GPIO8_BIT 26255 256#define PLX_GPIO4 (1 << PLX_GPIO4_BIT)257#define PLX_GPIO5 (1 << PLX_GPIO5_BIT)258#define PLX_GPIO6 (1 << PLX_GPIO6_BIT)259#define PLX_GPIO7 (1 << PLX_GPIO7_BIT)260#define PLX_GPIO8 (1 << PLX_GPIO8_BIT)261 262#define PLX_GPIO4_DIR (1 << PLX_GPIO4_DIR_BIT)263#define PLX_GPIO5_DIR (1 << PLX_GPIO5_DIR_BIT)264#define PLX_GPIO6_DIR (1 << PLX_GPIO6_DIR_BIT)265#define PLX_GPIO7_DIR (1 << PLX_GPIO7_DIR_BIT)266#define PLX_GPIO8_DIR (1 << PLX_GPIO8_DIR_BIT)267 268#define PLX_TERM_ON PLX_GPIO7269#define PLX_SLAVE_EN_N PLX_GPIO5270#define PLX_MASTER_EN PLX_GPIO6271#define PLX_SYNC_O_EN PLX_GPIO4272#define PLX_DSP_RES_N PLX_GPIO8273/* GPIO4..8 Enable & Set to OUT, SLAVE_EN_N = 1 */274#define PLX_GPIOC_INIT (PLX_GPIO4_DIR | PLX_GPIO5_DIR | PLX_GPIO6_DIR \275 | PLX_GPIO7_DIR | PLX_GPIO8_DIR | PLX_SLAVE_EN_N)276 277/* PLX Interrupt Control/STATUS */278#define PLX_INTCSR_LINTI1_ENABLE 0x01279#define PLX_INTCSR_LINTI1_STATUS 0x04280#define PLX_INTCSR_LINTI2_ENABLE 0x08281#define PLX_INTCSR_LINTI2_STATUS 0x20282#define PLX_INTCSR_PCIINT_ENABLE 0x40283 284/* PLX Registers */285#define PLX_INTCSR 0x4c286#define PLX_CNTRL 0x50287#define PLX_GPIOC 0x54288 289 290/*291 * REGISTER SETTING FOR HFC-4S/8S AND HFC-E1292 */293 294/* write only registers */295#define R_CIRM 0x00296#define R_CTRL 0x01297#define R_BRG_PCM_CFG 0x02298#define R_RAM_ADDR0 0x08299#define R_RAM_ADDR1 0x09300#define R_RAM_ADDR2 0x0A301#define R_FIRST_FIFO 0x0B302#define R_RAM_SZ 0x0C303#define R_FIFO_MD 0x0D304#define R_INC_RES_FIFO 0x0E305#define R_FSM_IDX 0x0F306#define R_FIFO 0x0F307#define R_SLOT 0x10308#define R_IRQMSK_MISC 0x11309#define R_SCI_MSK 0x12310#define R_IRQ_CTRL 0x13311#define R_PCM_MD0 0x14312#define R_PCM_MD1 0x15313#define R_PCM_MD2 0x15314#define R_SH0H 0x15315#define R_SH1H 0x15316#define R_SH0L 0x15317#define R_SH1L 0x15318#define R_SL_SEL0 0x15319#define R_SL_SEL1 0x15320#define R_SL_SEL2 0x15321#define R_SL_SEL3 0x15322#define R_SL_SEL4 0x15323#define R_SL_SEL5 0x15324#define R_SL_SEL6 0x15325#define R_SL_SEL7 0x15326#define R_ST_SEL 0x16327#define R_ST_SYNC 0x17328#define R_CONF_EN 0x18329#define R_TI_WD 0x1A330#define R_BERT_WD_MD 0x1B331#define R_DTMF 0x1C332#define R_DTMF_N 0x1D333#define R_E1_WR_STA 0x20334#define R_E1_RD_STA 0x20335#define R_LOS0 0x22336#define R_LOS1 0x23337#define R_RX0 0x24338#define R_RX_FR0 0x25339#define R_RX_FR1 0x26340#define R_TX0 0x28341#define R_TX1 0x29342#define R_TX_FR0 0x2C343 344#define R_TX_FR1 0x2D345#define R_TX_FR2 0x2E346#define R_JATT_ATT 0x2F /* undocumented */347#define A_ST_RD_STATE 0x30348#define A_ST_WR_STATE 0x30349#define R_RX_OFF 0x30350#define A_ST_CTRL0 0x31351#define R_SYNC_OUT 0x31352#define A_ST_CTRL1 0x32353#define A_ST_CTRL2 0x33354#define A_ST_SQ_WR 0x34355#define R_TX_OFF 0x34356#define R_SYNC_CTRL 0x35357#define A_ST_CLK_DLY 0x37358#define R_PWM0 0x38359#define R_PWM1 0x39360#define A_ST_B1_TX 0x3C361#define A_ST_B2_TX 0x3D362#define A_ST_D_TX 0x3E363#define R_GPIO_OUT0 0x40364#define R_GPIO_OUT1 0x41365#define R_GPIO_EN0 0x42366#define R_GPIO_EN1 0x43367#define R_GPIO_SEL 0x44368#define R_BRG_CTRL 0x45369#define R_PWM_MD 0x46370#define R_BRG_MD 0x47371#define R_BRG_TIM0 0x48372#define R_BRG_TIM1 0x49373#define R_BRG_TIM2 0x4A374#define R_BRG_TIM3 0x4B375#define R_BRG_TIM_SEL01 0x4C376#define R_BRG_TIM_SEL23 0x4D377#define R_BRG_TIM_SEL45 0x4E378#define R_BRG_TIM_SEL67 0x4F379#define A_SL_CFG 0xD0380#define A_CONF 0xD1381#define A_CH_MSK 0xF4382#define A_CON_HDLC 0xFA383#define A_SUBCH_CFG 0xFB384#define A_CHANNEL 0xFC385#define A_FIFO_SEQ 0xFD386#define A_IRQ_MSK 0xFF387 388/* read only registers */389#define A_Z12 0x04390#define A_Z1L 0x04391#define A_Z1 0x04392#define A_Z1H 0x05393#define A_Z2L 0x06394#define A_Z2 0x06395#define A_Z2H 0x07396#define A_F1 0x0C397#define A_F12 0x0C398#define A_F2 0x0D399#define R_IRQ_OVIEW 0x10400#define R_IRQ_MISC 0x11401#define R_IRQ_STATECH 0x12402#define R_CONF_OFLOW 0x14403#define R_RAM_USE 0x15404#define R_CHIP_ID 0x16405#define R_BERT_STA 0x17406#define R_F0_CNTL 0x18407#define R_F0_CNTH 0x19408#define R_BERT_EC 0x1A409#define R_BERT_ECL 0x1A410#define R_BERT_ECH 0x1B411#define R_STATUS 0x1C412#define R_CHIP_RV 0x1F413#define R_STATE 0x20414#define R_SYNC_STA 0x24415#define R_RX_SL0_0 0x25416#define R_RX_SL0_1 0x26417#define R_RX_SL0_2 0x27418#define R_JATT_DIR 0x2b /* undocumented */419#define R_SLIP 0x2c420#define A_ST_RD_STA 0x30421#define R_FAS_EC 0x30422#define R_FAS_ECL 0x30423#define R_FAS_ECH 0x31424#define R_VIO_EC 0x32425#define R_VIO_ECL 0x32426#define R_VIO_ECH 0x33427#define A_ST_SQ_RD 0x34428#define R_CRC_EC 0x34429#define R_CRC_ECL 0x34430#define R_CRC_ECH 0x35431#define R_E_EC 0x36432#define R_E_ECL 0x36433#define R_E_ECH 0x37434#define R_SA6_SA13_EC 0x38435#define R_SA6_SA13_ECL 0x38436#define R_SA6_SA13_ECH 0x39437#define R_SA6_SA23_EC 0x3A438#define R_SA6_SA23_ECL 0x3A439#define R_SA6_SA23_ECH 0x3B440#define A_ST_B1_RX 0x3C441#define A_ST_B2_RX 0x3D442#define A_ST_D_RX 0x3E443#define A_ST_E_RX 0x3F444#define R_GPIO_IN0 0x40445#define R_GPIO_IN1 0x41446#define R_GPI_IN0 0x44447#define R_GPI_IN1 0x45448#define R_GPI_IN2 0x46449#define R_GPI_IN3 0x47450#define R_INT_DATA 0x88451#define R_IRQ_FIFO_BL0 0xC8452#define R_IRQ_FIFO_BL1 0xC9453#define R_IRQ_FIFO_BL2 0xCA454#define R_IRQ_FIFO_BL3 0xCB455#define R_IRQ_FIFO_BL4 0xCC456#define R_IRQ_FIFO_BL5 0xCD457#define R_IRQ_FIFO_BL6 0xCE458#define R_IRQ_FIFO_BL7 0xCF459 460/* read and write registers */461#define A_FIFO_DATA0 0x80462#define A_FIFO_DATA1 0x80463#define A_FIFO_DATA2 0x80464#define A_FIFO_DATA0_NOINC 0x84465#define A_FIFO_DATA1_NOINC 0x84466#define A_FIFO_DATA2_NOINC 0x84467#define R_RAM_DATA 0xC0468 469 470/*471 * BIT SETTING FOR HFC-4S/8S AND HFC-E1472 */473 474/* chapter 2: universal bus interface */475/* R_CIRM */476#define V_IRQ_SEL 0x01477#define V_SRES 0x08478#define V_HFCRES 0x10479#define V_PCMRES 0x20480#define V_STRES 0x40481#define V_ETRES 0x40482#define V_RLD_EPR 0x80483/* R_CTRL */484#define V_FIFO_LPRIO 0x02485#define V_SLOW_RD 0x04486#define V_EXT_RAM 0x08487#define V_CLK_OFF 0x20488#define V_ST_CLK 0x40489/* R_RAM_ADDR0 */490#define V_RAM_ADDR2 0x01491#define V_ADDR_RES 0x40492#define V_ADDR_INC 0x80493/* R_RAM_SZ */494#define V_RAM_SZ 0x01495#define V_PWM0_16KHZ 0x10496#define V_PWM1_16KHZ 0x20497#define V_FZ_MD 0x80498/* R_CHIP_ID */499#define V_PNP_IRQ 0x01500#define V_CHIP_ID 0x10501 502/* chapter 3: data flow */503/* R_FIRST_FIFO */504#define V_FIRST_FIRO_DIR 0x01505#define V_FIRST_FIFO_NUM 0x02506/* R_FIFO_MD */507#define V_FIFO_MD 0x01508#define V_CSM_MD 0x04509#define V_FSM_MD 0x08510#define V_FIFO_SZ 0x10511/* R_FIFO */512#define V_FIFO_DIR 0x01513#define V_FIFO_NUM 0x02514#define V_REV 0x80515/* R_SLOT */516#define V_SL_DIR 0x01517#define V_SL_NUM 0x02518/* A_SL_CFG */519#define V_CH_DIR 0x01520#define V_CH_SEL 0x02521#define V_ROUTING 0x40522/* A_CON_HDLC */523#define V_IFF 0x01524#define V_HDLC_TRP 0x02525#define V_TRP_IRQ 0x04526#define V_DATA_FLOW 0x20527/* A_SUBCH_CFG */528#define V_BIT_CNT 0x01529#define V_START_BIT 0x08530#define V_LOOP_FIFO 0x40531#define V_INV_DATA 0x80532/* A_CHANNEL */533#define V_CH_DIR0 0x01534#define V_CH_NUM0 0x02535/* A_FIFO_SEQ */536#define V_NEXT_FIFO_DIR 0x01537#define V_NEXT_FIFO_NUM 0x02538#define V_SEQ_END 0x40539 540/* chapter 4: FIFO handling and HDLC controller */541/* R_INC_RES_FIFO */542#define V_INC_F 0x01543#define V_RES_F 0x02544#define V_RES_LOST 0x04545 546/* chapter 5: S/T interface */547/* R_SCI_MSK */548#define V_SCI_MSK_ST0 0x01549#define V_SCI_MSK_ST1 0x02550#define V_SCI_MSK_ST2 0x04551#define V_SCI_MSK_ST3 0x08552#define V_SCI_MSK_ST4 0x10553#define V_SCI_MSK_ST5 0x20554#define V_SCI_MSK_ST6 0x40555#define V_SCI_MSK_ST7 0x80556/* R_ST_SEL */557#define V_ST_SEL 0x01558#define V_MULT_ST 0x08559/* R_ST_SYNC */560#define V_SYNC_SEL 0x01561#define V_AUTO_SYNC 0x08562/* A_ST_WR_STA */563#define V_ST_SET_STA 0x01564#define V_ST_LD_STA 0x10565#define V_ST_ACT 0x20566#define V_SET_G2_G3 0x80567/* A_ST_CTRL0 */568#define V_B1_EN 0x01569#define V_B2_EN 0x02570#define V_ST_MD 0x04571#define V_D_PRIO 0x08572#define V_SQ_EN 0x10573#define V_96KHZ 0x20574#define V_TX_LI 0x40575#define V_ST_STOP 0x80576/* A_ST_CTRL1 */577#define V_G2_G3_EN 0x01578#define V_D_HI 0x04579#define V_E_IGNO 0x08580#define V_E_LO 0x10581#define V_B12_SWAP 0x80582/* A_ST_CTRL2 */583#define V_B1_RX_EN 0x01584#define V_B2_RX_EN 0x02585#define V_ST_TRIS 0x40586/* A_ST_CLK_DLY */587#define V_ST_CK_DLY 0x01588#define V_ST_SMPL 0x10589/* A_ST_D_TX */590#define V_ST_D_TX 0x40591/* R_IRQ_STATECH */592#define V_SCI_ST0 0x01593#define V_SCI_ST1 0x02594#define V_SCI_ST2 0x04595#define V_SCI_ST3 0x08596#define V_SCI_ST4 0x10597#define V_SCI_ST5 0x20598#define V_SCI_ST6 0x40599#define V_SCI_ST7 0x80600/* A_ST_RD_STA */601#define V_ST_STA 0x01602#define V_FR_SYNC_ST 0x10603#define V_TI2_EXP 0x20604#define V_INFO0 0x40605#define V_G2_G3 0x80606/* A_ST_SQ_RD */607#define V_ST_SQ 0x01608#define V_MF_RX_RDY 0x10609#define V_MF_TX_RDY 0x80610/* A_ST_D_RX */611#define V_ST_D_RX 0x40612/* A_ST_E_RX */613#define V_ST_E_RX 0x40614 615/* chapter 5: E1 interface */616/* R_E1_WR_STA */617/* R_E1_RD_STA */618#define V_E1_SET_STA 0x01619#define V_E1_LD_STA 0x10620/* R_RX0 */621#define V_RX_CODE 0x01622#define V_RX_FBAUD 0x04623#define V_RX_CMI 0x08624#define V_RX_INV_CMI 0x10625#define V_RX_INV_CLK 0x20626#define V_RX_INV_DATA 0x40627#define V_AIS_ITU 0x80628/* R_RX_FR0 */629#define V_NO_INSYNC 0x01630#define V_AUTO_RESYNC 0x02631#define V_AUTO_RECO 0x04632#define V_SWORD_COND 0x08633#define V_SYNC_LOSS 0x10634#define V_XCRC_SYNC 0x20635#define V_MF_RESYNC 0x40636#define V_RESYNC 0x80637/* R_RX_FR1 */638#define V_RX_MF 0x01639#define V_RX_MF_SYNC 0x02640#define V_RX_SL0_RAM 0x04641#define V_ERR_SIM 0x20642#define V_RES_NMF 0x40643/* R_TX0 */644#define V_TX_CODE 0x01645#define V_TX_FBAUD 0x04646#define V_TX_CMI_CODE 0x08647#define V_TX_INV_CMI_CODE 0x10648#define V_TX_INV_CLK 0x20649#define V_TX_INV_DATA 0x40650#define V_OUT_EN 0x80651/* R_TX1 */652#define V_INV_CLK 0x01653#define V_EXCHG_DATA_LI 0x02654#define V_AIS_OUT 0x04655#define V_ATX 0x20656#define V_NTRI 0x40657#define V_AUTO_ERR_RES 0x80658/* R_TX_FR0 */659#define V_TRP_FAS 0x01660#define V_TRP_NFAS 0x02661#define V_TRP_RAL 0x04662#define V_TRP_SA 0x08663/* R_TX_FR1 */664#define V_TX_FAS 0x01665#define V_TX_NFAS 0x02666#define V_TX_RAL 0x04667#define V_TX_SA 0x08668/* R_TX_FR2 */669#define V_TX_MF 0x01670#define V_TRP_SL0 0x02671#define V_TX_SL0_RAM 0x04672#define V_TX_E 0x10673#define V_NEG_E 0x20674#define V_XS12_ON 0x40675#define V_XS15_ON 0x80676/* R_RX_OFF */677#define V_RX_SZ 0x01678#define V_RX_INIT 0x04679/* R_SYNC_OUT */680#define V_SYNC_E1_RX 0x01681#define V_IPATS0 0x20682#define V_IPATS1 0x40683#define V_IPATS2 0x80684/* R_TX_OFF */685#define V_TX_SZ 0x01686#define V_TX_INIT 0x04687/* R_SYNC_CTRL */688#define V_EXT_CLK_SYNC 0x01689#define V_SYNC_OFFS 0x02690#define V_PCM_SYNC 0x04691#define V_NEG_CLK 0x08692#define V_HCLK 0x10693/*694 #define V_JATT_AUTO_DEL 0x20695 #define V_JATT_AUTO 0x40696*/697#define V_JATT_OFF 0x80698/* R_STATE */699#define V_E1_STA 0x01700#define V_ALT_FR_RX 0x40701#define V_ALT_FR_TX 0x80702/* R_SYNC_STA */703#define V_RX_STA 0x01704#define V_FR_SYNC_E1 0x04705#define V_SIG_LOS 0x08706#define V_MFA_STA 0x10707#define V_AIS 0x40708#define V_NO_MF_SYNC 0x80709/* R_RX_SL0_0 */710#define V_SI_FAS 0x01711#define V_SI_NFAS 0x02712#define V_A 0x04713#define V_CRC_OK 0x08714#define V_TX_E1 0x10715#define V_TX_E2 0x20716#define V_RX_E1 0x40717#define V_RX_E2 0x80718/* R_SLIP */719#define V_SLIP_RX 0x01720#define V_FOSLIP_RX 0x08721#define V_SLIP_TX 0x10722#define V_FOSLIP_TX 0x80723 724/* chapter 6: PCM interface */725/* R_PCM_MD0 */726#define V_PCM_MD 0x01727#define V_C4_POL 0x02728#define V_F0_NEG 0x04729#define V_F0_LEN 0x08730#define V_PCM_ADDR 0x10731/* R_SL_SEL0 */732#define V_SL_SEL0 0x01733#define V_SH_SEL0 0x80734/* R_SL_SEL1 */735#define V_SL_SEL1 0x01736#define V_SH_SEL1 0x80737/* R_SL_SEL2 */738#define V_SL_SEL2 0x01739#define V_SH_SEL2 0x80740/* R_SL_SEL3 */741#define V_SL_SEL3 0x01742#define V_SH_SEL3 0x80743/* R_SL_SEL4 */744#define V_SL_SEL4 0x01745#define V_SH_SEL4 0x80746/* R_SL_SEL5 */747#define V_SL_SEL5 0x01748#define V_SH_SEL5 0x80749/* R_SL_SEL6 */750#define V_SL_SEL6 0x01751#define V_SH_SEL6 0x80752/* R_SL_SEL7 */753#define V_SL_SEL7 0x01754#define V_SH_SEL7 0x80755/* R_PCM_MD1 */756#define V_ODEC_CON 0x01757#define V_PLL_ADJ 0x04758#define V_PCM_DR 0x10759#define V_PCM_LOOP 0x40760/* R_PCM_MD2 */761#define V_SYNC_PLL 0x02762#define V_SYNC_SRC 0x04763#define V_SYNC_OUT 0x08764#define V_ICR_FR_TIME 0x40765#define V_EN_PLL 0x80766 767/* chapter 7: pulse width modulation */768/* R_PWM_MD */769#define V_EXT_IRQ_EN 0x08770#define V_PWM0_MD 0x10771#define V_PWM1_MD 0x40772 773/* chapter 8: multiparty audio conferences */774/* R_CONF_EN */775#define V_CONF_EN 0x01776#define V_ULAW 0x80777/* A_CONF */778#define V_CONF_NUM 0x01779#define V_NOISE_SUPPR 0x08780#define V_ATT_LEV 0x20781#define V_CONF_SL 0x80782/* R_CONF_OFLOW */783#define V_CONF_OFLOW0 0x01784#define V_CONF_OFLOW1 0x02785#define V_CONF_OFLOW2 0x04786#define V_CONF_OFLOW3 0x08787#define V_CONF_OFLOW4 0x10788#define V_CONF_OFLOW5 0x20789#define V_CONF_OFLOW6 0x40790#define V_CONF_OFLOW7 0x80791 792/* chapter 9: DTMF contoller */793/* R_DTMF0 */794#define V_DTMF_EN 0x01795#define V_HARM_SEL 0x02796#define V_DTMF_RX_CH 0x04797#define V_DTMF_STOP 0x08798#define V_CHBL_SEL 0x10799#define V_RST_DTMF 0x40800#define V_ULAW_SEL 0x80801 802/* chapter 10: BERT */803/* R_BERT_WD_MD */804#define V_PAT_SEQ 0x01805#define V_BERT_ERR 0x08806#define V_AUTO_WD_RES 0x20807#define V_WD_RES 0x80808/* R_BERT_STA */809#define V_BERT_SYNC_SRC 0x01810#define V_BERT_SYNC 0x10811#define V_BERT_INV_DATA 0x20812 813/* chapter 11: auxiliary interface */814/* R_BRG_PCM_CFG */815#define V_BRG_EN 0x01816#define V_BRG_MD 0x02817#define V_PCM_CLK 0x20818#define V_ADDR_WRDLY 0x40819/* R_BRG_CTRL */820#define V_BRG_CS 0x01821#define V_BRG_ADDR 0x08822#define V_BRG_CS_SRC 0x80823/* R_BRG_MD */824#define V_BRG_MD0 0x01825#define V_BRG_MD1 0x02826#define V_BRG_MD2 0x04827#define V_BRG_MD3 0x08828#define V_BRG_MD4 0x10829#define V_BRG_MD5 0x20830#define V_BRG_MD6 0x40831#define V_BRG_MD7 0x80832/* R_BRG_TIM0 */833#define V_BRG_TIM0_IDLE 0x01834#define V_BRG_TIM0_CLK 0x10835/* R_BRG_TIM1 */836#define V_BRG_TIM1_IDLE 0x01837#define V_BRG_TIM1_CLK 0x10838/* R_BRG_TIM2 */839#define V_BRG_TIM2_IDLE 0x01840#define V_BRG_TIM2_CLK 0x10841/* R_BRG_TIM3 */842#define V_BRG_TIM3_IDLE 0x01843#define V_BRG_TIM3_CLK 0x10844/* R_BRG_TIM_SEL01 */845#define V_BRG_WR_SEL0 0x01846#define V_BRG_RD_SEL0 0x04847#define V_BRG_WR_SEL1 0x10848#define V_BRG_RD_SEL1 0x40849/* R_BRG_TIM_SEL23 */850#define V_BRG_WR_SEL2 0x01851#define V_BRG_RD_SEL2 0x04852#define V_BRG_WR_SEL3 0x10853#define V_BRG_RD_SEL3 0x40854/* R_BRG_TIM_SEL45 */855#define V_BRG_WR_SEL4 0x01856#define V_BRG_RD_SEL4 0x04857#define V_BRG_WR_SEL5 0x10858#define V_BRG_RD_SEL5 0x40859/* R_BRG_TIM_SEL67 */860#define V_BRG_WR_SEL6 0x01861#define V_BRG_RD_SEL6 0x04862#define V_BRG_WR_SEL7 0x10863#define V_BRG_RD_SEL7 0x40864 865/* chapter 12: clock, reset, interrupt, timer and watchdog */866/* R_IRQMSK_MISC */867#define V_STA_IRQMSK 0x01868#define V_TI_IRQMSK 0x02869#define V_PROC_IRQMSK 0x04870#define V_DTMF_IRQMSK 0x08871#define V_IRQ1S_MSK 0x10872#define V_SA6_IRQMSK 0x20873#define V_RX_EOMF_MSK 0x40874#define V_TX_EOMF_MSK 0x80875/* R_IRQ_CTRL */876#define V_FIFO_IRQ 0x01877#define V_GLOB_IRQ_EN 0x08878#define V_IRQ_POL 0x10879/* R_TI_WD */880#define V_EV_TS 0x01881#define V_WD_TS 0x10882/* A_IRQ_MSK */883#define V_IRQ 0x01884#define V_BERT_EN 0x02885#define V_MIX_IRQ 0x04886/* R_IRQ_OVIEW */887#define V_IRQ_FIFO_BL0 0x01888#define V_IRQ_FIFO_BL1 0x02889#define V_IRQ_FIFO_BL2 0x04890#define V_IRQ_FIFO_BL3 0x08891#define V_IRQ_FIFO_BL4 0x10892#define V_IRQ_FIFO_BL5 0x20893#define V_IRQ_FIFO_BL6 0x40894#define V_IRQ_FIFO_BL7 0x80895/* R_IRQ_MISC */896#define V_STA_IRQ 0x01897#define V_TI_IRQ 0x02898#define V_IRQ_PROC 0x04899#define V_DTMF_IRQ 0x08900#define V_IRQ1S 0x10901#define V_SA6_IRQ 0x20902#define V_RX_EOMF 0x40903#define V_TX_EOMF 0x80904/* R_STATUS */905#define V_BUSY 0x01906#define V_PROC 0x02907#define V_DTMF_STA 0x04908#define V_LOST_STA 0x08909#define V_SYNC_IN 0x10910#define V_EXT_IRQSTA 0x20911#define V_MISC_IRQSTA 0x40912#define V_FR_IRQSTA 0x80913/* R_IRQ_FIFO_BL0 */914#define V_IRQ_FIFO0_TX 0x01915#define V_IRQ_FIFO0_RX 0x02916#define V_IRQ_FIFO1_TX 0x04917#define V_IRQ_FIFO1_RX 0x08918#define V_IRQ_FIFO2_TX 0x10919#define V_IRQ_FIFO2_RX 0x20920#define V_IRQ_FIFO3_TX 0x40921#define V_IRQ_FIFO3_RX 0x80922/* R_IRQ_FIFO_BL1 */923#define V_IRQ_FIFO4_TX 0x01924#define V_IRQ_FIFO4_RX 0x02925#define V_IRQ_FIFO5_TX 0x04926#define V_IRQ_FIFO5_RX 0x08927#define V_IRQ_FIFO6_TX 0x10928#define V_IRQ_FIFO6_RX 0x20929#define V_IRQ_FIFO7_TX 0x40930#define V_IRQ_FIFO7_RX 0x80931/* R_IRQ_FIFO_BL2 */932#define V_IRQ_FIFO8_TX 0x01933#define V_IRQ_FIFO8_RX 0x02934#define V_IRQ_FIFO9_TX 0x04935#define V_IRQ_FIFO9_RX 0x08936#define V_IRQ_FIFO10_TX 0x10937#define V_IRQ_FIFO10_RX 0x20938#define V_IRQ_FIFO11_TX 0x40939#define V_IRQ_FIFO11_RX 0x80940/* R_IRQ_FIFO_BL3 */941#define V_IRQ_FIFO12_TX 0x01942#define V_IRQ_FIFO12_RX 0x02943#define V_IRQ_FIFO13_TX 0x04944#define V_IRQ_FIFO13_RX 0x08945#define V_IRQ_FIFO14_TX 0x10946#define V_IRQ_FIFO14_RX 0x20947#define V_IRQ_FIFO15_TX 0x40948#define V_IRQ_FIFO15_RX 0x80949/* R_IRQ_FIFO_BL4 */950#define V_IRQ_FIFO16_TX 0x01951#define V_IRQ_FIFO16_RX 0x02952#define V_IRQ_FIFO17_TX 0x04953#define V_IRQ_FIFO17_RX 0x08954#define V_IRQ_FIFO18_TX 0x10955#define V_IRQ_FIFO18_RX 0x20956#define V_IRQ_FIFO19_TX 0x40957#define V_IRQ_FIFO19_RX 0x80958/* R_IRQ_FIFO_BL5 */959#define V_IRQ_FIFO20_TX 0x01960#define V_IRQ_FIFO20_RX 0x02961#define V_IRQ_FIFO21_TX 0x04962#define V_IRQ_FIFO21_RX 0x08963#define V_IRQ_FIFO22_TX 0x10964#define V_IRQ_FIFO22_RX 0x20965#define V_IRQ_FIFO23_TX 0x40966#define V_IRQ_FIFO23_RX 0x80967/* R_IRQ_FIFO_BL6 */968#define V_IRQ_FIFO24_TX 0x01969#define V_IRQ_FIFO24_RX 0x02970#define V_IRQ_FIFO25_TX 0x04971#define V_IRQ_FIFO25_RX 0x08972#define V_IRQ_FIFO26_TX 0x10973#define V_IRQ_FIFO26_RX 0x20974#define V_IRQ_FIFO27_TX 0x40975#define V_IRQ_FIFO27_RX 0x80976/* R_IRQ_FIFO_BL7 */977#define V_IRQ_FIFO28_TX 0x01978#define V_IRQ_FIFO28_RX 0x02979#define V_IRQ_FIFO29_TX 0x04980#define V_IRQ_FIFO29_RX 0x08981#define V_IRQ_FIFO30_TX 0x10982#define V_IRQ_FIFO30_RX 0x20983#define V_IRQ_FIFO31_TX 0x40984#define V_IRQ_FIFO31_RX 0x80985 986/* chapter 13: general purpose I/O pins (GPIO) and input pins (GPI) */987/* R_GPIO_OUT0 */988#define V_GPIO_OUT0 0x01989#define V_GPIO_OUT1 0x02990#define V_GPIO_OUT2 0x04991#define V_GPIO_OUT3 0x08992#define V_GPIO_OUT4 0x10993#define V_GPIO_OUT5 0x20994#define V_GPIO_OUT6 0x40995#define V_GPIO_OUT7 0x80996/* R_GPIO_OUT1 */997#define V_GPIO_OUT8 0x01998#define V_GPIO_OUT9 0x02999#define V_GPIO_OUT10 0x041000#define V_GPIO_OUT11 0x081001#define V_GPIO_OUT12 0x101002#define V_GPIO_OUT13 0x201003#define V_GPIO_OUT14 0x401004#define V_GPIO_OUT15 0x801005/* R_GPIO_EN0 */1006#define V_GPIO_EN0 0x011007#define V_GPIO_EN1 0x021008#define V_GPIO_EN2 0x041009#define V_GPIO_EN3 0x081010#define V_GPIO_EN4 0x101011#define V_GPIO_EN5 0x201012#define V_GPIO_EN6 0x401013#define V_GPIO_EN7 0x801014/* R_GPIO_EN1 */1015#define V_GPIO_EN8 0x011016#define V_GPIO_EN9 0x021017#define V_GPIO_EN10 0x041018#define V_GPIO_EN11 0x081019#define V_GPIO_EN12 0x101020#define V_GPIO_EN13 0x201021#define V_GPIO_EN14 0x401022#define V_GPIO_EN15 0x801023/* R_GPIO_SEL */1024#define V_GPIO_SEL0 0x011025#define V_GPIO_SEL1 0x021026#define V_GPIO_SEL2 0x041027#define V_GPIO_SEL3 0x081028#define V_GPIO_SEL4 0x101029#define V_GPIO_SEL5 0x201030#define V_GPIO_SEL6 0x401031#define V_GPIO_SEL7 0x801032/* R_GPIO_IN0 */1033#define V_GPIO_IN0 0x011034#define V_GPIO_IN1 0x021035#define V_GPIO_IN2 0x041036#define V_GPIO_IN3 0x081037#define V_GPIO_IN4 0x101038#define V_GPIO_IN5 0x201039#define V_GPIO_IN6 0x401040#define V_GPIO_IN7 0x801041/* R_GPIO_IN1 */1042#define V_GPIO_IN8 0x011043#define V_GPIO_IN9 0x021044#define V_GPIO_IN10 0x041045#define V_GPIO_IN11 0x081046#define V_GPIO_IN12 0x101047#define V_GPIO_IN13 0x201048#define V_GPIO_IN14 0x401049#define V_GPIO_IN15 0x801050/* R_GPI_IN0 */1051#define V_GPI_IN0 0x011052#define V_GPI_IN1 0x021053#define V_GPI_IN2 0x041054#define V_GPI_IN3 0x081055#define V_GPI_IN4 0x101056#define V_GPI_IN5 0x201057#define V_GPI_IN6 0x401058#define V_GPI_IN7 0x801059/* R_GPI_IN1 */1060#define V_GPI_IN8 0x011061#define V_GPI_IN9 0x021062#define V_GPI_IN10 0x041063#define V_GPI_IN11 0x081064#define V_GPI_IN12 0x101065#define V_GPI_IN13 0x201066#define V_GPI_IN14 0x401067#define V_GPI_IN15 0x801068/* R_GPI_IN2 */1069#define V_GPI_IN16 0x011070#define V_GPI_IN17 0x021071#define V_GPI_IN18 0x041072#define V_GPI_IN19 0x081073#define V_GPI_IN20 0x101074#define V_GPI_IN21 0x201075#define V_GPI_IN22 0x401076#define V_GPI_IN23 0x801077/* R_GPI_IN3 */1078#define V_GPI_IN24 0x011079#define V_GPI_IN25 0x021080#define V_GPI_IN26 0x041081#define V_GPI_IN27 0x081082#define V_GPI_IN28 0x101083#define V_GPI_IN29 0x201084#define V_GPI_IN30 0x401085#define V_GPI_IN31 0x801086 1087/* map of all registers, used for debugging */1088 1089#ifdef HFC_REGISTER_DEBUG1090struct hfc_register_names {1091 char *name;1092 u_char reg;1093} hfc_register_names[] = {1094 /* write registers */1095 {"R_CIRM", 0x00},1096 {"R_CTRL", 0x01},1097 {"R_BRG_PCM_CFG ", 0x02},1098 {"R_RAM_ADDR0", 0x08},1099 {"R_RAM_ADDR1", 0x09},1100 {"R_RAM_ADDR2", 0x0A},1101 {"R_FIRST_FIFO", 0x0B},1102 {"R_RAM_SZ", 0x0C},1103 {"R_FIFO_MD", 0x0D},1104 {"R_INC_RES_FIFO", 0x0E},1105 {"R_FIFO / R_FSM_IDX", 0x0F},1106 {"R_SLOT", 0x10},1107 {"R_IRQMSK_MISC", 0x11},1108 {"R_SCI_MSK", 0x12},1109 {"R_IRQ_CTRL", 0x13},1110 {"R_PCM_MD0", 0x14},1111 {"R_0x15", 0x15},1112 {"R_ST_SEL", 0x16},1113 {"R_ST_SYNC", 0x17},1114 {"R_CONF_EN", 0x18},1115 {"R_TI_WD", 0x1A},1116 {"R_BERT_WD_MD", 0x1B},1117 {"R_DTMF", 0x1C},1118 {"R_DTMF_N", 0x1D},1119 {"R_E1_XX_STA", 0x20},1120 {"R_LOS0", 0x22},1121 {"R_LOS1", 0x23},1122 {"R_RX0", 0x24},1123 {"R_RX_FR0", 0x25},1124 {"R_RX_FR1", 0x26},1125 {"R_TX0", 0x28},1126 {"R_TX1", 0x29},1127 {"R_TX_FR0", 0x2C},1128 {"R_TX_FR1", 0x2D},1129 {"R_TX_FR2", 0x2E},1130 {"R_JATT_ATT", 0x2F},1131 {"A_ST_xx_STA/R_RX_OFF", 0x30},1132 {"A_ST_CTRL0/R_SYNC_OUT", 0x31},1133 {"A_ST_CTRL1", 0x32},1134 {"A_ST_CTRL2", 0x33},1135 {"A_ST_SQ_WR", 0x34},1136 {"R_TX_OFF", 0x34},1137 {"R_SYNC_CTRL", 0x35},1138 {"A_ST_CLK_DLY", 0x37},1139 {"R_PWM0", 0x38},1140 {"R_PWM1", 0x39},1141 {"A_ST_B1_TX", 0x3C},1142 {"A_ST_B2_TX", 0x3D},1143 {"A_ST_D_TX", 0x3E},1144 {"R_GPIO_OUT0", 0x40},1145 {"R_GPIO_OUT1", 0x41},1146 {"R_GPIO_EN0", 0x42},1147 {"R_GPIO_EN1", 0x43},1148 {"R_GPIO_SEL", 0x44},1149 {"R_BRG_CTRL", 0x45},1150 {"R_PWM_MD", 0x46},1151 {"R_BRG_MD", 0x47},1152 {"R_BRG_TIM0", 0x48},1153 {"R_BRG_TIM1", 0x49},1154 {"R_BRG_TIM2", 0x4A},1155 {"R_BRG_TIM3", 0x4B},1156 {"R_BRG_TIM_SEL01", 0x4C},1157 {"R_BRG_TIM_SEL23", 0x4D},1158 {"R_BRG_TIM_SEL45", 0x4E},1159 {"R_BRG_TIM_SEL67", 0x4F},1160 {"A_FIFO_DATA0-2", 0x80},1161 {"A_FIFO_DATA0-2_NOINC", 0x84},1162 {"R_RAM_DATA", 0xC0},1163 {"A_SL_CFG", 0xD0},1164 {"A_CONF", 0xD1},1165 {"A_CH_MSK", 0xF4},1166 {"A_CON_HDLC", 0xFA},1167 {"A_SUBCH_CFG", 0xFB},1168 {"A_CHANNEL", 0xFC},1169 {"A_FIFO_SEQ", 0xFD},1170 {"A_IRQ_MSK", 0xFF},1171 {NULL, 0},1172 1173 /* read registers */1174 {"A_Z1", 0x04},1175 {"A_Z1H", 0x05},1176 {"A_Z2", 0x06},1177 {"A_Z2H", 0x07},1178 {"A_F1", 0x0C},1179 {"A_F2", 0x0D},1180 {"R_IRQ_OVIEW", 0x10},1181 {"R_IRQ_MISC", 0x11},1182 {"R_IRQ_STATECH", 0x12},1183 {"R_CONF_OFLOW", 0x14},1184 {"R_RAM_USE", 0x15},1185 {"R_CHIP_ID", 0x16},1186 {"R_BERT_STA", 0x17},1187 {"R_F0_CNTL", 0x18},1188 {"R_F0_CNTH", 0x19},1189 {"R_BERT_ECL", 0x1A},1190 {"R_BERT_ECH", 0x1B},1191 {"R_STATUS", 0x1C},1192 {"R_CHIP_RV", 0x1F},1193 {"R_STATE", 0x20},1194 {"R_SYNC_STA", 0x24},1195 {"R_RX_SL0_0", 0x25},1196 {"R_RX_SL0_1", 0x26},1197 {"R_RX_SL0_2", 0x27},1198 {"R_JATT_DIR", 0x2b},1199 {"R_SLIP", 0x2c},1200 {"A_ST_RD_STA", 0x30},1201 {"R_FAS_ECL", 0x30},1202 {"R_FAS_ECH", 0x31},1203 {"R_VIO_ECL", 0x32},1204 {"R_VIO_ECH", 0x33},1205 {"R_CRC_ECL / A_ST_SQ_RD", 0x34},1206 {"R_CRC_ECH", 0x35},1207 {"R_E_ECL", 0x36},1208 {"R_E_ECH", 0x37},1209 {"R_SA6_SA13_ECL", 0x38},1210 {"R_SA6_SA13_ECH", 0x39},1211 {"R_SA6_SA23_ECL", 0x3A},1212 {"R_SA6_SA23_ECH", 0x3B},1213 {"A_ST_B1_RX", 0x3C},1214 {"A_ST_B2_RX", 0x3D},1215 {"A_ST_D_RX", 0x3E},1216 {"A_ST_E_RX", 0x3F},1217 {"R_GPIO_IN0", 0x40},1218 {"R_GPIO_IN1", 0x41},1219 {"R_GPI_IN0", 0x44},1220 {"R_GPI_IN1", 0x45},1221 {"R_GPI_IN2", 0x46},1222 {"R_GPI_IN3", 0x47},1223 {"A_FIFO_DATA0-2", 0x80},1224 {"A_FIFO_DATA0-2_NOINC", 0x84},1225 {"R_INT_DATA", 0x88},1226 {"R_RAM_DATA", 0xC0},1227 {"R_IRQ_FIFO_BL0", 0xC8},1228 {"R_IRQ_FIFO_BL1", 0xC9},1229 {"R_IRQ_FIFO_BL2", 0xCA},1230 {"R_IRQ_FIFO_BL3", 0xCB},1231 {"R_IRQ_FIFO_BL4", 0xCC},1232 {"R_IRQ_FIFO_BL5", 0xCD},1233 {"R_IRQ_FIFO_BL6", 0xCE},1234 {"R_IRQ_FIFO_BL7", 0xCF},1235};1236#endif /* HFC_REGISTER_DEBUG */1237