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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * specific defines for CCD's HFC 2BDS0 PCI chips4 *5 * Author Werner Cornelius (werner@isdn4linux.de)6 *7 * Copyright 1999 by Werner Cornelius (werner@isdn4linux.de)8 */9 10/*11 * thresholds for transparent B-channel mode12 * change mask and threshold simultaneously13 */14#define HFCPCI_BTRANS_THRESHOLD 12815#define HFCPCI_FILLEMPTY 6416#define HFCPCI_BTRANS_THRESMASK 0x0017 18/* defines for PCI config */19#define PCI_ENA_MEMIO 0x0220#define PCI_ENA_MASTER 0x0421 22/* GCI/IOM bus monitor registers */23#define HCFPCI_C_I 0x0824#define HFCPCI_TRxR 0x0C25#define HFCPCI_MON1_D 0x2826#define HFCPCI_MON2_D 0x2C27 28/* GCI/IOM bus timeslot registers */29#define HFCPCI_B1_SSL 0x8030#define HFCPCI_B2_SSL 0x8431#define HFCPCI_AUX1_SSL 0x8832#define HFCPCI_AUX2_SSL 0x8C33#define HFCPCI_B1_RSL 0x9034#define HFCPCI_B2_RSL 0x9435#define HFCPCI_AUX1_RSL 0x9836#define HFCPCI_AUX2_RSL 0x9C37 38/* GCI/IOM bus data registers */39#define HFCPCI_B1_D 0xA040#define HFCPCI_B2_D 0xA441#define HFCPCI_AUX1_D 0xA842#define HFCPCI_AUX2_D 0xAC43 44/* GCI/IOM bus configuration registers */45#define HFCPCI_MST_EMOD 0xB446#define HFCPCI_MST_MODE 0xB847#define HFCPCI_CONNECT 0xBC48 49 50/* Interrupt and status registers */51#define HFCPCI_FIFO_EN 0x4452#define HFCPCI_TRM 0x4853#define HFCPCI_B_MODE 0x4C54#define HFCPCI_CHIP_ID 0x5855#define HFCPCI_CIRM 0x6056#define HFCPCI_CTMT 0x6457#define HFCPCI_INT_M1 0x6858#define HFCPCI_INT_M2 0x6C59#define HFCPCI_INT_S1 0x7860#define HFCPCI_INT_S2 0x7C61#define HFCPCI_STATUS 0x7062 63/* S/T section registers */64#define HFCPCI_STATES 0xC065#define HFCPCI_SCTRL 0xC466#define HFCPCI_SCTRL_E 0xC867#define HFCPCI_SCTRL_R 0xCC68#define HFCPCI_SQ 0xD069#define HFCPCI_CLKDEL 0xDC70#define HFCPCI_B1_REC 0xF071#define HFCPCI_B1_SEND 0xF072#define HFCPCI_B2_REC 0xF473#define HFCPCI_B2_SEND 0xF474#define HFCPCI_D_REC 0xF875#define HFCPCI_D_SEND 0xF876#define HFCPCI_E_REC 0xFC77 78 79/* bits in status register (READ) */80#define HFCPCI_PCI_PROC 0x0281#define HFCPCI_NBUSY 0x0482#define HFCPCI_TIMER_ELAP 0x1083#define HFCPCI_STATINT 0x2084#define HFCPCI_FRAMEINT 0x4085#define HFCPCI_ANYINT 0x8086 87/* bits in CTMT (Write) */88#define HFCPCI_CLTIMER 0x8089#define HFCPCI_TIM3_125 0x0490#define HFCPCI_TIM25 0x1091#define HFCPCI_TIM50 0x1492#define HFCPCI_TIM400 0x1893#define HFCPCI_TIM800 0x1C94#define HFCPCI_AUTO_TIMER 0x2095#define HFCPCI_TRANSB2 0x0296#define HFCPCI_TRANSB1 0x0197 98/* bits in CIRM (Write) */99#define HFCPCI_AUX_MSK 0x07100#define HFCPCI_RESET 0x08101#define HFCPCI_B1_REV 0x40102#define HFCPCI_B2_REV 0x80103 104/* bits in INT_M1 and INT_S1 */105#define HFCPCI_INTS_B1TRANS 0x01106#define HFCPCI_INTS_B2TRANS 0x02107#define HFCPCI_INTS_DTRANS 0x04108#define HFCPCI_INTS_B1REC 0x08109#define HFCPCI_INTS_B2REC 0x10110#define HFCPCI_INTS_DREC 0x20111#define HFCPCI_INTS_L1STATE 0x40112#define HFCPCI_INTS_TIMER 0x80113 114/* bits in INT_M2 */115#define HFCPCI_PROC_TRANS 0x01116#define HFCPCI_GCI_I_CHG 0x02117#define HFCPCI_GCI_MON_REC 0x04118#define HFCPCI_IRQ_ENABLE 0x08119#define HFCPCI_PMESEL 0x80120 121/* bits in STATES */122#define HFCPCI_STATE_MSK 0x0F123#define HFCPCI_LOAD_STATE 0x10124#define HFCPCI_ACTIVATE 0x20125#define HFCPCI_DO_ACTION 0x40126#define HFCPCI_NT_G2_G3 0x80127 128/* bits in HFCD_MST_MODE */129#define HFCPCI_MASTER 0x01130#define HFCPCI_SLAVE 0x00131#define HFCPCI_F0IO_POSITIV 0x02132#define HFCPCI_F0_NEGATIV 0x04133#define HFCPCI_F0_2C4 0x08134/* remaining bits are for codecs control */135 136/* bits in HFCD_SCTRL */137#define SCTRL_B1_ENA 0x01138#define SCTRL_B2_ENA 0x02139#define SCTRL_MODE_TE 0x00140#define SCTRL_MODE_NT 0x04141#define SCTRL_LOW_PRIO 0x08142#define SCTRL_SQ_ENA 0x10143#define SCTRL_TEST 0x20144#define SCTRL_NONE_CAP 0x40145#define SCTRL_PWR_DOWN 0x80146 147/* bits in SCTRL_E */148#define HFCPCI_AUTO_AWAKE 0x01149#define HFCPCI_DBIT_1 0x04150#define HFCPCI_IGNORE_COL 0x08151#define HFCPCI_CHG_B1_B2 0x80152 153/* bits in FIFO_EN register */154#define HFCPCI_FIFOEN_B1 0x03155#define HFCPCI_FIFOEN_B2 0x0C156#define HFCPCI_FIFOEN_DTX 0x10157#define HFCPCI_FIFOEN_B1TX 0x01158#define HFCPCI_FIFOEN_B1RX 0x02159#define HFCPCI_FIFOEN_B2TX 0x04160#define HFCPCI_FIFOEN_B2RX 0x08161 162 163/* definitions of fifo memory area */164#define MAX_D_FRAMES 15165#define MAX_B_FRAMES 31166#define B_SUB_VAL 0x200167#define B_FIFO_SIZE (0x2000 - B_SUB_VAL)168#define D_FIFO_SIZE 512169#define D_FREG_MASK 0xF170 171struct zt {172 __le16 z1; /* Z1 pointer 16 Bit */173 __le16 z2; /* Z2 pointer 16 Bit */174};175 176struct dfifo {177 u_char data[D_FIFO_SIZE]; /* FIFO data space */178 u_char fill1[0x20A0 - D_FIFO_SIZE]; /* reserved, do not use */179 u_char f1, f2; /* f pointers */180 u_char fill2[0x20C0 - 0x20A2]; /* reserved, do not use */181 /* mask index with D_FREG_MASK for access */182 struct zt za[MAX_D_FRAMES + 1];183 u_char fill3[0x4000 - 0x2100]; /* align 16K */184};185 186struct bzfifo {187 struct zt za[MAX_B_FRAMES + 1]; /* only range 0x0..0x1F allowed */188 u_char f1, f2; /* f pointers */189 u_char fill[0x2100 - 0x2082]; /* alignment */190};191 192 193union fifo_area {194 struct {195 struct dfifo d_tx; /* D-send channel */196 struct dfifo d_rx; /* D-receive channel */197 } d_chan;198 struct {199 u_char fill1[0x200];200 u_char txdat_b1[B_FIFO_SIZE];201 struct bzfifo txbz_b1;202 struct bzfifo txbz_b2;203 u_char txdat_b2[B_FIFO_SIZE];204 u_char fill2[D_FIFO_SIZE];205 u_char rxdat_b1[B_FIFO_SIZE];206 struct bzfifo rxbz_b1;207 struct bzfifo rxbz_b2;208 u_char rxdat_b2[B_FIFO_SIZE];209 } b_chans;210 u_char fill[32768];211};212 213#define Write_hfc(a, b, c) (writeb(c, (a->hw.pci_io) + b))214#define Read_hfc(a, b) (readb((a->hw.pci_io) + b))215