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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * SS4200-E Hardware API4 * Copyright (c) 2009, Intel Corporation.5 * Copyright IBM Corporation, 20096 *7 * Author: Dave Hansen <dave@sr71.net>8 */9 10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt11 12#include <linux/dmi.h>13#include <linux/init.h>14#include <linux/ioport.h>15#include <linux/kernel.h>16#include <linux/leds.h>17#include <linux/module.h>18#include <linux/pci.h>19#include <linux/types.h>20#include <linux/uaccess.h>21 22MODULE_AUTHOR("Rodney Girod <rgirod@confocus.com>, Dave Hansen <dave@sr71.net>");23MODULE_DESCRIPTION("Intel NAS/Home Server ICH7 GPIO Driver");24MODULE_LICENSE("GPL");25 26/*27 * ICH7 LPC/GPIO PCI Config register offsets28 */29#define PMBASE 0x04030#define GPIO_BASE 0x04831#define GPIO_CTRL 0x04c32#define GPIO_EN 0x01033 34/*35 * The ICH7 GPIO register block is 64 bytes in size.36 */37#define ICH7_GPIO_SIZE 6438 39/*40 * Define register offsets within the ICH7 register block.41 */42#define GPIO_USE_SEL 0x00043#define GP_IO_SEL 0x00444#define GP_LVL 0x00c45#define GPO_BLINK 0x01846#define GPI_INV 0x03047#define GPIO_USE_SEL2 0x03448#define GP_IO_SEL2 0x03849#define GP_LVL2 0x03c50 51/*52 * PCI ID of the Intel ICH7 LPC Device within which the GPIO block lives.53 */54static const struct pci_device_id ich7_lpc_pci_id[] = {55 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0) },56 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1) },57 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_30) },58 { } /* NULL entry */59};60 61MODULE_DEVICE_TABLE(pci, ich7_lpc_pci_id);62 63static int __init ss4200_led_dmi_callback(const struct dmi_system_id *id)64{65 pr_info("detected '%s'\n", id->ident);66 return 1;67}68 69static bool nodetect;70module_param_named(nodetect, nodetect, bool, 0);71MODULE_PARM_DESC(nodetect, "Skip DMI-based hardware detection");72 73/*74 * struct nas_led_whitelist - List of known good models75 *76 * Contains the known good models this driver is compatible with.77 * When adding a new model try to be as strict as possible. This78 * makes it possible to keep the false positives (the model is79 * detected as working, but in reality it is not) as low as80 * possible.81 */82static const struct dmi_system_id nas_led_whitelist[] __initconst = {83 {84 .callback = ss4200_led_dmi_callback,85 .ident = "Intel SS4200-E",86 .matches = {87 DMI_MATCH(DMI_SYS_VENDOR, "Intel"),88 DMI_MATCH(DMI_PRODUCT_NAME, "SS4200-E"),89 DMI_MATCH(DMI_PRODUCT_VERSION, "1.00.00")90 }91 },92 {93 /*94 * FUJITSU SIEMENS SCALEO Home Server/SS4200-E95 * BIOS V090L 12/19/200796 */97 .callback = ss4200_led_dmi_callback,98 .ident = "Fujitsu Siemens SCALEO Home Server",99 .matches = {100 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU SIEMENS"),101 DMI_MATCH(DMI_PRODUCT_NAME, "SCALEO Home Server"),102 DMI_MATCH(DMI_PRODUCT_VERSION, "1.00.00")103 }104 },105 {}106};107 108/*109 * Base I/O address assigned to the Power Management register block110 */111static u32 g_pm_io_base;112 113/*114 * Base I/O address assigned to the ICH7 GPIO register block115 */116static u32 nas_gpio_io_base;117 118/*119 * When we successfully register a region, we are returned a resource.120 * We use these to identify which regions we need to release on our way121 * back out.122 */123static struct resource *gp_gpio_resource;124 125struct nasgpio_led {126 char *name;127 u32 gpio_bit;128 struct led_classdev led_cdev;129};130 131/*132 * gpio_bit(s) are the ICH7 GPIO bit assignments133 */134static struct nasgpio_led nasgpio_leds[] = {135 { .name = "hdd1:blue:sata", .gpio_bit = 0 },136 { .name = "hdd1:amber:sata", .gpio_bit = 1 },137 { .name = "hdd2:blue:sata", .gpio_bit = 2 },138 { .name = "hdd2:amber:sata", .gpio_bit = 3 },139 { .name = "hdd3:blue:sata", .gpio_bit = 4 },140 { .name = "hdd3:amber:sata", .gpio_bit = 5 },141 { .name = "hdd4:blue:sata", .gpio_bit = 6 },142 { .name = "hdd4:amber:sata", .gpio_bit = 7 },143 { .name = "power:blue:power", .gpio_bit = 27},144 { .name = "power:amber:power", .gpio_bit = 28},145};146 147#define NAS_RECOVERY 0x00000400 /* GPIO10 */148 149static struct nasgpio_led *150led_classdev_to_nasgpio_led(struct led_classdev *led_cdev)151{152 return container_of(led_cdev, struct nasgpio_led, led_cdev);153}154 155static struct nasgpio_led *get_led_named(char *name)156{157 int i;158 for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {159 if (strcmp(nasgpio_leds[i].name, name))160 continue;161 return &nasgpio_leds[i];162 }163 return NULL;164}165 166/*167 * This protects access to the gpio ports.168 */169static DEFINE_SPINLOCK(nasgpio_gpio_lock);170 171/*172 * There are two gpio ports, one for blinking and the other173 * for power. @port tells us if we're doing blinking or174 * power control.175 *176 * Caller must hold nasgpio_gpio_lock177 */178static void __nasgpio_led_set_attr(struct led_classdev *led_cdev,179 u32 port, u32 value)180{181 struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);182 u32 gpio_out;183 184 gpio_out = inl(nas_gpio_io_base + port);185 if (value)186 gpio_out |= (1<<led->gpio_bit);187 else188 gpio_out &= ~(1<<led->gpio_bit);189 190 outl(gpio_out, nas_gpio_io_base + port);191}192 193static void nasgpio_led_set_attr(struct led_classdev *led_cdev,194 u32 port, u32 value)195{196 spin_lock(&nasgpio_gpio_lock);197 __nasgpio_led_set_attr(led_cdev, port, value);198 spin_unlock(&nasgpio_gpio_lock);199}200 201static u32 nasgpio_led_get_attr(struct led_classdev *led_cdev, u32 port)202{203 struct nasgpio_led *led = led_classdev_to_nasgpio_led(led_cdev);204 u32 gpio_in;205 206 spin_lock(&nasgpio_gpio_lock);207 gpio_in = inl(nas_gpio_io_base + port);208 spin_unlock(&nasgpio_gpio_lock);209 if (gpio_in & (1<<led->gpio_bit))210 return 1;211 return 0;212}213 214/*215 * There is actual brightness control in the hardware,216 * but it is via smbus commands and not implemented217 * in this driver.218 */219static void nasgpio_led_set_brightness(struct led_classdev *led_cdev,220 enum led_brightness brightness)221{222 u32 setting = 0;223 if (brightness >= LED_HALF)224 setting = 1;225 /*226 * Hold the lock across both operations. This ensures227 * consistency so that both the "turn off blinking"228 * and "turn light off" operations complete as a set.229 */230 spin_lock(&nasgpio_gpio_lock);231 /*232 * LED class documentation asks that past blink state233 * be disabled when brightness is turned to zero.234 */235 if (brightness == 0)236 __nasgpio_led_set_attr(led_cdev, GPO_BLINK, 0);237 __nasgpio_led_set_attr(led_cdev, GP_LVL, setting);238 spin_unlock(&nasgpio_gpio_lock);239}240 241static int nasgpio_led_set_blink(struct led_classdev *led_cdev,242 unsigned long *delay_on,243 unsigned long *delay_off)244{245 u32 setting = 1;246 if (!(*delay_on == 0 && *delay_off == 0) &&247 !(*delay_on == 500 && *delay_off == 500))248 return -EINVAL;249 /*250 * These are very approximate.251 */252 *delay_on = 500;253 *delay_off = 500;254 255 nasgpio_led_set_attr(led_cdev, GPO_BLINK, setting);256 257 return 0;258}259 260 261/*262 * Initialize the ICH7 GPIO registers for NAS usage. The BIOS should have263 * already taken care of this, but we will do so in a non destructive manner264 * so that we have what we need whether the BIOS did it or not.265 */266static int ich7_gpio_init(struct device *dev)267{268 int i;269 u32 config_data = 0;270 u32 all_nas_led = 0;271 272 for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)273 all_nas_led |= (1<<nasgpio_leds[i].gpio_bit);274 275 spin_lock(&nasgpio_gpio_lock);276 /*277 * We need to enable all of the GPIO lines used by the NAS box,278 * so we will read the current Use Selection and add our usage279 * to it. This should be benign with regard to the original280 * BIOS configuration.281 */282 config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);283 dev_dbg(dev, ": Data read from GPIO_USE_SEL = 0x%08x\n", config_data);284 config_data |= all_nas_led + NAS_RECOVERY;285 outl(config_data, nas_gpio_io_base + GPIO_USE_SEL);286 config_data = inl(nas_gpio_io_base + GPIO_USE_SEL);287 dev_dbg(dev, ": GPIO_USE_SEL = 0x%08x\n\n", config_data);288 289 /*290 * The LED GPIO outputs need to be configured for output, so we291 * will ensure that all LED lines are cleared for output and the292 * RECOVERY line ready for input. This too should be benign with293 * regard to BIOS configuration.294 */295 config_data = inl(nas_gpio_io_base + GP_IO_SEL);296 dev_dbg(dev, ": Data read from GP_IO_SEL = 0x%08x\n",297 config_data);298 config_data &= ~all_nas_led;299 config_data |= NAS_RECOVERY;300 outl(config_data, nas_gpio_io_base + GP_IO_SEL);301 config_data = inl(nas_gpio_io_base + GP_IO_SEL);302 dev_dbg(dev, ": GP_IO_SEL = 0x%08x\n", config_data);303 304 /*305 * In our final system, the BIOS will initialize the state of all306 * of the LEDs. For now, we turn them all off (or Low).307 */308 config_data = inl(nas_gpio_io_base + GP_LVL);309 dev_dbg(dev, ": Data read from GP_LVL = 0x%08x\n", config_data);310 /*311 * In our final system, the BIOS will initialize the blink state of all312 * of the LEDs. For now, we turn blink off for all of them.313 */314 config_data = inl(nas_gpio_io_base + GPO_BLINK);315 dev_dbg(dev, ": Data read from GPO_BLINK = 0x%08x\n", config_data);316 317 /*318 * At this moment, I am unsure if anything needs to happen with GPI_INV319 */320 config_data = inl(nas_gpio_io_base + GPI_INV);321 dev_dbg(dev, ": Data read from GPI_INV = 0x%08x\n", config_data);322 323 spin_unlock(&nasgpio_gpio_lock);324 return 0;325}326 327static void ich7_lpc_cleanup(struct device *dev)328{329 /*330 * If we were given exclusive use of the GPIO331 * I/O Address range, we must return it.332 */333 if (gp_gpio_resource) {334 dev_dbg(dev, ": Releasing GPIO I/O addresses\n");335 release_region(nas_gpio_io_base, ICH7_GPIO_SIZE);336 gp_gpio_resource = NULL;337 }338}339 340/*341 * The OS has determined that the LPC of the Intel ICH7 Southbridge is present342 * so we can retrive the required operational information and prepare the GPIO.343 */344static struct pci_dev *nas_gpio_pci_dev;345static int ich7_lpc_probe(struct pci_dev *dev,346 const struct pci_device_id *id)347{348 int status;349 u32 gc = 0;350 351 status = pci_enable_device(dev);352 if (status) {353 dev_err(&dev->dev, "pci_enable_device failed\n");354 return -EIO;355 }356 357 nas_gpio_pci_dev = dev;358 status = pci_read_config_dword(dev, PMBASE, &g_pm_io_base);359 if (status) {360 status = pcibios_err_to_errno(status);361 goto out;362 }363 g_pm_io_base &= 0x00000ff80;364 365 status = pci_read_config_dword(dev, GPIO_CTRL, &gc);366 if (!(GPIO_EN & gc)) {367 status = -EEXIST;368 dev_info(&dev->dev,369 "ERROR: The LPC GPIO Block has not been enabled.\n");370 goto out;371 }372 373 status = pci_read_config_dword(dev, GPIO_BASE, &nas_gpio_io_base);374 if (status) {375 dev_info(&dev->dev, "Unable to read GPIOBASE.\n");376 status = pcibios_err_to_errno(status);377 goto out;378 }379 dev_dbg(&dev->dev, ": GPIOBASE = 0x%08x\n", nas_gpio_io_base);380 nas_gpio_io_base &= 0x00000ffc0;381 382 /*383 * Insure that we have exclusive access to the GPIO I/O address range.384 */385 gp_gpio_resource = request_region(nas_gpio_io_base, ICH7_GPIO_SIZE,386 KBUILD_MODNAME);387 if (NULL == gp_gpio_resource) {388 dev_info(&dev->dev,389 "ERROR Unable to register GPIO I/O addresses.\n");390 status = -1;391 goto out;392 }393 394 /*395 * Initialize the GPIO for NAS/Home Server Use396 */397 ich7_gpio_init(&dev->dev);398 399out:400 if (status) {401 ich7_lpc_cleanup(&dev->dev);402 pci_disable_device(dev);403 }404 return status;405}406 407static void ich7_lpc_remove(struct pci_dev *dev)408{409 ich7_lpc_cleanup(&dev->dev);410 pci_disable_device(dev);411}412 413/*414 * pci_driver structure passed to the PCI modules415 */416static struct pci_driver nas_gpio_pci_driver = {417 .name = KBUILD_MODNAME,418 .id_table = ich7_lpc_pci_id,419 .probe = ich7_lpc_probe,420 .remove = ich7_lpc_remove,421};422 423static struct led_classdev *get_classdev_for_led_nr(int nr)424{425 struct nasgpio_led *nas_led = &nasgpio_leds[nr];426 struct led_classdev *led = &nas_led->led_cdev;427 return led;428}429 430 431static void set_power_light_amber_noblink(void)432{433 struct nasgpio_led *amber = get_led_named("power:amber:power");434 struct nasgpio_led *blue = get_led_named("power:blue:power");435 436 if (!amber || !blue)437 return;438 /*439 * LED_OFF implies disabling future blinking440 */441 pr_debug("setting blue off and amber on\n");442 443 nasgpio_led_set_brightness(&blue->led_cdev, LED_OFF);444 nasgpio_led_set_brightness(&amber->led_cdev, LED_FULL);445}446 447static ssize_t blink_show(struct device *dev,448 struct device_attribute *attr, char *buf)449{450 struct led_classdev *led = dev_get_drvdata(dev);451 int blinking = 0;452 if (nasgpio_led_get_attr(led, GPO_BLINK))453 blinking = 1;454 return sprintf(buf, "%u\n", blinking);455}456 457static ssize_t blink_store(struct device *dev,458 struct device_attribute *attr,459 const char *buf, size_t size)460{461 int ret;462 struct led_classdev *led = dev_get_drvdata(dev);463 unsigned long blink_state;464 465 ret = kstrtoul(buf, 10, &blink_state);466 if (ret)467 return ret;468 469 nasgpio_led_set_attr(led, GPO_BLINK, blink_state);470 471 return size;472}473 474static DEVICE_ATTR_RW(blink);475 476static struct attribute *nasgpio_led_attrs[] = {477 &dev_attr_blink.attr,478 NULL479};480ATTRIBUTE_GROUPS(nasgpio_led);481 482static int register_nasgpio_led(int led_nr)483{484 struct nasgpio_led *nas_led = &nasgpio_leds[led_nr];485 struct led_classdev *led = get_classdev_for_led_nr(led_nr);486 487 led->name = nas_led->name;488 led->brightness = LED_OFF;489 if (nasgpio_led_get_attr(led, GP_LVL))490 led->brightness = LED_FULL;491 led->brightness_set = nasgpio_led_set_brightness;492 led->blink_set = nasgpio_led_set_blink;493 led->groups = nasgpio_led_groups;494 495 return led_classdev_register(&nas_gpio_pci_dev->dev, led);496}497 498static void unregister_nasgpio_led(int led_nr)499{500 struct led_classdev *led = get_classdev_for_led_nr(led_nr);501 led_classdev_unregister(led);502}503/*504 * module load/initialization505 */506static int __init nas_gpio_init(void)507{508 int i;509 int ret = 0;510 int nr_devices = 0;511 512 nr_devices = dmi_check_system(nas_led_whitelist);513 if (nodetect) {514 pr_info("skipping hardware autodetection\n");515 pr_info("Please send 'dmidecode' output to dave@sr71.net\n");516 nr_devices++;517 }518 519 if (nr_devices <= 0) {520 pr_info("no LED devices found\n");521 return -ENODEV;522 }523 524 pr_info("registering PCI driver\n");525 ret = pci_register_driver(&nas_gpio_pci_driver);526 if (ret)527 return ret;528 for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++) {529 ret = register_nasgpio_led(i);530 if (ret)531 goto out_err;532 }533 /*534 * When the system powers on, the BIOS leaves the power535 * light blue and blinking. This will turn it solid536 * amber once the driver is loaded.537 */538 set_power_light_amber_noblink();539 return 0;540out_err:541 for (i--; i >= 0; i--)542 unregister_nasgpio_led(i);543 pci_unregister_driver(&nas_gpio_pci_driver);544 return ret;545}546 547/*548 * module unload549 */550static void __exit nas_gpio_exit(void)551{552 int i;553 pr_info("Unregistering driver\n");554 for (i = 0; i < ARRAY_SIZE(nasgpio_leds); i++)555 unregister_nasgpio_led(i);556 pci_unregister_driver(&nas_gpio_pci_driver);557}558 559module_init(nas_gpio_init);560module_exit(nas_gpio_exit);561