1849 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2017-2022 Linaro Ltd4 * Copyright (c) 2010-2012, The Linux Foundation. All rights reserved.5 * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.6 */7#include <linux/bits.h>8#include <linux/bitfield.h>9#include <linux/led-class-multicolor.h>10#include <linux/module.h>11#include <linux/nvmem-consumer.h>12#include <linux/of.h>13#include <linux/platform_device.h>14#include <linux/pwm.h>15#include <linux/regmap.h>16#include <linux/slab.h>17#include <linux/soc/qcom/qcom-pbs.h>18 19#define LPG_SUBTYPE_REG 0x0520#define LPG_SUBTYPE_LPG 0x221#define LPG_SUBTYPE_PWM 0xb22#define LPG_SUBTYPE_HI_RES_PWM 0xc23#define LPG_SUBTYPE_LPG_LITE 0x1124#define LPG_PATTERN_CONFIG_REG 0x4025#define LPG_SIZE_CLK_REG 0x4126#define PWM_CLK_SELECT_MASK GENMASK(1, 0)27#define PWM_CLK_SELECT_HI_RES_MASK GENMASK(2, 0)28#define PWM_SIZE_HI_RES_MASK GENMASK(6, 4)29#define LPG_PREDIV_CLK_REG 0x4230#define PWM_FREQ_PRE_DIV_MASK GENMASK(6, 5)31#define PWM_FREQ_EXP_MASK GENMASK(2, 0)32#define PWM_TYPE_CONFIG_REG 0x4333#define PWM_VALUE_REG 0x4434#define PWM_ENABLE_CONTROL_REG 0x4635#define PWM_SYNC_REG 0x4736#define LPG_RAMP_DURATION_REG 0x5037#define LPG_HI_PAUSE_REG 0x5238#define LPG_LO_PAUSE_REG 0x5439#define LPG_HI_IDX_REG 0x5640#define LPG_LO_IDX_REG 0x5741#define PWM_SEC_ACCESS_REG 0xd042#define PWM_DTEST_REG(x) (0xe2 + (x) - 1)43 44#define SDAM_REG_PBS_SEQ_EN 0x4245#define SDAM_PBS_TRIG_SET 0xe546#define SDAM_PBS_TRIG_CLR 0xe647 48#define TRI_LED_SRC_SEL 0x4549#define TRI_LED_EN_CTL 0x4650#define TRI_LED_ATC_CTL 0x4751 52#define LPG_LUT_REG(x) (0x40 + (x) * 2)53#define RAMP_CONTROL_REG 0xc854 55#define LPG_RESOLUTION_9BIT BIT(9)56#define LPG_RESOLUTION_15BIT BIT(15)57#define PPG_MAX_LED_BRIGHTNESS 25558 59#define LPG_MAX_M 760#define LPG_MAX_PREDIV 661 62#define DEFAULT_TICK_DURATION_US 780063#define RAMP_STEP_DURATION(x) (((x) * 1000 / DEFAULT_TICK_DURATION_US) & 0xff)64 65#define SDAM_MAX_DEVICES 266/* LPG common config settings for PPG */67#define SDAM_START_BASE 0x4068#define SDAM_REG_RAMP_STEP_DURATION 0x4769 70#define SDAM_LUT_SDAM_LUT_PATTERN_OFFSET 0x4571#define SDAM_LPG_SDAM_LUT_PATTERN_OFFSET 0x8072 73/* LPG per channel config settings for PPG */74#define SDAM_LUT_EN_OFFSET 0x075#define SDAM_PATTERN_CONFIG_OFFSET 0x176#define SDAM_END_INDEX_OFFSET 0x377#define SDAM_START_INDEX_OFFSET 0x478#define SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET 0x679#define SDAM_PAUSE_HI_MULTIPLIER_OFFSET 0x880#define SDAM_PAUSE_LO_MULTIPLIER_OFFSET 0x981 82struct lpg_channel;83struct lpg_data;84 85/**86 * struct lpg - LPG device context87 * @dev: pointer to LPG device88 * @map: regmap for register access89 * @lock: used to synchronize LED and pwm callback requests90 * @pwm: PWM-chip object, if operating in PWM mode91 * @data: reference to version specific data92 * @lut_base: base address of the LUT block (optional)93 * @lut_size: number of entries in the LUT block94 * @lut_bitmap: allocation bitmap for LUT entries95 * @pbs_dev: PBS device96 * @lpg_chan_sdam: LPG SDAM peripheral device97 * @lut_sdam: LUT SDAM peripheral device98 * @pbs_en_bitmap: bitmap for tracking PBS triggers99 * @triled_base: base address of the TRILED block (optional)100 * @triled_src: power-source for the TRILED101 * @triled_has_atc_ctl: true if there is TRI_LED_ATC_CTL register102 * @triled_has_src_sel: true if there is TRI_LED_SRC_SEL register103 * @channels: list of PWM channels104 * @num_channels: number of @channels105 */106struct lpg {107 struct device *dev;108 struct regmap *map;109 110 struct mutex lock;111 112 struct pwm_chip *pwm;113 114 const struct lpg_data *data;115 116 u32 lut_base;117 u32 lut_size;118 unsigned long *lut_bitmap;119 120 struct pbs_dev *pbs_dev;121 struct nvmem_device *lpg_chan_sdam;122 struct nvmem_device *lut_sdam;123 unsigned long pbs_en_bitmap;124 125 u32 triled_base;126 u32 triled_src;127 bool triled_has_atc_ctl;128 bool triled_has_src_sel;129 130 struct lpg_channel *channels;131 unsigned int num_channels;132};133 134/**135 * struct lpg_channel - per channel data136 * @lpg: reference to parent lpg137 * @base: base address of the PWM channel138 * @triled_mask: mask in TRILED to enable this channel139 * @lut_mask: mask in LUT to start pattern generator for this channel140 * @subtype: PMIC hardware block subtype141 * @sdam_offset: channel offset in LPG SDAM142 * @in_use: channel is exposed to LED framework143 * @color: color of the LED attached to this channel144 * @dtest_line: DTEST line for output, or 0 if disabled145 * @dtest_value: DTEST line configuration146 * @pwm_value: duty (in microseconds) of the generated pulses, overridden by LUT147 * @enabled: output enabled?148 * @period: period (in nanoseconds) of the generated pulses149 * @clk_sel: reference clock frequency selector150 * @pre_div_sel: divider selector of the reference clock151 * @pre_div_exp: exponential divider of the reference clock152 * @pwm_resolution_sel: pwm resolution selector153 * @ramp_enabled: duty cycle is driven by iterating over lookup table154 * @ramp_ping_pong: reverse through pattern, rather than wrapping to start155 * @ramp_oneshot: perform only a single pass over the pattern156 * @ramp_reverse: iterate over pattern backwards157 * @ramp_tick_ms: length (in milliseconds) of one step in the pattern158 * @ramp_lo_pause_ms: pause (in milliseconds) before iterating over pattern159 * @ramp_hi_pause_ms: pause (in milliseconds) after iterating over pattern160 * @pattern_lo_idx: start index of associated pattern161 * @pattern_hi_idx: last index of associated pattern162 */163struct lpg_channel {164 struct lpg *lpg;165 166 u32 base;167 unsigned int triled_mask;168 unsigned int lut_mask;169 unsigned int subtype;170 u32 sdam_offset;171 172 bool in_use;173 174 int color;175 176 u32 dtest_line;177 u32 dtest_value;178 179 u16 pwm_value;180 bool enabled;181 182 u64 period;183 unsigned int clk_sel;184 unsigned int pre_div_sel;185 unsigned int pre_div_exp;186 unsigned int pwm_resolution_sel;187 188 bool ramp_enabled;189 bool ramp_ping_pong;190 bool ramp_oneshot;191 bool ramp_reverse;192 unsigned short ramp_tick_ms;193 unsigned long ramp_lo_pause_ms;194 unsigned long ramp_hi_pause_ms;195 196 unsigned int pattern_lo_idx;197 unsigned int pattern_hi_idx;198};199 200/**201 * struct lpg_led - logical LED object202 * @lpg: lpg context reference203 * @cdev: LED class device204 * @mcdev: Multicolor LED class device205 * @num_channels: number of @channels206 * @channels: list of channels associated with the LED207 */208struct lpg_led {209 struct lpg *lpg;210 211 struct led_classdev cdev;212 struct led_classdev_mc mcdev;213 214 unsigned int num_channels;215 struct lpg_channel *channels[] __counted_by(num_channels);216};217 218/**219 * struct lpg_channel_data - per channel initialization data220 * @sdam_offset: Channel offset in LPG SDAM221 * @base: base address for PWM channel registers222 * @triled_mask: bitmask for controlling this channel in TRILED223 */224struct lpg_channel_data {225 unsigned int sdam_offset;226 unsigned int base;227 u8 triled_mask;228};229 230/**231 * struct lpg_data - initialization data232 * @lut_base: base address of LUT block233 * @lut_size: number of entries in LUT234 * @triled_base: base address of TRILED235 * @triled_has_atc_ctl: true if there is TRI_LED_ATC_CTL register236 * @triled_has_src_sel: true if there is TRI_LED_SRC_SEL register237 * @num_channels: number of channels in LPG238 * @channels: list of channel initialization data239 */240struct lpg_data {241 unsigned int lut_base;242 unsigned int lut_size;243 unsigned int triled_base;244 bool triled_has_atc_ctl;245 bool triled_has_src_sel;246 int num_channels;247 const struct lpg_channel_data *channels;248};249 250#define PBS_SW_TRIG_BIT BIT(0)251 252static int lpg_clear_pbs_trigger(struct lpg *lpg, unsigned int lut_mask)253{254 u8 val = 0;255 int rc;256 257 if (!lpg->lpg_chan_sdam)258 return 0;259 260 lpg->pbs_en_bitmap &= (~lut_mask);261 if (!lpg->pbs_en_bitmap) {262 rc = nvmem_device_write(lpg->lpg_chan_sdam, SDAM_REG_PBS_SEQ_EN, 1, &val);263 if (rc < 0)264 return rc;265 266 if (lpg->lut_sdam) {267 val = PBS_SW_TRIG_BIT;268 rc = nvmem_device_write(lpg->lpg_chan_sdam, SDAM_PBS_TRIG_CLR, 1, &val);269 if (rc < 0)270 return rc;271 }272 }273 274 return 0;275}276 277static int lpg_set_pbs_trigger(struct lpg *lpg, unsigned int lut_mask)278{279 u8 val = PBS_SW_TRIG_BIT;280 int rc;281 282 if (!lpg->lpg_chan_sdam)283 return 0;284 285 if (!lpg->pbs_en_bitmap) {286 rc = nvmem_device_write(lpg->lpg_chan_sdam, SDAM_REG_PBS_SEQ_EN, 1, &val);287 if (rc < 0)288 return rc;289 290 if (lpg->lut_sdam) {291 rc = nvmem_device_write(lpg->lpg_chan_sdam, SDAM_PBS_TRIG_SET, 1, &val);292 if (rc < 0)293 return rc;294 } else {295 rc = qcom_pbs_trigger_event(lpg->pbs_dev, val);296 if (rc < 0)297 return rc;298 }299 }300 lpg->pbs_en_bitmap |= lut_mask;301 302 return 0;303}304 305static int lpg_sdam_configure_triggers(struct lpg_channel *chan, u8 set_trig)306{307 u32 addr = SDAM_LUT_EN_OFFSET + chan->sdam_offset;308 309 if (!chan->lpg->lpg_chan_sdam)310 return 0;311 312 return nvmem_device_write(chan->lpg->lpg_chan_sdam, addr, 1, &set_trig);313}314 315static int triled_set(struct lpg *lpg, unsigned int mask, unsigned int enable)316{317 /* Skip if we don't have a triled block */318 if (!lpg->triled_base)319 return 0;320 321 return regmap_update_bits(lpg->map, lpg->triled_base + TRI_LED_EN_CTL,322 mask, enable);323}324 325static int lpg_lut_store_sdam(struct lpg *lpg, struct led_pattern *pattern,326 size_t len, unsigned int *lo_idx, unsigned int *hi_idx)327{328 unsigned int idx;329 u8 brightness;330 int i, rc;331 u16 addr;332 333 if (len > lpg->lut_size) {334 dev_err(lpg->dev, "Pattern length (%zu) exceeds maximum pattern length (%d)\n",335 len, lpg->lut_size);336 return -EINVAL;337 }338 339 idx = bitmap_find_next_zero_area(lpg->lut_bitmap, lpg->lut_size, 0, len, 0);340 if (idx >= lpg->lut_size)341 return -ENOSPC;342 343 for (i = 0; i < len; i++) {344 brightness = pattern[i].brightness;345 346 if (lpg->lut_sdam) {347 addr = SDAM_LUT_SDAM_LUT_PATTERN_OFFSET + i + idx;348 rc = nvmem_device_write(lpg->lut_sdam, addr, 1, &brightness);349 } else {350 addr = SDAM_LPG_SDAM_LUT_PATTERN_OFFSET + i + idx;351 rc = nvmem_device_write(lpg->lpg_chan_sdam, addr, 1, &brightness);352 }353 354 if (rc < 0)355 return rc;356 }357 358 bitmap_set(lpg->lut_bitmap, idx, len);359 360 *lo_idx = idx;361 *hi_idx = idx + len - 1;362 363 return 0;364}365 366static int lpg_lut_store(struct lpg *lpg, struct led_pattern *pattern,367 size_t len, unsigned int *lo_idx, unsigned int *hi_idx)368{369 unsigned int idx;370 u16 val;371 int i;372 373 idx = bitmap_find_next_zero_area(lpg->lut_bitmap, lpg->lut_size,374 0, len, 0);375 if (idx >= lpg->lut_size)376 return -ENOMEM;377 378 for (i = 0; i < len; i++) {379 val = pattern[i].brightness;380 381 regmap_bulk_write(lpg->map, lpg->lut_base + LPG_LUT_REG(idx + i),382 &val, sizeof(val));383 }384 385 bitmap_set(lpg->lut_bitmap, idx, len);386 387 *lo_idx = idx;388 *hi_idx = idx + len - 1;389 390 return 0;391}392 393static void lpg_lut_free(struct lpg *lpg, unsigned int lo_idx, unsigned int hi_idx)394{395 int len;396 397 len = hi_idx - lo_idx + 1;398 if (len == 1)399 return;400 401 bitmap_clear(lpg->lut_bitmap, lo_idx, len);402}403 404static int lpg_lut_sync(struct lpg *lpg, unsigned int mask)405{406 if (!lpg->lut_base)407 return 0;408 409 return regmap_write(lpg->map, lpg->lut_base + RAMP_CONTROL_REG, mask);410}411 412static const unsigned int lpg_clk_rates[] = {0, 1024, 32768, 19200000};413static const unsigned int lpg_clk_rates_hi_res[] = {0, 1024, 32768, 19200000, 76800000};414static const unsigned int lpg_pre_divs[] = {1, 3, 5, 6};415static const unsigned int lpg_pwm_resolution[] = {9};416static const unsigned int lpg_pwm_resolution_hi_res[] = {8, 9, 10, 11, 12, 13, 14, 15};417 418static int lpg_calc_freq(struct lpg_channel *chan, uint64_t period)419{420 unsigned int i, pwm_resolution_count, best_pwm_resolution_sel = 0;421 const unsigned int *clk_rate_arr, *pwm_resolution_arr;422 unsigned int clk_sel, clk_len, best_clk = 0;423 unsigned int div, best_div = 0;424 unsigned int m, best_m = 0;425 unsigned int resolution;426 unsigned int error;427 unsigned int best_err = UINT_MAX;428 u64 max_period, min_period;429 u64 best_period = 0;430 u64 max_res;431 432 /*433 * The PWM period is determined by:434 *435 * resolution * pre_div * 2^M436 * period = --------------------------437 * refclk438 *439 * Resolution = 2^9 bits for PWM or440 * 2^{8, 9, 10, 11, 12, 13, 14, 15} bits for high resolution PWM441 * pre_div = {1, 3, 5, 6} and442 * M = [0..7].443 *444 * This allows for periods between 27uS and 384s for PWM channels and periods between445 * 3uS and 24576s for high resolution PWMs.446 * The PWM framework wants a period of equal or lower length than requested,447 * reject anything below minimum period.448 */449 450 if (chan->subtype == LPG_SUBTYPE_HI_RES_PWM) {451 clk_rate_arr = lpg_clk_rates_hi_res;452 clk_len = ARRAY_SIZE(lpg_clk_rates_hi_res);453 pwm_resolution_arr = lpg_pwm_resolution_hi_res;454 pwm_resolution_count = ARRAY_SIZE(lpg_pwm_resolution_hi_res);455 max_res = LPG_RESOLUTION_15BIT;456 } else {457 clk_rate_arr = lpg_clk_rates;458 clk_len = ARRAY_SIZE(lpg_clk_rates);459 pwm_resolution_arr = lpg_pwm_resolution;460 pwm_resolution_count = ARRAY_SIZE(lpg_pwm_resolution);461 max_res = LPG_RESOLUTION_9BIT;462 }463 464 min_period = div64_u64((u64)NSEC_PER_SEC * (1 << pwm_resolution_arr[0]),465 clk_rate_arr[clk_len - 1]);466 if (period <= min_period)467 return -EINVAL;468 469 /* Limit period to largest possible value, to avoid overflows */470 max_period = div64_u64((u64)NSEC_PER_SEC * max_res * LPG_MAX_PREDIV * (1 << LPG_MAX_M),471 1024);472 if (period > max_period)473 period = max_period;474 475 /*476 * Search for the pre_div, refclk, resolution and M by solving the rewritten formula477 * for each refclk, resolution and pre_div value:478 *479 * period * refclk480 * M = log2 -------------------------------------481 * NSEC_PER_SEC * pre_div * resolution482 */483 484 for (i = 0; i < pwm_resolution_count; i++) {485 resolution = 1 << pwm_resolution_arr[i];486 for (clk_sel = 1; clk_sel < clk_len; clk_sel++) {487 u64 numerator = period * clk_rate_arr[clk_sel];488 489 for (div = 0; div < ARRAY_SIZE(lpg_pre_divs); div++) {490 u64 denominator = (u64)NSEC_PER_SEC * lpg_pre_divs[div] *491 resolution;492 u64 actual;493 u64 ratio;494 495 if (numerator < denominator)496 continue;497 498 ratio = div64_u64(numerator, denominator);499 m = ilog2(ratio);500 if (m > LPG_MAX_M)501 m = LPG_MAX_M;502 503 actual = DIV_ROUND_UP_ULL(denominator * (1 << m),504 clk_rate_arr[clk_sel]);505 error = period - actual;506 if (error < best_err) {507 best_err = error;508 best_div = div;509 best_m = m;510 best_clk = clk_sel;511 best_period = actual;512 best_pwm_resolution_sel = i;513 }514 }515 }516 }517 chan->clk_sel = best_clk;518 chan->pre_div_sel = best_div;519 chan->pre_div_exp = best_m;520 chan->period = best_period;521 chan->pwm_resolution_sel = best_pwm_resolution_sel;522 return 0;523}524 525static void lpg_calc_duty(struct lpg_channel *chan, uint64_t duty)526{527 unsigned int max;528 unsigned int val;529 unsigned int clk_rate;530 531 if (chan->subtype == LPG_SUBTYPE_HI_RES_PWM) {532 max = LPG_RESOLUTION_15BIT - 1;533 clk_rate = lpg_clk_rates_hi_res[chan->clk_sel];534 } else {535 max = LPG_RESOLUTION_9BIT - 1;536 clk_rate = lpg_clk_rates[chan->clk_sel];537 }538 539 val = div64_u64(duty * clk_rate,540 (u64)NSEC_PER_SEC * lpg_pre_divs[chan->pre_div_sel] * (1 << chan->pre_div_exp));541 542 chan->pwm_value = min(val, max);543}544 545static void lpg_apply_freq(struct lpg_channel *chan)546{547 unsigned long val;548 struct lpg *lpg = chan->lpg;549 550 if (!chan->enabled)551 return;552 553 val = chan->clk_sel;554 555 /* Specify resolution, based on the subtype of the channel */556 switch (chan->subtype) {557 case LPG_SUBTYPE_LPG:558 val |= GENMASK(5, 4);559 break;560 case LPG_SUBTYPE_PWM:561 val |= BIT(2);562 break;563 case LPG_SUBTYPE_HI_RES_PWM:564 val |= FIELD_PREP(PWM_SIZE_HI_RES_MASK, chan->pwm_resolution_sel);565 break;566 case LPG_SUBTYPE_LPG_LITE:567 default:568 val |= BIT(4);569 break;570 }571 572 regmap_write(lpg->map, chan->base + LPG_SIZE_CLK_REG, val);573 574 val = FIELD_PREP(PWM_FREQ_PRE_DIV_MASK, chan->pre_div_sel) |575 FIELD_PREP(PWM_FREQ_EXP_MASK, chan->pre_div_exp);576 regmap_write(lpg->map, chan->base + LPG_PREDIV_CLK_REG, val);577}578 579#define LPG_ENABLE_GLITCH_REMOVAL BIT(5)580 581static void lpg_enable_glitch(struct lpg_channel *chan)582{583 struct lpg *lpg = chan->lpg;584 585 regmap_update_bits(lpg->map, chan->base + PWM_TYPE_CONFIG_REG,586 LPG_ENABLE_GLITCH_REMOVAL, 0);587}588 589static void lpg_disable_glitch(struct lpg_channel *chan)590{591 struct lpg *lpg = chan->lpg;592 593 regmap_update_bits(lpg->map, chan->base + PWM_TYPE_CONFIG_REG,594 LPG_ENABLE_GLITCH_REMOVAL,595 LPG_ENABLE_GLITCH_REMOVAL);596}597 598static void lpg_apply_pwm_value(struct lpg_channel *chan)599{600 struct lpg *lpg = chan->lpg;601 u16 val = chan->pwm_value;602 603 if (!chan->enabled)604 return;605 606 regmap_bulk_write(lpg->map, chan->base + PWM_VALUE_REG, &val, sizeof(val));607}608 609#define LPG_PATTERN_CONFIG_LO_TO_HI BIT(4)610#define LPG_PATTERN_CONFIG_REPEAT BIT(3)611#define LPG_PATTERN_CONFIG_TOGGLE BIT(2)612#define LPG_PATTERN_CONFIG_PAUSE_HI BIT(1)613#define LPG_PATTERN_CONFIG_PAUSE_LO BIT(0)614 615static void lpg_sdam_apply_lut_control(struct lpg_channel *chan)616{617 struct nvmem_device *lpg_chan_sdam = chan->lpg->lpg_chan_sdam;618 unsigned int lo_idx = chan->pattern_lo_idx;619 unsigned int hi_idx = chan->pattern_hi_idx;620 u8 val = 0, conf = 0, lut_offset = 0;621 unsigned int hi_pause, lo_pause;622 struct lpg *lpg = chan->lpg;623 624 if (!chan->ramp_enabled || chan->pattern_lo_idx == chan->pattern_hi_idx)625 return;626 627 hi_pause = DIV_ROUND_UP(chan->ramp_hi_pause_ms, chan->ramp_tick_ms);628 lo_pause = DIV_ROUND_UP(chan->ramp_lo_pause_ms, chan->ramp_tick_ms);629 630 if (!chan->ramp_oneshot)631 conf |= LPG_PATTERN_CONFIG_REPEAT;632 if (chan->ramp_hi_pause_ms && lpg->lut_sdam)633 conf |= LPG_PATTERN_CONFIG_PAUSE_HI;634 if (chan->ramp_lo_pause_ms && lpg->lut_sdam)635 conf |= LPG_PATTERN_CONFIG_PAUSE_LO;636 637 if (lpg->lut_sdam) {638 lut_offset = SDAM_LUT_SDAM_LUT_PATTERN_OFFSET - SDAM_START_BASE;639 hi_idx += lut_offset;640 lo_idx += lut_offset;641 }642 643 nvmem_device_write(lpg_chan_sdam, SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET + chan->sdam_offset, 1, &val);644 nvmem_device_write(lpg_chan_sdam, SDAM_PATTERN_CONFIG_OFFSET + chan->sdam_offset, 1, &conf);645 nvmem_device_write(lpg_chan_sdam, SDAM_END_INDEX_OFFSET + chan->sdam_offset, 1, &hi_idx);646 nvmem_device_write(lpg_chan_sdam, SDAM_START_INDEX_OFFSET + chan->sdam_offset, 1, &lo_idx);647 648 val = RAMP_STEP_DURATION(chan->ramp_tick_ms);649 nvmem_device_write(lpg_chan_sdam, SDAM_REG_RAMP_STEP_DURATION, 1, &val);650 651 if (lpg->lut_sdam) {652 nvmem_device_write(lpg_chan_sdam, SDAM_PAUSE_HI_MULTIPLIER_OFFSET + chan->sdam_offset, 1, &hi_pause);653 nvmem_device_write(lpg_chan_sdam, SDAM_PAUSE_LO_MULTIPLIER_OFFSET + chan->sdam_offset, 1, &lo_pause);654 }655 656}657 658static void lpg_apply_lut_control(struct lpg_channel *chan)659{660 struct lpg *lpg = chan->lpg;661 unsigned int hi_pause;662 unsigned int lo_pause;663 unsigned int conf = 0;664 unsigned int lo_idx = chan->pattern_lo_idx;665 unsigned int hi_idx = chan->pattern_hi_idx;666 u16 step = chan->ramp_tick_ms;667 668 if (!chan->ramp_enabled || chan->pattern_lo_idx == chan->pattern_hi_idx)669 return;670 671 hi_pause = DIV_ROUND_UP(chan->ramp_hi_pause_ms, step);672 lo_pause = DIV_ROUND_UP(chan->ramp_lo_pause_ms, step);673 674 if (!chan->ramp_reverse)675 conf |= LPG_PATTERN_CONFIG_LO_TO_HI;676 if (!chan->ramp_oneshot)677 conf |= LPG_PATTERN_CONFIG_REPEAT;678 if (chan->ramp_ping_pong)679 conf |= LPG_PATTERN_CONFIG_TOGGLE;680 if (chan->ramp_hi_pause_ms)681 conf |= LPG_PATTERN_CONFIG_PAUSE_HI;682 if (chan->ramp_lo_pause_ms)683 conf |= LPG_PATTERN_CONFIG_PAUSE_LO;684 685 regmap_write(lpg->map, chan->base + LPG_PATTERN_CONFIG_REG, conf);686 regmap_write(lpg->map, chan->base + LPG_HI_IDX_REG, hi_idx);687 regmap_write(lpg->map, chan->base + LPG_LO_IDX_REG, lo_idx);688 689 regmap_bulk_write(lpg->map, chan->base + LPG_RAMP_DURATION_REG, &step, sizeof(step));690 regmap_write(lpg->map, chan->base + LPG_HI_PAUSE_REG, hi_pause);691 regmap_write(lpg->map, chan->base + LPG_LO_PAUSE_REG, lo_pause);692}693 694#define LPG_ENABLE_CONTROL_OUTPUT BIT(7)695#define LPG_ENABLE_CONTROL_BUFFER_TRISTATE BIT(5)696#define LPG_ENABLE_CONTROL_SRC_PWM BIT(2)697#define LPG_ENABLE_CONTROL_RAMP_GEN BIT(1)698 699static void lpg_apply_control(struct lpg_channel *chan)700{701 unsigned int ctrl;702 struct lpg *lpg = chan->lpg;703 704 ctrl = LPG_ENABLE_CONTROL_BUFFER_TRISTATE;705 706 if (chan->enabled)707 ctrl |= LPG_ENABLE_CONTROL_OUTPUT;708 709 if (chan->pattern_lo_idx != chan->pattern_hi_idx)710 ctrl |= LPG_ENABLE_CONTROL_RAMP_GEN;711 else712 ctrl |= LPG_ENABLE_CONTROL_SRC_PWM;713 714 regmap_write(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, ctrl);715 716 /*717 * Due to LPG hardware bug, in the PWM mode, having enabled PWM,718 * We have to write PWM values one more time.719 */720 if (chan->enabled)721 lpg_apply_pwm_value(chan);722}723 724#define LPG_SYNC_PWM BIT(0)725 726static void lpg_apply_sync(struct lpg_channel *chan)727{728 struct lpg *lpg = chan->lpg;729 730 regmap_write(lpg->map, chan->base + PWM_SYNC_REG, LPG_SYNC_PWM);731}732 733static int lpg_parse_dtest(struct lpg *lpg)734{735 struct lpg_channel *chan;736 struct device_node *np = lpg->dev->of_node;737 int count;738 int ret;739 int i;740 741 count = of_property_count_u32_elems(np, "qcom,dtest");742 if (count == -EINVAL) {743 return 0;744 } else if (count < 0) {745 ret = count;746 goto err_malformed;747 } else if (count != lpg->data->num_channels * 2) {748 return dev_err_probe(lpg->dev, -EINVAL,749 "qcom,dtest needs to be %d items\n",750 lpg->data->num_channels * 2);751 }752 753 for (i = 0; i < lpg->data->num_channels; i++) {754 chan = &lpg->channels[i];755 756 ret = of_property_read_u32_index(np, "qcom,dtest", i * 2,757 &chan->dtest_line);758 if (ret)759 goto err_malformed;760 761 ret = of_property_read_u32_index(np, "qcom,dtest", i * 2 + 1,762 &chan->dtest_value);763 if (ret)764 goto err_malformed;765 }766 767 return 0;768 769err_malformed:770 return dev_err_probe(lpg->dev, ret, "malformed qcom,dtest\n");771}772 773static void lpg_apply_dtest(struct lpg_channel *chan)774{775 struct lpg *lpg = chan->lpg;776 777 if (!chan->dtest_line)778 return;779 780 regmap_write(lpg->map, chan->base + PWM_SEC_ACCESS_REG, 0xa5);781 regmap_write(lpg->map, chan->base + PWM_DTEST_REG(chan->dtest_line),782 chan->dtest_value);783}784 785static void lpg_apply(struct lpg_channel *chan)786{787 lpg_disable_glitch(chan);788 lpg_apply_freq(chan);789 lpg_apply_pwm_value(chan);790 lpg_apply_control(chan);791 lpg_apply_sync(chan);792 if (chan->lpg->lpg_chan_sdam)793 lpg_sdam_apply_lut_control(chan);794 else795 lpg_apply_lut_control(chan);796 lpg_enable_glitch(chan);797}798 799static void lpg_brightness_set(struct lpg_led *led, struct led_classdev *cdev,800 struct mc_subled *subleds)801{802 enum led_brightness brightness;803 struct lpg_channel *chan;804 unsigned int triled_enabled = 0;805 unsigned int triled_mask = 0;806 unsigned int lut_mask = 0;807 unsigned int duty;808 struct lpg *lpg = led->lpg;809 int i;810 811 for (i = 0; i < led->num_channels; i++) {812 chan = led->channels[i];813 brightness = subleds[i].brightness;814 815 if (brightness == LED_OFF) {816 chan->enabled = false;817 chan->ramp_enabled = false;818 } else if (chan->pattern_lo_idx != chan->pattern_hi_idx) {819 lpg_calc_freq(chan, NSEC_PER_MSEC);820 lpg_sdam_configure_triggers(chan, 1);821 822 chan->enabled = true;823 chan->ramp_enabled = true;824 825 lut_mask |= chan->lut_mask;826 triled_enabled |= chan->triled_mask;827 } else {828 lpg_calc_freq(chan, NSEC_PER_MSEC);829 830 duty = div_u64(brightness * chan->period, cdev->max_brightness);831 lpg_calc_duty(chan, duty);832 chan->enabled = true;833 chan->ramp_enabled = false;834 835 triled_enabled |= chan->triled_mask;836 }837 838 triled_mask |= chan->triled_mask;839 840 lpg_apply(chan);841 }842 843 /* Toggle triled lines */844 if (triled_mask)845 triled_set(lpg, triled_mask, triled_enabled);846 847 /* Trigger start of ramp generator(s) */848 if (lut_mask) {849 lpg_lut_sync(lpg, lut_mask);850 lpg_set_pbs_trigger(lpg, lut_mask);851 }852}853 854static int lpg_brightness_single_set(struct led_classdev *cdev,855 enum led_brightness value)856{857 struct lpg_led *led = container_of(cdev, struct lpg_led, cdev);858 struct mc_subled info;859 860 mutex_lock(&led->lpg->lock);861 862 info.brightness = value;863 lpg_brightness_set(led, cdev, &info);864 865 mutex_unlock(&led->lpg->lock);866 867 return 0;868}869 870static int lpg_brightness_mc_set(struct led_classdev *cdev,871 enum led_brightness value)872{873 struct led_classdev_mc *mc = lcdev_to_mccdev(cdev);874 struct lpg_led *led = container_of(mc, struct lpg_led, mcdev);875 876 mutex_lock(&led->lpg->lock);877 878 led_mc_calc_color_components(mc, value);879 lpg_brightness_set(led, cdev, mc->subled_info);880 881 mutex_unlock(&led->lpg->lock);882 883 return 0;884}885 886static int lpg_blink_set(struct lpg_led *led,887 unsigned long *delay_on, unsigned long *delay_off)888{889 struct lpg_channel *chan;890 unsigned int period;891 unsigned int triled_mask = 0;892 struct lpg *lpg = led->lpg;893 u64 duty;894 int i;895 896 if (!*delay_on && !*delay_off) {897 *delay_on = 500;898 *delay_off = 500;899 }900 901 duty = *delay_on * NSEC_PER_MSEC;902 period = (*delay_on + *delay_off) * NSEC_PER_MSEC;903 904 for (i = 0; i < led->num_channels; i++) {905 chan = led->channels[i];906 907 lpg_calc_freq(chan, period);908 lpg_calc_duty(chan, duty);909 910 chan->enabled = true;911 chan->ramp_enabled = false;912 913 triled_mask |= chan->triled_mask;914 915 lpg_apply(chan);916 }917 918 /* Enable triled lines */919 triled_set(lpg, triled_mask, triled_mask);920 921 chan = led->channels[0];922 duty = div_u64(chan->pwm_value * chan->period, LPG_RESOLUTION_9BIT);923 *delay_on = div_u64(duty, NSEC_PER_MSEC);924 *delay_off = div_u64(chan->period - duty, NSEC_PER_MSEC);925 926 return 0;927}928 929static int lpg_blink_single_set(struct led_classdev *cdev,930 unsigned long *delay_on, unsigned long *delay_off)931{932 struct lpg_led *led = container_of(cdev, struct lpg_led, cdev);933 int ret;934 935 mutex_lock(&led->lpg->lock);936 937 ret = lpg_blink_set(led, delay_on, delay_off);938 939 mutex_unlock(&led->lpg->lock);940 941 return ret;942}943 944static int lpg_blink_mc_set(struct led_classdev *cdev,945 unsigned long *delay_on, unsigned long *delay_off)946{947 struct led_classdev_mc *mc = lcdev_to_mccdev(cdev);948 struct lpg_led *led = container_of(mc, struct lpg_led, mcdev);949 int ret;950 951 mutex_lock(&led->lpg->lock);952 953 ret = lpg_blink_set(led, delay_on, delay_off);954 955 mutex_unlock(&led->lpg->lock);956 957 return ret;958}959 960static int lpg_pattern_set(struct lpg_led *led, struct led_pattern *led_pattern,961 u32 len, int repeat)962{963 struct lpg_channel *chan;964 struct lpg *lpg = led->lpg;965 struct led_pattern *pattern;966 unsigned int brightness_a;967 unsigned int brightness_b;968 unsigned int hi_pause = 0;969 unsigned int lo_pause = 0;970 unsigned int actual_len;971 unsigned int delta_t;972 unsigned int lo_idx;973 unsigned int hi_idx;974 unsigned int i;975 bool ping_pong = true;976 int ret = -EINVAL;977 978 /* Hardware only support oneshot or indefinite loops */979 if (repeat != -1 && repeat != 1)980 return -EINVAL;981 982 /*983 * The standardized leds-trigger-pattern format defines that the984 * brightness of the LED follows a linear transition from one entry985 * in the pattern to the next, over the given delta_t time. It986 * describes that the way to perform instant transitions a zero-length987 * entry should be added following a pattern entry.988 *989 * The LPG hardware is only able to perform the latter (no linear990 * transitions), so require each entry in the pattern to be followed by991 * a zero-length transition.992 */993 if (len % 2)994 return -EINVAL;995 996 pattern = kcalloc(len / 2, sizeof(*pattern), GFP_KERNEL);997 if (!pattern)998 return -ENOMEM;999 1000 for (i = 0; i < len; i += 2) {1001 if (led_pattern[i].brightness != led_pattern[i + 1].brightness)1002 goto out_free_pattern;1003 if (led_pattern[i + 1].delta_t != 0)1004 goto out_free_pattern;1005 1006 pattern[i / 2].brightness = led_pattern[i].brightness;1007 pattern[i / 2].delta_t = led_pattern[i].delta_t;1008 }1009 1010 len /= 2;1011 1012 /*1013 * Specifying a pattern of length 1 causes the hardware to iterate1014 * through the entire LUT, so prohibit this.1015 */1016 if (len < 2)1017 goto out_free_pattern;1018 1019 /*1020 * The LPG plays patterns with at a fixed pace, a "low pause" can be1021 * used to stretch the first delay of the pattern and a "high pause"1022 * the last one.1023 *1024 * In order to save space the pattern can be played in "ping pong"1025 * mode, in which the pattern is first played forward, then "high1026 * pause" is applied, then the pattern is played backwards and finally1027 * the "low pause" is applied.1028 *1029 * The middle elements of the pattern are used to determine delta_t and1030 * the "low pause" and "high pause" multipliers are derrived from this.1031 *1032 * The first element in the pattern is used to determine "low pause".1033 *1034 * If the specified pattern is a palindrome the ping pong mode is1035 * enabled. In this scenario the delta_t of the middle entry (i.e. the1036 * last in the programmed pattern) determines the "high pause".1037 *1038 * SDAM-based devices do not support "ping pong", and only supports1039 * "low pause" and "high pause" with a dedicated SDAM LUT.1040 */1041 1042 /* Detect palindromes and use "ping pong" to reduce LUT usage */1043 if (lpg->lut_base) {1044 for (i = 0; i < len / 2; i++) {1045 brightness_a = pattern[i].brightness;1046 brightness_b = pattern[len - i - 1].brightness;1047 1048 if (brightness_a != brightness_b) {1049 ping_pong = false;1050 break;1051 }1052 }1053 } else1054 ping_pong = false;1055 1056 /* The pattern length to be written to the LUT */1057 if (ping_pong)1058 actual_len = (len + 1) / 2;1059 else1060 actual_len = len;1061 1062 /*1063 * Validate that all delta_t in the pattern are the same, with the1064 * exception of the middle element in case of ping_pong.1065 */1066 delta_t = pattern[1].delta_t;1067 for (i = 2; i < len; i++) {1068 if (pattern[i].delta_t != delta_t) {1069 /*1070 * Allow last entry in the full or shortened pattern to1071 * specify hi pause. Reject other variations.1072 */1073 if (i != actual_len - 1)1074 goto out_free_pattern;1075 }1076 }1077 1078 /* LPG_RAMP_DURATION_REG is a 9bit */1079 if (delta_t >= BIT(9))1080 goto out_free_pattern;1081 1082 /*1083 * Find "low pause" and "high pause" in the pattern in the LUT case.1084 * SDAM-based devices without dedicated LUT SDAM require equal1085 * duration of all steps.1086 */1087 if (lpg->lut_base || lpg->lut_sdam) {1088 lo_pause = pattern[0].delta_t;1089 hi_pause = pattern[actual_len - 1].delta_t;1090 } else {1091 if (delta_t != pattern[0].delta_t || delta_t != pattern[actual_len - 1].delta_t)1092 goto out_free_pattern;1093 }1094 1095 1096 mutex_lock(&lpg->lock);1097 1098 if (lpg->lut_base)1099 ret = lpg_lut_store(lpg, pattern, actual_len, &lo_idx, &hi_idx);1100 else1101 ret = lpg_lut_store_sdam(lpg, pattern, actual_len, &lo_idx, &hi_idx);1102 1103 if (ret < 0)1104 goto out_unlock;1105 1106 for (i = 0; i < led->num_channels; i++) {1107 chan = led->channels[i];1108 1109 chan->ramp_tick_ms = delta_t;1110 chan->ramp_ping_pong = ping_pong;1111 chan->ramp_oneshot = repeat != -1;1112 1113 chan->ramp_lo_pause_ms = lo_pause;1114 chan->ramp_hi_pause_ms = hi_pause;1115 1116 chan->pattern_lo_idx = lo_idx;1117 chan->pattern_hi_idx = hi_idx;1118 }1119 1120out_unlock:1121 mutex_unlock(&lpg->lock);1122out_free_pattern:1123 kfree(pattern);1124 1125 return ret;1126}1127 1128static int lpg_pattern_single_set(struct led_classdev *cdev,1129 struct led_pattern *pattern, u32 len,1130 int repeat)1131{1132 struct lpg_led *led = container_of(cdev, struct lpg_led, cdev);1133 int ret;1134 1135 ret = lpg_pattern_set(led, pattern, len, repeat);1136 if (ret < 0)1137 return ret;1138 1139 lpg_brightness_single_set(cdev, LED_FULL);1140 1141 return 0;1142}1143 1144static int lpg_pattern_mc_set(struct led_classdev *cdev,1145 struct led_pattern *pattern, u32 len,1146 int repeat)1147{1148 struct led_classdev_mc *mc = lcdev_to_mccdev(cdev);1149 struct lpg_led *led = container_of(mc, struct lpg_led, mcdev);1150 unsigned int triled_mask = 0;1151 int ret, i;1152 1153 for (i = 0; i < led->num_channels; i++)1154 triled_mask |= led->channels[i]->triled_mask;1155 triled_set(led->lpg, triled_mask, 0);1156 1157 ret = lpg_pattern_set(led, pattern, len, repeat);1158 if (ret < 0)1159 return ret;1160 1161 led_mc_calc_color_components(mc, LED_FULL);1162 lpg_brightness_set(led, cdev, mc->subled_info);1163 1164 return 0;1165}1166 1167static int lpg_pattern_clear(struct lpg_led *led)1168{1169 struct lpg_channel *chan;1170 struct lpg *lpg = led->lpg;1171 int i;1172 1173 mutex_lock(&lpg->lock);1174 1175 chan = led->channels[0];1176 lpg_lut_free(lpg, chan->pattern_lo_idx, chan->pattern_hi_idx);1177 1178 for (i = 0; i < led->num_channels; i++) {1179 chan = led->channels[i];1180 lpg_sdam_configure_triggers(chan, 0);1181 lpg_clear_pbs_trigger(chan->lpg, chan->lut_mask);1182 chan->pattern_lo_idx = 0;1183 chan->pattern_hi_idx = 0;1184 }1185 1186 mutex_unlock(&lpg->lock);1187 1188 return 0;1189}1190 1191static int lpg_pattern_single_clear(struct led_classdev *cdev)1192{1193 struct lpg_led *led = container_of(cdev, struct lpg_led, cdev);1194 1195 return lpg_pattern_clear(led);1196}1197 1198static int lpg_pattern_mc_clear(struct led_classdev *cdev)1199{1200 struct led_classdev_mc *mc = lcdev_to_mccdev(cdev);1201 struct lpg_led *led = container_of(mc, struct lpg_led, mcdev);1202 1203 return lpg_pattern_clear(led);1204}1205 1206static inline struct lpg *lpg_pwm_from_chip(struct pwm_chip *chip)1207{1208 return pwmchip_get_drvdata(chip);1209}1210 1211static int lpg_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)1212{1213 struct lpg *lpg = lpg_pwm_from_chip(chip);1214 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];1215 1216 return chan->in_use ? -EBUSY : 0;1217}1218 1219/*1220 * Limitations:1221 * - Updating both duty and period is not done atomically, so the output signal1222 * will momentarily be a mix of the settings.1223 * - Changed parameters takes effect immediately.1224 * - A disabled channel outputs a logical 0.1225 */1226static int lpg_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,1227 const struct pwm_state *state)1228{1229 struct lpg *lpg = lpg_pwm_from_chip(chip);1230 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];1231 int ret = 0;1232 1233 if (state->polarity != PWM_POLARITY_NORMAL)1234 return -EINVAL;1235 1236 mutex_lock(&lpg->lock);1237 1238 if (state->enabled) {1239 ret = lpg_calc_freq(chan, state->period);1240 if (ret < 0)1241 goto out_unlock;1242 1243 lpg_calc_duty(chan, state->duty_cycle);1244 }1245 chan->enabled = state->enabled;1246 1247 lpg_apply(chan);1248 1249 triled_set(lpg, chan->triled_mask, chan->enabled ? chan->triled_mask : 0);1250 1251out_unlock:1252 mutex_unlock(&lpg->lock);1253 1254 return ret;1255}1256 1257static int lpg_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,1258 struct pwm_state *state)1259{1260 struct lpg *lpg = lpg_pwm_from_chip(chip);1261 struct lpg_channel *chan = &lpg->channels[pwm->hwpwm];1262 unsigned int resolution;1263 unsigned int pre_div;1264 unsigned int refclk;1265 unsigned int val;1266 unsigned int m;1267 u16 pwm_value;1268 int ret;1269 1270 ret = regmap_read(lpg->map, chan->base + LPG_SIZE_CLK_REG, &val);1271 if (ret)1272 return ret;1273 1274 if (chan->subtype == LPG_SUBTYPE_HI_RES_PWM) {1275 refclk = lpg_clk_rates_hi_res[FIELD_GET(PWM_CLK_SELECT_HI_RES_MASK, val)];1276 resolution = lpg_pwm_resolution_hi_res[FIELD_GET(PWM_SIZE_HI_RES_MASK, val)];1277 } else {1278 refclk = lpg_clk_rates[FIELD_GET(PWM_CLK_SELECT_MASK, val)];1279 resolution = 9;1280 }1281 1282 if (refclk) {1283 ret = regmap_read(lpg->map, chan->base + LPG_PREDIV_CLK_REG, &val);1284 if (ret)1285 return ret;1286 1287 pre_div = lpg_pre_divs[FIELD_GET(PWM_FREQ_PRE_DIV_MASK, val)];1288 m = FIELD_GET(PWM_FREQ_EXP_MASK, val);1289 1290 ret = regmap_bulk_read(lpg->map, chan->base + PWM_VALUE_REG, &pwm_value, sizeof(pwm_value));1291 if (ret)1292 return ret;1293 1294 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * (1 << resolution) *1295 pre_div * (1 << m), refclk);1296 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pwm_value * pre_div * (1 << m), refclk);1297 } else {1298 state->period = 0;1299 state->duty_cycle = 0;1300 }1301 1302 ret = regmap_read(lpg->map, chan->base + PWM_ENABLE_CONTROL_REG, &val);1303 if (ret)1304 return ret;1305 1306 state->enabled = FIELD_GET(LPG_ENABLE_CONTROL_OUTPUT, val);1307 state->polarity = PWM_POLARITY_NORMAL;1308 1309 if (state->duty_cycle > state->period)1310 state->duty_cycle = state->period;1311 1312 return 0;1313}1314 1315static const struct pwm_ops lpg_pwm_ops = {1316 .request = lpg_pwm_request,1317 .apply = lpg_pwm_apply,1318 .get_state = lpg_pwm_get_state,1319};1320 1321static int lpg_add_pwm(struct lpg *lpg)1322{1323 struct pwm_chip *chip;1324 int ret;1325 1326 lpg->pwm = chip = devm_pwmchip_alloc(lpg->dev, lpg->num_channels, 0);1327 if (IS_ERR(chip))1328 return PTR_ERR(chip);1329 1330 chip->ops = &lpg_pwm_ops;1331 pwmchip_set_drvdata(chip, lpg);1332 1333 ret = devm_pwmchip_add(lpg->dev, chip);1334 if (ret)1335 dev_err_probe(lpg->dev, ret, "failed to add PWM chip\n");1336 1337 return ret;1338}1339 1340static int lpg_parse_channel(struct lpg *lpg, struct device_node *np,1341 struct lpg_channel **channel)1342{1343 struct lpg_channel *chan;1344 u32 color = LED_COLOR_ID_GREEN;1345 u32 reg;1346 int ret;1347 1348 ret = of_property_read_u32(np, "reg", ®);1349 if (ret || !reg || reg > lpg->num_channels)1350 return dev_err_probe(lpg->dev, -EINVAL, "invalid \"reg\" of %pOFn\n", np);1351 1352 chan = &lpg->channels[reg - 1];1353 chan->in_use = true;1354 1355 ret = of_property_read_u32(np, "color", &color);1356 if (ret < 0 && ret != -EINVAL)1357 return dev_err_probe(lpg->dev, ret,1358 "failed to parse \"color\" of %pOF\n", np);1359 1360 chan->color = color;1361 1362 *channel = chan;1363 1364 return 0;1365}1366 1367static int lpg_add_led(struct lpg *lpg, struct device_node *np)1368{1369 struct led_init_data init_data = {};1370 struct led_classdev *cdev;1371 struct mc_subled *info;1372 struct lpg_led *led;1373 const char *state;1374 int num_channels;1375 u32 color = 0;1376 int ret;1377 int i;1378 1379 ret = of_property_read_u32(np, "color", &color);1380 if (ret < 0 && ret != -EINVAL)1381 return dev_err_probe(lpg->dev, ret,1382 "failed to parse \"color\" of %pOF\n", np);1383 1384 if (color == LED_COLOR_ID_RGB)1385 num_channels = of_get_available_child_count(np);1386 else1387 num_channels = 1;1388 1389 led = devm_kzalloc(lpg->dev, struct_size(led, channels, num_channels), GFP_KERNEL);1390 if (!led)1391 return -ENOMEM;1392 1393 led->lpg = lpg;1394 led->num_channels = num_channels;1395 1396 if (color == LED_COLOR_ID_RGB) {1397 info = devm_kcalloc(lpg->dev, num_channels, sizeof(*info), GFP_KERNEL);1398 if (!info)1399 return -ENOMEM;1400 i = 0;1401 for_each_available_child_of_node_scoped(np, child) {1402 ret = lpg_parse_channel(lpg, child, &led->channels[i]);1403 if (ret < 0)1404 return ret;1405 1406 info[i].color_index = led->channels[i]->color;1407 info[i].intensity = 0;1408 i++;1409 }1410 1411 led->mcdev.subled_info = info;1412 led->mcdev.num_colors = num_channels;1413 1414 cdev = &led->mcdev.led_cdev;1415 cdev->brightness_set_blocking = lpg_brightness_mc_set;1416 cdev->blink_set = lpg_blink_mc_set;1417 1418 /* Register pattern accessors if we have a LUT block or when using PPG */1419 if (lpg->lut_base || lpg->lpg_chan_sdam) {1420 cdev->pattern_set = lpg_pattern_mc_set;1421 cdev->pattern_clear = lpg_pattern_mc_clear;1422 }1423 } else {1424 ret = lpg_parse_channel(lpg, np, &led->channels[0]);1425 if (ret < 0)1426 return ret;1427 1428 cdev = &led->cdev;1429 cdev->brightness_set_blocking = lpg_brightness_single_set;1430 cdev->blink_set = lpg_blink_single_set;1431 1432 /* Register pattern accessors if we have a LUT block or when using PPG */1433 if (lpg->lut_base || lpg->lpg_chan_sdam) {1434 cdev->pattern_set = lpg_pattern_single_set;1435 cdev->pattern_clear = lpg_pattern_single_clear;1436 }1437 }1438 1439 cdev->default_trigger = of_get_property(np, "linux,default-trigger", NULL);1440 1441 if (lpg->lpg_chan_sdam)1442 cdev->max_brightness = PPG_MAX_LED_BRIGHTNESS;1443 else1444 cdev->max_brightness = LPG_RESOLUTION_9BIT - 1;1445 1446 if (!of_property_read_string(np, "default-state", &state) &&1447 !strcmp(state, "on"))1448 cdev->brightness = cdev->max_brightness;1449 else1450 cdev->brightness = LED_OFF;1451 1452 cdev->brightness_set_blocking(cdev, cdev->brightness);1453 1454 init_data.fwnode = of_fwnode_handle(np);1455 1456 if (color == LED_COLOR_ID_RGB)1457 ret = devm_led_classdev_multicolor_register_ext(lpg->dev, &led->mcdev, &init_data);1458 else1459 ret = devm_led_classdev_register_ext(lpg->dev, &led->cdev, &init_data);1460 if (ret)1461 dev_err_probe(lpg->dev, ret, "unable to register %s\n", cdev->name);1462 1463 return ret;1464}1465 1466static int lpg_init_channels(struct lpg *lpg)1467{1468 const struct lpg_data *data = lpg->data;1469 struct lpg_channel *chan;1470 int i;1471 1472 lpg->num_channels = data->num_channels;1473 lpg->channels = devm_kcalloc(lpg->dev, data->num_channels,1474 sizeof(struct lpg_channel), GFP_KERNEL);1475 if (!lpg->channels)1476 return -ENOMEM;1477 1478 for (i = 0; i < data->num_channels; i++) {1479 chan = &lpg->channels[i];1480 1481 chan->lpg = lpg;1482 chan->base = data->channels[i].base;1483 chan->triled_mask = data->channels[i].triled_mask;1484 chan->lut_mask = BIT(i);1485 chan->sdam_offset = data->channels[i].sdam_offset;1486 1487 regmap_read(lpg->map, chan->base + LPG_SUBTYPE_REG, &chan->subtype);1488 }1489 1490 return 0;1491}1492 1493static int lpg_init_triled(struct lpg *lpg)1494{1495 struct device_node *np = lpg->dev->of_node;1496 int ret;1497 1498 /* Skip initialization if we don't have a triled block */1499 if (!lpg->data->triled_base)1500 return 0;1501 1502 lpg->triled_base = lpg->data->triled_base;1503 lpg->triled_has_atc_ctl = lpg->data->triled_has_atc_ctl;1504 lpg->triled_has_src_sel = lpg->data->triled_has_src_sel;1505 1506 if (lpg->triled_has_src_sel) {1507 ret = of_property_read_u32(np, "qcom,power-source", &lpg->triled_src);1508 if (ret || lpg->triled_src == 2 || lpg->triled_src > 3)1509 return dev_err_probe(lpg->dev, -EINVAL,1510 "invalid power source\n");1511 }1512 1513 /* Disable automatic trickle charge LED */1514 if (lpg->triled_has_atc_ctl)1515 regmap_write(lpg->map, lpg->triled_base + TRI_LED_ATC_CTL, 0);1516 1517 /* Configure power source */1518 if (lpg->triled_has_src_sel)1519 regmap_write(lpg->map, lpg->triled_base + TRI_LED_SRC_SEL, lpg->triled_src);1520 1521 /* Default all outputs to off */1522 regmap_write(lpg->map, lpg->triled_base + TRI_LED_EN_CTL, 0);1523 1524 return 0;1525}1526 1527static int lpg_init_lut(struct lpg *lpg)1528{1529 const struct lpg_data *data = lpg->data;1530 1531 if (!data->lut_size)1532 return 0;1533 1534 lpg->lut_size = data->lut_size;1535 if (data->lut_base)1536 lpg->lut_base = data->lut_base;1537 1538 lpg->lut_bitmap = devm_bitmap_zalloc(lpg->dev, lpg->lut_size, GFP_KERNEL);1539 if (!lpg->lut_bitmap)1540 return -ENOMEM;1541 1542 return 0;1543}1544 1545static int lpg_init_sdam(struct lpg *lpg)1546{1547 int i, sdam_count, rc;1548 u8 val = 0;1549 1550 sdam_count = of_property_count_strings(lpg->dev->of_node, "nvmem-names");1551 if (sdam_count <= 0)1552 return 0;1553 if (sdam_count > SDAM_MAX_DEVICES)1554 return -EINVAL;1555 1556 /* Get the 1st SDAM device for LPG/LUT config */1557 lpg->lpg_chan_sdam = devm_nvmem_device_get(lpg->dev, "lpg_chan_sdam");1558 if (IS_ERR(lpg->lpg_chan_sdam))1559 return dev_err_probe(lpg->dev, PTR_ERR(lpg->lpg_chan_sdam),1560 "Failed to get LPG chan SDAM device\n");1561 1562 if (sdam_count == 1) {1563 /* Get PBS device node if single SDAM device */1564 lpg->pbs_dev = get_pbs_client_device(lpg->dev);1565 if (IS_ERR(lpg->pbs_dev))1566 return dev_err_probe(lpg->dev, PTR_ERR(lpg->pbs_dev),1567 "Failed to get PBS client device\n");1568 } else if (sdam_count == 2) {1569 /* Get the 2nd SDAM device for LUT pattern */1570 lpg->lut_sdam = devm_nvmem_device_get(lpg->dev, "lut_sdam");1571 if (IS_ERR(lpg->lut_sdam))1572 return dev_err_probe(lpg->dev, PTR_ERR(lpg->lut_sdam),1573 "Failed to get LPG LUT SDAM device\n");1574 }1575 1576 for (i = 0; i < lpg->num_channels; i++) {1577 struct lpg_channel *chan = &lpg->channels[i];1578 1579 if (chan->sdam_offset) {1580 rc = nvmem_device_write(lpg->lpg_chan_sdam,1581 SDAM_PBS_SCRATCH_LUT_COUNTER_OFFSET + chan->sdam_offset, 1, &val);1582 if (rc < 0)1583 return rc;1584 1585 rc = lpg_sdam_configure_triggers(chan, 0);1586 if (rc < 0)1587 return rc;1588 1589 rc = lpg_clear_pbs_trigger(chan->lpg, chan->lut_mask);1590 if (rc < 0)1591 return rc;1592 }1593 }1594 1595 return 0;1596}1597 1598static int lpg_probe(struct platform_device *pdev)1599{1600 struct lpg *lpg;1601 int ret;1602 int i;1603 1604 lpg = devm_kzalloc(&pdev->dev, sizeof(*lpg), GFP_KERNEL);1605 if (!lpg)1606 return -ENOMEM;1607 1608 lpg->data = of_device_get_match_data(&pdev->dev);1609 if (!lpg->data)1610 return -EINVAL;1611 1612 lpg->dev = &pdev->dev;1613 mutex_init(&lpg->lock);1614 1615 lpg->map = dev_get_regmap(pdev->dev.parent, NULL);1616 if (!lpg->map)1617 return dev_err_probe(&pdev->dev, -ENXIO, "parent regmap unavailable\n");1618 1619 ret = lpg_init_channels(lpg);1620 if (ret < 0)1621 return ret;1622 1623 ret = lpg_parse_dtest(lpg);1624 if (ret < 0)1625 return ret;1626 1627 ret = lpg_init_triled(lpg);1628 if (ret < 0)1629 return ret;1630 1631 ret = lpg_init_sdam(lpg);1632 if (ret < 0)1633 return ret;1634 1635 ret = lpg_init_lut(lpg);1636 if (ret < 0)1637 return ret;1638 1639 for_each_available_child_of_node_scoped(pdev->dev.of_node, np) {1640 ret = lpg_add_led(lpg, np);1641 if (ret)1642 return ret;1643 }1644 1645 for (i = 0; i < lpg->num_channels; i++)1646 lpg_apply_dtest(&lpg->channels[i]);1647 1648 return lpg_add_pwm(lpg);1649}1650 1651static const struct lpg_data pm660l_lpg_data = {1652 .lut_base = 0xb000,1653 .lut_size = 49,1654 1655 .triled_base = 0xd000,1656 .triled_has_atc_ctl = true,1657 .triled_has_src_sel = true,1658 1659 .num_channels = 4,1660 .channels = (const struct lpg_channel_data[]) {1661 { .base = 0xb100, .triled_mask = BIT(5) },1662 { .base = 0xb200, .triled_mask = BIT(6) },1663 { .base = 0xb300, .triled_mask = BIT(7) },1664 { .base = 0xb400 },1665 },1666};1667 1668static const struct lpg_data pm8916_pwm_data = {1669 .num_channels = 1,1670 .channels = (const struct lpg_channel_data[]) {1671 { .base = 0xbc00 },1672 },1673};1674 1675static const struct lpg_data pm8941_lpg_data = {1676 .lut_base = 0xb000,1677 .lut_size = 64,1678 1679 .triled_base = 0xd000,1680 .triled_has_atc_ctl = true,1681 .triled_has_src_sel = true,1682 1683 .num_channels = 8,1684 .channels = (const struct lpg_channel_data[]) {1685 { .base = 0xb100 },1686 { .base = 0xb200 },1687 { .base = 0xb300 },1688 { .base = 0xb400 },1689 { .base = 0xb500, .triled_mask = BIT(5) },1690 { .base = 0xb600, .triled_mask = BIT(6) },1691 { .base = 0xb700, .triled_mask = BIT(7) },1692 { .base = 0xb800 },1693 },1694};1695 1696static const struct lpg_data pmi8950_pwm_data = {1697 .num_channels = 1,1698 .channels = (const struct lpg_channel_data[]) {1699 { .base = 0xb000 },1700 },1701};1702 1703static const struct lpg_data pm8994_lpg_data = {1704 .lut_base = 0xb000,1705 .lut_size = 64,1706 1707 .num_channels = 6,1708 .channels = (const struct lpg_channel_data[]) {1709 { .base = 0xb100 },1710 { .base = 0xb200 },1711 { .base = 0xb300 },1712 { .base = 0xb400 },1713 { .base = 0xb500 },1714 { .base = 0xb600 },1715 },1716};1717 1718/* PMI632 uses SDAM instead of LUT for pattern */1719static const struct lpg_data pmi632_lpg_data = {1720 .triled_base = 0xd000,1721 1722 .lut_size = 64,1723 1724 .num_channels = 5,1725 .channels = (const struct lpg_channel_data[]) {1726 { .base = 0xb300, .triled_mask = BIT(7), .sdam_offset = 0x48 },1727 { .base = 0xb400, .triled_mask = BIT(6), .sdam_offset = 0x56 },1728 { .base = 0xb500, .triled_mask = BIT(5), .sdam_offset = 0x64 },1729 { .base = 0xb600 },1730 { .base = 0xb700 },1731 },1732};1733 1734static const struct lpg_data pmi8994_lpg_data = {1735 .lut_base = 0xb000,1736 .lut_size = 24,1737 1738 .triled_base = 0xd000,1739 .triled_has_atc_ctl = true,1740 .triled_has_src_sel = true,1741 1742 .num_channels = 4,1743 .channels = (const struct lpg_channel_data[]) {1744 { .base = 0xb100, .triled_mask = BIT(5) },1745 { .base = 0xb200, .triled_mask = BIT(6) },1746 { .base = 0xb300, .triled_mask = BIT(7) },1747 { .base = 0xb400 },1748 },1749};1750 1751static const struct lpg_data pmi8998_lpg_data = {1752 .lut_base = 0xb000,1753 .lut_size = 49,1754 1755 .triled_base = 0xd000,1756 1757 .num_channels = 6,1758 .channels = (const struct lpg_channel_data[]) {1759 { .base = 0xb100 },1760 { .base = 0xb200 },1761 { .base = 0xb300, .triled_mask = BIT(5) },1762 { .base = 0xb400, .triled_mask = BIT(6) },1763 { .base = 0xb500, .triled_mask = BIT(7) },1764 { .base = 0xb600 },1765 },1766};1767 1768static const struct lpg_data pm8150b_lpg_data = {1769 .lut_base = 0xb000,1770 .lut_size = 24,1771 1772 .triled_base = 0xd000,1773 1774 .num_channels = 2,1775 .channels = (const struct lpg_channel_data[]) {1776 { .base = 0xb100, .triled_mask = BIT(7) },1777 { .base = 0xb200, .triled_mask = BIT(6) },1778 },1779};1780 1781static const struct lpg_data pm8150l_lpg_data = {1782 .lut_base = 0xb000,1783 .lut_size = 48,1784 1785 .triled_base = 0xd000,1786 1787 .num_channels = 5,1788 .channels = (const struct lpg_channel_data[]) {1789 { .base = 0xb100, .triled_mask = BIT(7) },1790 { .base = 0xb200, .triled_mask = BIT(6) },1791 { .base = 0xb300, .triled_mask = BIT(5) },1792 { .base = 0xbc00 },1793 { .base = 0xbd00 },1794 1795 },1796};1797 1798static const struct lpg_data pm8350c_pwm_data = {1799 .triled_base = 0xef00,1800 1801 .lut_size = 122,1802 1803 .num_channels = 4,1804 .channels = (const struct lpg_channel_data[]) {1805 { .base = 0xe800, .triled_mask = BIT(7), .sdam_offset = 0x48 },1806 { .base = 0xe900, .triled_mask = BIT(6), .sdam_offset = 0x56 },1807 { .base = 0xea00, .triled_mask = BIT(5), .sdam_offset = 0x64 },1808 { .base = 0xeb00 },1809 },1810};1811 1812static const struct lpg_data pmk8550_pwm_data = {1813 .num_channels = 2,1814 .channels = (const struct lpg_channel_data[]) {1815 { .base = 0xe800 },1816 { .base = 0xe900 },1817 },1818};1819 1820static const struct of_device_id lpg_of_table[] = {1821 { .compatible = "qcom,pm660l-lpg", .data = &pm660l_lpg_data },1822 { .compatible = "qcom,pm8150b-lpg", .data = &pm8150b_lpg_data },1823 { .compatible = "qcom,pm8150l-lpg", .data = &pm8150l_lpg_data },1824 { .compatible = "qcom,pm8350c-pwm", .data = &pm8350c_pwm_data },1825 { .compatible = "qcom,pm8916-pwm", .data = &pm8916_pwm_data },1826 { .compatible = "qcom,pm8941-lpg", .data = &pm8941_lpg_data },1827 { .compatible = "qcom,pm8994-lpg", .data = &pm8994_lpg_data },1828 { .compatible = "qcom,pmi632-lpg", .data = &pmi632_lpg_data },1829 { .compatible = "qcom,pmi8950-pwm", .data = &pmi8950_pwm_data },1830 { .compatible = "qcom,pmi8994-lpg", .data = &pmi8994_lpg_data },1831 { .compatible = "qcom,pmi8998-lpg", .data = &pmi8998_lpg_data },1832 { .compatible = "qcom,pmc8180c-lpg", .data = &pm8150l_lpg_data },1833 { .compatible = "qcom,pmk8550-pwm", .data = &pmk8550_pwm_data },1834 {}1835};1836MODULE_DEVICE_TABLE(of, lpg_of_table);1837 1838static struct platform_driver lpg_driver = {1839 .probe = lpg_probe,1840 .driver = {1841 .name = "qcom-spmi-lpg",1842 .of_match_table = lpg_of_table,1843 },1844};1845module_platform_driver(lpg_driver);1846 1847MODULE_DESCRIPTION("Qualcomm LPG LED driver");1848MODULE_LICENSE("GPL v2");1849