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1# SPDX-License-Identifier: GPL-2.0-only2menuconfig MAILBOX3 bool "Mailbox Hardware Support"4 help5 Mailbox is a framework to control hardware communication between6 on-chip processors through queued messages and interrupt driven7 signals. Say Y if your platform supports hardware mailboxes.8 9if MAILBOX10 11config ARM_MHU12 tristate "ARM MHU Mailbox"13 depends on ARM_AMBA14 help15 Say Y here if you want to build the ARM MHU controller driver.16 The controller has 3 mailbox channels, the last of which can be17 used in Secure mode only.18 19config ARM_MHU_V220 tristate "ARM MHUv2 Mailbox"21 depends on ARM_AMBA22 help23 Say Y here if you want to build the ARM MHUv2 controller driver,24 which provides unidirectional mailboxes between processing elements.25 26config ARM_MHU_V327 tristate "ARM MHUv3 Mailbox"28 depends on ARM64 || COMPILE_TEST29 depends on HAS_IOMEM || COMPILE_TEST30 depends on OF31 help32 Say Y here if you want to build the ARM MHUv3 controller driver,33 which provides unidirectional mailboxes between processing elements.34 35 ARM MHUv3 controllers can implement a varying number of extensions36 that provides different means of transports: supported extensions37 will be discovered and possibly managed at probe-time.38 39config IMX_MBOX40 tristate "i.MX Mailbox"41 depends on ARCH_MXC || COMPILE_TEST42 help43 Mailbox implementation for i.MX Messaging Unit (MU).44 45config PLATFORM_MHU46 tristate "Platform MHU Mailbox"47 depends on OF48 depends on HAS_IOMEM49 help50 Say Y here if you want to build a platform specific variant MHU51 controller driver.52 The controller has a maximum of 3 mailbox channels, the last of53 which can be used in Secure mode only.54 55config PL320_MBOX56 bool "ARM PL320 Mailbox"57 depends on ARM_AMBA58 help59 An implementation of the ARM PL320 Interprocessor Communication60 Mailbox (IPCM), tailored for the Calxeda Highbank. It is used to61 send short messages between Highbank's A9 cores and the EnergyCore62 Management Engine, primarily for cpufreq. Say Y here if you want63 to use the PL320 IPCM support.64 65config ARMADA_37XX_RWTM_MBOX66 tristate "Armada 37xx rWTM BIU Mailbox"67 depends on ARCH_MVEBU || COMPILE_TEST68 depends on OF69 help70 Mailbox implementation for communication with the the firmware71 running on the Cortex-M3 rWTM secure processor of the Armada 37xx72 SOC. Say Y here if you are building for such a device (for example73 the Turris Mox router).74 75config OMAP2PLUS_MBOX76 tristate "OMAP2+ Mailbox framework support"77 depends on ARCH_OMAP2PLUS || ARCH_K3 || COMPILE_TEST78 help79 Mailbox implementation for OMAP family chips with hardware for80 interprocessor communication involving DSP, IVA1.0 and IVA2 in81 OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you82 want to use OMAP2+ Mailbox framework support.83 84config ROCKCHIP_MBOX85 bool "Rockchip Soc Integrated Mailbox Support"86 depends on ARCH_ROCKCHIP || COMPILE_TEST87 help88 This driver provides support for inter-processor communication89 between CPU cores and MCU processor on Some Rockchip SOCs.90 Please check it that the Soc you use have Mailbox hardware.91 Say Y here if you want to use the Rockchip Mailbox support.92 93config PCC94 bool "Platform Communication Channel Driver"95 depends on ACPI96 default n97 help98 ACPI 5.0+ spec defines a generic mode of communication99 between the OS and a platform such as the BMC. This medium100 (PCC) is typically used by CPPC (ACPI CPU Performance management),101 RAS (ACPI reliability protocol) and MPST (ACPI Memory power102 states). Select this driver if your platform implements the103 PCC clients mentioned above.104 105config ALTERA_MBOX106 tristate "Altera Mailbox"107 depends on HAS_IOMEM108 help109 An implementation of the Altera Mailbox soft core. It is used110 to send message between processors. Say Y here if you want to use the111 Altera mailbox support.112 113config BCM2835_MBOX114 tristate "BCM2835 Mailbox"115 depends on ARCH_BCM2835116 help117 An implementation of the BCM2385 Mailbox. It is used to invoke118 the services of the Videocore. Say Y here if you want to use the119 BCM2835 Mailbox.120 121config STI_MBOX122 tristate "STI Mailbox framework support"123 depends on ARCH_STI && OF124 help125 Mailbox implementation for STMicroelectonics family chips with126 hardware for interprocessor communication.127 128config TI_MESSAGE_MANAGER129 tristate "Texas Instruments Message Manager Driver"130 depends on ARCH_KEYSTONE || ARCH_K3131 default ARCH_K3132 help133 An implementation of Message Manager slave driver for Keystone134 and K3 architecture SoCs from Texas Instruments. Message Manager135 is a communication entity found on few of Texas Instrument's keystone136 and K3 architecture SoCs. These may be used for communication between137 multiple processors within the SoC. Select this driver if your138 platform has support for the hardware block.139 140config HI3660_MBOX141 tristate "Hi3660 Mailbox" if EXPERT142 depends on (ARCH_HISI || COMPILE_TEST)143 depends on OF144 default ARCH_HISI145 help146 An implementation of the hi3660 mailbox. It is used to send message147 between application processors and other processors/MCU/DSP. Select148 Y here if you want to use Hi3660 mailbox controller.149 150config HI6220_MBOX151 tristate "Hi6220 Mailbox" if EXPERT152 depends on (ARCH_HISI || COMPILE_TEST)153 depends on OF154 default ARCH_HISI155 help156 An implementation of the hi6220 mailbox. It is used to send message157 between application processors and MCU. Say Y here if you want to158 build Hi6220 mailbox controller driver.159 160config MAILBOX_TEST161 tristate "Mailbox Test Client"162 depends on OF163 depends on HAS_IOMEM164 help165 Test client to help with testing new Controller driver166 implementations.167 168config POLARFIRE_SOC_MAILBOX169 tristate "PolarFire SoC (MPFS) Mailbox"170 depends on HAS_IOMEM171 depends on ARCH_MICROCHIP_POLARFIRE || COMPILE_TEST172 help173 This driver adds support for the PolarFire SoC (MPFS) mailbox controller.174 175 To compile this driver as a module, choose M here. the176 module will be called mailbox-mpfs.177 178 If unsure, say N.179 180config QCOM_APCS_IPC181 tristate "Qualcomm APCS IPC driver"182 depends on ARCH_QCOM || COMPILE_TEST183 help184 Say y here to enable support for the APCS IPC mailbox driver,185 providing an interface for invoking the inter-process communication186 signals from the application processor to other masters.187 188config TEGRA_HSP_MBOX189 bool "Tegra HSP (Hardware Synchronization Primitives) Driver"190 depends on ARCH_TEGRA191 help192 The Tegra HSP driver is used for the interprocessor communication193 between different remote processors and host processors on Tegra186194 and later SoCs. Say Y here if you want to have this support.195 If unsure say N.196 197config XGENE_SLIMPRO_MBOX198 tristate "APM SoC X-Gene SLIMpro Mailbox Controller"199 depends on ARCH_XGENE200 help201 An implementation of the APM X-Gene Interprocessor Communication202 Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.203 It is used to send short messages between ARM64-bit cores and204 the SLIMpro Management Engine, primarily for PM. Say Y here if you205 want to use the APM X-Gene SLIMpro IPCM support.206 207config BCM_PDC_MBOX208 tristate "Broadcom FlexSparx DMA Mailbox"209 depends on ARCH_BCM_IPROC || COMPILE_TEST210 help211 Mailbox implementation for the Broadcom FlexSparx DMA ring manager,212 which provides access to various offload engines on Broadcom213 SoCs, including FA2/FA+ on Northstar Plus and PDC on Northstar 2.214 215config BCM_FLEXRM_MBOX216 tristate "Broadcom FlexRM Mailbox"217 depends on ARM64218 depends on ARCH_BCM_IPROC || COMPILE_TEST219 select GENERIC_MSI_IRQ220 default m if ARCH_BCM_IPROC221 help222 Mailbox implementation of the Broadcom FlexRM ring manager,223 which provides access to various offload engines on Broadcom224 SoCs. Say Y here if you want to use the Broadcom FlexRM.225 226config STM32_IPCC227 tristate "STM32 IPCC Mailbox"228 depends on MACH_STM32MP157 || COMPILE_TEST229 help230 Mailbox implementation for STMicroelectonics STM32 family chips231 with hardware for Inter-Processor Communication Controller (IPCC)232 between processors. Say Y here if you want to have this support.233 234config MTK_ADSP_MBOX235 tristate "MediaTek ADSP Mailbox Controller"236 depends on ARCH_MEDIATEK || COMPILE_TEST237 help238 Say yes here to add support for "MediaTek ADSP Mailbox Controller.239 This mailbox driver is used to send notification or short message240 between processors with ADSP. It will place the message to share241 buffer and will access the ipc control.242 243config MTK_CMDQ_MBOX244 tristate "MediaTek CMDQ Mailbox Support"245 depends on ARCH_MEDIATEK || COMPILE_TEST246 select MTK_INFRACFG247 help248 Say yes here to add support for the MediaTek Command Queue (CMDQ)249 mailbox driver. The CMDQ is used to help read/write registers with250 critical time limitation, such as updating display configuration251 during the vblank.252 253config ZYNQMP_IPI_MBOX254 tristate "Xilinx ZynqMP IPI Mailbox"255 depends on ARCH_ZYNQMP && OF256 help257 Say yes here to add support for Xilinx IPI mailbox driver.258 This mailbox driver is used to send notification or short message259 between processors with Xilinx ZynqMP IPI. It will place the260 message to the IPI buffer and will access the IPI control261 registers to kick the other processor or enquire status.262 263config SUN6I_MSGBOX264 tristate "Allwinner sun6i/sun8i/sun9i/sun50i Message Box"265 depends on ARCH_SUNXI || COMPILE_TEST266 default ARCH_SUNXI267 help268 Mailbox implementation for the hardware message box present in269 various Allwinner SoCs. This mailbox is used for communication270 between the application CPUs and the power management coprocessor.271 272config SPRD_MBOX273 tristate "Spreadtrum Mailbox"274 depends on ARCH_SPRD || COMPILE_TEST275 help276 Mailbox driver implementation for the Spreadtrum platform. It is used277 to send message between application processors and MCU. Say Y here if278 you want to build the Spreatrum mailbox controller driver.279 280config QCOM_CPUCP_MBOX281 tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"282 depends on (ARCH_QCOM || COMPILE_TEST) && 64BIT283 help284 Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox285 controller driver enables communication between AP and CPUCP. Say286 Y here if you want to build this driver.287 288config QCOM_IPCC289 tristate "Qualcomm Technologies, Inc. IPCC driver"290 depends on ARCH_QCOM || COMPILE_TEST291 help292 Qualcomm Technologies, Inc. Inter-Processor Communication Controller293 (IPCC) driver for MSM devices. The driver provides mailbox support for294 sending interrupts to the clients. On the other hand, the driver also295 acts as an interrupt controller for receiving interrupts from clients.296 Say Y here if you want to build this driver.297 298endif299