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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.4 */5 6#include <linux/bitfield.h>7#include <linux/interrupt.h>8#include <linux/irq.h>9#include <linux/irqdomain.h>10#include <linux/mailbox_controller.h>11#include <linux/module.h>12#include <linux/platform_device.h>13 14#include <dt-bindings/mailbox/qcom-ipcc.h>15 16/* IPCC Register offsets */17#define IPCC_REG_SEND_ID 0x0c18#define IPCC_REG_RECV_ID 0x1019#define IPCC_REG_RECV_SIGNAL_ENABLE 0x1420#define IPCC_REG_RECV_SIGNAL_DISABLE 0x1821#define IPCC_REG_RECV_SIGNAL_CLEAR 0x1c22#define IPCC_REG_CLIENT_CLEAR 0x3823 24#define IPCC_SIGNAL_ID_MASK GENMASK(15, 0)25#define IPCC_CLIENT_ID_MASK GENMASK(31, 16)26 27#define IPCC_NO_PENDING_IRQ GENMASK(31, 0)28 29/**30 * struct qcom_ipcc_chan_info - Per-mailbox-channel info31 * @client_id: The client-id to which the interrupt has to be triggered32 * @signal_id: The signal-id to which the interrupt has to be triggered33 */34struct qcom_ipcc_chan_info {35 u16 client_id;36 u16 signal_id;37};38 39/**40 * struct qcom_ipcc - Holder for the mailbox driver41 * @dev: Device associated with this instance42 * @base: Base address of the IPCC frame associated to APSS43 * @irq_domain: The irq_domain associated with this instance44 * @chans: The mailbox channels array45 * @mchan: The per-mailbox channel info array46 * @mbox: The mailbox controller47 * @num_chans: Number of @chans elements48 * @irq: Summary irq49 */50struct qcom_ipcc {51 struct device *dev;52 void __iomem *base;53 struct irq_domain *irq_domain;54 struct mbox_chan *chans;55 struct qcom_ipcc_chan_info *mchan;56 struct mbox_controller mbox;57 int num_chans;58 int irq;59};60 61static inline struct qcom_ipcc *to_qcom_ipcc(struct mbox_controller *mbox)62{63 return container_of(mbox, struct qcom_ipcc, mbox);64}65 66static inline u32 qcom_ipcc_get_hwirq(u16 client_id, u16 signal_id)67{68 return FIELD_PREP(IPCC_CLIENT_ID_MASK, client_id) |69 FIELD_PREP(IPCC_SIGNAL_ID_MASK, signal_id);70}71 72static irqreturn_t qcom_ipcc_irq_fn(int irq, void *data)73{74 struct qcom_ipcc *ipcc = data;75 u32 hwirq;76 int virq;77 78 for (;;) {79 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);80 if (hwirq == IPCC_NO_PENDING_IRQ)81 break;82 83 virq = irq_find_mapping(ipcc->irq_domain, hwirq);84 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_CLEAR);85 generic_handle_irq(virq);86 }87 88 return IRQ_HANDLED;89}90 91static void qcom_ipcc_mask_irq(struct irq_data *irqd)92{93 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);94 irq_hw_number_t hwirq = irqd_to_hwirq(irqd);95 96 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_DISABLE);97}98 99static void qcom_ipcc_unmask_irq(struct irq_data *irqd)100{101 struct qcom_ipcc *ipcc = irq_data_get_irq_chip_data(irqd);102 irq_hw_number_t hwirq = irqd_to_hwirq(irqd);103 104 writel(hwirq, ipcc->base + IPCC_REG_RECV_SIGNAL_ENABLE);105}106 107static struct irq_chip qcom_ipcc_irq_chip = {108 .name = "ipcc",109 .irq_mask = qcom_ipcc_mask_irq,110 .irq_unmask = qcom_ipcc_unmask_irq,111 .flags = IRQCHIP_SKIP_SET_WAKE,112};113 114static int qcom_ipcc_domain_map(struct irq_domain *d, unsigned int irq,115 irq_hw_number_t hw)116{117 struct qcom_ipcc *ipcc = d->host_data;118 119 irq_set_chip_and_handler(irq, &qcom_ipcc_irq_chip, handle_level_irq);120 irq_set_chip_data(irq, ipcc);121 irq_set_noprobe(irq);122 123 return 0;124}125 126static int qcom_ipcc_domain_xlate(struct irq_domain *d,127 struct device_node *node, const u32 *intspec,128 unsigned int intsize,129 unsigned long *out_hwirq,130 unsigned int *out_type)131{132 if (intsize != 3)133 return -EINVAL;134 135 *out_hwirq = qcom_ipcc_get_hwirq(intspec[0], intspec[1]);136 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;137 138 return 0;139}140 141static const struct irq_domain_ops qcom_ipcc_irq_ops = {142 .map = qcom_ipcc_domain_map,143 .xlate = qcom_ipcc_domain_xlate,144};145 146static int qcom_ipcc_mbox_send_data(struct mbox_chan *chan, void *data)147{148 struct qcom_ipcc *ipcc = to_qcom_ipcc(chan->mbox);149 struct qcom_ipcc_chan_info *mchan = chan->con_priv;150 u32 hwirq;151 152 hwirq = qcom_ipcc_get_hwirq(mchan->client_id, mchan->signal_id);153 writel(hwirq, ipcc->base + IPCC_REG_SEND_ID);154 155 return 0;156}157 158static void qcom_ipcc_mbox_shutdown(struct mbox_chan *chan)159{160 chan->con_priv = NULL;161}162 163static struct mbox_chan *qcom_ipcc_mbox_xlate(struct mbox_controller *mbox,164 const struct of_phandle_args *ph)165{166 struct qcom_ipcc *ipcc = to_qcom_ipcc(mbox);167 struct qcom_ipcc_chan_info *mchan;168 struct mbox_chan *chan;169 struct device *dev;170 int chan_id;171 172 dev = ipcc->dev;173 174 if (ph->args_count != 2)175 return ERR_PTR(-EINVAL);176 177 for (chan_id = 0; chan_id < mbox->num_chans; chan_id++) {178 chan = &ipcc->chans[chan_id];179 mchan = chan->con_priv;180 181 if (!mchan)182 break;183 else if (mchan->client_id == ph->args[0] &&184 mchan->signal_id == ph->args[1])185 return ERR_PTR(-EBUSY);186 }187 188 if (chan_id >= mbox->num_chans)189 return ERR_PTR(-EBUSY);190 191 mchan = devm_kzalloc(dev, sizeof(*mchan), GFP_KERNEL);192 if (!mchan)193 return ERR_PTR(-ENOMEM);194 195 mchan->client_id = ph->args[0];196 mchan->signal_id = ph->args[1];197 chan->con_priv = mchan;198 199 return chan;200}201 202static const struct mbox_chan_ops ipcc_mbox_chan_ops = {203 .send_data = qcom_ipcc_mbox_send_data,204 .shutdown = qcom_ipcc_mbox_shutdown,205};206 207static int qcom_ipcc_setup_mbox(struct qcom_ipcc *ipcc,208 struct device_node *controller_dn)209{210 struct of_phandle_args curr_ph;211 struct device_node *client_dn;212 struct mbox_controller *mbox;213 struct device *dev = ipcc->dev;214 int i, j, ret;215 216 /*217 * Find out the number of clients interested in this mailbox218 * and create channels accordingly.219 */220 ipcc->num_chans = 0;221 for_each_node_with_property(client_dn, "mboxes") {222 if (!of_device_is_available(client_dn))223 continue;224 i = of_count_phandle_with_args(client_dn,225 "mboxes", "#mbox-cells");226 for (j = 0; j < i; j++) {227 ret = of_parse_phandle_with_args(client_dn, "mboxes",228 "#mbox-cells", j, &curr_ph);229 of_node_put(curr_ph.np);230 if (!ret && curr_ph.np == controller_dn)231 ipcc->num_chans++;232 }233 }234 235 /* If no clients are found, skip registering as a mbox controller */236 if (!ipcc->num_chans)237 return 0;238 239 ipcc->chans = devm_kcalloc(dev, ipcc->num_chans,240 sizeof(struct mbox_chan), GFP_KERNEL);241 if (!ipcc->chans)242 return -ENOMEM;243 244 mbox = &ipcc->mbox;245 mbox->dev = dev;246 mbox->num_chans = ipcc->num_chans;247 mbox->chans = ipcc->chans;248 mbox->ops = &ipcc_mbox_chan_ops;249 mbox->of_xlate = qcom_ipcc_mbox_xlate;250 mbox->txdone_irq = false;251 mbox->txdone_poll = false;252 253 return devm_mbox_controller_register(dev, mbox);254}255 256static int qcom_ipcc_pm_resume(struct device *dev)257{258 struct qcom_ipcc *ipcc = dev_get_drvdata(dev);259 u32 hwirq;260 int virq;261 262 hwirq = readl(ipcc->base + IPCC_REG_RECV_ID);263 if (hwirq == IPCC_NO_PENDING_IRQ)264 return 0;265 266 virq = irq_find_mapping(ipcc->irq_domain, hwirq);267 268 dev_dbg(dev, "virq: %d triggered client-id: %ld; signal-id: %ld\n", virq,269 FIELD_GET(IPCC_CLIENT_ID_MASK, hwirq), FIELD_GET(IPCC_SIGNAL_ID_MASK, hwirq));270 271 return 0;272}273 274static int qcom_ipcc_probe(struct platform_device *pdev)275{276 struct qcom_ipcc *ipcc;277 static int id;278 char *name;279 int ret;280 281 ipcc = devm_kzalloc(&pdev->dev, sizeof(*ipcc), GFP_KERNEL);282 if (!ipcc)283 return -ENOMEM;284 285 ipcc->dev = &pdev->dev;286 287 ipcc->base = devm_platform_ioremap_resource(pdev, 0);288 if (IS_ERR(ipcc->base))289 return PTR_ERR(ipcc->base);290 291 ipcc->irq = platform_get_irq(pdev, 0);292 if (ipcc->irq < 0)293 return ipcc->irq;294 295 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "ipcc_%d", id++);296 if (!name)297 return -ENOMEM;298 299 ipcc->irq_domain = irq_domain_add_tree(pdev->dev.of_node,300 &qcom_ipcc_irq_ops, ipcc);301 if (!ipcc->irq_domain)302 return -ENOMEM;303 304 ret = qcom_ipcc_setup_mbox(ipcc, pdev->dev.of_node);305 if (ret)306 goto err_mbox;307 308 ret = devm_request_irq(&pdev->dev, ipcc->irq, qcom_ipcc_irq_fn,309 IRQF_TRIGGER_HIGH | IRQF_NO_SUSPEND |310 IRQF_NO_THREAD, name, ipcc);311 if (ret < 0) {312 dev_err(&pdev->dev, "Failed to register the irq: %d\n", ret);313 goto err_req_irq;314 }315 316 platform_set_drvdata(pdev, ipcc);317 318 return 0;319 320err_req_irq:321 if (ipcc->num_chans)322 mbox_controller_unregister(&ipcc->mbox);323err_mbox:324 irq_domain_remove(ipcc->irq_domain);325 326 return ret;327}328 329static void qcom_ipcc_remove(struct platform_device *pdev)330{331 struct qcom_ipcc *ipcc = platform_get_drvdata(pdev);332 333 disable_irq_wake(ipcc->irq);334 irq_domain_remove(ipcc->irq_domain);335}336 337static const struct of_device_id qcom_ipcc_of_match[] = {338 { .compatible = "qcom,ipcc"},339 {}340};341MODULE_DEVICE_TABLE(of, qcom_ipcc_of_match);342 343static const struct dev_pm_ops qcom_ipcc_dev_pm_ops = {344 NOIRQ_SYSTEM_SLEEP_PM_OPS(NULL, qcom_ipcc_pm_resume)345};346 347static struct platform_driver qcom_ipcc_driver = {348 .probe = qcom_ipcc_probe,349 .remove_new = qcom_ipcc_remove,350 .driver = {351 .name = "qcom-ipcc",352 .of_match_table = qcom_ipcc_of_match,353 .suppress_bind_attrs = true,354 .pm = pm_sleep_ptr(&qcom_ipcc_dev_pm_ops),355 },356};357 358static int __init qcom_ipcc_init(void)359{360 return platform_driver_register(&qcom_ipcc_driver);361}362arch_initcall(qcom_ipcc_init);363 364MODULE_AUTHOR("Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>");365MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");366MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPCC driver");367MODULE_LICENSE("GPL v2");368