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1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */2/*3 * SECO X86 Boards CEC register defines4 *5 * Author: Ettore Chimenti <ek5.chimenti@gmail.com>6 * Copyright (C) 2018, SECO Spa.7 * Copyright (C) 2018, Aidilab Srl.8 */9 10#ifndef __SECO_CEC_H__11#define __SECO_CEC_H__12 13#define SECOCEC_MAX_ADDRS 114#define SECOCEC_DEV_NAME "secocec"15#define SECOCEC_LATEST_FW 0x0f0b16 17#define SMBTIMEOUT 0xfff18#define SMB_POLL_UDELAY 1019 20#define SMBUS_WRITE 021#define SMBUS_READ 122 23#define CMD_BYTE_DATA 024#define CMD_WORD_DATA 125 26/*27 * SMBus definitons for Braswell28 */29 30#define BRA_DONE_STATUS BIT(7)31#define BRA_INUSE_STS BIT(6)32#define BRA_FAILED_OP BIT(4)33#define BRA_BUS_ERR BIT(3)34#define BRA_DEV_ERR BIT(2)35#define BRA_INTR BIT(1)36#define BRA_HOST_BUSY BIT(0)37#define BRA_HSTS_ERR_MASK (BRA_FAILED_OP | BRA_BUS_ERR | BRA_DEV_ERR)38 39#define BRA_PEC_EN BIT(7)40#define BRA_START BIT(6)41#define BRA_LAST__BYTE BIT(5)42#define BRA_INTREN BIT(0)43#define BRA_SMB_CMD (7 << 2)44#define BRA_SMB_CMD_QUICK (0 << 2)45#define BRA_SMB_CMD_BYTE (1 << 2)46#define BRA_SMB_CMD_BYTE_DATA (2 << 2)47#define BRA_SMB_CMD_WORD_DATA (3 << 2)48#define BRA_SMB_CMD_PROCESS_CALL (4 << 2)49#define BRA_SMB_CMD_BLOCK (5 << 2)50#define BRA_SMB_CMD_I2CREAD (6 << 2)51#define BRA_SMB_CMD_BLOCK_PROCESS (7 << 2)52 53#define BRA_SMB_BASE_ADDR 0x204054#define HSTS (BRA_SMB_BASE_ADDR + 0)55#define HCNT (BRA_SMB_BASE_ADDR + 2)56#define HCMD (BRA_SMB_BASE_ADDR + 3)57#define XMIT_SLVA (BRA_SMB_BASE_ADDR + 4)58#define HDAT0 (BRA_SMB_BASE_ADDR + 5)59#define HDAT1 (BRA_SMB_BASE_ADDR + 6)60 61/*62 * Microcontroller Address63 */64 65#define SECOCEC_MICRO_ADDRESS 0x4066 67/*68 * STM32 SMBus Registers69 */70 71#define SECOCEC_VERSION 0x0072#define SECOCEC_ENABLE_REG_1 0x0173#define SECOCEC_ENABLE_REG_2 0x0274#define SECOCEC_STATUS_REG_1 0x0375#define SECOCEC_STATUS_REG_2 0x0476 77#define SECOCEC_STATUS 0x2878#define SECOCEC_DEVICE_LA 0x2979#define SECOCEC_READ_OPERATION_ID 0x2a80#define SECOCEC_READ_DATA_LENGTH 0x2b81#define SECOCEC_READ_DATA_00 0x2c82#define SECOCEC_READ_DATA_02 0x2d83#define SECOCEC_READ_DATA_04 0x2e84#define SECOCEC_READ_DATA_06 0x2f85#define SECOCEC_READ_DATA_08 0x3086#define SECOCEC_READ_DATA_10 0x3187#define SECOCEC_READ_DATA_12 0x3288#define SECOCEC_READ_BYTE0 0x3389#define SECOCEC_WRITE_OPERATION_ID 0x3490#define SECOCEC_WRITE_DATA_LENGTH 0x3591#define SECOCEC_WRITE_DATA_00 0x3692#define SECOCEC_WRITE_DATA_02 0x3793#define SECOCEC_WRITE_DATA_04 0x3894#define SECOCEC_WRITE_DATA_06 0x3995#define SECOCEC_WRITE_DATA_08 0x3a96#define SECOCEC_WRITE_DATA_10 0x3b97#define SECOCEC_WRITE_DATA_12 0x3c98#define SECOCEC_WRITE_BYTE0 0x3d99 100#define SECOCEC_IR_READ_DATA 0x3e101 102/*103 * IR104 */105 106#define SECOCEC_IR_COMMAND_MASK 0x007F107#define SECOCEC_IR_COMMAND_SHL 0108#define SECOCEC_IR_ADDRESS_MASK 0x1F00109#define SECOCEC_IR_ADDRESS_SHL 8110#define SECOCEC_IR_TOGGLE_MASK 0x8000111#define SECOCEC_IR_TOGGLE_SHL 15112 113/*114 * Enabling register115 */116 117#define SECOCEC_ENABLE_REG_1_CEC 0x1000118#define SECOCEC_ENABLE_REG_1_IR 0x2000119#define SECOCEC_ENABLE_REG_1_IR_PASSTHROUGH 0x4000120 121/*122 * Status register123 */124 125#define SECOCEC_STATUS_REG_1_CEC SECOCEC_ENABLE_REG_1_CEC126#define SECOCEC_STATUS_REG_1_IR SECOCEC_ENABLE_REG_1_IR127#define SECOCEC_STATUS_REG_1_IR_PASSTHR SECOCEC_ENABLE_REG_1_IR_PASSTHR128 129/*130 * Status data131 */132 133#define SECOCEC_STATUS_MSG_RECEIVED_MASK BIT(0)134#define SECOCEC_STATUS_RX_ERROR_MASK BIT(1)135#define SECOCEC_STATUS_MSG_SENT_MASK BIT(2)136#define SECOCEC_STATUS_TX_ERROR_MASK BIT(3)137 138#define SECOCEC_STATUS_TX_NACK_ERROR BIT(4)139#define SECOCEC_STATUS_RX_OVERFLOW_MASK BIT(5)140 141#endif /* __SECO_CEC_H__ */142