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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 Auvitek AU8522 QAM/8VSB demodulator driver4 5 Copyright (C) 2008 Steven Toth <stoth@linuxtv.org>6 Copyright (C) 2008 Devin Heitmueller <dheitmueller@linuxtv.org>7 Copyright (C) 2005-2008 Auvitek International, Ltd.8 9 10*/11 12#include <linux/kernel.h>13#include <linux/init.h>14#include <linux/module.h>15#include <linux/string.h>16#include <linux/slab.h>17#include <linux/delay.h>18#include <linux/videodev2.h>19#include <media/v4l2-device.h>20#include <media/v4l2-ctrls.h>21#include <media/v4l2-mc.h>22#include <linux/i2c.h>23#include <media/dvb_frontend.h>24#include "au8522.h"25#include "tuner-i2c.h"26 27#define AU8522_ANALOG_MODE 028#define AU8522_DIGITAL_MODE 129#define AU8522_SUSPEND_MODE 230 31enum au8522_pads {32 AU8522_PAD_IF_INPUT,33 AU8522_PAD_VID_OUT,34 AU8522_PAD_AUDIO_OUT,35 AU8522_NUM_PADS36};37 38struct au8522_state {39 struct i2c_client *c;40 struct i2c_adapter *i2c;41 42 u8 operational_mode;43 44 /* Used for sharing of the state between analog and digital mode */45 struct tuner_i2c_props i2c_props;46 struct list_head hybrid_tuner_instance_list;47 48 /* configuration settings */49 struct au8522_config config;50 51 struct dvb_frontend frontend;52 53 u32 current_frequency;54 enum fe_modulation current_modulation;55 56 u32 fe_status;57 unsigned int led_state;58 59 /* Analog settings */60 struct v4l2_subdev sd;61 v4l2_std_id std;62 int vid_input;63 int aud_input;64 u32 id;65 u32 rev;66 struct v4l2_ctrl_handler hdl;67 68#ifdef CONFIG_MEDIA_CONTROLLER69 struct media_pad pads[AU8522_NUM_PADS];70#endif71};72 73/* These are routines shared by both the VSB/QAM demodulator and the analog74 decoder */75int au8522_writereg(struct au8522_state *state, u16 reg, u8 data);76u8 au8522_readreg(struct au8522_state *state, u16 reg);77int au8522_init(struct dvb_frontend *fe);78int au8522_sleep(struct dvb_frontend *fe);79 80int au8522_get_state(struct au8522_state **state, struct i2c_adapter *i2c,81 u8 client_address);82void au8522_release_state(struct au8522_state *state);83int au8522_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);84int au8522_analog_i2c_gate_ctrl(struct dvb_frontend *fe, int enable);85int au8522_led_ctrl(struct au8522_state *state, int led);86 87/* REGISTERS */88#define AU8522_INPUT_CONTROL_REG081H 0x08189#define AU8522_PGA_CONTROL_REG082H 0x08290#define AU8522_CLAMPING_CONTROL_REG083H 0x08391 92#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H 0x0A393#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H 0x0A494#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H 0x0A595#define AU8522_AGC_CONTROL_RANGE_REG0A6H 0x0A696#define AU8522_SYSTEM_GAIN_CONTROL_REG0A7H 0x0A797#define AU8522_TUNER_AGC_RF_STOP_REG0A8H 0x0A898#define AU8522_TUNER_AGC_RF_START_REG0A9H 0x0A999#define AU8522_TUNER_RF_AGC_DEFAULT_REG0AAH 0x0AA100#define AU8522_TUNER_AGC_IF_STOP_REG0ABH 0x0AB101#define AU8522_TUNER_AGC_IF_START_REG0ACH 0x0AC102#define AU8522_TUNER_AGC_IF_DEFAULT_REG0ADH 0x0AD103#define AU8522_TUNER_AGC_STEP_REG0AEH 0x0AE104#define AU8522_TUNER_GAIN_STEP_REG0AFH 0x0AF105 106/* Receiver registers */107#define AU8522_FRMREGTHRD1_REG0B0H 0x0B0108#define AU8522_FRMREGAGC1H_REG0B1H 0x0B1109#define AU8522_FRMREGSHIFT1_REG0B2H 0x0B2110#define AU8522_TOREGAGC1_REG0B3H 0x0B3111#define AU8522_TOREGASHIFT1_REG0B4H 0x0B4112#define AU8522_FRMREGBBH_REG0B5H 0x0B5113#define AU8522_FRMREGBBM_REG0B6H 0x0B6114#define AU8522_FRMREGBBL_REG0B7H 0x0B7115/* 0xB8 TO 0xD7 are the filter coefficients */116#define AU8522_FRMREGTHRD2_REG0D8H 0x0D8117#define AU8522_FRMREGAGC2H_REG0D9H 0x0D9118#define AU8522_TOREGAGC2_REG0DAH 0x0DA119#define AU8522_TOREGSHIFT2_REG0DBH 0x0DB120#define AU8522_FRMREGPILOTH_REG0DCH 0x0DC121#define AU8522_FRMREGPILOTM_REG0DDH 0x0DD122#define AU8522_FRMREGPILOTL_REG0DEH 0x0DE123#define AU8522_TOREGFREQ_REG0DFH 0x0DF124 125#define AU8522_RX_PGA_RFOUT_REG0EBH 0x0EB126#define AU8522_RX_PGA_IFOUT_REG0ECH 0x0EC127#define AU8522_RX_PGA_PGAOUT_REG0EDH 0x0ED128 129#define AU8522_CHIP_MODE_REG0FEH 0x0FE130 131/* I2C bus control registers */132#define AU8522_I2C_CONTROL_REG0_REG090H 0x090133#define AU8522_I2C_CONTROL_REG1_REG091H 0x091134#define AU8522_I2C_STATUS_REG092H 0x092135#define AU8522_I2C_WR_DATA0_REG093H 0x093136#define AU8522_I2C_WR_DATA1_REG094H 0x094137#define AU8522_I2C_WR_DATA2_REG095H 0x095138#define AU8522_I2C_WR_DATA3_REG096H 0x096139#define AU8522_I2C_WR_DATA4_REG097H 0x097140#define AU8522_I2C_WR_DATA5_REG098H 0x098141#define AU8522_I2C_WR_DATA6_REG099H 0x099142#define AU8522_I2C_WR_DATA7_REG09AH 0x09A143#define AU8522_I2C_RD_DATA0_REG09BH 0x09B144#define AU8522_I2C_RD_DATA1_REG09CH 0x09C145#define AU8522_I2C_RD_DATA2_REG09DH 0x09D146#define AU8522_I2C_RD_DATA3_REG09EH 0x09E147#define AU8522_I2C_RD_DATA4_REG09FH 0x09F148#define AU8522_I2C_RD_DATA5_REG0A0H 0x0A0149#define AU8522_I2C_RD_DATA6_REG0A1H 0x0A1150#define AU8522_I2C_RD_DATA7_REG0A2H 0x0A2151 152#define AU8522_ENA_USB_REG101H 0x101153 154#define AU8522_I2S_CTRL_0_REG110H 0x110155#define AU8522_I2S_CTRL_1_REG111H 0x111156#define AU8522_I2S_CTRL_2_REG112H 0x112157 158#define AU8522_FRMREGFFECONTROL_REG121H 0x121159#define AU8522_FRMREGDFECONTROL_REG122H 0x122160 161#define AU8522_CARRFREQOFFSET0_REG201H 0x201162#define AU8522_CARRFREQOFFSET1_REG202H 0x202163 164#define AU8522_DECIMATION_GAIN_REG21AH 0x21A165#define AU8522_FRMREGIFSLP_REG21BH 0x21B166#define AU8522_FRMREGTHRDL2_REG21CH 0x21C167#define AU8522_FRMREGSTEP3DB_REG21DH 0x21D168#define AU8522_DAGC_GAIN_ADJUSTMENT_REG21EH 0x21E169#define AU8522_FRMREGPLLMODE_REG21FH 0x21F170#define AU8522_FRMREGCSTHRD_REG220H 0x220171#define AU8522_FRMREGCRLOCKDMAX_REG221H 0x221172#define AU8522_FRMREGCRPERIODMASK_REG222H 0x222173#define AU8522_FRMREGCRLOCK0THH_REG223H 0x223174#define AU8522_FRMREGCRLOCK1THH_REG224H 0x224175#define AU8522_FRMREGCRLOCK0THL_REG225H 0x225176#define AU8522_FRMREGCRLOCK1THL_REG226H 0x226177#define AU_FRMREGPLLACQPHASESCL_REG227H 0x227178#define AU8522_FRMREGFREQFBCTRL_REG228H 0x228179 180/* Analog TV Decoder */181#define AU8522_TVDEC_STATUS_REG000H 0x000182#define AU8522_TVDEC_INT_STATUS_REG001H 0x001183#define AU8522_TVDEC_MACROVISION_STATUS_REG002H 0x002184#define AU8522_TVDEC_SHARPNESSREG009H 0x009185#define AU8522_TVDEC_BRIGHTNESS_REG00AH 0x00A186#define AU8522_TVDEC_CONTRAST_REG00BH 0x00B187#define AU8522_TVDEC_SATURATION_CB_REG00CH 0x00C188#define AU8522_TVDEC_SATURATION_CR_REG00DH 0x00D189#define AU8522_TVDEC_HUE_H_REG00EH 0x00E190#define AU8522_TVDEC_HUE_L_REG00FH 0x00F191#define AU8522_TVDEC_INT_MASK_REG010H 0x010192#define AU8522_VIDEO_MODE_REG011H 0x011193#define AU8522_TVDEC_PGA_REG012H 0x012194#define AU8522_TVDEC_COMB_MODE_REG015H 0x015195#define AU8522_REG016H 0x016196#define AU8522_TVDED_DBG_MODE_REG060H 0x060197#define AU8522_TVDEC_FORMAT_CTRL1_REG061H 0x061198#define AU8522_TVDEC_FORMAT_CTRL2_REG062H 0x062199#define AU8522_TVDEC_VCR_DET_LLIM_REG063H 0x063200#define AU8522_TVDEC_VCR_DET_HLIM_REG064H 0x064201#define AU8522_TVDEC_COMB_VDIF_THR1_REG065H 0x065202#define AU8522_TVDEC_COMB_VDIF_THR2_REG066H 0x066203#define AU8522_TVDEC_COMB_VDIF_THR3_REG067H 0x067204#define AU8522_TVDEC_COMB_NOTCH_THR_REG068H 0x068205#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H 0x069206#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH 0x06A207#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH 0x06B208#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH 0x06C209#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH 0x06D210#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH 0x06E211#define AU8522_TVDEC_UV_SEP_THR_REG06FH 0x06F212#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H 0x070213#define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H 0x073214#define AU8522_TVDEC_DCAGC_CTRL_REG077H 0x077215#define AU8522_TVDEC_PIC_START_ADJ_REG078H 0x078216#define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H 0x079217#define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH 0x07A218#define AU8522_TVDEC_INTRP_CTRL_REG07BH 0x07B219#define AU8522_TVDEC_PLL_STATUS_REG07EH 0x07E220#define AU8522_TVDEC_FSC_FREQ_REG07FH 0x07F221 222#define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H 0x0E4223#define AU8522_TOREGAAGC_REG0E5H 0x0E5224 225#define AU8522_TVDEC_CHROMA_AGC_REG401H 0x401226#define AU8522_TVDEC_CHROMA_SFT_REG402H 0x402227#define AU8522_FILTER_COEF_R410 0x410228#define AU8522_FILTER_COEF_R411 0x411229#define AU8522_FILTER_COEF_R412 0x412230#define AU8522_FILTER_COEF_R413 0x413231#define AU8522_FILTER_COEF_R414 0x414232#define AU8522_FILTER_COEF_R415 0x415233#define AU8522_FILTER_COEF_R416 0x416234#define AU8522_FILTER_COEF_R417 0x417235#define AU8522_FILTER_COEF_R418 0x418236#define AU8522_FILTER_COEF_R419 0x419237#define AU8522_FILTER_COEF_R41A 0x41A238#define AU8522_FILTER_COEF_R41B 0x41B239#define AU8522_FILTER_COEF_R41C 0x41C240#define AU8522_FILTER_COEF_R41D 0x41D241#define AU8522_FILTER_COEF_R41E 0x41E242#define AU8522_FILTER_COEF_R41F 0x41F243#define AU8522_FILTER_COEF_R420 0x420244#define AU8522_FILTER_COEF_R421 0x421245#define AU8522_FILTER_COEF_R422 0x422246#define AU8522_FILTER_COEF_R423 0x423247#define AU8522_FILTER_COEF_R424 0x424248#define AU8522_FILTER_COEF_R425 0x425249#define AU8522_FILTER_COEF_R426 0x426250#define AU8522_FILTER_COEF_R427 0x427251#define AU8522_FILTER_COEF_R428 0x428252#define AU8522_FILTER_COEF_R429 0x429253#define AU8522_FILTER_COEF_R42A 0x42A254#define AU8522_FILTER_COEF_R42B 0x42B255#define AU8522_FILTER_COEF_R42C 0x42C256#define AU8522_FILTER_COEF_R42D 0x42D257 258/* VBI Control Registers */259#define AU8522_TVDEC_VBI_RX_FIFO_CONTAIN_REG004H 0x004260#define AU8522_TVDEC_VBI_TX_FIFO_CONTAIN_REG005H 0x005261#define AU8522_TVDEC_VBI_RX_FIFO_READ_REG006H 0x006262#define AU8522_TVDEC_VBI_FIFO_STATUS_REG007H 0x007263#define AU8522_TVDEC_VBI_CTRL_H_REG017H 0x017264#define AU8522_TVDEC_VBI_CTRL_L_REG018H 0x018265#define AU8522_TVDEC_VBI_USER_TOTAL_BITS_REG019H 0x019266#define AU8522_TVDEC_VBI_USER_TUNIT_H_REG01AH 0x01A267#define AU8522_TVDEC_VBI_USER_TUNIT_L_REG01BH 0x01B268#define AU8522_TVDEC_VBI_USER_THRESH1_REG01CH 0x01C269#define AU8522_TVDEC_VBI_USER_FRAME_PAT2_REG01EH 0x01E270#define AU8522_TVDEC_VBI_USER_FRAME_PAT1_REG01FH 0x01F271#define AU8522_TVDEC_VBI_USER_FRAME_PAT0_REG020H 0x020272#define AU8522_TVDEC_VBI_USER_FRAME_MASK2_REG021H 0x021273#define AU8522_TVDEC_VBI_USER_FRAME_MASK1_REG022H 0x022274#define AU8522_TVDEC_VBI_USER_FRAME_MASK0_REG023H 0x023275 276#define AU8522_REG071H 0x071277#define AU8522_REG072H 0x072278#define AU8522_REG074H 0x074279#define AU8522_REG075H 0x075280 281/* Digital Demodulator Registers */282#define AU8522_FRAME_COUNT0_REG084H 0x084283#define AU8522_RS_STATUS_G0_REG085H 0x085284#define AU8522_RS_STATUS_B0_REG086H 0x086285#define AU8522_RS_STATUS_E_REG087H 0x087286#define AU8522_DEMODULATION_STATUS_REG088H 0x088287#define AU8522_TOREGTRESTATUS_REG0E6H 0x0E6288#define AU8522_TSPORT_CONTROL_REG10BH 0x10B289#define AU8522_TSTHES_REG10CH 0x10C290#define AU8522_FRMREGDFEKEEP_REG301H 0x301291#define AU8522_DFE_AVERAGE_REG302H 0x302292#define AU8522_FRMREGEQLERRWIN_REG303H 0x303293#define AU8522_FRMREGFFEKEEP_REG304H 0x304294#define AU8522_FRMREGDFECONTROL1_REG305H 0x305295#define AU8522_FRMREGEQLERRLOW_REG306H 0x306296 297#define AU8522_REG42EH 0x42E298#define AU8522_REG42FH 0x42F299#define AU8522_REG430H 0x430300#define AU8522_REG431H 0x431301#define AU8522_REG432H 0x432302#define AU8522_REG433H 0x433303#define AU8522_REG434H 0x434304#define AU8522_REG435H 0x435305#define AU8522_REG436H 0x436306 307/* GPIO Registers */308#define AU8522_GPIO_CONTROL_REG0E0H 0x0E0309#define AU8522_GPIO_STATUS_REG0E1H 0x0E1310#define AU8522_GPIO_DATA_REG0E2H 0x0E2311 312/* Audio Control Registers */313#define AU8522_AUDIOAGC_REG0EEH 0x0EE314#define AU8522_AUDIO_STATUS_REG0F0H 0x0F0315#define AU8522_AUDIO_MODE_REG0F1H 0x0F1316#define AU8522_AUDIO_VOLUME_L_REG0F2H 0x0F2317#define AU8522_AUDIO_VOLUME_R_REG0F3H 0x0F3318#define AU8522_AUDIO_VOLUME_REG0F4H 0x0F4319#define AU8522_FRMREGAUPHASE_REG0F7H 0x0F7320#define AU8522_REG0F9H 0x0F9321 322#define AU8522_AUDIOAGC2_REG605H 0x605323#define AU8522_AUDIOFREQ_REG606H 0x606324 325 326/**************************************************************/327 328/* Format control 1 */329 330/* VCR Mode 7-6 */331#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_YES 0x80332#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_NO 0x40333#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_VCR_MODE_AUTO 0x00334/* Field len 5-4 */335#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_625 0x20336#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_525 0x10337#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_FIELD_LEN_AUTO 0x00338/* Line len (us) 3-2 */339#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_64_000 0x0b340#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_492 0x08341#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_LINE_LEN_63_556 0x04342/* Subcarrier freq 1-0 */343#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_AUTO 0x03344#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_443 0x02345#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_MN 0x01346#define AU8522_TVDEC_FORMAT_CTRL1_REG061H_SUBCARRIER_NTSC_50 0x00347 348/* Format control 2 */349#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_AUTODETECT 0x00350#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_NTSC 0x01351#define AU8522_TVDEC_FORMAT_CTRL2_REG062H_STD_PAL_M 0x02352 353 354#define AU8522_INPUT_CONTROL_REG081H_ATSC 0xC4355#define AU8522_INPUT_CONTROL_REG081H_ATVRF 0xC4356#define AU8522_INPUT_CONTROL_REG081H_ATVRF13 0xC4357#define AU8522_INPUT_CONTROL_REG081H_J83B64 0xC4358#define AU8522_INPUT_CONTROL_REG081H_J83B256 0xC4359#define AU8522_INPUT_CONTROL_REG081H_CVBS 0x20360#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH1 0xA2361#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH2 0xA0362#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH3 0x69363#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4 0x68364#define AU8522_INPUT_CONTROL_REG081H_CVBS_CH4_SIF 0x28365/* CH1 AS Y,CH3 AS C */366#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH13 0x23367/* CH2 AS Y,CH4 AS C */368#define AU8522_INPUT_CONTROL_REG081H_SVIDEO_CH24 0x20369#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATSC 0x0C370#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B64 0x09371#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_J83B256 0x09372#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_CVBS 0x12373#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF 0x1A374#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_ATVRF13 0x1A375#define AU8522_MODULE_CLOCK_CONTROL_REG0A3H_SVIDEO 0x02376 377#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CLEAR 0x00378#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_SVIDEO 0x9C379#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_CVBS 0x9D380#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATSC 0xE8381#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B256 0xCA382#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_J83B64 0xCA383#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF 0xDD384#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_ATVRF13 0xDD385#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_PAL 0xDD386#define AU8522_SYSTEM_MODULE_CONTROL_0_REG0A4H_FM 0xDD387 388#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATSC 0x80389#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B256 0x80390#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_J83B64 0x80391#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_ATSC 0x40392#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B256 0x40393#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_J83B64 0x40394#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_DONGLE_CLEAR 0x00395#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF 0x01396#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_ATVRF13 0x01397#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_SVIDEO 0x04398#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_CVBS 0x01399#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PWM 0x03400#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_IIS 0x09401#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_PAL 0x01402#define AU8522_SYSTEM_MODULE_CONTROL_1_REG0A5H_FM 0x01403 404/* STILL NEED TO BE REFACTORED @@@@@@@@@@@@@@ */405#define AU8522_TVDEC_CONTRAST_REG00BH_CVBS 0x79406#define AU8522_TVDEC_SATURATION_CB_REG00CH_CVBS 0x80407#define AU8522_TVDEC_SATURATION_CR_REG00DH_CVBS 0x80408#define AU8522_TVDEC_HUE_H_REG00EH_CVBS 0x00409#define AU8522_TVDEC_HUE_L_REG00FH_CVBS 0x00410#define AU8522_TVDEC_PGA_REG012H_CVBS 0x0F411#define AU8522_TVDEC_COMB_MODE_REG015H_CVBS 0x00412#define AU8522_REG016H_CVBS 0x00413#define AU8522_TVDED_DBG_MODE_REG060H_CVBS 0x00414#define AU8522_TVDEC_VCR_DET_LLIM_REG063H_CVBS 0x19415#define AU8522_REG0F9H_AUDIO 0x20416#define AU8522_TVDEC_VCR_DET_HLIM_REG064H_CVBS 0xA7417#define AU8522_TVDEC_COMB_VDIF_THR1_REG065H_CVBS 0x0A418#define AU8522_TVDEC_COMB_VDIF_THR2_REG066H_CVBS 0x32419#define AU8522_TVDEC_COMB_VDIF_THR3_REG067H_CVBS 0x19420#define AU8522_TVDEC_COMB_NOTCH_THR_REG068H_CVBS 0x23421#define AU8522_TVDEC_COMB_HDIF_THR1_REG069H_CVBS 0x41422#define AU8522_TVDEC_COMB_HDIF_THR2_REG06AH_CVBS 0x0A423#define AU8522_TVDEC_COMB_HDIF_THR3_REG06BH_CVBS 0x32424#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_CVBS 0x34425#define AU8522_TVDEC_COMB_DCDIF_THR1_REG06CH_SVIDEO 0x2a426#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_CVBS 0x05427#define AU8522_TVDEC_COMB_DCDIF_THR2_REG06DH_SVIDEO 0x15428#define AU8522_TVDEC_COMB_DCDIF_THR3_REG06EH_CVBS 0x6E429#define AU8522_TVDEC_UV_SEP_THR_REG06FH_CVBS 0x0F430#define AU8522_TVDEC_COMB_DC_THR1_NTSC_REG070H_CVBS 0x80431#define AU8522_REG071H_CVBS 0x18432#define AU8522_REG072H_CVBS 0x30433#define AU8522_TVDEC_COMB_DC_THR2_NTSC_REG073H_CVBS 0xF0434#define AU8522_REG074H_CVBS 0x80435#define AU8522_REG075H_CVBS 0xF0436#define AU8522_TVDEC_DCAGC_CTRL_REG077H_CVBS 0xFB437#define AU8522_TVDEC_PIC_START_ADJ_REG078H_CVBS 0x04438#define AU8522_TVDEC_AGC_HIGH_LIMIT_REG079H_CVBS 0x00439#define AU8522_TVDEC_MACROVISION_SYNC_THR_REG07AH_CVBS 0x00440#define AU8522_TVDEC_INTRP_CTRL_REG07BH_CVBS 0xEE441#define AU8522_TVDEC_AGC_LOW_LIMIT_REG0E4H_CVBS 0xFE442#define AU8522_TOREGAAGC_REG0E5H_CVBS 0x00443#define AU8522_TVDEC_VBI6A_REG035H_CVBS 0x40444 445/* Enables Closed captioning */446#define AU8522_TVDEC_VBI_CTRL_H_REG017H_CCON 0x21447