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1/*2 Copyright (c), 2004-2005,2007-2010 Trident Microsystems, Inc.3 All rights reserved.4 5 Redistribution and use in source and binary forms, with or without6 modification, are permitted provided that the following conditions are met:7 8 * Redistributions of source code must retain the above copyright notice,9 this list of conditions and the following disclaimer.10 * Redistributions in binary form must reproduce the above copyright notice,11 this list of conditions and the following disclaimer in the documentation12 and/or other materials provided with the distribution.13 * Neither the name of Trident Microsystems nor Hauppauge Computer Works14 nor the names of its contributors may be used to endorse or promote15 products derived from this software without specific prior written16 permission.17 18 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"19 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE20 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE21 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE22 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR23 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF24 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS25 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN26 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)27 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE28 POSSIBILITY OF SUCH DAMAGE.29*/30 31/*32 ***********************************************************************************************************************33 * WARNING - THIS FILE HAS BEEN GENERATED - DO NOT CHANGE34 *35 * Filename: drxj_map.h36 * Generated on: Mon Jan 18 12:09:24 201037 * Generated by: IDF:x 1.3.038 * Generated from: reg_map39 * Output start: [entry point]40 *41 * filename last modified re-use42 * -----------------------------------------------------43 * reg_map.1.tmp Mon Jan 18 12:09:24 2010 -44 *45 */46 47#ifndef __DRXJ_MAP__H__48#define __DRXJ_MAP__H__ INCLUDED49 50#ifdef _REGISTERTABLE_51#include <registertable.h>52 extern register_table_t drxj_map[];53 extern register_table_info_t drxj_map_info[];54#endif55 56#define ATV_COMM_EXEC__A 0xC0000057#define ATV_COMM_EXEC__W 258#define ATV_COMM_EXEC__M 0x359#define ATV_COMM_EXEC__PRE 0x060#define ATV_COMM_EXEC_STOP 0x061#define ATV_COMM_EXEC_ACTIVE 0x162#define ATV_COMM_EXEC_HOLD 0x263 64#define ATV_COMM_STATE__A 0xC0000165#define ATV_COMM_STATE__W 1666#define ATV_COMM_STATE__M 0xFFFF67#define ATV_COMM_STATE__PRE 0x068#define ATV_COMM_MB__A 0xC0000269#define ATV_COMM_MB__W 1670#define ATV_COMM_MB__M 0xFFFF71#define ATV_COMM_MB__PRE 0x072#define ATV_COMM_INT_REQ__A 0xC0000373#define ATV_COMM_INT_REQ__W 1674#define ATV_COMM_INT_REQ__M 0xFFFF75#define ATV_COMM_INT_REQ__PRE 0x076#define ATV_COMM_INT_REQ_COMM_INT_REQ__B 077#define ATV_COMM_INT_REQ_COMM_INT_REQ__W 178#define ATV_COMM_INT_REQ_COMM_INT_REQ__M 0x179#define ATV_COMM_INT_REQ_COMM_INT_REQ__PRE 0x080 81#define ATV_COMM_INT_STA__A 0xC0000582#define ATV_COMM_INT_STA__W 1683#define ATV_COMM_INT_STA__M 0xFFFF84#define ATV_COMM_INT_STA__PRE 0x085#define ATV_COMM_INT_MSK__A 0xC0000686#define ATV_COMM_INT_MSK__W 1687#define ATV_COMM_INT_MSK__M 0xFFFF88#define ATV_COMM_INT_MSK__PRE 0x089#define ATV_COMM_INT_STM__A 0xC0000790#define ATV_COMM_INT_STM__W 1691#define ATV_COMM_INT_STM__M 0xFFFF92#define ATV_COMM_INT_STM__PRE 0x093 94#define ATV_COMM_KEY__A 0xC0000F95#define ATV_COMM_KEY__W 1696#define ATV_COMM_KEY__M 0xFFFF97#define ATV_COMM_KEY__PRE 0x098#define ATV_COMM_KEY_KEY 0xFABA99#define ATV_COMM_KEY_MIN 0x0100#define ATV_COMM_KEY_MAX 0xFFFF101 102#define ATV_TOP_COMM_EXEC__A 0xC10000103#define ATV_TOP_COMM_EXEC__W 2104#define ATV_TOP_COMM_EXEC__M 0x3105#define ATV_TOP_COMM_EXEC__PRE 0x0106#define ATV_TOP_COMM_EXEC_STOP 0x0107#define ATV_TOP_COMM_EXEC_ACTIVE 0x1108#define ATV_TOP_COMM_EXEC_HOLD 0x2109 110#define ATV_TOP_COMM_STATE__A 0xC10001111#define ATV_TOP_COMM_STATE__W 16112#define ATV_TOP_COMM_STATE__M 0xFFFF113#define ATV_TOP_COMM_STATE__PRE 0x0114#define ATV_TOP_COMM_STATE_STATE__B 0115#define ATV_TOP_COMM_STATE_STATE__W 16116#define ATV_TOP_COMM_STATE_STATE__M 0xFFFF117#define ATV_TOP_COMM_STATE_STATE__PRE 0x0118 119#define ATV_TOP_COMM_MB__A 0xC10002120#define ATV_TOP_COMM_MB__W 16121#define ATV_TOP_COMM_MB__M 0xFFFF122#define ATV_TOP_COMM_MB__PRE 0x0123#define ATV_TOP_COMM_MB_CTL__B 0124#define ATV_TOP_COMM_MB_CTL__W 1125#define ATV_TOP_COMM_MB_CTL__M 0x1126#define ATV_TOP_COMM_MB_CTL__PRE 0x0127#define ATV_TOP_COMM_MB_OBS__B 1128#define ATV_TOP_COMM_MB_OBS__W 1129#define ATV_TOP_COMM_MB_OBS__M 0x2130#define ATV_TOP_COMM_MB_OBS__PRE 0x0131 132#define ATV_TOP_COMM_MB_MUX_CTRL__B 2133#define ATV_TOP_COMM_MB_MUX_CTRL__W 4134#define ATV_TOP_COMM_MB_MUX_CTRL__M 0x3C135#define ATV_TOP_COMM_MB_MUX_CTRL__PRE 0x0136#define ATV_TOP_COMM_MB_MUX_CTRL_PEAK_S 0x0137#define ATV_TOP_COMM_MB_MUX_CTRL_VID_GAIN 0x4138#define ATV_TOP_COMM_MB_MUX_CTRL_CORR_O 0x8139#define ATV_TOP_COMM_MB_MUX_CTRL_CR_ROT_O 0xC140#define ATV_TOP_COMM_MB_MUX_CTRL_CR_IIR_IQ 0x10141#define ATV_TOP_COMM_MB_MUX_CTRL_VIDEO_O 0x14142#define ATV_TOP_COMM_MB_MUX_CTRL_SIF_O 0x18143#define ATV_TOP_COMM_MB_MUX_CTRL_SIF2025_O 0x1C144#define ATV_TOP_COMM_MB_MUX_CTRL_POST_S 0x20145 146#define ATV_TOP_COMM_MB_MUX_OBS__B 6147#define ATV_TOP_COMM_MB_MUX_OBS__W 4148#define ATV_TOP_COMM_MB_MUX_OBS__M 0x3C0149#define ATV_TOP_COMM_MB_MUX_OBS__PRE 0x0150#define ATV_TOP_COMM_MB_MUX_OBS_PEAK_S 0x0151#define ATV_TOP_COMM_MB_MUX_OBS_VID_GAIN 0x40152#define ATV_TOP_COMM_MB_MUX_OBS_CORR_O 0x80153#define ATV_TOP_COMM_MB_MUX_OBS_CR_ROT_O 0xC0154#define ATV_TOP_COMM_MB_MUX_OBS_CR_IIR_IQ 0x100155#define ATV_TOP_COMM_MB_MUX_OBS_VIDEO_O 0x140156#define ATV_TOP_COMM_MB_MUX_OBS_SIF_O 0x180157#define ATV_TOP_COMM_MB_MUX_OBS_SIF2025_O 0x1C0158#define ATV_TOP_COMM_MB_MUX_OBS_POST_S 0x200159 160#define ATV_TOP_COMM_INT_REQ__A 0xC10003161#define ATV_TOP_COMM_INT_REQ__W 16162#define ATV_TOP_COMM_INT_REQ__M 0xFFFF163#define ATV_TOP_COMM_INT_REQ__PRE 0x0164#define ATV_TOP_COMM_INT_STA__A 0xC10005165#define ATV_TOP_COMM_INT_STA__W 16166#define ATV_TOP_COMM_INT_STA__M 0xFFFF167#define ATV_TOP_COMM_INT_STA__PRE 0x0168 169#define ATV_TOP_COMM_INT_STA_FAGC_STA__B 0170#define ATV_TOP_COMM_INT_STA_FAGC_STA__W 1171#define ATV_TOP_COMM_INT_STA_FAGC_STA__M 0x1172#define ATV_TOP_COMM_INT_STA_FAGC_STA__PRE 0x0173 174#define ATV_TOP_COMM_INT_STA_OVM_STA__B 1175#define ATV_TOP_COMM_INT_STA_OVM_STA__W 1176#define ATV_TOP_COMM_INT_STA_OVM_STA__M 0x2177#define ATV_TOP_COMM_INT_STA_OVM_STA__PRE 0x0178 179#define ATV_TOP_COMM_INT_STA_AMPTH_STA__B 2180#define ATV_TOP_COMM_INT_STA_AMPTH_STA__W 1181#define ATV_TOP_COMM_INT_STA_AMPTH_STA__M 0x4182#define ATV_TOP_COMM_INT_STA_AMPTH_STA__PRE 0x0183 184#define ATV_TOP_COMM_INT_MSK__A 0xC10006185#define ATV_TOP_COMM_INT_MSK__W 16186#define ATV_TOP_COMM_INT_MSK__M 0xFFFF187#define ATV_TOP_COMM_INT_MSK__PRE 0x0188 189#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__B 0190#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__W 1191#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__M 0x1192#define ATV_TOP_COMM_INT_MSK_FAGC_MSK__PRE 0x0193 194#define ATV_TOP_COMM_INT_MSK_OVM_MSK__B 1195#define ATV_TOP_COMM_INT_MSK_OVM_MSK__W 1196#define ATV_TOP_COMM_INT_MSK_OVM_MSK__M 0x2197#define ATV_TOP_COMM_INT_MSK_OVM_MSK__PRE 0x0198 199#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__B 2200#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__W 1201#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__M 0x4202#define ATV_TOP_COMM_INT_MSK_AMPTH_MSK__PRE 0x0203 204#define ATV_TOP_COMM_INT_STM__A 0xC10007205#define ATV_TOP_COMM_INT_STM__W 16206#define ATV_TOP_COMM_INT_STM__M 0xFFFF207#define ATV_TOP_COMM_INT_STM__PRE 0x0208 209#define ATV_TOP_COMM_INT_STM_FAGC_STM__B 0210#define ATV_TOP_COMM_INT_STM_FAGC_STM__W 1211#define ATV_TOP_COMM_INT_STM_FAGC_STM__M 0x1212#define ATV_TOP_COMM_INT_STM_FAGC_STM__PRE 0x0213 214#define ATV_TOP_COMM_INT_STM_OVM_STM__B 1215#define ATV_TOP_COMM_INT_STM_OVM_STM__W 1216#define ATV_TOP_COMM_INT_STM_OVM_STM__M 0x2217#define ATV_TOP_COMM_INT_STM_OVM_STM__PRE 0x0218 219#define ATV_TOP_COMM_INT_STM_AMPTH_STM__B 2220#define ATV_TOP_COMM_INT_STM_AMPTH_STM__W 1221#define ATV_TOP_COMM_INT_STM_AMPTH_STM__M 0x4222#define ATV_TOP_COMM_INT_STM_AMPTH_STM__PRE 0x0223 224#define ATV_TOP_COMM_KEY__A 0xC1000F225#define ATV_TOP_COMM_KEY__W 16226#define ATV_TOP_COMM_KEY__M 0xFFFF227#define ATV_TOP_COMM_KEY__PRE 0x0228 229#define ATV_TOP_COMM_KEY_KEY__B 0230#define ATV_TOP_COMM_KEY_KEY__W 16231#define ATV_TOP_COMM_KEY_KEY__M 0xFFFF232#define ATV_TOP_COMM_KEY_KEY__PRE 0x0233#define ATV_TOP_COMM_KEY_KEY_KEY 0xFABA234#define ATV_TOP_COMM_KEY_KEY_MIN 0x0235#define ATV_TOP_COMM_KEY_KEY_MAX 0xFFFF236 237#define ATV_TOP_CR_AMP_TH__A 0xC10010238#define ATV_TOP_CR_AMP_TH__W 8239#define ATV_TOP_CR_AMP_TH__M 0xFF240#define ATV_TOP_CR_AMP_TH__PRE 0x8241#define ATV_TOP_CR_AMP_TH_MN 0x8242 243#define ATV_TOP_CR_CONT__A 0xC10011244#define ATV_TOP_CR_CONT__W 9245#define ATV_TOP_CR_CONT__M 0x1FF246#define ATV_TOP_CR_CONT__PRE 0x9C247 248#define ATV_TOP_CR_CONT_CR_P__B 0249#define ATV_TOP_CR_CONT_CR_P__W 3250#define ATV_TOP_CR_CONT_CR_P__M 0x7251#define ATV_TOP_CR_CONT_CR_P__PRE 0x4252#define ATV_TOP_CR_CONT_CR_P_MN 0x4253#define ATV_TOP_CR_CONT_CR_P_FM 0x0254 255#define ATV_TOP_CR_CONT_CR_D__B 3256#define ATV_TOP_CR_CONT_CR_D__W 3257#define ATV_TOP_CR_CONT_CR_D__M 0x38258#define ATV_TOP_CR_CONT_CR_D__PRE 0x18259#define ATV_TOP_CR_CONT_CR_D_MN 0x18260#define ATV_TOP_CR_CONT_CR_D_FM 0x0261 262#define ATV_TOP_CR_CONT_CR_I__B 6263#define ATV_TOP_CR_CONT_CR_I__W 3264#define ATV_TOP_CR_CONT_CR_I__M 0x1C0265#define ATV_TOP_CR_CONT_CR_I__PRE 0x80266#define ATV_TOP_CR_CONT_CR_I_MN 0x80267#define ATV_TOP_CR_CONT_CR_I_FM 0x0268 269#define ATV_TOP_CR_OVM_TH__A 0xC10012270#define ATV_TOP_CR_OVM_TH__W 8271#define ATV_TOP_CR_OVM_TH__M 0xFF272#define ATV_TOP_CR_OVM_TH__PRE 0xA0273#define ATV_TOP_CR_OVM_TH_MN 0xA0274#define ATV_TOP_CR_OVM_TH_FM 0x0275 276#define ATV_TOP_NOISE_TH__A 0xC10013277#define ATV_TOP_NOISE_TH__W 4278#define ATV_TOP_NOISE_TH__M 0xF279#define ATV_TOP_NOISE_TH__PRE 0x8280#define ATV_TOP_NOISE_TH_MN 0x8281 282#define ATV_TOP_EQU0__A 0xC10014283#define ATV_TOP_EQU0__W 9284#define ATV_TOP_EQU0__M 0x1FF285#define ATV_TOP_EQU0__PRE 0x1FB286 287#define ATV_TOP_EQU0_EQU_C0__B 0288#define ATV_TOP_EQU0_EQU_C0__W 9289#define ATV_TOP_EQU0_EQU_C0__M 0x1FF290#define ATV_TOP_EQU0_EQU_C0__PRE 0x1FB291#define ATV_TOP_EQU0_EQU_C0_MN 0xFB292 293#define ATV_TOP_EQU1__A 0xC10015294#define ATV_TOP_EQU1__W 9295#define ATV_TOP_EQU1__M 0x1FF296#define ATV_TOP_EQU1__PRE 0x1CE297 298#define ATV_TOP_EQU1_EQU_C1__B 0299#define ATV_TOP_EQU1_EQU_C1__W 9300#define ATV_TOP_EQU1_EQU_C1__M 0x1FF301#define ATV_TOP_EQU1_EQU_C1__PRE 0x1CE302#define ATV_TOP_EQU1_EQU_C1_MN 0xCE303 304#define ATV_TOP_EQU2__A 0xC10016305#define ATV_TOP_EQU2__W 9306#define ATV_TOP_EQU2__M 0x1FF307#define ATV_TOP_EQU2__PRE 0xD2308 309#define ATV_TOP_EQU2_EQU_C2__B 0310#define ATV_TOP_EQU2_EQU_C2__W 9311#define ATV_TOP_EQU2_EQU_C2__M 0x1FF312#define ATV_TOP_EQU2_EQU_C2__PRE 0xD2313#define ATV_TOP_EQU2_EQU_C2_MN 0xD2314 315#define ATV_TOP_EQU3__A 0xC10017316#define ATV_TOP_EQU3__W 9317#define ATV_TOP_EQU3__M 0x1FF318#define ATV_TOP_EQU3__PRE 0x160319 320#define ATV_TOP_EQU3_EQU_C3__B 0321#define ATV_TOP_EQU3_EQU_C3__W 9322#define ATV_TOP_EQU3_EQU_C3__M 0x1FF323#define ATV_TOP_EQU3_EQU_C3__PRE 0x160324#define ATV_TOP_EQU3_EQU_C3_MN 0x60325 326#define ATV_TOP_ROT_MODE__A 0xC10018327#define ATV_TOP_ROT_MODE__W 1328#define ATV_TOP_ROT_MODE__M 0x1329#define ATV_TOP_ROT_MODE__PRE 0x0330#define ATV_TOP_ROT_MODE_AMPTH_DEPEND 0x0331#define ATV_TOP_ROT_MODE_ALWAYS 0x1332 333#define ATV_TOP_MOD_CONTROL__A 0xC10019334#define ATV_TOP_MOD_CONTROL__W 12335#define ATV_TOP_MOD_CONTROL__M 0xFFF336#define ATV_TOP_MOD_CONTROL__PRE 0x5B1337 338#define ATV_TOP_MOD_CONTROL_MOD_IR__B 0339#define ATV_TOP_MOD_CONTROL_MOD_IR__W 3340#define ATV_TOP_MOD_CONTROL_MOD_IR__M 0x7341#define ATV_TOP_MOD_CONTROL_MOD_IR__PRE 0x1342#define ATV_TOP_MOD_CONTROL_MOD_IR_MN 0x1343#define ATV_TOP_MOD_CONTROL_MOD_IR_FM 0x0344 345#define ATV_TOP_MOD_CONTROL_MOD_IF__B 3346#define ATV_TOP_MOD_CONTROL_MOD_IF__W 4347#define ATV_TOP_MOD_CONTROL_MOD_IF__M 0x78348#define ATV_TOP_MOD_CONTROL_MOD_IF__PRE 0x30349#define ATV_TOP_MOD_CONTROL_MOD_IF_MN 0x30350#define ATV_TOP_MOD_CONTROL_MOD_IF_FM 0x0351 352#define ATV_TOP_MOD_CONTROL_MOD_MODE__B 7353#define ATV_TOP_MOD_CONTROL_MOD_MODE__W 1354#define ATV_TOP_MOD_CONTROL_MOD_MODE__M 0x80355#define ATV_TOP_MOD_CONTROL_MOD_MODE__PRE 0x80356#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE 0x0357#define ATV_TOP_MOD_CONTROL_MOD_MODE_RISE_FALL 0x80358 359#define ATV_TOP_MOD_CONTROL_MOD_TH__B 8360#define ATV_TOP_MOD_CONTROL_MOD_TH__W 4361#define ATV_TOP_MOD_CONTROL_MOD_TH__M 0xF00362#define ATV_TOP_MOD_CONTROL_MOD_TH__PRE 0x500363#define ATV_TOP_MOD_CONTROL_MOD_TH_MN 0x500364#define ATV_TOP_MOD_CONTROL_MOD_TH_FM 0x0365 366#define ATV_TOP_STD__A 0xC1001A367#define ATV_TOP_STD__W 2368#define ATV_TOP_STD__M 0x3369#define ATV_TOP_STD__PRE 0x0370 371#define ATV_TOP_STD_MODE__B 0372#define ATV_TOP_STD_MODE__W 1373#define ATV_TOP_STD_MODE__M 0x1374#define ATV_TOP_STD_MODE__PRE 0x0375#define ATV_TOP_STD_MODE_MN 0x0376#define ATV_TOP_STD_MODE_FM 0x1377 378#define ATV_TOP_STD_VID_POL__B 1379#define ATV_TOP_STD_VID_POL__W 1380#define ATV_TOP_STD_VID_POL__M 0x2381#define ATV_TOP_STD_VID_POL__PRE 0x0382#define ATV_TOP_STD_VID_POL_NEG 0x0383#define ATV_TOP_STD_VID_POL_POS 0x2384 385#define ATV_TOP_VID_AMP__A 0xC1001B386#define ATV_TOP_VID_AMP__W 12387#define ATV_TOP_VID_AMP__M 0xFFF388#define ATV_TOP_VID_AMP__PRE 0x380389#define ATV_TOP_VID_AMP_MN 0x380390#define ATV_TOP_VID_AMP_FM 0x0391 392#define ATV_TOP_VID_PEAK__A 0xC1001C393#define ATV_TOP_VID_PEAK__W 5394#define ATV_TOP_VID_PEAK__M 0x1F395#define ATV_TOP_VID_PEAK__PRE 0x1396 397#define ATV_TOP_FAGC_TH__A 0xC1001D398#define ATV_TOP_FAGC_TH__W 11399#define ATV_TOP_FAGC_TH__M 0x7FF400#define ATV_TOP_FAGC_TH__PRE 0x2B2401#define ATV_TOP_FAGC_TH_MN 0x2B2402 403#define ATV_TOP_SYNC_SLICE__A 0xC1001E404#define ATV_TOP_SYNC_SLICE__W 11405#define ATV_TOP_SYNC_SLICE__M 0x7FF406#define ATV_TOP_SYNC_SLICE__PRE 0x243407#define ATV_TOP_SYNC_SLICE_MN 0x243408 409#define ATV_TOP_SIF_GAIN__A 0xC1001F410#define ATV_TOP_SIF_GAIN__W 11411#define ATV_TOP_SIF_GAIN__M 0x7FF412#define ATV_TOP_SIF_GAIN__PRE 0x0413 414#define ATV_TOP_SIF_TP__A 0xC10020415#define ATV_TOP_SIF_TP__W 6416#define ATV_TOP_SIF_TP__M 0x3F417#define ATV_TOP_SIF_TP__PRE 0x0418 419#define ATV_TOP_MOD_ACCU__A 0xC10021420#define ATV_TOP_MOD_ACCU__W 10421#define ATV_TOP_MOD_ACCU__M 0x3FF422#define ATV_TOP_MOD_ACCU__PRE 0x0423 424#define ATV_TOP_CR_FREQ__A 0xC10022425#define ATV_TOP_CR_FREQ__W 8426#define ATV_TOP_CR_FREQ__M 0xFF427#define ATV_TOP_CR_FREQ__PRE 0x0428 429#define ATV_TOP_CR_PHAD__A 0xC10023430#define ATV_TOP_CR_PHAD__W 12431#define ATV_TOP_CR_PHAD__M 0xFFF432#define ATV_TOP_CR_PHAD__PRE 0x0433 434#define ATV_TOP_AF_SIF_ATT__A 0xC10024435#define ATV_TOP_AF_SIF_ATT__W 2436#define ATV_TOP_AF_SIF_ATT__M 0x3437#define ATV_TOP_AF_SIF_ATT__PRE 0x0438#define ATV_TOP_AF_SIF_ATT_0DB 0x0439#define ATV_TOP_AF_SIF_ATT_M3DB 0x1440#define ATV_TOP_AF_SIF_ATT_M6DB 0x2441#define ATV_TOP_AF_SIF_ATT_M9DB 0x3442 443#define ATV_TOP_STDBY__A 0xC10025444#define ATV_TOP_STDBY__W 2445#define ATV_TOP_STDBY__M 0x3446#define ATV_TOP_STDBY__PRE 0x1447 448#define ATV_TOP_STDBY_SIF_STDBY__B 0449#define ATV_TOP_STDBY_SIF_STDBY__W 1450#define ATV_TOP_STDBY_SIF_STDBY__M 0x1451#define ATV_TOP_STDBY_SIF_STDBY__PRE 0x1452#define ATV_TOP_STDBY_SIF_STDBY_ACTIVE 0x0453#define ATV_TOP_STDBY_SIF_STDBY_STANDBY 0x1454 455#define ATV_TOP_STDBY_CVBS_STDBY__B 1456#define ATV_TOP_STDBY_CVBS_STDBY__W 1457#define ATV_TOP_STDBY_CVBS_STDBY__M 0x2458#define ATV_TOP_STDBY_CVBS_STDBY__PRE 0x0459#define ATV_TOP_STDBY_CVBS_STDBY_A1_ACTIVE 0x0460#define ATV_TOP_STDBY_CVBS_STDBY_A1_STANDBY 0x2461#define ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE 0x2462#define ATV_TOP_STDBY_CVBS_STDBY_A2_STANDBY 0x0463 464#define ATV_TOP_OVERRIDE_SFR__A 0xC10026465#define ATV_TOP_OVERRIDE_SFR__W 1466#define ATV_TOP_OVERRIDE_SFR__M 0x1467#define ATV_TOP_OVERRIDE_SFR__PRE 0x0468#define ATV_TOP_OVERRIDE_SFR_ACTIVE 0x0469#define ATV_TOP_OVERRIDE_SFR_OVERRIDE 0x1470 471#define ATV_TOP_SFR_VID_GAIN__A 0xC10027472#define ATV_TOP_SFR_VID_GAIN__W 16473#define ATV_TOP_SFR_VID_GAIN__M 0xFFFF474#define ATV_TOP_SFR_VID_GAIN__PRE 0x0475 476#define ATV_TOP_SFR_AGC_RES__A 0xC10028477#define ATV_TOP_SFR_AGC_RES__W 5478#define ATV_TOP_SFR_AGC_RES__M 0x1F479#define ATV_TOP_SFR_AGC_RES__PRE 0x0480 481#define ATV_TOP_OVM_COMP__A 0xC10029482#define ATV_TOP_OVM_COMP__W 12483#define ATV_TOP_OVM_COMP__M 0xFFF484#define ATV_TOP_OVM_COMP__PRE 0x0485#define ATV_TOP_OUT_CONF__A 0xC1002A486#define ATV_TOP_OUT_CONF__W 5487#define ATV_TOP_OUT_CONF__M 0x1F488#define ATV_TOP_OUT_CONF__PRE 0x0489 490#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__B 0491#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__W 1492#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__M 0x1493#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN__PRE 0x0494#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_UNSIGNED 0x0495#define ATV_TOP_OUT_CONF_CVBS_DAC_SIGN_SIGNED 0x1496 497#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__B 1498#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__W 1499#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__M 0x2500#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN__PRE 0x0501#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_UNSIGNED 0x0502#define ATV_TOP_OUT_CONF_SIF_DAC_SIGN_SIGNED 0x2503 504#define ATV_TOP_OUT_CONF_SIF20_SIGN__B 2505#define ATV_TOP_OUT_CONF_SIF20_SIGN__W 1506#define ATV_TOP_OUT_CONF_SIF20_SIGN__M 0x4507#define ATV_TOP_OUT_CONF_SIF20_SIGN__PRE 0x0508#define ATV_TOP_OUT_CONF_SIF20_SIGN_UNSIGNED 0x0509#define ATV_TOP_OUT_CONF_SIF20_SIGN_SIGNED 0x4510 511#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__B 3512#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__W 1513#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__M 0x8514#define ATV_TOP_OUT_CONF_CVBS_DAC_BR__PRE 0x0515#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_NORMAL 0x0516#define ATV_TOP_OUT_CONF_CVBS_DAC_BR_BITREVERSED 0x8517 518#define ATV_TOP_OUT_CONF_SIF_DAC_BR__B 4519#define ATV_TOP_OUT_CONF_SIF_DAC_BR__W 1520#define ATV_TOP_OUT_CONF_SIF_DAC_BR__M 0x10521#define ATV_TOP_OUT_CONF_SIF_DAC_BR__PRE 0x0522#define ATV_TOP_OUT_CONF_SIF_DAC_BR_NORMAL 0x0523#define ATV_TOP_OUT_CONF_SIF_DAC_BR_BITREVERSED 0x10524 525#define ATV_AFT_COMM_EXEC__A 0xFF0000526#define ATV_AFT_COMM_EXEC__W 2527#define ATV_AFT_COMM_EXEC__M 0x3528#define ATV_AFT_COMM_EXEC__PRE 0x0529#define ATV_AFT_COMM_EXEC_STOP 0x0530#define ATV_AFT_COMM_EXEC_ACTIVE 0x1531#define ATV_AFT_COMM_EXEC_HOLD 0x2532 533#define ATV_AFT_TST__A 0xFF0010534#define ATV_AFT_TST__W 4535#define ATV_AFT_TST__M 0xF536#define ATV_AFT_TST__PRE 0x0537 538#define AUD_COMM_EXEC__A 0x1000000539#define AUD_COMM_EXEC__W 2540#define AUD_COMM_EXEC__M 0x3541#define AUD_COMM_EXEC__PRE 0x0542#define AUD_COMM_EXEC_STOP 0x0543#define AUD_COMM_EXEC_ACTIVE 0x1544 545#define AUD_COMM_MB__A 0x1000002546#define AUD_COMM_MB__W 16547#define AUD_COMM_MB__M 0xFFFF548#define AUD_COMM_MB__PRE 0x0549 550#define AUD_TOP_COMM_EXEC__A 0x1010000551#define AUD_TOP_COMM_EXEC__W 2552#define AUD_TOP_COMM_EXEC__M 0x3553#define AUD_TOP_COMM_EXEC__PRE 0x0554#define AUD_TOP_COMM_EXEC_STOP 0x0555#define AUD_TOP_COMM_EXEC_ACTIVE 0x1556 557#define AUD_TOP_COMM_MB__A 0x1010002558#define AUD_TOP_COMM_MB__W 16559#define AUD_TOP_COMM_MB__M 0xFFFF560#define AUD_TOP_COMM_MB__PRE 0x0561 562#define AUD_TOP_COMM_MB_CTL__B 0563#define AUD_TOP_COMM_MB_CTL__W 1564#define AUD_TOP_COMM_MB_CTL__M 0x1565#define AUD_TOP_COMM_MB_CTL__PRE 0x0566#define AUD_TOP_COMM_MB_CTL_CTR_OFF 0x0567#define AUD_TOP_COMM_MB_CTL_CTR_ON 0x1568 569#define AUD_TOP_COMM_MB_OBS__B 1570#define AUD_TOP_COMM_MB_OBS__W 1571#define AUD_TOP_COMM_MB_OBS__M 0x2572#define AUD_TOP_COMM_MB_OBS__PRE 0x0573#define AUD_TOP_COMM_MB_OBS_OBS_OFF 0x0574#define AUD_TOP_COMM_MB_OBS_OBS_ON 0x2575 576#define AUD_TOP_COMM_MB_MUX_CTRL__B 2577#define AUD_TOP_COMM_MB_MUX_CTRL__W 4578#define AUD_TOP_COMM_MB_MUX_CTRL__M 0x3C579#define AUD_TOP_COMM_MB_MUX_CTRL__PRE 0x0580#define AUD_TOP_COMM_MB_MUX_CTRL_DEMOD_TBO 0x0581#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_IRQS 0x4582#define AUD_TOP_COMM_MB_MUX_CTRL_OBSERVEPC 0x8583#define AUD_TOP_COMM_MB_MUX_CTRL_SAOUT 0xC584#define AUD_TOP_COMM_MB_MUX_CTRL_XDFP_SCHEQ 0x10585 586#define AUD_TOP_COMM_MB_MUX_OBS__B 6587#define AUD_TOP_COMM_MB_MUX_OBS__W 4588#define AUD_TOP_COMM_MB_MUX_OBS__M 0x3C0589#define AUD_TOP_COMM_MB_MUX_OBS__PRE 0x0590#define AUD_TOP_COMM_MB_MUX_OBS_DEMOD_TBO 0x0591#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_IRQS 0x40592#define AUD_TOP_COMM_MB_MUX_OBS_OBSERVEPC 0x80593#define AUD_TOP_COMM_MB_MUX_OBS_SAOUT 0xC0594#define AUD_TOP_COMM_MB_MUX_OBS_XDFP_SCHEQ 0x100595 596#define AUD_TOP_TR_MDE__A 0x1010010597#define AUD_TOP_TR_MDE__W 5598#define AUD_TOP_TR_MDE__M 0x1F599#define AUD_TOP_TR_MDE__PRE 0x18600 601#define AUD_TOP_TR_MDE_FIFO_SIZE__B 0602#define AUD_TOP_TR_MDE_FIFO_SIZE__W 4603#define AUD_TOP_TR_MDE_FIFO_SIZE__M 0xF604#define AUD_TOP_TR_MDE_FIFO_SIZE__PRE 0x8605 606#define AUD_TOP_TR_MDE_RD_LOCK__B 4607#define AUD_TOP_TR_MDE_RD_LOCK__W 1608#define AUD_TOP_TR_MDE_RD_LOCK__M 0x10609#define AUD_TOP_TR_MDE_RD_LOCK__PRE 0x10610#define AUD_TOP_TR_MDE_RD_LOCK_NORMAL 0x0611#define AUD_TOP_TR_MDE_RD_LOCK_LOCK 0x10612 613#define AUD_TOP_TR_CTR__A 0x1010011614#define AUD_TOP_TR_CTR__W 4615#define AUD_TOP_TR_CTR__M 0xF616#define AUD_TOP_TR_CTR__PRE 0x0617 618#define AUD_TOP_TR_CTR_FIFO_RD_RDY__B 0619#define AUD_TOP_TR_CTR_FIFO_RD_RDY__W 1620#define AUD_TOP_TR_CTR_FIFO_RD_RDY__M 0x1621#define AUD_TOP_TR_CTR_FIFO_RD_RDY__PRE 0x0622#define AUD_TOP_TR_CTR_FIFO_RD_RDY_NOT_READY 0x0623#define AUD_TOP_TR_CTR_FIFO_RD_RDY_READY 0x1624 625#define AUD_TOP_TR_CTR_FIFO_EMPTY__B 1626#define AUD_TOP_TR_CTR_FIFO_EMPTY__W 1627#define AUD_TOP_TR_CTR_FIFO_EMPTY__M 0x2628#define AUD_TOP_TR_CTR_FIFO_EMPTY__PRE 0x0629#define AUD_TOP_TR_CTR_FIFO_EMPTY_NOT_EMPTY 0x0630#define AUD_TOP_TR_CTR_FIFO_EMPTY_EMPTY 0x2631 632#define AUD_TOP_TR_CTR_FIFO_LOCK__B 2633#define AUD_TOP_TR_CTR_FIFO_LOCK__W 1634#define AUD_TOP_TR_CTR_FIFO_LOCK__M 0x4635#define AUD_TOP_TR_CTR_FIFO_LOCK__PRE 0x0636#define AUD_TOP_TR_CTR_FIFO_LOCK_UNLOCKED 0x0637#define AUD_TOP_TR_CTR_FIFO_LOCK_LOCKED 0x4638 639#define AUD_TOP_TR_CTR_FIFO_FULL__B 3640#define AUD_TOP_TR_CTR_FIFO_FULL__W 1641#define AUD_TOP_TR_CTR_FIFO_FULL__M 0x8642#define AUD_TOP_TR_CTR_FIFO_FULL__PRE 0x0643#define AUD_TOP_TR_CTR_FIFO_FULL_EMPTY 0x0644#define AUD_TOP_TR_CTR_FIFO_FULL_FULL 0x8645 646#define AUD_TOP_TR_RD_REG__A 0x1010012647#define AUD_TOP_TR_RD_REG__W 16648#define AUD_TOP_TR_RD_REG__M 0xFFFF649#define AUD_TOP_TR_RD_REG__PRE 0x0650 651#define AUD_TOP_TR_RD_REG_RESULT__B 0652#define AUD_TOP_TR_RD_REG_RESULT__W 16653#define AUD_TOP_TR_RD_REG_RESULT__M 0xFFFF654#define AUD_TOP_TR_RD_REG_RESULT__PRE 0x0655 656#define AUD_TOP_TR_TIMER__A 0x1010013657#define AUD_TOP_TR_TIMER__W 16658#define AUD_TOP_TR_TIMER__M 0xFFFF659#define AUD_TOP_TR_TIMER__PRE 0x0660 661#define AUD_TOP_TR_TIMER_CYCLES__B 0662#define AUD_TOP_TR_TIMER_CYCLES__W 16663#define AUD_TOP_TR_TIMER_CYCLES__M 0xFFFF664#define AUD_TOP_TR_TIMER_CYCLES__PRE 0x0665 666#define AUD_TOP_DEMOD_TBO_SEL__A 0x1010014667#define AUD_TOP_DEMOD_TBO_SEL__W 5668#define AUD_TOP_DEMOD_TBO_SEL__M 0x1F669#define AUD_TOP_DEMOD_TBO_SEL__PRE 0x0670 671#define AUD_DEM_WR_MODUS__A 0x1030030672#define AUD_DEM_WR_MODUS__W 16673#define AUD_DEM_WR_MODUS__M 0xFFFF674#define AUD_DEM_WR_MODUS__PRE 0x0675 676#define AUD_DEM_WR_MODUS_MOD_ASS__B 0677#define AUD_DEM_WR_MODUS_MOD_ASS__W 1678#define AUD_DEM_WR_MODUS_MOD_ASS__M 0x1679#define AUD_DEM_WR_MODUS_MOD_ASS__PRE 0x0680#define AUD_DEM_WR_MODUS_MOD_ASS_OFF 0x0681#define AUD_DEM_WR_MODUS_MOD_ASS_ON 0x1682 683#define AUD_DEM_WR_MODUS_MOD_STATINTERR__B 1684#define AUD_DEM_WR_MODUS_MOD_STATINTERR__W 1685#define AUD_DEM_WR_MODUS_MOD_STATINTERR__M 0x2686#define AUD_DEM_WR_MODUS_MOD_STATINTERR__PRE 0x0687#define AUD_DEM_WR_MODUS_MOD_STATINTERR_DISABLE 0x0688#define AUD_DEM_WR_MODUS_MOD_STATINTERR_ENABLE 0x2689 690#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__B 2691#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__W 1692#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__M 0x4693#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG__PRE 0x0694#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_ENABLED 0x0695#define AUD_DEM_WR_MODUS_MOD_DIS_STD_CHG_DISABLED 0x4696 697#define AUD_DEM_WR_MODUS_MOD_HDEV_A__B 8698#define AUD_DEM_WR_MODUS_MOD_HDEV_A__W 1699#define AUD_DEM_WR_MODUS_MOD_HDEV_A__M 0x100700#define AUD_DEM_WR_MODUS_MOD_HDEV_A__PRE 0x0701#define AUD_DEM_WR_MODUS_MOD_HDEV_A_NORMAL 0x0702#define AUD_DEM_WR_MODUS_MOD_HDEV_A_HIGH_DEVIATION 0x100703 704#define AUD_DEM_WR_MODUS_MOD_CM_A__B 9705#define AUD_DEM_WR_MODUS_MOD_CM_A__W 1706#define AUD_DEM_WR_MODUS_MOD_CM_A__M 0x200707#define AUD_DEM_WR_MODUS_MOD_CM_A__PRE 0x0708#define AUD_DEM_WR_MODUS_MOD_CM_A_MUTE 0x0709#define AUD_DEM_WR_MODUS_MOD_CM_A_NOISE 0x200710 711#define AUD_DEM_WR_MODUS_MOD_CM_B__B 10712#define AUD_DEM_WR_MODUS_MOD_CM_B__W 1713#define AUD_DEM_WR_MODUS_MOD_CM_B__M 0x400714#define AUD_DEM_WR_MODUS_MOD_CM_B__PRE 0x0715#define AUD_DEM_WR_MODUS_MOD_CM_B_MUTE 0x0716#define AUD_DEM_WR_MODUS_MOD_CM_B_NOISE 0x400717 718#define AUD_DEM_WR_MODUS_MOD_FMRADIO__B 11719#define AUD_DEM_WR_MODUS_MOD_FMRADIO__W 1720#define AUD_DEM_WR_MODUS_MOD_FMRADIO__M 0x800721#define AUD_DEM_WR_MODUS_MOD_FMRADIO__PRE 0x0722#define AUD_DEM_WR_MODUS_MOD_FMRADIO_US_75U 0x0723#define AUD_DEM_WR_MODUS_MOD_FMRADIO_EU_50U 0x800724 725#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__B 12726#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__W 1727#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__M 0x1000728#define AUD_DEM_WR_MODUS_MOD_6_5MHZ__PRE 0x0729#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_SECAM 0x0730#define AUD_DEM_WR_MODUS_MOD_6_5MHZ_D_K 0x1000731 732#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__B 13733#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__W 2734#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__M 0x6000735#define AUD_DEM_WR_MODUS_MOD_4_5MHZ__PRE 0x0736#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_KOREA 0x0737#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_BTSC 0x2000738#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_M_EIAJ 0x4000739#define AUD_DEM_WR_MODUS_MOD_4_5MHZ_CHROMA 0x6000740 741#define AUD_DEM_WR_MODUS_MOD_BTSC__B 15742#define AUD_DEM_WR_MODUS_MOD_BTSC__W 1743#define AUD_DEM_WR_MODUS_MOD_BTSC__M 0x8000744#define AUD_DEM_WR_MODUS_MOD_BTSC__PRE 0x0745#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_STEREO 0x0746#define AUD_DEM_WR_MODUS_MOD_BTSC_BTSC_SAP 0x8000747 748#define AUD_DEM_WR_STANDARD_SEL__A 0x1030020749#define AUD_DEM_WR_STANDARD_SEL__W 16750#define AUD_DEM_WR_STANDARD_SEL__M 0xFFFF751#define AUD_DEM_WR_STANDARD_SEL__PRE 0x0752 753#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__B 0754#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__W 12755#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__M 0xFFF756#define AUD_DEM_WR_STANDARD_SEL_STD_SEL__PRE 0x0757#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_AUTO 0x1758#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_M_KOREA 0x2759#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_FM 0x3760#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K1 0x4761#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K2 0x5762#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K3 0x7763#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BG_NICAM_FM 0x8764#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_L_NICAM_AM 0x9765#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_I_NICAM_FM 0xA766#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_D_K_NICAM_FM 0xB767#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_STEREO 0x20768#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_BTSC_SAP 0x21769#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_EIA_J 0x30770#define AUD_DEM_WR_STANDARD_SEL_STD_SEL_FM_RADIO 0x40771 772#define AUD_DEM_RD_STANDARD_RES__A 0x102007E773#define AUD_DEM_RD_STANDARD_RES__W 16774#define AUD_DEM_RD_STANDARD_RES__M 0xFFFF775#define AUD_DEM_RD_STANDARD_RES__PRE 0x0776 777#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__B 0778#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__W 16779#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__M 0xFFFF780#define AUD_DEM_RD_STANDARD_RES_STD_RESULT__PRE 0x0781#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NO_SOUND_STANDARD 0x0782#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_M_DUAL_CARRIER_FM 0x2783#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_DUAL_CARRIER_FM 0x3784#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K1_DUAL_CARRIER_FM 0x4785#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K2_DUAL_CARRIER_FM 0x5786#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K3_DUAL_CARRIER_FM 0x7787#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_B_G_NICAM_FM 0x8788#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_L_NICAM_AM 0x9789#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_I_NICAM_FM 0xA790#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_D_K_NICAM_FM 0xB791#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_STEREO 0x20792#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_BTSC_MONO_SAP 0x21793#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_NTSC_EIA_J 0x30794#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_FM_RADIO 0x40795#define AUD_DEM_RD_STANDARD_RES_STD_RESULT_DETECTION_STILL_ACTIVE 0x7FF796 797#define AUD_DEM_RD_STATUS__A 0x1020200798#define AUD_DEM_RD_STATUS__W 16799#define AUD_DEM_RD_STATUS__M 0xFFFF800#define AUD_DEM_RD_STATUS__PRE 0x0801 802#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__B 0803#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__W 1804#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__M 0x1805#define AUD_DEM_RD_STATUS_STAT_NEW_RDS__PRE 0x0806#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NO_RDS_DATA 0x0807#define AUD_DEM_RD_STATUS_STAT_NEW_RDS_NEW_RDS_DATA 0x1808 809#define AUD_DEM_RD_STATUS_STAT_CARR_A__B 1810#define AUD_DEM_RD_STATUS_STAT_CARR_A__W 1811#define AUD_DEM_RD_STATUS_STAT_CARR_A__M 0x2812#define AUD_DEM_RD_STATUS_STAT_CARR_A__PRE 0x0813#define AUD_DEM_RD_STATUS_STAT_CARR_A_DETECTED 0x0814#define AUD_DEM_RD_STATUS_STAT_CARR_A_NOT_DETECTED 0x2815 816#define AUD_DEM_RD_STATUS_STAT_CARR_B__B 2817#define AUD_DEM_RD_STATUS_STAT_CARR_B__W 1818#define AUD_DEM_RD_STATUS_STAT_CARR_B__M 0x4819#define AUD_DEM_RD_STATUS_STAT_CARR_B__PRE 0x0820#define AUD_DEM_RD_STATUS_STAT_CARR_B_DETECTED 0x0821#define AUD_DEM_RD_STATUS_STAT_CARR_B_NOT_DETECTED 0x4822 823#define AUD_DEM_RD_STATUS_STAT_NICAM__B 5824#define AUD_DEM_RD_STATUS_STAT_NICAM__W 1825#define AUD_DEM_RD_STATUS_STAT_NICAM__M 0x20826#define AUD_DEM_RD_STATUS_STAT_NICAM__PRE 0x0827#define AUD_DEM_RD_STATUS_STAT_NICAM_NO_NICAM 0x0828#define AUD_DEM_RD_STATUS_STAT_NICAM_NICAM_DETECTED 0x20829 830#define AUD_DEM_RD_STATUS_STAT_STEREO__B 6831#define AUD_DEM_RD_STATUS_STAT_STEREO__W 1832#define AUD_DEM_RD_STATUS_STAT_STEREO__M 0x40833#define AUD_DEM_RD_STATUS_STAT_STEREO__PRE 0x0834#define AUD_DEM_RD_STATUS_STAT_STEREO_NO_STEREO 0x0835#define AUD_DEM_RD_STATUS_STAT_STEREO_STEREO 0x40836 837#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__B 7838#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__W 1839#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__M 0x80840#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO__PRE 0x0841#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_DEPENDENT_FM_MONO_PROGRAM 0x0842#define AUD_DEM_RD_STATUS_STAT_INDEP_MONO_INDEPENDENT_FM_MONO_PROGRAM 0x80843 844#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__B 8845#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__W 1846#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__M 0x100847#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP__PRE 0x0848#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_NO_SAP 0x0849#define AUD_DEM_RD_STATUS_STAT_BIL_OR_SAP_SAP 0x100850 851#define AUD_DEM_RD_STATUS_BAD_NICAM__B 9852#define AUD_DEM_RD_STATUS_BAD_NICAM__W 1853#define AUD_DEM_RD_STATUS_BAD_NICAM__M 0x200854#define AUD_DEM_RD_STATUS_BAD_NICAM__PRE 0x0855#define AUD_DEM_RD_STATUS_BAD_NICAM_OK 0x0856#define AUD_DEM_RD_STATUS_BAD_NICAM_BAD 0x200857 858#define AUD_DEM_RD_RDS_ARRAY_CNT__A 0x102020F859#define AUD_DEM_RD_RDS_ARRAY_CNT__W 12860#define AUD_DEM_RD_RDS_ARRAY_CNT__M 0xFFF861#define AUD_DEM_RD_RDS_ARRAY_CNT__PRE 0x0862 863#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__B 0864#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__W 12865#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__M 0xFFF866#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT__PRE 0x0867#define AUD_DEM_RD_RDS_ARRAY_CNT_RDS_ARRAY_CT_RDS_DATA_NOT_VALID 0xFFF868 869#define AUD_DEM_RD_RDS_DATA__A 0x1020210870#define AUD_DEM_RD_RDS_DATA__W 12871#define AUD_DEM_RD_RDS_DATA__M 0xFFF872#define AUD_DEM_RD_RDS_DATA__PRE 0x0873 874#define AUD_DSP_WR_FM_PRESC__A 0x105000E875#define AUD_DSP_WR_FM_PRESC__W 16876#define AUD_DSP_WR_FM_PRESC__M 0xFFFF877#define AUD_DSP_WR_FM_PRESC__PRE 0x0878 879#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__B 8880#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__W 8881#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__M 0xFF00882#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC__PRE 0x0883#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_28_KHZ_FM_DEVIATION 0x7F00884#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_50_KHZ_FM_DEVIATION 0x4800885#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_75_KHZ_FM_DEVIATION 0x3000886#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_100_KHZ_FM_DEVIATION 0x2400887#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_150_KHZ_FM_DEVIATION 0x1800888#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_180_KHZ_FM_DEVIATION 0x1300889#define AUD_DSP_WR_FM_PRESC_FM_AM_PRESC_380_KHZ_FM_DEVIATION 0x900890 891#define AUD_DSP_WR_NICAM_PRESC__A 0x1050010892#define AUD_DSP_WR_NICAM_PRESC__W 16893#define AUD_DSP_WR_NICAM_PRESC__M 0xFFFF894#define AUD_DSP_WR_NICAM_PRESC__PRE 0x0895#define AUD_DSP_WR_VOLUME__A 0x1050000896#define AUD_DSP_WR_VOLUME__W 16897#define AUD_DSP_WR_VOLUME__M 0xFFFF898#define AUD_DSP_WR_VOLUME__PRE 0x0899 900#define AUD_DSP_WR_VOLUME_VOL_MAIN__B 8901#define AUD_DSP_WR_VOLUME_VOL_MAIN__W 8902#define AUD_DSP_WR_VOLUME_VOL_MAIN__M 0xFF00903#define AUD_DSP_WR_VOLUME_VOL_MAIN__PRE 0x0904 905#define AUD_DSP_WR_SRC_I2S_MATR__A 0x1050038906#define AUD_DSP_WR_SRC_I2S_MATR__W 16907#define AUD_DSP_WR_SRC_I2S_MATR__M 0xFFFF908#define AUD_DSP_WR_SRC_I2S_MATR__PRE 0x0909 910#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__B 8911#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__W 8912#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__M 0xFF00913#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S__PRE 0x0914#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_MONO 0x0915#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_AB 0x100916#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_A 0x300917#define AUD_DSP_WR_SRC_I2S_MATR_SRC_I2S_STEREO_B 0x400918 919#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__B 0920#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__W 8921#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__M 0xFF922#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S__PRE 0x0923#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_A 0x0924#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_SOUND_B 0x10925#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_STEREO 0x20926#define AUD_DSP_WR_SRC_I2S_MATR_MAT_I2S_MONO 0x30927 928#define AUD_DSP_WR_AVC__A 0x1050029929#define AUD_DSP_WR_AVC__W 16930#define AUD_DSP_WR_AVC__M 0xFFFF931#define AUD_DSP_WR_AVC__PRE 0x0932 933#define AUD_DSP_WR_AVC_AVC_ON__B 14934#define AUD_DSP_WR_AVC_AVC_ON__W 2935#define AUD_DSP_WR_AVC_AVC_ON__M 0xC000936#define AUD_DSP_WR_AVC_AVC_ON__PRE 0x0937#define AUD_DSP_WR_AVC_AVC_ON_OFF 0x0938#define AUD_DSP_WR_AVC_AVC_ON_ON 0xC000939 940#define AUD_DSP_WR_AVC_AVC_DECAY__B 8941#define AUD_DSP_WR_AVC_AVC_DECAY__W 4942#define AUD_DSP_WR_AVC_AVC_DECAY__M 0xF00943#define AUD_DSP_WR_AVC_AVC_DECAY__PRE 0x0944#define AUD_DSP_WR_AVC_AVC_DECAY_8_SEC 0x800945#define AUD_DSP_WR_AVC_AVC_DECAY_4_SEC 0x400946#define AUD_DSP_WR_AVC_AVC_DECAY_2_SEC 0x200947#define AUD_DSP_WR_AVC_AVC_DECAY_20_MSEC 0x100948 949#define AUD_DSP_WR_AVC_AVC_REF_LEV__B 4950#define AUD_DSP_WR_AVC_AVC_REF_LEV__W 4951#define AUD_DSP_WR_AVC_AVC_REF_LEV__M 0xF0952#define AUD_DSP_WR_AVC_AVC_REF_LEV__PRE 0x0953 954#define AUD_DSP_WR_AVC_AVC_MAX_ATT__B 2955#define AUD_DSP_WR_AVC_AVC_MAX_ATT__W 2956#define AUD_DSP_WR_AVC_AVC_MAX_ATT__M 0xC957#define AUD_DSP_WR_AVC_AVC_MAX_ATT__PRE 0x0958#define AUD_DSP_WR_AVC_AVC_MAX_ATT_24DB 0x0959#define AUD_DSP_WR_AVC_AVC_MAX_ATT_18DB 0x4960#define AUD_DSP_WR_AVC_AVC_MAX_ATT_12DB 0x8961 962#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__B 0963#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__W 2964#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__M 0x3965#define AUD_DSP_WR_AVC_AVC_MAX_GAIN__PRE 0x0966#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_6DB 0x0967#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_12DB 0x1968#define AUD_DSP_WR_AVC_AVC_MAX_GAIN_0DB 0x3969 970#define AUD_DSP_WR_QPEAK__A 0x105000C971#define AUD_DSP_WR_QPEAK__W 16972#define AUD_DSP_WR_QPEAK__M 0xFFFF973#define AUD_DSP_WR_QPEAK__PRE 0x0974 975#define AUD_DSP_WR_QPEAK_SRC_QP__B 8976#define AUD_DSP_WR_QPEAK_SRC_QP__W 8977#define AUD_DSP_WR_QPEAK_SRC_QP__M 0xFF00978#define AUD_DSP_WR_QPEAK_SRC_QP__PRE 0x0979#define AUD_DSP_WR_QPEAK_SRC_QP_MONO 0x0980#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_AB 0x100981#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_A 0x300982#define AUD_DSP_WR_QPEAK_SRC_QP_STEREO_B 0x400983 984#define AUD_DSP_WR_QPEAK_MAT_QP__B 0985#define AUD_DSP_WR_QPEAK_MAT_QP__W 8986#define AUD_DSP_WR_QPEAK_MAT_QP__M 0xFF987#define AUD_DSP_WR_QPEAK_MAT_QP__PRE 0x0988#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_A 0x0989#define AUD_DSP_WR_QPEAK_MAT_QP_SOUND_B 0x10990#define AUD_DSP_WR_QPEAK_MAT_QP_STEREO 0x20991#define AUD_DSP_WR_QPEAK_MAT_QP_MONO 0x30992 993#define AUD_DSP_RD_QPEAK_L__A 0x1040019994#define AUD_DSP_RD_QPEAK_L__W 16995#define AUD_DSP_RD_QPEAK_L__M 0xFFFF996#define AUD_DSP_RD_QPEAK_L__PRE 0x0997 998#define AUD_DSP_RD_QPEAK_R__A 0x104001A999#define AUD_DSP_RD_QPEAK_R__W 161000#define AUD_DSP_RD_QPEAK_R__M 0xFFFF1001#define AUD_DSP_RD_QPEAK_R__PRE 0x01002 1003#define AUD_DSP_WR_BEEPER__A 0x10500141004#define AUD_DSP_WR_BEEPER__W 161005#define AUD_DSP_WR_BEEPER__M 0xFFFF1006#define AUD_DSP_WR_BEEPER__PRE 0x01007 1008#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__B 81009#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__W 71010#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__M 0x7F001011#define AUD_DSP_WR_BEEPER_BEEP_VOLUME__PRE 0x01012 1013#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__B 01014#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__W 71015#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__M 0x7F1016#define AUD_DSP_WR_BEEPER_BEEP_FREQUENCY__PRE 0x01017 1018#define AUD_DEM_WR_I2S_CONFIG2__A 0x10300501019#define AUD_DEM_WR_I2S_CONFIG2__W 161020#define AUD_DEM_WR_I2S_CONFIG2__M 0xFFFF1021#define AUD_DEM_WR_I2S_CONFIG2__PRE 0x01022 1023#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__B 61024#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__W 11025#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__M 0x401026#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL__PRE 0x01027#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_NORMAL 0x01028#define AUD_DEM_WR_I2S_CONFIG2_I2S_CL_POL_INVERTED 0x401029 1030#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__B 41031#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__W 11032#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__M 0x101033#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE__PRE 0x01034#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_DISABLE 0x01035#define AUD_DEM_WR_I2S_CONFIG2_I2S_ENABLE_ENABLE 0x101036 1037#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__B 31038#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__W 11039#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__M 0x81040#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST__PRE 0x01041#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_MASTER 0x01042#define AUD_DEM_WR_I2S_CONFIG2_I2S_SLV_MST_SLAVE 0x81043 1044#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__B 21045#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__W 11046#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__M 0x41047#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL__PRE 0x01048#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_LOW 0x01049#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_POL_LEFT_HIGH 0x41050 1051#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__B 11052#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__W 11053#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__M 0x21054#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE__PRE 0x01055#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_NO_DELAY 0x01056#define AUD_DEM_WR_I2S_CONFIG2_I2S_WS_MODE_DELAY 0x21057 1058#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__B 01059#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__W 11060#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__M 0x11061#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN__PRE 0x01062#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_32 0x01063#define AUD_DEM_WR_I2S_CONFIG2_I2S_WORD_LEN_BIT_16 0x11064 1065#define AUD_DSP_WR_I2S_OUT_FS__A 0x105002A1066#define AUD_DSP_WR_I2S_OUT_FS__W 161067#define AUD_DSP_WR_I2S_OUT_FS__M 0xFFFF1068#define AUD_DSP_WR_I2S_OUT_FS__PRE 0x01069 1070#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__B 01071#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__W 161072#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__M 0xFFFF1073#define AUD_DSP_WR_I2S_OUT_FS_FS_OUT__PRE 0x01074 1075#define AUD_DSP_WR_AV_SYNC__A 0x105002B1076#define AUD_DSP_WR_AV_SYNC__W 161077#define AUD_DSP_WR_AV_SYNC__M 0xFFFF1078#define AUD_DSP_WR_AV_SYNC__PRE 0x01079 1080#define AUD_DSP_WR_AV_SYNC_AV_ON__B 151081#define AUD_DSP_WR_AV_SYNC_AV_ON__W 11082#define AUD_DSP_WR_AV_SYNC_AV_ON__M 0x80001083#define AUD_DSP_WR_AV_SYNC_AV_ON__PRE 0x01084#define AUD_DSP_WR_AV_SYNC_AV_ON_DISABLE 0x01085#define AUD_DSP_WR_AV_SYNC_AV_ON_ENABLE 0x80001086 1087#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__B 141088#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__W 11089#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__M 0x40001090#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ__PRE 0x01091#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_MONOCHROME 0x01092#define AUD_DSP_WR_AV_SYNC_AV_AUTO_FREQ_NTSC 0x40001093 1094#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__B 01095#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__W 21096#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__M 0x31097#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL__PRE 0x01098#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_AUTO 0x01099#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_PAL_SECAM 0x11100#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_NTSC 0x21101#define AUD_DSP_WR_AV_SYNC_AV_STD_SEL_MONOCHROME 0x31102 1103#define AUD_DSP_RD_STATUS2__A 0x104007B1104#define AUD_DSP_RD_STATUS2__W 161105#define AUD_DSP_RD_STATUS2__M 0xFFFF1106#define AUD_DSP_RD_STATUS2__PRE 0x01107 1108#define AUD_DSP_RD_STATUS2_AV_ACTIVE__B 151109#define AUD_DSP_RD_STATUS2_AV_ACTIVE__W 11110#define AUD_DSP_RD_STATUS2_AV_ACTIVE__M 0x80001111#define AUD_DSP_RD_STATUS2_AV_ACTIVE__PRE 0x01112#define AUD_DSP_RD_STATUS2_AV_ACTIVE_NO_SYNC 0x01113#define AUD_DSP_RD_STATUS2_AV_ACTIVE_SYNC_ACTIVE 0x80001114 1115#define AUD_DSP_RD_XDFP_FW__A 0x104001D1116#define AUD_DSP_RD_XDFP_FW__W 161117#define AUD_DSP_RD_XDFP_FW__M 0xFFFF1118#define AUD_DSP_RD_XDFP_FW__PRE 0x3441119 1120#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__B 01121#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__W 161122#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__M 0xFFFF1123#define AUD_DSP_RD_XDFP_FW_DSP_FW_REV__PRE 0x3441124 1125#define AUD_DSP_RD_XFP_FW__A 0x10404B81126#define AUD_DSP_RD_XFP_FW__W 161127#define AUD_DSP_RD_XFP_FW__M 0xFFFF1128#define AUD_DSP_RD_XFP_FW__PRE 0x421129 1130#define AUD_DSP_RD_XFP_FW_FP_FW_REV__B 01131#define AUD_DSP_RD_XFP_FW_FP_FW_REV__W 161132#define AUD_DSP_RD_XFP_FW_FP_FW_REV__M 0xFFFF1133#define AUD_DSP_RD_XFP_FW_FP_FW_REV__PRE 0x421134 1135#define AUD_DEM_WR_DCO_B_HI__A 0x103009B1136#define AUD_DEM_WR_DCO_B_HI__W 161137#define AUD_DEM_WR_DCO_B_HI__M 0xFFFF1138#define AUD_DEM_WR_DCO_B_HI__PRE 0x01139 1140#define AUD_DEM_WR_DCO_B_LO__A 0x10300931141#define AUD_DEM_WR_DCO_B_LO__W 161142#define AUD_DEM_WR_DCO_B_LO__M 0xFFFF1143#define AUD_DEM_WR_DCO_B_LO__PRE 0x01144 1145#define AUD_DEM_WR_DCO_A_HI__A 0x10300AB1146#define AUD_DEM_WR_DCO_A_HI__W 161147#define AUD_DEM_WR_DCO_A_HI__M 0xFFFF1148#define AUD_DEM_WR_DCO_A_HI__PRE 0x01149 1150#define AUD_DEM_WR_DCO_A_LO__A 0x10300A31151#define AUD_DEM_WR_DCO_A_LO__W 161152#define AUD_DEM_WR_DCO_A_LO__M 0xFFFF1153#define AUD_DEM_WR_DCO_A_LO__PRE 0x01154#define AUD_DEM_WR_NICAM_THRSHLD__A 0x10300211155#define AUD_DEM_WR_NICAM_THRSHLD__W 161156#define AUD_DEM_WR_NICAM_THRSHLD__M 0xFFFF1157#define AUD_DEM_WR_NICAM_THRSHLD__PRE 0x2BC1158 1159#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__B 01160#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__W 121161#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__M 0xFFF1162#define AUD_DEM_WR_NICAM_THRSHLD_NICAM_THLD__PRE 0x2BC1163 1164#define AUD_DEM_WR_A2_THRSHLD__A 0x10300221165#define AUD_DEM_WR_A2_THRSHLD__W 161166#define AUD_DEM_WR_A2_THRSHLD__M 0xFFFF1167#define AUD_DEM_WR_A2_THRSHLD__PRE 0x1901168 1169#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__B 01170#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__W 121171#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__M 0xFFF1172#define AUD_DEM_WR_A2_THRSHLD_A2_THLD__PRE 0x1901173 1174#define AUD_DEM_WR_BTSC_THRSHLD__A 0x10300231175#define AUD_DEM_WR_BTSC_THRSHLD__W 161176#define AUD_DEM_WR_BTSC_THRSHLD__M 0xFFFF1177#define AUD_DEM_WR_BTSC_THRSHLD__PRE 0xC1178 1179#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__B 01180#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__W 121181#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__M 0xFFF1182#define AUD_DEM_WR_BTSC_THRSHLD_BTSC_THLD__PRE 0xC1183 1184#define AUD_DEM_WR_CM_A_THRSHLD__A 0x10300241185#define AUD_DEM_WR_CM_A_THRSHLD__W 161186#define AUD_DEM_WR_CM_A_THRSHLD__M 0xFFFF1187#define AUD_DEM_WR_CM_A_THRSHLD__PRE 0x2A1188 1189#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__B 01190#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__W 121191#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__M 0xFFF1192#define AUD_DEM_WR_CM_A_THRSHLD_CM_A_THLD__PRE 0x2A1193 1194#define AUD_DEM_WR_CM_B_THRSHLD__A 0x10300251195#define AUD_DEM_WR_CM_B_THRSHLD__W 161196#define AUD_DEM_WR_CM_B_THRSHLD__M 0xFFFF1197#define AUD_DEM_WR_CM_B_THRSHLD__PRE 0x2A1198 1199#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__B 01200#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__W 121201#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__M 0xFFF1202#define AUD_DEM_WR_CM_B_THRSHLD_CM_B_THLD__PRE 0x2A1203 1204#define AUD_DEM_RD_NIC_C_AD_BITS__A 0x10200231205#define AUD_DEM_RD_NIC_C_AD_BITS__W 161206#define AUD_DEM_RD_NIC_C_AD_BITS__M 0xFFFF1207#define AUD_DEM_RD_NIC_C_AD_BITS__PRE 0x01208 1209#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__B 01210#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__W 11211#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__M 0x11212#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC__PRE 0x01213#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_NOT_SYNCED 0x01214#define AUD_DEM_RD_NIC_C_AD_BITS_NICAM_SYNC_SYNCED 0x11215 1216#define AUD_DEM_RD_NIC_C_AD_BITS_C__B 11217#define AUD_DEM_RD_NIC_C_AD_BITS_C__W 41218#define AUD_DEM_RD_NIC_C_AD_BITS_C__M 0x1E1219#define AUD_DEM_RD_NIC_C_AD_BITS_C__PRE 0x01220 1221#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__B 51222#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__W 31223#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__M 0xE01224#define AUD_DEM_RD_NIC_C_AD_BITS_ADD_BIT_LO__PRE 0x01225 1226#define AUD_DEM_RD_NIC_ADD_BITS_HI__A 0x10200381227#define AUD_DEM_RD_NIC_ADD_BITS_HI__W 161228#define AUD_DEM_RD_NIC_ADD_BITS_HI__M 0xFFFF1229#define AUD_DEM_RD_NIC_ADD_BITS_HI__PRE 0x01230 1231#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__B 01232#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__W 81233#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__M 0xFF1234#define AUD_DEM_RD_NIC_ADD_BITS_HI_ADD_BIT_HI__PRE 0x01235 1236#define AUD_DEM_RD_NIC_CIB__A 0x10200381237#define AUD_DEM_RD_NIC_CIB__W 161238#define AUD_DEM_RD_NIC_CIB__M 0xFFFF1239#define AUD_DEM_RD_NIC_CIB__PRE 0x01240 1241#define AUD_DEM_RD_NIC_CIB_CIB2__B 01242#define AUD_DEM_RD_NIC_CIB_CIB2__W 11243#define AUD_DEM_RD_NIC_CIB_CIB2__M 0x11244#define AUD_DEM_RD_NIC_CIB_CIB2__PRE 0x01245 1246#define AUD_DEM_RD_NIC_CIB_CIB1__B 11247#define AUD_DEM_RD_NIC_CIB_CIB1__W 11248#define AUD_DEM_RD_NIC_CIB_CIB1__M 0x21249#define AUD_DEM_RD_NIC_CIB_CIB1__PRE 0x01250 1251#define AUD_DEM_RD_NIC_ERROR_RATE__A 0x10200571252#define AUD_DEM_RD_NIC_ERROR_RATE__W 161253#define AUD_DEM_RD_NIC_ERROR_RATE__M 0xFFFF1254#define AUD_DEM_RD_NIC_ERROR_RATE__PRE 0x01255 1256#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__B 01257#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__W 121258#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__M 0xFFF1259#define AUD_DEM_RD_NIC_ERROR_RATE_ERROR_RATE__PRE 0x01260 1261#define AUD_DEM_WR_FM_DEEMPH__A 0x103000F1262#define AUD_DEM_WR_FM_DEEMPH__W 161263#define AUD_DEM_WR_FM_DEEMPH__M 0xFFFF1264#define AUD_DEM_WR_FM_DEEMPH__PRE 0x01265#define AUD_DEM_WR_FM_DEEMPH_50US 0x01266#define AUD_DEM_WR_FM_DEEMPH_75US 0x11267#define AUD_DEM_WR_FM_DEEMPH_OFF 0x3F1268 1269#define AUD_DEM_WR_FM_MATRIX__A 0x103006F1270#define AUD_DEM_WR_FM_MATRIX__W 161271#define AUD_DEM_WR_FM_MATRIX__M 0xFFFF1272#define AUD_DEM_WR_FM_MATRIX__PRE 0x01273#define AUD_DEM_WR_FM_MATRIX_NO_MATRIX 0x01274#define AUD_DEM_WR_FM_MATRIX_GERMAN_MATRIX 0x11275#define AUD_DEM_WR_FM_MATRIX_KOREAN_MATRIX 0x21276#define AUD_DEM_WR_FM_MATRIX_SOUND_A 0x31277#define AUD_DEM_WR_FM_MATRIX_SOUND_B 0x41278 1279#define AUD_DSP_RD_FM_IDENT_VALUE__A 0x10400181280#define AUD_DSP_RD_FM_IDENT_VALUE__W 161281#define AUD_DSP_RD_FM_IDENT_VALUE__M 0xFFFF1282#define AUD_DSP_RD_FM_IDENT_VALUE__PRE 0x01283 1284#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__B 81285#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__W 81286#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__M 0xFF001287#define AUD_DSP_RD_FM_IDENT_VALUE_FM_IDENT__PRE 0x01288 1289#define AUD_DSP_RD_FM_DC_LEVEL_A__A 0x104001B1290#define AUD_DSP_RD_FM_DC_LEVEL_A__W 161291#define AUD_DSP_RD_FM_DC_LEVEL_A__M 0xFFFF1292#define AUD_DSP_RD_FM_DC_LEVEL_A__PRE 0x01293 1294#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__B 01295#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__W 161296#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__M 0xFFFF1297#define AUD_DSP_RD_FM_DC_LEVEL_A_FM_DC_LEV_A__PRE 0x01298 1299#define AUD_DSP_RD_FM_DC_LEVEL_B__A 0x104001C1300#define AUD_DSP_RD_FM_DC_LEVEL_B__W 161301#define AUD_DSP_RD_FM_DC_LEVEL_B__M 0xFFFF1302#define AUD_DSP_RD_FM_DC_LEVEL_B__PRE 0x01303 1304#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__B 01305#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__W 161306#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__M 0xFFFF1307#define AUD_DSP_RD_FM_DC_LEVEL_B_FM_DC_LEV_B__PRE 0x01308 1309#define AUD_DEM_WR_FM_DC_NOTCH_SW__A 0x10300171310#define AUD_DEM_WR_FM_DC_NOTCH_SW__W 161311#define AUD_DEM_WR_FM_DC_NOTCH_SW__M 0xFFFF1312#define AUD_DEM_WR_FM_DC_NOTCH_SW__PRE 0x01313 1314#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__B 01315#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__W 161316#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__M 0xFFFF1317#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW__PRE 0x01318#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_ON 0x01319#define AUD_DEM_WR_FM_DC_NOTCH_SW_FM_DC_NO_SW_OFF 0x3F1320 1321#define AUD_DSP_WR_SYNC_OUT__A 0x10500261322#define AUD_DSP_WR_SYNC_OUT__W 161323#define AUD_DSP_WR_SYNC_OUT__M 0xFFFF1324#define AUD_DSP_WR_SYNC_OUT__PRE 0x01325#define AUD_DSP_WR_SYNC_OUT_OFF 0x01326#define AUD_DSP_WR_SYNC_OUT_SYNCHRONOUS 0x11327 1328#define AUD_XFP_DRAM_1K__A 0x10600001329#define AUD_XFP_DRAM_1K__W 161330#define AUD_XFP_DRAM_1K__M 0xFFFF1331#define AUD_XFP_DRAM_1K__PRE 0x01332#define AUD_XFP_DRAM_1K_D__B 01333#define AUD_XFP_DRAM_1K_D__W 161334#define AUD_XFP_DRAM_1K_D__M 0xFFFF1335#define AUD_XFP_DRAM_1K_D__PRE 0x01336 1337#define AUD_XFP_PRAM_4K__A 0x10700001338#define AUD_XFP_PRAM_4K__W 161339#define AUD_XFP_PRAM_4K__M 0xFFFF1340#define AUD_XFP_PRAM_4K__PRE 0x01341#define AUD_XFP_PRAM_4K_D__B 01342#define AUD_XFP_PRAM_4K_D__W 161343#define AUD_XFP_PRAM_4K_D__M 0xFFFF1344#define AUD_XFP_PRAM_4K_D__PRE 0x01345 1346#define AUD_XDFP_DRAM_1K__A 0x10800001347#define AUD_XDFP_DRAM_1K__W 161348#define AUD_XDFP_DRAM_1K__M 0xFFFF1349#define AUD_XDFP_DRAM_1K__PRE 0x01350#define AUD_XDFP_DRAM_1K_D__B 01351#define AUD_XDFP_DRAM_1K_D__W 161352#define AUD_XDFP_DRAM_1K_D__M 0xFFFF1353#define AUD_XDFP_DRAM_1K_D__PRE 0x01354 1355#define AUD_XDFP_PRAM_4K__A 0x10900001356#define AUD_XDFP_PRAM_4K__W 161357#define AUD_XDFP_PRAM_4K__M 0xFFFF1358#define AUD_XDFP_PRAM_4K__PRE 0x01359#define AUD_XDFP_PRAM_4K_D__B 01360#define AUD_XDFP_PRAM_4K_D__W 161361#define AUD_XDFP_PRAM_4K_D__M 0xFFFF1362#define AUD_XDFP_PRAM_4K_D__PRE 0x01363 1364#define FEC_COMM_EXEC__A 0x24000001365#define FEC_COMM_EXEC__W 21366#define FEC_COMM_EXEC__M 0x31367#define FEC_COMM_EXEC__PRE 0x01368#define FEC_COMM_EXEC_STOP 0x01369#define FEC_COMM_EXEC_ACTIVE 0x11370#define FEC_COMM_EXEC_HOLD 0x21371 1372#define FEC_COMM_MB__A 0x24000021373#define FEC_COMM_MB__W 161374#define FEC_COMM_MB__M 0xFFFF1375#define FEC_COMM_MB__PRE 0x01376#define FEC_COMM_INT_REQ__A 0x24000031377#define FEC_COMM_INT_REQ__W 161378#define FEC_COMM_INT_REQ__M 0xFFFF1379#define FEC_COMM_INT_REQ__PRE 0x01380#define FEC_COMM_INT_REQ_OC_REQ__B 01381#define FEC_COMM_INT_REQ_OC_REQ__W 11382#define FEC_COMM_INT_REQ_OC_REQ__M 0x11383#define FEC_COMM_INT_REQ_OC_REQ__PRE 0x01384#define FEC_COMM_INT_REQ_RS_REQ__B 11385#define FEC_COMM_INT_REQ_RS_REQ__W 11386#define FEC_COMM_INT_REQ_RS_REQ__M 0x21387#define FEC_COMM_INT_REQ_RS_REQ__PRE 0x01388#define FEC_COMM_INT_REQ_DI_REQ__B 21389#define FEC_COMM_INT_REQ_DI_REQ__W 11390#define FEC_COMM_INT_REQ_DI_REQ__M 0x41391#define FEC_COMM_INT_REQ_DI_REQ__PRE 0x01392 1393#define FEC_COMM_INT_STA__A 0x24000051394#define FEC_COMM_INT_STA__W 161395#define FEC_COMM_INT_STA__M 0xFFFF1396#define FEC_COMM_INT_STA__PRE 0x01397#define FEC_COMM_INT_MSK__A 0x24000061398#define FEC_COMM_INT_MSK__W 161399#define FEC_COMM_INT_MSK__M 0xFFFF1400#define FEC_COMM_INT_MSK__PRE 0x01401#define FEC_COMM_INT_STM__A 0x24000071402#define FEC_COMM_INT_STM__W 161403#define FEC_COMM_INT_STM__M 0xFFFF1404#define FEC_COMM_INT_STM__PRE 0x01405 1406#define FEC_TOP_COMM_EXEC__A 0x24100001407#define FEC_TOP_COMM_EXEC__W 21408#define FEC_TOP_COMM_EXEC__M 0x31409#define FEC_TOP_COMM_EXEC__PRE 0x01410#define FEC_TOP_COMM_EXEC_STOP 0x01411#define FEC_TOP_COMM_EXEC_ACTIVE 0x11412#define FEC_TOP_COMM_EXEC_HOLD 0x21413 1414#define FEC_TOP_ANNEX__A 0x24100101415#define FEC_TOP_ANNEX__W 21416#define FEC_TOP_ANNEX__M 0x31417#define FEC_TOP_ANNEX__PRE 0x01418#define FEC_TOP_ANNEX_A 0x01419#define FEC_TOP_ANNEX_B 0x11420#define FEC_TOP_ANNEX_C 0x21421#define FEC_TOP_ANNEX_D 0x31422 1423#define FEC_DI_COMM_EXEC__A 0x24200001424#define FEC_DI_COMM_EXEC__W 21425#define FEC_DI_COMM_EXEC__M 0x31426#define FEC_DI_COMM_EXEC__PRE 0x01427#define FEC_DI_COMM_EXEC_STOP 0x01428#define FEC_DI_COMM_EXEC_ACTIVE 0x11429#define FEC_DI_COMM_EXEC_HOLD 0x21430 1431#define FEC_DI_COMM_MB__A 0x24200021432#define FEC_DI_COMM_MB__W 21433#define FEC_DI_COMM_MB__M 0x31434#define FEC_DI_COMM_MB__PRE 0x01435#define FEC_DI_COMM_MB_CTL__B 01436#define FEC_DI_COMM_MB_CTL__W 11437#define FEC_DI_COMM_MB_CTL__M 0x11438#define FEC_DI_COMM_MB_CTL__PRE 0x01439#define FEC_DI_COMM_MB_CTL_OFF 0x01440#define FEC_DI_COMM_MB_CTL_ON 0x11441#define FEC_DI_COMM_MB_OBS__B 11442#define FEC_DI_COMM_MB_OBS__W 11443#define FEC_DI_COMM_MB_OBS__M 0x21444#define FEC_DI_COMM_MB_OBS__PRE 0x01445#define FEC_DI_COMM_MB_OBS_OFF 0x01446#define FEC_DI_COMM_MB_OBS_ON 0x21447 1448#define FEC_DI_COMM_INT_REQ__A 0x24200031449#define FEC_DI_COMM_INT_REQ__W 11450#define FEC_DI_COMM_INT_REQ__M 0x11451#define FEC_DI_COMM_INT_REQ__PRE 0x01452#define FEC_DI_COMM_INT_STA__A 0x24200051453#define FEC_DI_COMM_INT_STA__W 21454#define FEC_DI_COMM_INT_STA__M 0x31455#define FEC_DI_COMM_INT_STA__PRE 0x01456 1457#define FEC_DI_COMM_INT_STA_STAT_INT__B 01458#define FEC_DI_COMM_INT_STA_STAT_INT__W 11459#define FEC_DI_COMM_INT_STA_STAT_INT__M 0x11460#define FEC_DI_COMM_INT_STA_STAT_INT__PRE 0x01461 1462#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__B 11463#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__W 11464#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__M 0x21465#define FEC_DI_COMM_INT_STA_TIMEOUT_INT__PRE 0x01466 1467#define FEC_DI_COMM_INT_MSK__A 0x24200061468#define FEC_DI_COMM_INT_MSK__W 21469#define FEC_DI_COMM_INT_MSK__M 0x31470#define FEC_DI_COMM_INT_MSK__PRE 0x01471#define FEC_DI_COMM_INT_MSK_STAT_INT__B 01472#define FEC_DI_COMM_INT_MSK_STAT_INT__W 11473#define FEC_DI_COMM_INT_MSK_STAT_INT__M 0x11474#define FEC_DI_COMM_INT_MSK_STAT_INT__PRE 0x01475#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__B 11476#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__W 11477#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__M 0x21478#define FEC_DI_COMM_INT_MSK_TIMEOUT_INT__PRE 0x01479 1480#define FEC_DI_COMM_INT_STM__A 0x24200071481#define FEC_DI_COMM_INT_STM__W 21482#define FEC_DI_COMM_INT_STM__M 0x31483#define FEC_DI_COMM_INT_STM__PRE 0x01484#define FEC_DI_COMM_INT_STM_STAT_INT__B 01485#define FEC_DI_COMM_INT_STM_STAT_INT__W 11486#define FEC_DI_COMM_INT_STM_STAT_INT__M 0x11487#define FEC_DI_COMM_INT_STM_STAT_INT__PRE 0x01488#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__B 11489#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__W 11490#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__M 0x21491#define FEC_DI_COMM_INT_STM_TIMEOUT_INT__PRE 0x01492 1493#define FEC_DI_STATUS__A 0x24200101494#define FEC_DI_STATUS__W 11495#define FEC_DI_STATUS__M 0x11496#define FEC_DI_STATUS__PRE 0x01497#define FEC_DI_MODE__A 0x24200111498#define FEC_DI_MODE__W 31499#define FEC_DI_MODE__M 0x71500#define FEC_DI_MODE__PRE 0x01501 1502#define FEC_DI_MODE_NO_SYNC__B 01503#define FEC_DI_MODE_NO_SYNC__W 11504#define FEC_DI_MODE_NO_SYNC__M 0x11505#define FEC_DI_MODE_NO_SYNC__PRE 0x01506 1507#define FEC_DI_MODE_IGNORE_LOST_SYNC__B 11508#define FEC_DI_MODE_IGNORE_LOST_SYNC__W 11509#define FEC_DI_MODE_IGNORE_LOST_SYNC__M 0x21510#define FEC_DI_MODE_IGNORE_LOST_SYNC__PRE 0x01511 1512#define FEC_DI_MODE_IGNORE_TIMEOUT__B 21513#define FEC_DI_MODE_IGNORE_TIMEOUT__W 11514#define FEC_DI_MODE_IGNORE_TIMEOUT__M 0x41515#define FEC_DI_MODE_IGNORE_TIMEOUT__PRE 0x01516 1517#define FEC_DI_CONTROL_WORD__A 0x24200121518#define FEC_DI_CONTROL_WORD__W 41519#define FEC_DI_CONTROL_WORD__M 0xF1520#define FEC_DI_CONTROL_WORD__PRE 0x01521 1522#define FEC_DI_RESTART__A 0x24200131523#define FEC_DI_RESTART__W 11524#define FEC_DI_RESTART__M 0x11525#define FEC_DI_RESTART__PRE 0x01526 1527#define FEC_DI_TIMEOUT_LO__A 0x24200141528#define FEC_DI_TIMEOUT_LO__W 161529#define FEC_DI_TIMEOUT_LO__M 0xFFFF1530#define FEC_DI_TIMEOUT_LO__PRE 0x01531 1532#define FEC_DI_TIMEOUT_HI__A 0x24200151533#define FEC_DI_TIMEOUT_HI__W 81534#define FEC_DI_TIMEOUT_HI__M 0xFF1535#define FEC_DI_TIMEOUT_HI__PRE 0xA1536 1537#define FEC_RS_COMM_EXEC__A 0x24300001538#define FEC_RS_COMM_EXEC__W 21539#define FEC_RS_COMM_EXEC__M 0x31540#define FEC_RS_COMM_EXEC__PRE 0x01541#define FEC_RS_COMM_EXEC_STOP 0x01542#define FEC_RS_COMM_EXEC_ACTIVE 0x11543#define FEC_RS_COMM_EXEC_HOLD 0x21544 1545#define FEC_RS_COMM_MB__A 0x24300021546#define FEC_RS_COMM_MB__W 21547#define FEC_RS_COMM_MB__M 0x31548#define FEC_RS_COMM_MB__PRE 0x01549#define FEC_RS_COMM_MB_CTL__B 01550#define FEC_RS_COMM_MB_CTL__W 11551#define FEC_RS_COMM_MB_CTL__M 0x11552#define FEC_RS_COMM_MB_CTL__PRE 0x01553#define FEC_RS_COMM_MB_CTL_OFF 0x01554#define FEC_RS_COMM_MB_CTL_ON 0x11555#define FEC_RS_COMM_MB_OBS__B 11556#define FEC_RS_COMM_MB_OBS__W 11557#define FEC_RS_COMM_MB_OBS__M 0x21558#define FEC_RS_COMM_MB_OBS__PRE 0x01559#define FEC_RS_COMM_MB_OBS_OFF 0x01560#define FEC_RS_COMM_MB_OBS_ON 0x21561 1562#define FEC_RS_COMM_INT_REQ__A 0x24300031563#define FEC_RS_COMM_INT_REQ__W 11564#define FEC_RS_COMM_INT_REQ__M 0x11565#define FEC_RS_COMM_INT_REQ__PRE 0x01566#define FEC_RS_COMM_INT_STA__A 0x24300051567#define FEC_RS_COMM_INT_STA__W 21568#define FEC_RS_COMM_INT_STA__M 0x31569#define FEC_RS_COMM_INT_STA__PRE 0x01570 1571#define FEC_RS_COMM_INT_STA_FAILURE_INT__B 01572#define FEC_RS_COMM_INT_STA_FAILURE_INT__W 11573#define FEC_RS_COMM_INT_STA_FAILURE_INT__M 0x11574#define FEC_RS_COMM_INT_STA_FAILURE_INT__PRE 0x01575 1576#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__B 11577#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__W 11578#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__M 0x21579#define FEC_RS_COMM_INT_STA_MEASUREMENT_INT__PRE 0x01580 1581#define FEC_RS_COMM_INT_MSK__A 0x24300061582#define FEC_RS_COMM_INT_MSK__W 21583#define FEC_RS_COMM_INT_MSK__M 0x31584#define FEC_RS_COMM_INT_MSK__PRE 0x01585#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__B 01586#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__W 11587#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__M 0x11588#define FEC_RS_COMM_INT_MSK_FAILURE_MSK__PRE 0x01589#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__B 11590#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__W 11591#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__M 0x21592#define FEC_RS_COMM_INT_MSK_MEASUREMENT_MSK__PRE 0x01593 1594#define FEC_RS_COMM_INT_STM__A 0x24300071595#define FEC_RS_COMM_INT_STM__W 21596#define FEC_RS_COMM_INT_STM__M 0x31597#define FEC_RS_COMM_INT_STM__PRE 0x01598#define FEC_RS_COMM_INT_STM_FAILURE_MSK__B 01599#define FEC_RS_COMM_INT_STM_FAILURE_MSK__W 11600#define FEC_RS_COMM_INT_STM_FAILURE_MSK__M 0x11601#define FEC_RS_COMM_INT_STM_FAILURE_MSK__PRE 0x01602#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__B 11603#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__W 11604#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__M 0x21605#define FEC_RS_COMM_INT_STM_MEASUREMENT_MSK__PRE 0x01606 1607#define FEC_RS_STATUS__A 0x24300101608#define FEC_RS_STATUS__W 11609#define FEC_RS_STATUS__M 0x11610#define FEC_RS_STATUS__PRE 0x01611#define FEC_RS_MODE__A 0x24300111612#define FEC_RS_MODE__W 11613#define FEC_RS_MODE__M 0x11614#define FEC_RS_MODE__PRE 0x01615 1616#define FEC_RS_MODE_BYPASS__B 01617#define FEC_RS_MODE_BYPASS__W 11618#define FEC_RS_MODE_BYPASS__M 0x11619#define FEC_RS_MODE_BYPASS__PRE 0x01620 1621#define FEC_RS_MEASUREMENT_PERIOD__A 0x24300121622#define FEC_RS_MEASUREMENT_PERIOD__W 161623#define FEC_RS_MEASUREMENT_PERIOD__M 0xFFFF1624#define FEC_RS_MEASUREMENT_PERIOD__PRE 0x11711625 1626#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__B 01627#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__W 161628#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF1629#define FEC_RS_MEASUREMENT_PERIOD_PERIOD__PRE 0x11711630 1631#define FEC_RS_MEASUREMENT_PRESCALE__A 0x24300131632#define FEC_RS_MEASUREMENT_PRESCALE__W 161633#define FEC_RS_MEASUREMENT_PRESCALE__M 0xFFFF1634#define FEC_RS_MEASUREMENT_PRESCALE__PRE 0x11635 1636#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__B 01637#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__W 161638#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF1639#define FEC_RS_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x11640 1641#define FEC_RS_NR_BIT_ERRORS__A 0x24300141642#define FEC_RS_NR_BIT_ERRORS__W 161643#define FEC_RS_NR_BIT_ERRORS__M 0xFFFF1644#define FEC_RS_NR_BIT_ERRORS__PRE 0xFFFF1645 1646#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__B 01647#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__W 121648#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__M 0xFFF1649#define FEC_RS_NR_BIT_ERRORS_FIXED_MANT__PRE 0xFFF1650 1651#define FEC_RS_NR_BIT_ERRORS_EXP__B 121652#define FEC_RS_NR_BIT_ERRORS_EXP__W 41653#define FEC_RS_NR_BIT_ERRORS_EXP__M 0xF0001654#define FEC_RS_NR_BIT_ERRORS_EXP__PRE 0xF0001655 1656#define FEC_RS_NR_SYMBOL_ERRORS__A 0x24300151657#define FEC_RS_NR_SYMBOL_ERRORS__W 161658#define FEC_RS_NR_SYMBOL_ERRORS__M 0xFFFF1659#define FEC_RS_NR_SYMBOL_ERRORS__PRE 0xFFFF1660 1661#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__B 01662#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__W 121663#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF1664#define FEC_RS_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF1665 1666#define FEC_RS_NR_SYMBOL_ERRORS_EXP__B 121667#define FEC_RS_NR_SYMBOL_ERRORS_EXP__W 41668#define FEC_RS_NR_SYMBOL_ERRORS_EXP__M 0xF0001669#define FEC_RS_NR_SYMBOL_ERRORS_EXP__PRE 0xF0001670 1671#define FEC_RS_NR_PACKET_ERRORS__A 0x24300161672#define FEC_RS_NR_PACKET_ERRORS__W 161673#define FEC_RS_NR_PACKET_ERRORS__M 0xFFFF1674#define FEC_RS_NR_PACKET_ERRORS__PRE 0xFFFF1675 1676#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__B 01677#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__W 121678#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__M 0xFFF1679#define FEC_RS_NR_PACKET_ERRORS_FIXED_MANT__PRE 0xFFF1680 1681#define FEC_RS_NR_PACKET_ERRORS_EXP__B 121682#define FEC_RS_NR_PACKET_ERRORS_EXP__W 41683#define FEC_RS_NR_PACKET_ERRORS_EXP__M 0xF0001684#define FEC_RS_NR_PACKET_ERRORS_EXP__PRE 0xF0001685 1686#define FEC_RS_NR_FAILURES__A 0x24300171687#define FEC_RS_NR_FAILURES__W 161688#define FEC_RS_NR_FAILURES__M 0xFFFF1689#define FEC_RS_NR_FAILURES__PRE 0x01690 1691#define FEC_RS_NR_FAILURES_FIXED_MANT__B 01692#define FEC_RS_NR_FAILURES_FIXED_MANT__W 121693#define FEC_RS_NR_FAILURES_FIXED_MANT__M 0xFFF1694#define FEC_RS_NR_FAILURES_FIXED_MANT__PRE 0x01695 1696#define FEC_RS_NR_FAILURES_EXP__B 121697#define FEC_RS_NR_FAILURES_EXP__W 41698#define FEC_RS_NR_FAILURES_EXP__M 0xF0001699#define FEC_RS_NR_FAILURES_EXP__PRE 0x01700 1701#define FEC_OC_COMM_EXEC__A 0x24400001702#define FEC_OC_COMM_EXEC__W 21703#define FEC_OC_COMM_EXEC__M 0x31704#define FEC_OC_COMM_EXEC__PRE 0x01705#define FEC_OC_COMM_EXEC_STOP 0x01706#define FEC_OC_COMM_EXEC_ACTIVE 0x11707#define FEC_OC_COMM_EXEC_HOLD 0x21708 1709#define FEC_OC_COMM_MB__A 0x24400021710#define FEC_OC_COMM_MB__W 21711#define FEC_OC_COMM_MB__M 0x31712#define FEC_OC_COMM_MB__PRE 0x01713#define FEC_OC_COMM_MB_CTL__B 01714#define FEC_OC_COMM_MB_CTL__W 11715#define FEC_OC_COMM_MB_CTL__M 0x11716#define FEC_OC_COMM_MB_CTL__PRE 0x01717#define FEC_OC_COMM_MB_CTL_OFF 0x01718#define FEC_OC_COMM_MB_CTL_ON 0x11719#define FEC_OC_COMM_MB_OBS__B 11720#define FEC_OC_COMM_MB_OBS__W 11721#define FEC_OC_COMM_MB_OBS__M 0x21722#define FEC_OC_COMM_MB_OBS__PRE 0x01723#define FEC_OC_COMM_MB_OBS_OFF 0x01724#define FEC_OC_COMM_MB_OBS_ON 0x21725 1726#define FEC_OC_COMM_INT_REQ__A 0x24400031727#define FEC_OC_COMM_INT_REQ__W 11728#define FEC_OC_COMM_INT_REQ__M 0x11729#define FEC_OC_COMM_INT_REQ__PRE 0x01730#define FEC_OC_COMM_INT_STA__A 0x24400051731#define FEC_OC_COMM_INT_STA__W 81732#define FEC_OC_COMM_INT_STA__M 0xFF1733#define FEC_OC_COMM_INT_STA__PRE 0x01734 1735#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__B 01736#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__W 11737#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__M 0x11738#define FEC_OC_COMM_INT_STA_DPR_LOCK_INT__PRE 0x01739 1740#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__B 11741#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__W 11742#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__M 0x21743#define FEC_OC_COMM_INT_STA_SNC_LOCK_INT__PRE 0x01744 1745#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__B 21746#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__W 11747#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__M 0x41748#define FEC_OC_COMM_INT_STA_SNC_LOST_INT__PRE 0x01749 1750#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__B 31751#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__W 11752#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__M 0x81753#define FEC_OC_COMM_INT_STA_SNC_PAR_INT__PRE 0x01754 1755#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__B 41756#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__W 11757#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__M 0x101758#define FEC_OC_COMM_INT_STA_FIFO_FULL_INT__PRE 0x01759 1760#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__B 51761#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__W 11762#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__M 0x201763#define FEC_OC_COMM_INT_STA_FIFO_EMPTY_INT__PRE 0x01764 1765#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__B 61766#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__W 11767#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__M 0x401768#define FEC_OC_COMM_INT_STA_OCR_ACQ_INT__PRE 0x01769 1770#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__B 71771#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__W 11772#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__M 0x801773#define FEC_OC_COMM_INT_STA_STAT_CHG_INT__PRE 0x01774 1775#define FEC_OC_COMM_INT_MSK__A 0x24400061776#define FEC_OC_COMM_INT_MSK__W 81777#define FEC_OC_COMM_INT_MSK__M 0xFF1778#define FEC_OC_COMM_INT_MSK__PRE 0x01779#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__B 01780#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__W 11781#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__M 0x11782#define FEC_OC_COMM_INT_MSK_DPR_LOCK_MSK__PRE 0x01783#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__B 11784#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__W 11785#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__M 0x21786#define FEC_OC_COMM_INT_MSK_SNC_LOCK_MSK__PRE 0x01787#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__B 21788#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__W 11789#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__M 0x41790#define FEC_OC_COMM_INT_MSK_SNC_LOST_MSK__PRE 0x01791#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__B 31792#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__W 11793#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__M 0x81794#define FEC_OC_COMM_INT_MSK_SNC_PAR_MSK__PRE 0x01795#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__B 41796#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__W 11797#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__M 0x101798#define FEC_OC_COMM_INT_MSK_FIFO_FULL_MSK__PRE 0x01799#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__B 51800#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__W 11801#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__M 0x201802#define FEC_OC_COMM_INT_MSK_FIFO_EMPTY_MSK__PRE 0x01803#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__B 61804#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__W 11805#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__M 0x401806#define FEC_OC_COMM_INT_MSK_OCR_ACQ_MSK__PRE 0x01807#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__B 71808#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__W 11809#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__M 0x801810#define FEC_OC_COMM_INT_MSK_STAT_CHG_MSK__PRE 0x01811 1812#define FEC_OC_COMM_INT_STM__A 0x24400071813#define FEC_OC_COMM_INT_STM__W 81814#define FEC_OC_COMM_INT_STM__M 0xFF1815#define FEC_OC_COMM_INT_STM__PRE 0x01816#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__B 01817#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__W 11818#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__M 0x11819#define FEC_OC_COMM_INT_STM_DPR_LOCK_MSK__PRE 0x01820#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__B 11821#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__W 11822#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__M 0x21823#define FEC_OC_COMM_INT_STM_SNC_LOCK_MSK__PRE 0x01824#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__B 21825#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__W 11826#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__M 0x41827#define FEC_OC_COMM_INT_STM_SNC_LOST_MSK__PRE 0x01828#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__B 31829#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__W 11830#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__M 0x81831#define FEC_OC_COMM_INT_STM_SNC_PAR_MSK__PRE 0x01832#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__B 41833#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__W 11834#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__M 0x101835#define FEC_OC_COMM_INT_STM_FIFO_FULL_MSK__PRE 0x01836#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__B 51837#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__W 11838#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__M 0x201839#define FEC_OC_COMM_INT_STM_FIFO_EMPTY_MSK__PRE 0x01840#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__B 61841#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__W 11842#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__M 0x401843#define FEC_OC_COMM_INT_STM_OCR_ACQ_MSK__PRE 0x01844#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__B 71845#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__W 11846#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__M 0x801847#define FEC_OC_COMM_INT_STM_STAT_CHG_MSK__PRE 0x01848 1849#define FEC_OC_STATUS__A 0x24400101850#define FEC_OC_STATUS__W 51851#define FEC_OC_STATUS__M 0x1F1852#define FEC_OC_STATUS__PRE 0x01853 1854#define FEC_OC_STATUS_DPR_STATUS__B 01855#define FEC_OC_STATUS_DPR_STATUS__W 11856#define FEC_OC_STATUS_DPR_STATUS__M 0x11857#define FEC_OC_STATUS_DPR_STATUS__PRE 0x01858 1859#define FEC_OC_STATUS_SNC_STATUS__B 11860#define FEC_OC_STATUS_SNC_STATUS__W 21861#define FEC_OC_STATUS_SNC_STATUS__M 0x61862#define FEC_OC_STATUS_SNC_STATUS__PRE 0x01863 1864#define FEC_OC_STATUS_FIFO_FULL__B 31865#define FEC_OC_STATUS_FIFO_FULL__W 11866#define FEC_OC_STATUS_FIFO_FULL__M 0x81867#define FEC_OC_STATUS_FIFO_FULL__PRE 0x01868 1869#define FEC_OC_STATUS_FIFO_EMPTY__B 41870#define FEC_OC_STATUS_FIFO_EMPTY__W 11871#define FEC_OC_STATUS_FIFO_EMPTY__M 0x101872#define FEC_OC_STATUS_FIFO_EMPTY__PRE 0x01873 1874#define FEC_OC_MODE__A 0x24400111875#define FEC_OC_MODE__W 41876#define FEC_OC_MODE__M 0xF1877#define FEC_OC_MODE__PRE 0x01878 1879#define FEC_OC_MODE_PARITY__B 01880#define FEC_OC_MODE_PARITY__W 11881#define FEC_OC_MODE_PARITY__M 0x11882#define FEC_OC_MODE_PARITY__PRE 0x01883 1884#define FEC_OC_MODE_TRANSPARENT__B 11885#define FEC_OC_MODE_TRANSPARENT__W 11886#define FEC_OC_MODE_TRANSPARENT__M 0x21887#define FEC_OC_MODE_TRANSPARENT__PRE 0x01888 1889#define FEC_OC_MODE_CLEAR__B 21890#define FEC_OC_MODE_CLEAR__W 11891#define FEC_OC_MODE_CLEAR__M 0x41892#define FEC_OC_MODE_CLEAR__PRE 0x01893 1894#define FEC_OC_MODE_RETAIN_FRAMING__B 31895#define FEC_OC_MODE_RETAIN_FRAMING__W 11896#define FEC_OC_MODE_RETAIN_FRAMING__M 0x81897#define FEC_OC_MODE_RETAIN_FRAMING__PRE 0x01898 1899#define FEC_OC_DPR_MODE__A 0x24400121900#define FEC_OC_DPR_MODE__W 21901#define FEC_OC_DPR_MODE__M 0x31902#define FEC_OC_DPR_MODE__PRE 0x01903 1904#define FEC_OC_DPR_MODE_ERR_DISABLE__B 01905#define FEC_OC_DPR_MODE_ERR_DISABLE__W 11906#define FEC_OC_DPR_MODE_ERR_DISABLE__M 0x11907#define FEC_OC_DPR_MODE_ERR_DISABLE__PRE 0x01908 1909#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__B 11910#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__W 11911#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__M 0x21912#define FEC_OC_DPR_MODE_NOSYNC_ENABLE__PRE 0x01913 1914#define FEC_OC_DPR_UNLOCK__A 0x24400131915#define FEC_OC_DPR_UNLOCK__W 11916#define FEC_OC_DPR_UNLOCK__M 0x11917#define FEC_OC_DPR_UNLOCK__PRE 0x01918#define FEC_OC_DTO_MODE__A 0x24400141919#define FEC_OC_DTO_MODE__W 31920#define FEC_OC_DTO_MODE__M 0x71921#define FEC_OC_DTO_MODE__PRE 0x01922 1923#define FEC_OC_DTO_MODE_DYNAMIC__B 01924#define FEC_OC_DTO_MODE_DYNAMIC__W 11925#define FEC_OC_DTO_MODE_DYNAMIC__M 0x11926#define FEC_OC_DTO_MODE_DYNAMIC__PRE 0x01927 1928#define FEC_OC_DTO_MODE_DUTY_CYCLE__B 11929#define FEC_OC_DTO_MODE_DUTY_CYCLE__W 11930#define FEC_OC_DTO_MODE_DUTY_CYCLE__M 0x21931#define FEC_OC_DTO_MODE_DUTY_CYCLE__PRE 0x01932 1933#define FEC_OC_DTO_MODE_OFFSET_ENABLE__B 21934#define FEC_OC_DTO_MODE_OFFSET_ENABLE__W 11935#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x41936#define FEC_OC_DTO_MODE_OFFSET_ENABLE__PRE 0x01937 1938#define FEC_OC_DTO_PERIOD__A 0x24400151939#define FEC_OC_DTO_PERIOD__W 81940#define FEC_OC_DTO_PERIOD__M 0xFF1941#define FEC_OC_DTO_PERIOD__PRE 0x01942#define FEC_OC_DTO_RATE_LO__A 0x24400161943#define FEC_OC_DTO_RATE_LO__W 161944#define FEC_OC_DTO_RATE_LO__M 0xFFFF1945#define FEC_OC_DTO_RATE_LO__PRE 0x01946 1947#define FEC_OC_DTO_RATE_LO_RATE_LO__B 01948#define FEC_OC_DTO_RATE_LO_RATE_LO__W 161949#define FEC_OC_DTO_RATE_LO_RATE_LO__M 0xFFFF1950#define FEC_OC_DTO_RATE_LO_RATE_LO__PRE 0x01951 1952#define FEC_OC_DTO_RATE_HI__A 0x24400171953#define FEC_OC_DTO_RATE_HI__W 101954#define FEC_OC_DTO_RATE_HI__M 0x3FF1955#define FEC_OC_DTO_RATE_HI__PRE 0xC01956 1957#define FEC_OC_DTO_RATE_HI_RATE_HI__B 01958#define FEC_OC_DTO_RATE_HI_RATE_HI__W 101959#define FEC_OC_DTO_RATE_HI_RATE_HI__M 0x3FF1960#define FEC_OC_DTO_RATE_HI_RATE_HI__PRE 0xC01961 1962#define FEC_OC_DTO_BURST_LEN__A 0x24400181963#define FEC_OC_DTO_BURST_LEN__W 81964#define FEC_OC_DTO_BURST_LEN__M 0xFF1965#define FEC_OC_DTO_BURST_LEN__PRE 0xBC1966 1967#define FEC_OC_DTO_BURST_LEN_BURST_LEN__B 01968#define FEC_OC_DTO_BURST_LEN_BURST_LEN__W 81969#define FEC_OC_DTO_BURST_LEN_BURST_LEN__M 0xFF1970#define FEC_OC_DTO_BURST_LEN_BURST_LEN__PRE 0xBC1971 1972#define FEC_OC_FCT_MODE__A 0x244001A1973#define FEC_OC_FCT_MODE__W 21974#define FEC_OC_FCT_MODE__M 0x31975#define FEC_OC_FCT_MODE__PRE 0x01976 1977#define FEC_OC_FCT_MODE_RAT_ENA__B 01978#define FEC_OC_FCT_MODE_RAT_ENA__W 11979#define FEC_OC_FCT_MODE_RAT_ENA__M 0x11980#define FEC_OC_FCT_MODE_RAT_ENA__PRE 0x01981 1982#define FEC_OC_FCT_MODE_VIRT_ENA__B 11983#define FEC_OC_FCT_MODE_VIRT_ENA__W 11984#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x21985#define FEC_OC_FCT_MODE_VIRT_ENA__PRE 0x01986 1987#define FEC_OC_FCT_USAGE__A 0x244001B1988#define FEC_OC_FCT_USAGE__W 31989#define FEC_OC_FCT_USAGE__M 0x71990#define FEC_OC_FCT_USAGE__PRE 0x21991 1992#define FEC_OC_FCT_USAGE_USAGE__B 01993#define FEC_OC_FCT_USAGE_USAGE__W 31994#define FEC_OC_FCT_USAGE_USAGE__M 0x71995#define FEC_OC_FCT_USAGE_USAGE__PRE 0x21996 1997#define FEC_OC_FCT_OCCUPATION__A 0x244001C1998#define FEC_OC_FCT_OCCUPATION__W 121999#define FEC_OC_FCT_OCCUPATION__M 0xFFF2000#define FEC_OC_FCT_OCCUPATION__PRE 0x02001 2002#define FEC_OC_FCT_OCCUPATION_OCCUPATION__B 02003#define FEC_OC_FCT_OCCUPATION_OCCUPATION__W 122004#define FEC_OC_FCT_OCCUPATION_OCCUPATION__M 0xFFF2005#define FEC_OC_FCT_OCCUPATION_OCCUPATION__PRE 0x02006 2007#define FEC_OC_TMD_MODE__A 0x244001E2008#define FEC_OC_TMD_MODE__W 32009#define FEC_OC_TMD_MODE__M 0x72010#define FEC_OC_TMD_MODE__PRE 0x42011 2012#define FEC_OC_TMD_MODE_MODE__B 02013#define FEC_OC_TMD_MODE_MODE__W 32014#define FEC_OC_TMD_MODE_MODE__M 0x72015#define FEC_OC_TMD_MODE_MODE__PRE 0x42016 2017#define FEC_OC_TMD_COUNT__A 0x244001F2018#define FEC_OC_TMD_COUNT__W 102019#define FEC_OC_TMD_COUNT__M 0x3FF2020#define FEC_OC_TMD_COUNT__PRE 0x1F42021 2022#define FEC_OC_TMD_COUNT_COUNT__B 02023#define FEC_OC_TMD_COUNT_COUNT__W 102024#define FEC_OC_TMD_COUNT_COUNT__M 0x3FF2025#define FEC_OC_TMD_COUNT_COUNT__PRE 0x1F42026 2027#define FEC_OC_TMD_HI_MARGIN__A 0x24400202028#define FEC_OC_TMD_HI_MARGIN__W 112029#define FEC_OC_TMD_HI_MARGIN__M 0x7FF2030#define FEC_OC_TMD_HI_MARGIN__PRE 0x2002031 2032#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__B 02033#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__W 112034#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__M 0x7FF2035#define FEC_OC_TMD_HI_MARGIN_HI_MARGIN__PRE 0x2002036 2037#define FEC_OC_TMD_LO_MARGIN__A 0x24400212038#define FEC_OC_TMD_LO_MARGIN__W 112039#define FEC_OC_TMD_LO_MARGIN__M 0x7FF2040#define FEC_OC_TMD_LO_MARGIN__PRE 0x1002041 2042#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__B 02043#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__W 112044#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__M 0x7FF2045#define FEC_OC_TMD_LO_MARGIN_LO_MARGIN__PRE 0x1002046 2047#define FEC_OC_TMD_CTL_UPD_RATE__A 0x24400222048#define FEC_OC_TMD_CTL_UPD_RATE__W 42049#define FEC_OC_TMD_CTL_UPD_RATE__M 0xF2050#define FEC_OC_TMD_CTL_UPD_RATE__PRE 0x12051 2052#define FEC_OC_TMD_CTL_UPD_RATE_RATE__B 02053#define FEC_OC_TMD_CTL_UPD_RATE_RATE__W 42054#define FEC_OC_TMD_CTL_UPD_RATE_RATE__M 0xF2055#define FEC_OC_TMD_CTL_UPD_RATE_RATE__PRE 0x12056 2057#define FEC_OC_TMD_INT_UPD_RATE__A 0x24400232058#define FEC_OC_TMD_INT_UPD_RATE__W 42059#define FEC_OC_TMD_INT_UPD_RATE__M 0xF2060#define FEC_OC_TMD_INT_UPD_RATE__PRE 0x42061 2062#define FEC_OC_TMD_INT_UPD_RATE_RATE__B 02063#define FEC_OC_TMD_INT_UPD_RATE_RATE__W 42064#define FEC_OC_TMD_INT_UPD_RATE_RATE__M 0xF2065#define FEC_OC_TMD_INT_UPD_RATE_RATE__PRE 0x42066 2067#define FEC_OC_AVR_PARM_A__A 0x24400262068#define FEC_OC_AVR_PARM_A__W 42069#define FEC_OC_AVR_PARM_A__M 0xF2070#define FEC_OC_AVR_PARM_A__PRE 0x62071 2072#define FEC_OC_AVR_PARM_A_PARM__B 02073#define FEC_OC_AVR_PARM_A_PARM__W 42074#define FEC_OC_AVR_PARM_A_PARM__M 0xF2075#define FEC_OC_AVR_PARM_A_PARM__PRE 0x62076 2077#define FEC_OC_AVR_PARM_B__A 0x24400272078#define FEC_OC_AVR_PARM_B__W 42079#define FEC_OC_AVR_PARM_B__M 0xF2080#define FEC_OC_AVR_PARM_B__PRE 0x42081 2082#define FEC_OC_AVR_PARM_B_PARM__B 02083#define FEC_OC_AVR_PARM_B_PARM__W 42084#define FEC_OC_AVR_PARM_B_PARM__M 0xF2085#define FEC_OC_AVR_PARM_B_PARM__PRE 0x42086 2087#define FEC_OC_AVR_AVG_LO__A 0x24400282088#define FEC_OC_AVR_AVG_LO__W 162089#define FEC_OC_AVR_AVG_LO__M 0xFFFF2090#define FEC_OC_AVR_AVG_LO__PRE 0x02091 2092#define FEC_OC_AVR_AVG_LO_AVG_LO__B 02093#define FEC_OC_AVR_AVG_LO_AVG_LO__W 162094#define FEC_OC_AVR_AVG_LO_AVG_LO__M 0xFFFF2095#define FEC_OC_AVR_AVG_LO_AVG_LO__PRE 0x02096 2097#define FEC_OC_AVR_AVG_HI__A 0x24400292098#define FEC_OC_AVR_AVG_HI__W 62099#define FEC_OC_AVR_AVG_HI__M 0x3F2100#define FEC_OC_AVR_AVG_HI__PRE 0x02101 2102#define FEC_OC_AVR_AVG_HI_AVG_HI__B 02103#define FEC_OC_AVR_AVG_HI_AVG_HI__W 62104#define FEC_OC_AVR_AVG_HI_AVG_HI__M 0x3F2105#define FEC_OC_AVR_AVG_HI_AVG_HI__PRE 0x02106 2107#define FEC_OC_RCN_MODE__A 0x244002C2108#define FEC_OC_RCN_MODE__W 52109#define FEC_OC_RCN_MODE__M 0x1F2110#define FEC_OC_RCN_MODE__PRE 0x1F2111 2112#define FEC_OC_RCN_MODE_MODE__B 02113#define FEC_OC_RCN_MODE_MODE__W 52114#define FEC_OC_RCN_MODE_MODE__M 0x1F2115#define FEC_OC_RCN_MODE_MODE__PRE 0x1F2116 2117#define FEC_OC_RCN_OCC_SETTLE__A 0x244002D2118#define FEC_OC_RCN_OCC_SETTLE__W 112119#define FEC_OC_RCN_OCC_SETTLE__M 0x7FF2120#define FEC_OC_RCN_OCC_SETTLE__PRE 0x1802121 2122#define FEC_OC_RCN_OCC_SETTLE_LEVEL__B 02123#define FEC_OC_RCN_OCC_SETTLE_LEVEL__W 112124#define FEC_OC_RCN_OCC_SETTLE_LEVEL__M 0x7FF2125#define FEC_OC_RCN_OCC_SETTLE_LEVEL__PRE 0x1802126 2127#define FEC_OC_RCN_GAIN__A 0x244002E2128#define FEC_OC_RCN_GAIN__W 42129#define FEC_OC_RCN_GAIN__M 0xF2130#define FEC_OC_RCN_GAIN__PRE 0xC2131 2132#define FEC_OC_RCN_GAIN_GAIN__B 02133#define FEC_OC_RCN_GAIN_GAIN__W 42134#define FEC_OC_RCN_GAIN_GAIN__M 0xF2135#define FEC_OC_RCN_GAIN_GAIN__PRE 0xC2136 2137#define FEC_OC_RCN_CTL_RATE_LO__A 0x24400302138#define FEC_OC_RCN_CTL_RATE_LO__W 162139#define FEC_OC_RCN_CTL_RATE_LO__M 0xFFFF2140#define FEC_OC_RCN_CTL_RATE_LO__PRE 0x02141 2142#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__B 02143#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__W 162144#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__M 0xFFFF2145#define FEC_OC_RCN_CTL_RATE_LO_CTL_LO__PRE 0x02146 2147#define FEC_OC_RCN_CTL_RATE_HI__A 0x24400312148#define FEC_OC_RCN_CTL_RATE_HI__W 82149#define FEC_OC_RCN_CTL_RATE_HI__M 0xFF2150#define FEC_OC_RCN_CTL_RATE_HI__PRE 0xC02151 2152#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__B 02153#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__W 82154#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__M 0xFF2155#define FEC_OC_RCN_CTL_RATE_HI_CTL_HI__PRE 0xC02156 2157#define FEC_OC_RCN_CTL_STEP_LO__A 0x24400322158#define FEC_OC_RCN_CTL_STEP_LO__W 162159#define FEC_OC_RCN_CTL_STEP_LO__M 0xFFFF2160#define FEC_OC_RCN_CTL_STEP_LO__PRE 0x02161 2162#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__B 02163#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__W 162164#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__M 0xFFFF2165#define FEC_OC_RCN_CTL_STEP_LO_CTL_LO__PRE 0x02166 2167#define FEC_OC_RCN_CTL_STEP_HI__A 0x24400332168#define FEC_OC_RCN_CTL_STEP_HI__W 82169#define FEC_OC_RCN_CTL_STEP_HI__M 0xFF2170#define FEC_OC_RCN_CTL_STEP_HI__PRE 0x82171 2172#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__B 02173#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__W 82174#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__M 0xFF2175#define FEC_OC_RCN_CTL_STEP_HI_CTL_HI__PRE 0x82176 2177#define FEC_OC_RCN_DTO_OFS_LO__A 0x24400342178#define FEC_OC_RCN_DTO_OFS_LO__W 162179#define FEC_OC_RCN_DTO_OFS_LO__M 0xFFFF2180#define FEC_OC_RCN_DTO_OFS_LO__PRE 0x02181 2182#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__B 02183#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__W 162184#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__M 0xFFFF2185#define FEC_OC_RCN_DTO_OFS_LO_OFS_LO__PRE 0x02186 2187#define FEC_OC_RCN_DTO_OFS_HI__A 0x24400352188#define FEC_OC_RCN_DTO_OFS_HI__W 82189#define FEC_OC_RCN_DTO_OFS_HI__M 0xFF2190#define FEC_OC_RCN_DTO_OFS_HI__PRE 0x02191 2192#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__B 02193#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__W 82194#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__M 0xFF2195#define FEC_OC_RCN_DTO_OFS_HI_OFS_HI__PRE 0x02196 2197#define FEC_OC_RCN_DTO_RATE_LO__A 0x24400362198#define FEC_OC_RCN_DTO_RATE_LO__W 162199#define FEC_OC_RCN_DTO_RATE_LO__M 0xFFFF2200#define FEC_OC_RCN_DTO_RATE_LO__PRE 0x02201 2202#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__B 02203#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__W 162204#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__M 0xFFFF2205#define FEC_OC_RCN_DTO_RATE_LO_OFS_LO__PRE 0x02206 2207#define FEC_OC_RCN_DTO_RATE_HI__A 0x24400372208#define FEC_OC_RCN_DTO_RATE_HI__W 82209#define FEC_OC_RCN_DTO_RATE_HI__M 0xFF2210#define FEC_OC_RCN_DTO_RATE_HI__PRE 0x02211 2212#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__B 02213#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__W 82214#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__M 0xFF2215#define FEC_OC_RCN_DTO_RATE_HI_OFS_HI__PRE 0x02216 2217#define FEC_OC_RCN_RATE_CLIP_LO__A 0x24400382218#define FEC_OC_RCN_RATE_CLIP_LO__W 162219#define FEC_OC_RCN_RATE_CLIP_LO__M 0xFFFF2220#define FEC_OC_RCN_RATE_CLIP_LO__PRE 0x02221 2222#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__B 02223#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__W 162224#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__M 0xFFFF2225#define FEC_OC_RCN_RATE_CLIP_LO_CLIP_LO__PRE 0x02226 2227#define FEC_OC_RCN_RATE_CLIP_HI__A 0x24400392228#define FEC_OC_RCN_RATE_CLIP_HI__W 82229#define FEC_OC_RCN_RATE_CLIP_HI__M 0xFF2230#define FEC_OC_RCN_RATE_CLIP_HI__PRE 0xF02231 2232#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__B 02233#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__W 82234#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__M 0xFF2235#define FEC_OC_RCN_RATE_CLIP_HI_CLIP_HI__PRE 0xF02236 2237#define FEC_OC_RCN_DYN_RATE_LO__A 0x244003A2238#define FEC_OC_RCN_DYN_RATE_LO__W 162239#define FEC_OC_RCN_DYN_RATE_LO__M 0xFFFF2240#define FEC_OC_RCN_DYN_RATE_LO__PRE 0x02241 2242#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__B 02243#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__W 162244#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__M 0xFFFF2245#define FEC_OC_RCN_DYN_RATE_LO_RATE_LO__PRE 0x02246 2247#define FEC_OC_RCN_DYN_RATE_HI__A 0x244003B2248#define FEC_OC_RCN_DYN_RATE_HI__W 82249#define FEC_OC_RCN_DYN_RATE_HI__M 0xFF2250#define FEC_OC_RCN_DYN_RATE_HI__PRE 0x02251 2252#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__B 02253#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__W 82254#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__M 0xFF2255#define FEC_OC_RCN_DYN_RATE_HI_RATE_HI__PRE 0x02256 2257#define FEC_OC_SNC_MODE__A 0x24400402258#define FEC_OC_SNC_MODE__W 42259#define FEC_OC_SNC_MODE__M 0xF2260#define FEC_OC_SNC_MODE__PRE 0x02261 2262#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__B 02263#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__W 12264#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__M 0x12265#define FEC_OC_SNC_MODE_UNLOCK_ENABLE__PRE 0x02266 2267#define FEC_OC_SNC_MODE_ERROR_CTL__B 12268#define FEC_OC_SNC_MODE_ERROR_CTL__W 22269#define FEC_OC_SNC_MODE_ERROR_CTL__M 0x62270#define FEC_OC_SNC_MODE_ERROR_CTL__PRE 0x02271 2272#define FEC_OC_SNC_MODE_CORR_DISABLE__B 32273#define FEC_OC_SNC_MODE_CORR_DISABLE__W 12274#define FEC_OC_SNC_MODE_CORR_DISABLE__M 0x82275#define FEC_OC_SNC_MODE_CORR_DISABLE__PRE 0x02276 2277#define FEC_OC_SNC_LWM__A 0x24400412278#define FEC_OC_SNC_LWM__W 42279#define FEC_OC_SNC_LWM__M 0xF2280#define FEC_OC_SNC_LWM__PRE 0x32281 2282#define FEC_OC_SNC_LWM_MARK__B 02283#define FEC_OC_SNC_LWM_MARK__W 42284#define FEC_OC_SNC_LWM_MARK__M 0xF2285#define FEC_OC_SNC_LWM_MARK__PRE 0x32286 2287#define FEC_OC_SNC_HWM__A 0x24400422288#define FEC_OC_SNC_HWM__W 42289#define FEC_OC_SNC_HWM__M 0xF2290#define FEC_OC_SNC_HWM__PRE 0x52291 2292#define FEC_OC_SNC_HWM_MARK__B 02293#define FEC_OC_SNC_HWM_MARK__W 42294#define FEC_OC_SNC_HWM_MARK__M 0xF2295#define FEC_OC_SNC_HWM_MARK__PRE 0x52296 2297#define FEC_OC_SNC_UNLOCK__A 0x24400432298#define FEC_OC_SNC_UNLOCK__W 12299#define FEC_OC_SNC_UNLOCK__M 0x12300#define FEC_OC_SNC_UNLOCK__PRE 0x02301 2302#define FEC_OC_SNC_UNLOCK_RESTART__B 02303#define FEC_OC_SNC_UNLOCK_RESTART__W 12304#define FEC_OC_SNC_UNLOCK_RESTART__M 0x12305#define FEC_OC_SNC_UNLOCK_RESTART__PRE 0x02306 2307#define FEC_OC_SNC_LOCK_COUNT__A 0x24400442308#define FEC_OC_SNC_LOCK_COUNT__W 122309#define FEC_OC_SNC_LOCK_COUNT__M 0xFFF2310#define FEC_OC_SNC_LOCK_COUNT__PRE 0x02311 2312#define FEC_OC_SNC_LOCK_COUNT_COUNT__B 02313#define FEC_OC_SNC_LOCK_COUNT_COUNT__W 122314#define FEC_OC_SNC_LOCK_COUNT_COUNT__M 0xFFF2315#define FEC_OC_SNC_LOCK_COUNT_COUNT__PRE 0x02316 2317#define FEC_OC_SNC_FAIL_COUNT__A 0x24400452318#define FEC_OC_SNC_FAIL_COUNT__W 122319#define FEC_OC_SNC_FAIL_COUNT__M 0xFFF2320#define FEC_OC_SNC_FAIL_COUNT__PRE 0x02321 2322#define FEC_OC_SNC_FAIL_COUNT_COUNT__B 02323#define FEC_OC_SNC_FAIL_COUNT_COUNT__W 122324#define FEC_OC_SNC_FAIL_COUNT_COUNT__M 0xFFF2325#define FEC_OC_SNC_FAIL_COUNT_COUNT__PRE 0x02326 2327#define FEC_OC_SNC_FAIL_PERIOD__A 0x24400462328#define FEC_OC_SNC_FAIL_PERIOD__W 162329#define FEC_OC_SNC_FAIL_PERIOD__M 0xFFFF2330#define FEC_OC_SNC_FAIL_PERIOD__PRE 0x11712331 2332#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__B 02333#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__W 162334#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__M 0xFFFF2335#define FEC_OC_SNC_FAIL_PERIOD_PERIOD__PRE 0x11712336 2337#define FEC_OC_EMS_MODE__A 0x24400472338#define FEC_OC_EMS_MODE__W 22339#define FEC_OC_EMS_MODE__M 0x32340#define FEC_OC_EMS_MODE__PRE 0x02341 2342#define FEC_OC_EMS_MODE_MODE__B 02343#define FEC_OC_EMS_MODE_MODE__W 22344#define FEC_OC_EMS_MODE_MODE__M 0x32345#define FEC_OC_EMS_MODE_MODE__PRE 0x02346 2347#define FEC_OC_IPR_MODE__A 0x24400482348#define FEC_OC_IPR_MODE__W 122349#define FEC_OC_IPR_MODE__M 0xFFF2350#define FEC_OC_IPR_MODE__PRE 0x02351 2352#define FEC_OC_IPR_MODE_SERIAL__B 02353#define FEC_OC_IPR_MODE_SERIAL__W 12354#define FEC_OC_IPR_MODE_SERIAL__M 0x12355#define FEC_OC_IPR_MODE_SERIAL__PRE 0x02356 2357#define FEC_OC_IPR_MODE_REVERSE_ORDER__B 12358#define FEC_OC_IPR_MODE_REVERSE_ORDER__W 12359#define FEC_OC_IPR_MODE_REVERSE_ORDER__M 0x22360#define FEC_OC_IPR_MODE_REVERSE_ORDER__PRE 0x02361 2362#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__B 22363#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__W 12364#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x42365#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__PRE 0x02366 2367#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__B 32368#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__W 12369#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__M 0x82370#define FEC_OC_IPR_MODE_MCLK_DIS_PAR__PRE 0x02371 2372#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__B 42373#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__W 12374#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x102375#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__PRE 0x02376 2377#define FEC_OC_IPR_MODE_MERR_DIS_PAR__B 52378#define FEC_OC_IPR_MODE_MERR_DIS_PAR__W 12379#define FEC_OC_IPR_MODE_MERR_DIS_PAR__M 0x202380#define FEC_OC_IPR_MODE_MERR_DIS_PAR__PRE 0x02381 2382#define FEC_OC_IPR_MODE_MD_DIS_PAR__B 62383#define FEC_OC_IPR_MODE_MD_DIS_PAR__W 12384#define FEC_OC_IPR_MODE_MD_DIS_PAR__M 0x402385#define FEC_OC_IPR_MODE_MD_DIS_PAR__PRE 0x02386 2387#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__B 72388#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__W 12389#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__M 0x802390#define FEC_OC_IPR_MODE_MCLK_DIS_ERR__PRE 0x02391 2392#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__B 82393#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__W 12394#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__M 0x1002395#define FEC_OC_IPR_MODE_MVAL_DIS_ERR__PRE 0x02396 2397#define FEC_OC_IPR_MODE_MERR_DIS_ERR__B 92398#define FEC_OC_IPR_MODE_MERR_DIS_ERR__W 12399#define FEC_OC_IPR_MODE_MERR_DIS_ERR__M 0x2002400#define FEC_OC_IPR_MODE_MERR_DIS_ERR__PRE 0x02401 2402#define FEC_OC_IPR_MODE_MD_DIS_ERR__B 102403#define FEC_OC_IPR_MODE_MD_DIS_ERR__W 12404#define FEC_OC_IPR_MODE_MD_DIS_ERR__M 0x4002405#define FEC_OC_IPR_MODE_MD_DIS_ERR__PRE 0x02406 2407#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__B 112408#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__W 12409#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__M 0x8002410#define FEC_OC_IPR_MODE_MSTRT_DIS_ERR__PRE 0x02411 2412#define FEC_OC_IPR_INVERT__A 0x24400492413#define FEC_OC_IPR_INVERT__W 122414#define FEC_OC_IPR_INVERT__M 0xFFF2415#define FEC_OC_IPR_INVERT__PRE 0x02416 2417#define FEC_OC_IPR_INVERT_MD0__B 02418#define FEC_OC_IPR_INVERT_MD0__W 12419#define FEC_OC_IPR_INVERT_MD0__M 0x12420#define FEC_OC_IPR_INVERT_MD0__PRE 0x02421 2422#define FEC_OC_IPR_INVERT_MD1__B 12423#define FEC_OC_IPR_INVERT_MD1__W 12424#define FEC_OC_IPR_INVERT_MD1__M 0x22425#define FEC_OC_IPR_INVERT_MD1__PRE 0x02426 2427#define FEC_OC_IPR_INVERT_MD2__B 22428#define FEC_OC_IPR_INVERT_MD2__W 12429#define FEC_OC_IPR_INVERT_MD2__M 0x42430#define FEC_OC_IPR_INVERT_MD2__PRE 0x02431 2432#define FEC_OC_IPR_INVERT_MD3__B 32433#define FEC_OC_IPR_INVERT_MD3__W 12434#define FEC_OC_IPR_INVERT_MD3__M 0x82435#define FEC_OC_IPR_INVERT_MD3__PRE 0x02436 2437#define FEC_OC_IPR_INVERT_MD4__B 42438#define FEC_OC_IPR_INVERT_MD4__W 12439#define FEC_OC_IPR_INVERT_MD4__M 0x102440#define FEC_OC_IPR_INVERT_MD4__PRE 0x02441 2442#define FEC_OC_IPR_INVERT_MD5__B 52443#define FEC_OC_IPR_INVERT_MD5__W 12444#define FEC_OC_IPR_INVERT_MD5__M 0x202445#define FEC_OC_IPR_INVERT_MD5__PRE 0x02446 2447#define FEC_OC_IPR_INVERT_MD6__B 62448#define FEC_OC_IPR_INVERT_MD6__W 12449#define FEC_OC_IPR_INVERT_MD6__M 0x402450#define FEC_OC_IPR_INVERT_MD6__PRE 0x02451 2452#define FEC_OC_IPR_INVERT_MD7__B 72453#define FEC_OC_IPR_INVERT_MD7__W 12454#define FEC_OC_IPR_INVERT_MD7__M 0x802455#define FEC_OC_IPR_INVERT_MD7__PRE 0x02456 2457#define FEC_OC_IPR_INVERT_MERR__B 82458#define FEC_OC_IPR_INVERT_MERR__W 12459#define FEC_OC_IPR_INVERT_MERR__M 0x1002460#define FEC_OC_IPR_INVERT_MERR__PRE 0x02461 2462#define FEC_OC_IPR_INVERT_MSTRT__B 92463#define FEC_OC_IPR_INVERT_MSTRT__W 12464#define FEC_OC_IPR_INVERT_MSTRT__M 0x2002465#define FEC_OC_IPR_INVERT_MSTRT__PRE 0x02466 2467#define FEC_OC_IPR_INVERT_MVAL__B 102468#define FEC_OC_IPR_INVERT_MVAL__W 12469#define FEC_OC_IPR_INVERT_MVAL__M 0x4002470#define FEC_OC_IPR_INVERT_MVAL__PRE 0x02471 2472#define FEC_OC_IPR_INVERT_MCLK__B 112473#define FEC_OC_IPR_INVERT_MCLK__W 12474#define FEC_OC_IPR_INVERT_MCLK__M 0x8002475#define FEC_OC_IPR_INVERT_MCLK__PRE 0x02476 2477#define FEC_OC_OCR_MODE__A 0x24400502478#define FEC_OC_OCR_MODE__W 42479#define FEC_OC_OCR_MODE__M 0xF2480#define FEC_OC_OCR_MODE__PRE 0x02481 2482#define FEC_OC_OCR_MODE_MB_SELECT__B 02483#define FEC_OC_OCR_MODE_MB_SELECT__W 12484#define FEC_OC_OCR_MODE_MB_SELECT__M 0x12485#define FEC_OC_OCR_MODE_MB_SELECT__PRE 0x02486 2487#define FEC_OC_OCR_MODE_GRAB_ENABLE__B 12488#define FEC_OC_OCR_MODE_GRAB_ENABLE__W 12489#define FEC_OC_OCR_MODE_GRAB_ENABLE__M 0x22490#define FEC_OC_OCR_MODE_GRAB_ENABLE__PRE 0x02491 2492#define FEC_OC_OCR_MODE_GRAB_SELECT__B 22493#define FEC_OC_OCR_MODE_GRAB_SELECT__W 12494#define FEC_OC_OCR_MODE_GRAB_SELECT__M 0x42495#define FEC_OC_OCR_MODE_GRAB_SELECT__PRE 0x02496 2497#define FEC_OC_OCR_MODE_GRAB_COUNTED__B 32498#define FEC_OC_OCR_MODE_GRAB_COUNTED__W 12499#define FEC_OC_OCR_MODE_GRAB_COUNTED__M 0x82500#define FEC_OC_OCR_MODE_GRAB_COUNTED__PRE 0x02501 2502#define FEC_OC_OCR_RATE__A 0x24400512503#define FEC_OC_OCR_RATE__W 42504#define FEC_OC_OCR_RATE__M 0xF2505#define FEC_OC_OCR_RATE__PRE 0x02506 2507#define FEC_OC_OCR_RATE_RATE__B 02508#define FEC_OC_OCR_RATE_RATE__W 42509#define FEC_OC_OCR_RATE_RATE__M 0xF2510#define FEC_OC_OCR_RATE_RATE__PRE 0x02511 2512#define FEC_OC_OCR_INVERT__A 0x24400522513#define FEC_OC_OCR_INVERT__W 122514#define FEC_OC_OCR_INVERT__M 0xFFF2515#define FEC_OC_OCR_INVERT__PRE 0x8002516 2517#define FEC_OC_OCR_INVERT_INVERT__B 02518#define FEC_OC_OCR_INVERT_INVERT__W 122519#define FEC_OC_OCR_INVERT_INVERT__M 0xFFF2520#define FEC_OC_OCR_INVERT_INVERT__PRE 0x8002521 2522#define FEC_OC_OCR_GRAB_COUNT__A 0x24400532523#define FEC_OC_OCR_GRAB_COUNT__W 162524#define FEC_OC_OCR_GRAB_COUNT__M 0xFFFF2525#define FEC_OC_OCR_GRAB_COUNT__PRE 0x02526 2527#define FEC_OC_OCR_GRAB_COUNT_COUNT__B 02528#define FEC_OC_OCR_GRAB_COUNT_COUNT__W 162529#define FEC_OC_OCR_GRAB_COUNT_COUNT__M 0xFFFF2530#define FEC_OC_OCR_GRAB_COUNT_COUNT__PRE 0x02531 2532#define FEC_OC_OCR_GRAB_SYNC__A 0x24400542533#define FEC_OC_OCR_GRAB_SYNC__W 82534#define FEC_OC_OCR_GRAB_SYNC__M 0xFF2535#define FEC_OC_OCR_GRAB_SYNC__PRE 0x02536 2537#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__B 02538#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__W 32539#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__M 0x72540#define FEC_OC_OCR_GRAB_SYNC_BYTE_SEL__PRE 0x02541 2542#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__B 32543#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__W 42544#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__M 0x782545#define FEC_OC_OCR_GRAB_SYNC_BIT_SEL__PRE 0x02546 2547#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__B 72548#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__W 12549#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__M 0x802550#define FEC_OC_OCR_GRAB_SYNC_VALUE_SEL__PRE 0x02551 2552#define FEC_OC_OCR_GRAB_RD0__A 0x24400552553#define FEC_OC_OCR_GRAB_RD0__W 102554#define FEC_OC_OCR_GRAB_RD0__M 0x3FF2555#define FEC_OC_OCR_GRAB_RD0__PRE 0x02556 2557#define FEC_OC_OCR_GRAB_RD0_DATA__B 02558#define FEC_OC_OCR_GRAB_RD0_DATA__W 102559#define FEC_OC_OCR_GRAB_RD0_DATA__M 0x3FF2560#define FEC_OC_OCR_GRAB_RD0_DATA__PRE 0x02561 2562#define FEC_OC_OCR_GRAB_RD1__A 0x24400562563#define FEC_OC_OCR_GRAB_RD1__W 102564#define FEC_OC_OCR_GRAB_RD1__M 0x3FF2565#define FEC_OC_OCR_GRAB_RD1__PRE 0x02566 2567#define FEC_OC_OCR_GRAB_RD1_DATA__B 02568#define FEC_OC_OCR_GRAB_RD1_DATA__W 102569#define FEC_OC_OCR_GRAB_RD1_DATA__M 0x3FF2570#define FEC_OC_OCR_GRAB_RD1_DATA__PRE 0x02571 2572#define FEC_OC_OCR_GRAB_RD2__A 0x24400572573#define FEC_OC_OCR_GRAB_RD2__W 102574#define FEC_OC_OCR_GRAB_RD2__M 0x3FF2575#define FEC_OC_OCR_GRAB_RD2__PRE 0x02576 2577#define FEC_OC_OCR_GRAB_RD2_DATA__B 02578#define FEC_OC_OCR_GRAB_RD2_DATA__W 102579#define FEC_OC_OCR_GRAB_RD2_DATA__M 0x3FF2580#define FEC_OC_OCR_GRAB_RD2_DATA__PRE 0x02581 2582#define FEC_OC_OCR_GRAB_RD3__A 0x24400582583#define FEC_OC_OCR_GRAB_RD3__W 102584#define FEC_OC_OCR_GRAB_RD3__M 0x3FF2585#define FEC_OC_OCR_GRAB_RD3__PRE 0x02586 2587#define FEC_OC_OCR_GRAB_RD3_DATA__B 02588#define FEC_OC_OCR_GRAB_RD3_DATA__W 102589#define FEC_OC_OCR_GRAB_RD3_DATA__M 0x3FF2590#define FEC_OC_OCR_GRAB_RD3_DATA__PRE 0x02591 2592#define FEC_OC_OCR_GRAB_RD4__A 0x24400592593#define FEC_OC_OCR_GRAB_RD4__W 102594#define FEC_OC_OCR_GRAB_RD4__M 0x3FF2595#define FEC_OC_OCR_GRAB_RD4__PRE 0x02596 2597#define FEC_OC_OCR_GRAB_RD4_DATA__B 02598#define FEC_OC_OCR_GRAB_RD4_DATA__W 102599#define FEC_OC_OCR_GRAB_RD4_DATA__M 0x3FF2600#define FEC_OC_OCR_GRAB_RD4_DATA__PRE 0x02601 2602#define FEC_OC_OCR_GRAB_RD5__A 0x244005A2603#define FEC_OC_OCR_GRAB_RD5__W 102604#define FEC_OC_OCR_GRAB_RD5__M 0x3FF2605#define FEC_OC_OCR_GRAB_RD5__PRE 0x02606 2607#define FEC_OC_OCR_GRAB_RD5_DATA__B 02608#define FEC_OC_OCR_GRAB_RD5_DATA__W 102609#define FEC_OC_OCR_GRAB_RD5_DATA__M 0x3FF2610#define FEC_OC_OCR_GRAB_RD5_DATA__PRE 0x02611 2612#define FEC_DI_RAM__A 0x24500002613 2614#define FEC_RS_RAM__A 0x24600002615 2616#define FEC_OC_RAM__A 0x24700002617 2618#define IQM_COMM_EXEC__A 0x18000002619#define IQM_COMM_EXEC__W 22620#define IQM_COMM_EXEC__M 0x32621#define IQM_COMM_EXEC__PRE 0x02622#define IQM_COMM_EXEC_STOP 0x02623#define IQM_COMM_EXEC_ACTIVE 0x12624#define IQM_COMM_EXEC_HOLD 0x22625 2626#define IQM_COMM_MB__A 0x18000022627#define IQM_COMM_MB__W 162628#define IQM_COMM_MB__M 0xFFFF2629#define IQM_COMM_MB__PRE 0x02630#define IQM_COMM_INT_REQ__A 0x18000032631#define IQM_COMM_INT_REQ__W 22632#define IQM_COMM_INT_REQ__M 0x32633#define IQM_COMM_INT_REQ__PRE 0x02634 2635#define IQM_COMM_INT_REQ_AF_REQ__B 02636#define IQM_COMM_INT_REQ_AF_REQ__W 12637#define IQM_COMM_INT_REQ_AF_REQ__M 0x12638#define IQM_COMM_INT_REQ_AF_REQ__PRE 0x02639 2640#define IQM_COMM_INT_REQ_CF_REQ__B 12641#define IQM_COMM_INT_REQ_CF_REQ__W 12642#define IQM_COMM_INT_REQ_CF_REQ__M 0x22643#define IQM_COMM_INT_REQ_CF_REQ__PRE 0x02644 2645#define IQM_COMM_INT_STA__A 0x18000052646#define IQM_COMM_INT_STA__W 162647#define IQM_COMM_INT_STA__M 0xFFFF2648#define IQM_COMM_INT_STA__PRE 0x02649#define IQM_COMM_INT_MSK__A 0x18000062650#define IQM_COMM_INT_MSK__W 162651#define IQM_COMM_INT_MSK__M 0xFFFF2652#define IQM_COMM_INT_MSK__PRE 0x02653#define IQM_COMM_INT_STM__A 0x18000072654#define IQM_COMM_INT_STM__W 162655#define IQM_COMM_INT_STM__M 0xFFFF2656#define IQM_COMM_INT_STM__PRE 0x02657 2658#define IQM_FS_COMM_EXEC__A 0x18200002659#define IQM_FS_COMM_EXEC__W 22660#define IQM_FS_COMM_EXEC__M 0x32661#define IQM_FS_COMM_EXEC__PRE 0x02662#define IQM_FS_COMM_EXEC_STOP 0x02663#define IQM_FS_COMM_EXEC_ACTIVE 0x12664#define IQM_FS_COMM_EXEC_HOLD 0x22665 2666#define IQM_FS_COMM_MB__A 0x18200022667#define IQM_FS_COMM_MB__W 22668#define IQM_FS_COMM_MB__M 0x32669#define IQM_FS_COMM_MB__PRE 0x02670#define IQM_FS_COMM_MB_CTL__B 02671#define IQM_FS_COMM_MB_CTL__W 12672#define IQM_FS_COMM_MB_CTL__M 0x12673#define IQM_FS_COMM_MB_CTL__PRE 0x02674#define IQM_FS_COMM_MB_CTL_CTL_OFF 0x02675#define IQM_FS_COMM_MB_CTL_CTL_ON 0x12676#define IQM_FS_COMM_MB_OBS__B 12677#define IQM_FS_COMM_MB_OBS__W 12678#define IQM_FS_COMM_MB_OBS__M 0x22679#define IQM_FS_COMM_MB_OBS__PRE 0x02680#define IQM_FS_COMM_MB_OBS_OBS_OFF 0x02681#define IQM_FS_COMM_MB_OBS_OBS_ON 0x22682 2683#define IQM_FS_RATE_OFS_LO__A 0x18200102684#define IQM_FS_RATE_OFS_LO__W 162685#define IQM_FS_RATE_OFS_LO__M 0xFFFF2686#define IQM_FS_RATE_OFS_LO__PRE 0x02687#define IQM_FS_RATE_OFS_HI__A 0x18200112688#define IQM_FS_RATE_OFS_HI__W 122689#define IQM_FS_RATE_OFS_HI__M 0xFFF2690#define IQM_FS_RATE_OFS_HI__PRE 0x02691#define IQM_FS_RATE_LO__A 0x18200122692#define IQM_FS_RATE_LO__W 162693#define IQM_FS_RATE_LO__M 0xFFFF2694#define IQM_FS_RATE_LO__PRE 0x02695#define IQM_FS_RATE_HI__A 0x18200132696#define IQM_FS_RATE_HI__W 122697#define IQM_FS_RATE_HI__M 0xFFF2698#define IQM_FS_RATE_HI__PRE 0x02699 2700#define IQM_FS_ADJ_SEL__A 0x18200142701#define IQM_FS_ADJ_SEL__W 22702#define IQM_FS_ADJ_SEL__M 0x32703#define IQM_FS_ADJ_SEL__PRE 0x02704#define IQM_FS_ADJ_SEL_OFF 0x02705#define IQM_FS_ADJ_SEL_QAM 0x12706#define IQM_FS_ADJ_SEL_VSB 0x22707 2708#define IQM_FD_COMM_EXEC__A 0x18300002709#define IQM_FD_COMM_EXEC__W 22710#define IQM_FD_COMM_EXEC__M 0x32711#define IQM_FD_COMM_EXEC__PRE 0x02712#define IQM_FD_COMM_EXEC_STOP 0x02713#define IQM_FD_COMM_EXEC_ACTIVE 0x12714#define IQM_FD_COMM_EXEC_HOLD 0x22715 2716#define IQM_FD_COMM_MB__A 0x18300022717#define IQM_FD_COMM_MB__W 22718#define IQM_FD_COMM_MB__M 0x32719#define IQM_FD_COMM_MB__PRE 0x02720#define IQM_FD_COMM_MB_CTL__B 02721#define IQM_FD_COMM_MB_CTL__W 12722#define IQM_FD_COMM_MB_CTL__M 0x12723#define IQM_FD_COMM_MB_CTL__PRE 0x02724#define IQM_FD_COMM_MB_CTL_CTL_OFF 0x02725#define IQM_FD_COMM_MB_CTL_CTL_ON 0x12726#define IQM_FD_COMM_MB_OBS__B 12727#define IQM_FD_COMM_MB_OBS__W 12728#define IQM_FD_COMM_MB_OBS__M 0x22729#define IQM_FD_COMM_MB_OBS__PRE 0x02730#define IQM_FD_COMM_MB_OBS_OBS_OFF 0x02731#define IQM_FD_COMM_MB_OBS_OBS_ON 0x22732 2733#define IQM_RC_COMM_EXEC__A 0x18400002734#define IQM_RC_COMM_EXEC__W 22735#define IQM_RC_COMM_EXEC__M 0x32736#define IQM_RC_COMM_EXEC__PRE 0x02737#define IQM_RC_COMM_EXEC_STOP 0x02738#define IQM_RC_COMM_EXEC_ACTIVE 0x12739#define IQM_RC_COMM_EXEC_HOLD 0x22740 2741#define IQM_RC_COMM_MB__A 0x18400022742#define IQM_RC_COMM_MB__W 22743#define IQM_RC_COMM_MB__M 0x32744#define IQM_RC_COMM_MB__PRE 0x02745#define IQM_RC_COMM_MB_CTL__B 02746#define IQM_RC_COMM_MB_CTL__W 12747#define IQM_RC_COMM_MB_CTL__M 0x12748#define IQM_RC_COMM_MB_CTL__PRE 0x02749#define IQM_RC_COMM_MB_CTL_CTL_OFF 0x02750#define IQM_RC_COMM_MB_CTL_CTL_ON 0x12751#define IQM_RC_COMM_MB_OBS__B 12752#define IQM_RC_COMM_MB_OBS__W 12753#define IQM_RC_COMM_MB_OBS__M 0x22754#define IQM_RC_COMM_MB_OBS__PRE 0x02755#define IQM_RC_COMM_MB_OBS_OBS_OFF 0x02756#define IQM_RC_COMM_MB_OBS_OBS_ON 0x22757 2758#define IQM_RC_RATE_OFS_LO__A 0x18400102759#define IQM_RC_RATE_OFS_LO__W 162760#define IQM_RC_RATE_OFS_LO__M 0xFFFF2761#define IQM_RC_RATE_OFS_LO__PRE 0x02762#define IQM_RC_RATE_OFS_HI__A 0x18400112763#define IQM_RC_RATE_OFS_HI__W 82764#define IQM_RC_RATE_OFS_HI__M 0xFF2765#define IQM_RC_RATE_OFS_HI__PRE 0x02766#define IQM_RC_RATE_LO__A 0x18400122767#define IQM_RC_RATE_LO__W 162768#define IQM_RC_RATE_LO__M 0xFFFF2769#define IQM_RC_RATE_LO__PRE 0x02770#define IQM_RC_RATE_HI__A 0x18400132771#define IQM_RC_RATE_HI__W 82772#define IQM_RC_RATE_HI__M 0xFF2773#define IQM_RC_RATE_HI__PRE 0x02774 2775#define IQM_RC_ADJ_SEL__A 0x18400142776#define IQM_RC_ADJ_SEL__W 22777#define IQM_RC_ADJ_SEL__M 0x32778#define IQM_RC_ADJ_SEL__PRE 0x02779#define IQM_RC_ADJ_SEL_OFF 0x02780#define IQM_RC_ADJ_SEL_QAM 0x12781#define IQM_RC_ADJ_SEL_VSB 0x22782 2783#define IQM_RC_CROUT_ENA__A 0x18400152784#define IQM_RC_CROUT_ENA__W 12785#define IQM_RC_CROUT_ENA__M 0x12786#define IQM_RC_CROUT_ENA__PRE 0x02787 2788#define IQM_RC_CROUT_ENA_ENA__B 02789#define IQM_RC_CROUT_ENA_ENA__W 12790#define IQM_RC_CROUT_ENA_ENA__M 0x12791#define IQM_RC_CROUT_ENA_ENA__PRE 0x02792 2793#define IQM_RC_STRETCH__A 0x18400162794#define IQM_RC_STRETCH__W 52795#define IQM_RC_STRETCH__M 0x1F2796#define IQM_RC_STRETCH__PRE 0x02797#define IQM_RC_STRETCH_QAM_B_64 0x1E2798#define IQM_RC_STRETCH_QAM_B_256 0x1C2799#define IQM_RC_STRETCH_ATV 0xF2800 2801#define IQM_RT_COMM_EXEC__A 0x18500002802#define IQM_RT_COMM_EXEC__W 22803#define IQM_RT_COMM_EXEC__M 0x32804#define IQM_RT_COMM_EXEC__PRE 0x02805#define IQM_RT_COMM_EXEC_STOP 0x02806#define IQM_RT_COMM_EXEC_ACTIVE 0x12807#define IQM_RT_COMM_EXEC_HOLD 0x22808 2809#define IQM_RT_COMM_MB__A 0x18500022810#define IQM_RT_COMM_MB__W 22811#define IQM_RT_COMM_MB__M 0x32812#define IQM_RT_COMM_MB__PRE 0x02813#define IQM_RT_COMM_MB_CTL__B 02814#define IQM_RT_COMM_MB_CTL__W 12815#define IQM_RT_COMM_MB_CTL__M 0x12816#define IQM_RT_COMM_MB_CTL__PRE 0x02817#define IQM_RT_COMM_MB_CTL_CTL_OFF 0x02818#define IQM_RT_COMM_MB_CTL_CTL_ON 0x12819#define IQM_RT_COMM_MB_OBS__B 12820#define IQM_RT_COMM_MB_OBS__W 12821#define IQM_RT_COMM_MB_OBS__M 0x22822#define IQM_RT_COMM_MB_OBS__PRE 0x02823#define IQM_RT_COMM_MB_OBS_OBS_OFF 0x02824#define IQM_RT_COMM_MB_OBS_OBS_ON 0x22825 2826#define IQM_RT_ACTIVE__A 0x18500102827#define IQM_RT_ACTIVE__W 22828#define IQM_RT_ACTIVE__M 0x32829#define IQM_RT_ACTIVE__PRE 0x02830 2831#define IQM_RT_ACTIVE_ACTIVE_RT__B 02832#define IQM_RT_ACTIVE_ACTIVE_RT__W 12833#define IQM_RT_ACTIVE_ACTIVE_RT__M 0x12834#define IQM_RT_ACTIVE_ACTIVE_RT__PRE 0x02835#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_OFF 0x02836#define IQM_RT_ACTIVE_ACTIVE_RT_ATV_FCR_ON 0x12837 2838#define IQM_RT_ACTIVE_ACTIVE_CR__B 12839#define IQM_RT_ACTIVE_ACTIVE_CR__W 12840#define IQM_RT_ACTIVE_ACTIVE_CR__M 0x22841#define IQM_RT_ACTIVE_ACTIVE_CR__PRE 0x02842#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_OFF 0x02843#define IQM_RT_ACTIVE_ACTIVE_CR_ATV_CR_ON 0x22844 2845#define IQM_RT_LO_INCR__A 0x18500112846#define IQM_RT_LO_INCR__W 122847#define IQM_RT_LO_INCR__M 0xFFF2848#define IQM_RT_LO_INCR__PRE 0x5882849#define IQM_RT_LO_INCR_FM 0x02850#define IQM_RT_LO_INCR_MN 0x5882851 2852#define IQM_RT_ROT_BP__A 0x18500122853#define IQM_RT_ROT_BP__W 22854#define IQM_RT_ROT_BP__M 0x32855#define IQM_RT_ROT_BP__PRE 0x02856 2857#define IQM_RT_ROT_BP_ROT_OFF__B 02858#define IQM_RT_ROT_BP_ROT_OFF__W 12859#define IQM_RT_ROT_BP_ROT_OFF__M 0x12860#define IQM_RT_ROT_BP_ROT_OFF__PRE 0x02861#define IQM_RT_ROT_BP_ROT_OFF_ACTIVE 0x02862#define IQM_RT_ROT_BP_ROT_OFF_OFF 0x12863 2864#define IQM_RT_ROT_BP_ROT_BPF__B 12865#define IQM_RT_ROT_BP_ROT_BPF__W 12866#define IQM_RT_ROT_BP_ROT_BPF__M 0x22867#define IQM_RT_ROT_BP_ROT_BPF__PRE 0x02868 2869#define IQM_RT_LP_BP__A 0x18500132870#define IQM_RT_LP_BP__W 12871#define IQM_RT_LP_BP__M 0x12872#define IQM_RT_LP_BP__PRE 0x02873 2874#define IQM_RT_DELAY__A 0x18500142875#define IQM_RT_DELAY__W 72876#define IQM_RT_DELAY__M 0x7F2877#define IQM_RT_DELAY__PRE 0x452878 2879#define IQM_CF_COMM_EXEC__A 0x18600002880#define IQM_CF_COMM_EXEC__W 22881#define IQM_CF_COMM_EXEC__M 0x32882#define IQM_CF_COMM_EXEC__PRE 0x02883#define IQM_CF_COMM_EXEC_STOP 0x02884#define IQM_CF_COMM_EXEC_ACTIVE 0x12885#define IQM_CF_COMM_EXEC_HOLD 0x22886 2887#define IQM_CF_COMM_MB__A 0x18600022888#define IQM_CF_COMM_MB__W 22889#define IQM_CF_COMM_MB__M 0x32890#define IQM_CF_COMM_MB__PRE 0x02891#define IQM_CF_COMM_MB_CTL__B 02892#define IQM_CF_COMM_MB_CTL__W 12893#define IQM_CF_COMM_MB_CTL__M 0x12894#define IQM_CF_COMM_MB_CTL__PRE 0x02895#define IQM_CF_COMM_MB_CTL_CTL_OFF 0x02896#define IQM_CF_COMM_MB_CTL_CTL_ON 0x12897#define IQM_CF_COMM_MB_OBS__B 12898#define IQM_CF_COMM_MB_OBS__W 12899#define IQM_CF_COMM_MB_OBS__M 0x22900#define IQM_CF_COMM_MB_OBS__PRE 0x02901#define IQM_CF_COMM_MB_OBS_OBS_OFF 0x02902#define IQM_CF_COMM_MB_OBS_OBS_ON 0x22903 2904#define IQM_CF_COMM_INT_REQ__A 0x18600032905#define IQM_CF_COMM_INT_REQ__W 12906#define IQM_CF_COMM_INT_REQ__M 0x12907#define IQM_CF_COMM_INT_REQ__PRE 0x02908#define IQM_CF_COMM_INT_STA__A 0x18600052909#define IQM_CF_COMM_INT_STA__W 12910#define IQM_CF_COMM_INT_STA__M 0x12911#define IQM_CF_COMM_INT_STA__PRE 0x02912#define IQM_CF_COMM_INT_STA_PM__B 02913#define IQM_CF_COMM_INT_STA_PM__W 12914#define IQM_CF_COMM_INT_STA_PM__M 0x12915#define IQM_CF_COMM_INT_STA_PM__PRE 0x02916 2917#define IQM_CF_COMM_INT_MSK__A 0x18600062918#define IQM_CF_COMM_INT_MSK__W 12919#define IQM_CF_COMM_INT_MSK__M 0x12920#define IQM_CF_COMM_INT_MSK__PRE 0x02921#define IQM_CF_COMM_INT_MSK_PM__B 02922#define IQM_CF_COMM_INT_MSK_PM__W 12923#define IQM_CF_COMM_INT_MSK_PM__M 0x12924#define IQM_CF_COMM_INT_MSK_PM__PRE 0x02925 2926#define IQM_CF_COMM_INT_STM__A 0x18600072927#define IQM_CF_COMM_INT_STM__W 12928#define IQM_CF_COMM_INT_STM__M 0x12929#define IQM_CF_COMM_INT_STM__PRE 0x02930#define IQM_CF_COMM_INT_STM_PM__B 02931#define IQM_CF_COMM_INT_STM_PM__W 12932#define IQM_CF_COMM_INT_STM_PM__M 0x12933#define IQM_CF_COMM_INT_STM_PM__PRE 0x02934 2935#define IQM_CF_SYMMETRIC__A 0x18600102936#define IQM_CF_SYMMETRIC__W 22937#define IQM_CF_SYMMETRIC__M 0x32938#define IQM_CF_SYMMETRIC__PRE 0x02939 2940#define IQM_CF_SYMMETRIC_RE__B 02941#define IQM_CF_SYMMETRIC_RE__W 12942#define IQM_CF_SYMMETRIC_RE__M 0x12943#define IQM_CF_SYMMETRIC_RE__PRE 0x02944 2945#define IQM_CF_SYMMETRIC_IM__B 12946#define IQM_CF_SYMMETRIC_IM__W 12947#define IQM_CF_SYMMETRIC_IM__M 0x22948#define IQM_CF_SYMMETRIC_IM__PRE 0x02949 2950#define IQM_CF_MIDTAP__A 0x18600112951#define IQM_CF_MIDTAP__W 22952#define IQM_CF_MIDTAP__M 0x32953#define IQM_CF_MIDTAP__PRE 0x32954 2955#define IQM_CF_MIDTAP_RE__B 02956#define IQM_CF_MIDTAP_RE__W 12957#define IQM_CF_MIDTAP_RE__M 0x12958#define IQM_CF_MIDTAP_RE__PRE 0x12959 2960#define IQM_CF_MIDTAP_IM__B 12961#define IQM_CF_MIDTAP_IM__W 12962#define IQM_CF_MIDTAP_IM__M 0x22963#define IQM_CF_MIDTAP_IM__PRE 0x22964 2965#define IQM_CF_OUT_ENA__A 0x18600122966#define IQM_CF_OUT_ENA__W 32967#define IQM_CF_OUT_ENA__M 0x72968#define IQM_CF_OUT_ENA__PRE 0x02969 2970#define IQM_CF_OUT_ENA_ATV__B 02971#define IQM_CF_OUT_ENA_ATV__W 12972#define IQM_CF_OUT_ENA_ATV__M 0x12973#define IQM_CF_OUT_ENA_ATV__PRE 0x02974 2975#define IQM_CF_OUT_ENA_QAM__B 12976#define IQM_CF_OUT_ENA_QAM__W 12977#define IQM_CF_OUT_ENA_QAM__M 0x22978#define IQM_CF_OUT_ENA_QAM__PRE 0x02979 2980#define IQM_CF_OUT_ENA_VSB__B 22981#define IQM_CF_OUT_ENA_VSB__W 12982#define IQM_CF_OUT_ENA_VSB__M 0x42983#define IQM_CF_OUT_ENA_VSB__PRE 0x02984 2985#define IQM_CF_ADJ_SEL__A 0x18600132986#define IQM_CF_ADJ_SEL__W 22987#define IQM_CF_ADJ_SEL__M 0x32988#define IQM_CF_ADJ_SEL__PRE 0x02989#define IQM_CF_SCALE__A 0x18600142990#define IQM_CF_SCALE__W 142991#define IQM_CF_SCALE__M 0x3FFF2992#define IQM_CF_SCALE__PRE 0x4002993 2994#define IQM_CF_SCALE_SH__A 0x18600152995#define IQM_CF_SCALE_SH__W 22996#define IQM_CF_SCALE_SH__M 0x32997#define IQM_CF_SCALE_SH__PRE 0x02998 2999#define IQM_CF_AMP__A 0x18600163000#define IQM_CF_AMP__W 143001#define IQM_CF_AMP__M 0x3FFF3002#define IQM_CF_AMP__PRE 0x03003 3004#define IQM_CF_POW_MEAS_LEN__A 0x18600173005#define IQM_CF_POW_MEAS_LEN__W 33006#define IQM_CF_POW_MEAS_LEN__M 0x73007#define IQM_CF_POW_MEAS_LEN__PRE 0x23008#define IQM_CF_POW_MEAS_LEN_QAM_B_64 0x13009#define IQM_CF_POW_MEAS_LEN_QAM_B_256 0x13010 3011#define IQM_CF_POW__A 0x18600183012#define IQM_CF_POW__W 163013#define IQM_CF_POW__M 0xFFFF3014#define IQM_CF_POW__PRE 0x23015#define IQM_CF_TAP_RE0__A 0x18600203016#define IQM_CF_TAP_RE0__W 73017#define IQM_CF_TAP_RE0__M 0x7F3018#define IQM_CF_TAP_RE0__PRE 0x23019#define IQM_CF_TAP_RE1__A 0x18600213020#define IQM_CF_TAP_RE1__W 73021#define IQM_CF_TAP_RE1__M 0x7F3022#define IQM_CF_TAP_RE1__PRE 0x23023#define IQM_CF_TAP_RE2__A 0x18600223024#define IQM_CF_TAP_RE2__W 73025#define IQM_CF_TAP_RE2__M 0x7F3026#define IQM_CF_TAP_RE2__PRE 0x23027#define IQM_CF_TAP_RE3__A 0x18600233028#define IQM_CF_TAP_RE3__W 73029#define IQM_CF_TAP_RE3__M 0x7F3030#define IQM_CF_TAP_RE3__PRE 0x23031#define IQM_CF_TAP_RE4__A 0x18600243032#define IQM_CF_TAP_RE4__W 73033#define IQM_CF_TAP_RE4__M 0x7F3034#define IQM_CF_TAP_RE4__PRE 0x23035#define IQM_CF_TAP_RE5__A 0x18600253036#define IQM_CF_TAP_RE5__W 73037#define IQM_CF_TAP_RE5__M 0x7F3038#define IQM_CF_TAP_RE5__PRE 0x23039#define IQM_CF_TAP_RE6__A 0x18600263040#define IQM_CF_TAP_RE6__W 73041#define IQM_CF_TAP_RE6__M 0x7F3042#define IQM_CF_TAP_RE6__PRE 0x23043#define IQM_CF_TAP_RE7__A 0x18600273044#define IQM_CF_TAP_RE7__W 93045#define IQM_CF_TAP_RE7__M 0x1FF3046#define IQM_CF_TAP_RE7__PRE 0x23047#define IQM_CF_TAP_RE8__A 0x18600283048#define IQM_CF_TAP_RE8__W 93049#define IQM_CF_TAP_RE8__M 0x1FF3050#define IQM_CF_TAP_RE8__PRE 0x23051#define IQM_CF_TAP_RE9__A 0x18600293052#define IQM_CF_TAP_RE9__W 93053#define IQM_CF_TAP_RE9__M 0x1FF3054#define IQM_CF_TAP_RE9__PRE 0x23055#define IQM_CF_TAP_RE10__A 0x186002A3056#define IQM_CF_TAP_RE10__W 93057#define IQM_CF_TAP_RE10__M 0x1FF3058#define IQM_CF_TAP_RE10__PRE 0x23059#define IQM_CF_TAP_RE11__A 0x186002B3060#define IQM_CF_TAP_RE11__W 93061#define IQM_CF_TAP_RE11__M 0x1FF3062#define IQM_CF_TAP_RE11__PRE 0x23063#define IQM_CF_TAP_RE12__A 0x186002C3064#define IQM_CF_TAP_RE12__W 93065#define IQM_CF_TAP_RE12__M 0x1FF3066#define IQM_CF_TAP_RE12__PRE 0x23067#define IQM_CF_TAP_RE13__A 0x186002D3068#define IQM_CF_TAP_RE13__W 93069#define IQM_CF_TAP_RE13__M 0x1FF3070#define IQM_CF_TAP_RE13__PRE 0x23071#define IQM_CF_TAP_RE14__A 0x186002E3072#define IQM_CF_TAP_RE14__W 93073#define IQM_CF_TAP_RE14__M 0x1FF3074#define IQM_CF_TAP_RE14__PRE 0x23075#define IQM_CF_TAP_RE15__A 0x186002F3076#define IQM_CF_TAP_RE15__W 93077#define IQM_CF_TAP_RE15__M 0x1FF3078#define IQM_CF_TAP_RE15__PRE 0x23079#define IQM_CF_TAP_RE16__A 0x18600303080#define IQM_CF_TAP_RE16__W 93081#define IQM_CF_TAP_RE16__M 0x1FF3082#define IQM_CF_TAP_RE16__PRE 0x23083#define IQM_CF_TAP_RE17__A 0x18600313084#define IQM_CF_TAP_RE17__W 93085#define IQM_CF_TAP_RE17__M 0x1FF3086#define IQM_CF_TAP_RE17__PRE 0x23087#define IQM_CF_TAP_RE18__A 0x18600323088#define IQM_CF_TAP_RE18__W 93089#define IQM_CF_TAP_RE18__M 0x1FF3090#define IQM_CF_TAP_RE18__PRE 0x23091#define IQM_CF_TAP_RE19__A 0x18600333092#define IQM_CF_TAP_RE19__W 93093#define IQM_CF_TAP_RE19__M 0x1FF3094#define IQM_CF_TAP_RE19__PRE 0x23095#define IQM_CF_TAP_RE20__A 0x18600343096#define IQM_CF_TAP_RE20__W 93097#define IQM_CF_TAP_RE20__M 0x1FF3098#define IQM_CF_TAP_RE20__PRE 0x23099#define IQM_CF_TAP_RE21__A 0x18600353100#define IQM_CF_TAP_RE21__W 113101#define IQM_CF_TAP_RE21__M 0x7FF3102#define IQM_CF_TAP_RE21__PRE 0x23103#define IQM_CF_TAP_RE22__A 0x18600363104#define IQM_CF_TAP_RE22__W 113105#define IQM_CF_TAP_RE22__M 0x7FF3106#define IQM_CF_TAP_RE22__PRE 0x23107#define IQM_CF_TAP_RE23__A 0x18600373108#define IQM_CF_TAP_RE23__W 113109#define IQM_CF_TAP_RE23__M 0x7FF3110#define IQM_CF_TAP_RE23__PRE 0x23111#define IQM_CF_TAP_RE24__A 0x18600383112#define IQM_CF_TAP_RE24__W 113113#define IQM_CF_TAP_RE24__M 0x7FF3114#define IQM_CF_TAP_RE24__PRE 0x23115#define IQM_CF_TAP_RE25__A 0x18600393116#define IQM_CF_TAP_RE25__W 113117#define IQM_CF_TAP_RE25__M 0x7FF3118#define IQM_CF_TAP_RE25__PRE 0x23119#define IQM_CF_TAP_RE26__A 0x186003A3120#define IQM_CF_TAP_RE26__W 113121#define IQM_CF_TAP_RE26__M 0x7FF3122#define IQM_CF_TAP_RE26__PRE 0x23123#define IQM_CF_TAP_RE27__A 0x186003B3124#define IQM_CF_TAP_RE27__W 113125#define IQM_CF_TAP_RE27__M 0x7FF3126#define IQM_CF_TAP_RE27__PRE 0x23127#define IQM_CF_TAP_IM0__A 0x18600403128#define IQM_CF_TAP_IM0__W 73129#define IQM_CF_TAP_IM0__M 0x7F3130#define IQM_CF_TAP_IM0__PRE 0x23131#define IQM_CF_TAP_IM1__A 0x18600413132#define IQM_CF_TAP_IM1__W 73133#define IQM_CF_TAP_IM1__M 0x7F3134#define IQM_CF_TAP_IM1__PRE 0x23135#define IQM_CF_TAP_IM2__A 0x18600423136#define IQM_CF_TAP_IM2__W 73137#define IQM_CF_TAP_IM2__M 0x7F3138#define IQM_CF_TAP_IM2__PRE 0x23139#define IQM_CF_TAP_IM3__A 0x18600433140#define IQM_CF_TAP_IM3__W 73141#define IQM_CF_TAP_IM3__M 0x7F3142#define IQM_CF_TAP_IM3__PRE 0x23143#define IQM_CF_TAP_IM4__A 0x18600443144#define IQM_CF_TAP_IM4__W 73145#define IQM_CF_TAP_IM4__M 0x7F3146#define IQM_CF_TAP_IM4__PRE 0x23147#define IQM_CF_TAP_IM5__A 0x18600453148#define IQM_CF_TAP_IM5__W 73149#define IQM_CF_TAP_IM5__M 0x7F3150#define IQM_CF_TAP_IM5__PRE 0x23151#define IQM_CF_TAP_IM6__A 0x18600463152#define IQM_CF_TAP_IM6__W 73153#define IQM_CF_TAP_IM6__M 0x7F3154#define IQM_CF_TAP_IM6__PRE 0x23155#define IQM_CF_TAP_IM7__A 0x18600473156#define IQM_CF_TAP_IM7__W 93157#define IQM_CF_TAP_IM7__M 0x1FF3158#define IQM_CF_TAP_IM7__PRE 0x23159#define IQM_CF_TAP_IM8__A 0x18600483160#define IQM_CF_TAP_IM8__W 93161#define IQM_CF_TAP_IM8__M 0x1FF3162#define IQM_CF_TAP_IM8__PRE 0x23163#define IQM_CF_TAP_IM9__A 0x18600493164#define IQM_CF_TAP_IM9__W 93165#define IQM_CF_TAP_IM9__M 0x1FF3166#define IQM_CF_TAP_IM9__PRE 0x23167#define IQM_CF_TAP_IM10__A 0x186004A3168#define IQM_CF_TAP_IM10__W 93169#define IQM_CF_TAP_IM10__M 0x1FF3170#define IQM_CF_TAP_IM10__PRE 0x23171#define IQM_CF_TAP_IM11__A 0x186004B3172#define IQM_CF_TAP_IM11__W 93173#define IQM_CF_TAP_IM11__M 0x1FF3174#define IQM_CF_TAP_IM11__PRE 0x23175#define IQM_CF_TAP_IM12__A 0x186004C3176#define IQM_CF_TAP_IM12__W 93177#define IQM_CF_TAP_IM12__M 0x1FF3178#define IQM_CF_TAP_IM12__PRE 0x23179#define IQM_CF_TAP_IM13__A 0x186004D3180#define IQM_CF_TAP_IM13__W 93181#define IQM_CF_TAP_IM13__M 0x1FF3182#define IQM_CF_TAP_IM13__PRE 0x23183#define IQM_CF_TAP_IM14__A 0x186004E3184#define IQM_CF_TAP_IM14__W 93185#define IQM_CF_TAP_IM14__M 0x1FF3186#define IQM_CF_TAP_IM14__PRE 0x23187#define IQM_CF_TAP_IM15__A 0x186004F3188#define IQM_CF_TAP_IM15__W 93189#define IQM_CF_TAP_IM15__M 0x1FF3190#define IQM_CF_TAP_IM15__PRE 0x23191#define IQM_CF_TAP_IM16__A 0x18600503192#define IQM_CF_TAP_IM16__W 93193#define IQM_CF_TAP_IM16__M 0x1FF3194#define IQM_CF_TAP_IM16__PRE 0x23195#define IQM_CF_TAP_IM17__A 0x18600513196#define IQM_CF_TAP_IM17__W 93197#define IQM_CF_TAP_IM17__M 0x1FF3198#define IQM_CF_TAP_IM17__PRE 0x23199#define IQM_CF_TAP_IM18__A 0x18600523200#define IQM_CF_TAP_IM18__W 93201#define IQM_CF_TAP_IM18__M 0x1FF3202#define IQM_CF_TAP_IM18__PRE 0x23203#define IQM_CF_TAP_IM19__A 0x18600533204#define IQM_CF_TAP_IM19__W 93205#define IQM_CF_TAP_IM19__M 0x1FF3206#define IQM_CF_TAP_IM19__PRE 0x23207#define IQM_CF_TAP_IM20__A 0x18600543208#define IQM_CF_TAP_IM20__W 93209#define IQM_CF_TAP_IM20__M 0x1FF3210#define IQM_CF_TAP_IM20__PRE 0x23211#define IQM_CF_TAP_IM21__A 0x18600553212#define IQM_CF_TAP_IM21__W 113213#define IQM_CF_TAP_IM21__M 0x7FF3214#define IQM_CF_TAP_IM21__PRE 0x23215#define IQM_CF_TAP_IM22__A 0x18600563216#define IQM_CF_TAP_IM22__W 113217#define IQM_CF_TAP_IM22__M 0x7FF3218#define IQM_CF_TAP_IM22__PRE 0x23219#define IQM_CF_TAP_IM23__A 0x18600573220#define IQM_CF_TAP_IM23__W 113221#define IQM_CF_TAP_IM23__M 0x7FF3222#define IQM_CF_TAP_IM23__PRE 0x23223#define IQM_CF_TAP_IM24__A 0x18600583224#define IQM_CF_TAP_IM24__W 113225#define IQM_CF_TAP_IM24__M 0x7FF3226#define IQM_CF_TAP_IM24__PRE 0x23227#define IQM_CF_TAP_IM25__A 0x18600593228#define IQM_CF_TAP_IM25__W 113229#define IQM_CF_TAP_IM25__M 0x7FF3230#define IQM_CF_TAP_IM25__PRE 0x23231#define IQM_CF_TAP_IM26__A 0x186005A3232#define IQM_CF_TAP_IM26__W 113233#define IQM_CF_TAP_IM26__M 0x7FF3234#define IQM_CF_TAP_IM26__PRE 0x23235#define IQM_CF_TAP_IM27__A 0x186005B3236#define IQM_CF_TAP_IM27__W 113237#define IQM_CF_TAP_IM27__M 0x7FF3238#define IQM_CF_TAP_IM27__PRE 0x23239 3240#define IQM_AF_COMM_EXEC__A 0x18700003241#define IQM_AF_COMM_EXEC__W 23242#define IQM_AF_COMM_EXEC__M 0x33243#define IQM_AF_COMM_EXEC__PRE 0x03244#define IQM_AF_COMM_EXEC_STOP 0x03245#define IQM_AF_COMM_EXEC_ACTIVE 0x13246#define IQM_AF_COMM_EXEC_HOLD 0x23247 3248#define IQM_AF_COMM_MB__A 0x18700023249#define IQM_AF_COMM_MB__W 83250#define IQM_AF_COMM_MB__M 0xFF3251#define IQM_AF_COMM_MB__PRE 0x03252#define IQM_AF_COMM_MB_CTL__B 03253#define IQM_AF_COMM_MB_CTL__W 13254#define IQM_AF_COMM_MB_CTL__M 0x13255#define IQM_AF_COMM_MB_CTL__PRE 0x03256#define IQM_AF_COMM_MB_CTL_CTL_OFF 0x03257#define IQM_AF_COMM_MB_CTL_CTL_ON 0x13258#define IQM_AF_COMM_MB_OBS__B 13259#define IQM_AF_COMM_MB_OBS__W 13260#define IQM_AF_COMM_MB_OBS__M 0x23261#define IQM_AF_COMM_MB_OBS__PRE 0x03262#define IQM_AF_COMM_MB_OBS_OBS_OFF 0x03263#define IQM_AF_COMM_MB_OBS_OBS_ON 0x23264#define IQM_AF_COMM_MB_MUX_CTRL__B 23265#define IQM_AF_COMM_MB_MUX_CTRL__W 33266#define IQM_AF_COMM_MB_MUX_CTRL__M 0x1C3267#define IQM_AF_COMM_MB_MUX_CTRL__PRE 0x03268#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_INPUT 0x03269#define IQM_AF_COMM_MB_MUX_CTRL_SENSE_INPUT 0x43270#define IQM_AF_COMM_MB_MUX_CTRL_AF_DATA_OUTPUT 0x83271#define IQM_AF_COMM_MB_MUX_CTRL_IF_AGC_OUTPUT 0xC3272#define IQM_AF_COMM_MB_MUX_CTRL_RF_AGC_OUTPUT 0x103273#define IQM_AF_COMM_MB_MUX_OBS__B 53274#define IQM_AF_COMM_MB_MUX_OBS__W 33275#define IQM_AF_COMM_MB_MUX_OBS__M 0xE03276#define IQM_AF_COMM_MB_MUX_OBS__PRE 0x03277#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_INPUT 0x03278#define IQM_AF_COMM_MB_MUX_OBS_SENSE_INPUT 0x203279#define IQM_AF_COMM_MB_MUX_OBS_AF_DATA_OUTPUT 0x403280#define IQM_AF_COMM_MB_MUX_OBS_IF_AGC_OUTPUT 0x603281#define IQM_AF_COMM_MB_MUX_OBS_RF_AGC_OUTPUT 0x803282 3283#define IQM_AF_COMM_INT_REQ__A 0x18700033284#define IQM_AF_COMM_INT_REQ__W 13285#define IQM_AF_COMM_INT_REQ__M 0x13286#define IQM_AF_COMM_INT_REQ__PRE 0x03287#define IQM_AF_COMM_INT_STA__A 0x18700053288#define IQM_AF_COMM_INT_STA__W 23289#define IQM_AF_COMM_INT_STA__M 0x33290#define IQM_AF_COMM_INT_STA__PRE 0x03291#define IQM_AF_COMM_INT_STA_CLP_INT_STA__B 03292#define IQM_AF_COMM_INT_STA_CLP_INT_STA__W 13293#define IQM_AF_COMM_INT_STA_CLP_INT_STA__M 0x13294#define IQM_AF_COMM_INT_STA_CLP_INT_STA__PRE 0x03295#define IQM_AF_COMM_INT_STA_SNS_INT_STA__B 13296#define IQM_AF_COMM_INT_STA_SNS_INT_STA__W 13297#define IQM_AF_COMM_INT_STA_SNS_INT_STA__M 0x23298#define IQM_AF_COMM_INT_STA_SNS_INT_STA__PRE 0x03299 3300#define IQM_AF_COMM_INT_MSK__A 0x18700063301#define IQM_AF_COMM_INT_MSK__W 23302#define IQM_AF_COMM_INT_MSK__M 0x33303#define IQM_AF_COMM_INT_MSK__PRE 0x03304#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__B 03305#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__W 13306#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__M 0x13307#define IQM_AF_COMM_INT_MSK_CLP_INT_MSK__PRE 0x03308#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__B 13309#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__W 13310#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__M 0x23311#define IQM_AF_COMM_INT_MSK_SNS_INT_MSK__PRE 0x03312 3313#define IQM_AF_COMM_INT_STM__A 0x18700073314#define IQM_AF_COMM_INT_STM__W 23315#define IQM_AF_COMM_INT_STM__M 0x33316#define IQM_AF_COMM_INT_STM__PRE 0x03317#define IQM_AF_COMM_INT_STM_CLP_INT_STA__B 03318#define IQM_AF_COMM_INT_STM_CLP_INT_STA__W 13319#define IQM_AF_COMM_INT_STM_CLP_INT_STA__M 0x13320#define IQM_AF_COMM_INT_STM_CLP_INT_STA__PRE 0x03321#define IQM_AF_COMM_INT_STM_SNS_INT_STA__B 13322#define IQM_AF_COMM_INT_STM_SNS_INT_STA__W 13323#define IQM_AF_COMM_INT_STM_SNS_INT_STA__M 0x23324#define IQM_AF_COMM_INT_STM_SNS_INT_STA__PRE 0x03325 3326#define IQM_AF_FDB_SEL__A 0x18700103327#define IQM_AF_FDB_SEL__W 13328#define IQM_AF_FDB_SEL__M 0x13329#define IQM_AF_FDB_SEL__PRE 0x03330 3331#define IQM_AF_INVEXT__A 0x18700113332#define IQM_AF_INVEXT__W 13333#define IQM_AF_INVEXT__M 0x13334#define IQM_AF_INVEXT__PRE 0x03335#define IQM_AF_CLKNEG__A 0x18700123336#define IQM_AF_CLKNEG__W 23337#define IQM_AF_CLKNEG__M 0x33338#define IQM_AF_CLKNEG__PRE 0x03339 3340#define IQM_AF_CLKNEG_CLKNEGPEAK__B 03341#define IQM_AF_CLKNEG_CLKNEGPEAK__W 13342#define IQM_AF_CLKNEG_CLKNEGPEAK__M 0x13343#define IQM_AF_CLKNEG_CLKNEGPEAK__PRE 0x03344#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_POS 0x03345#define IQM_AF_CLKNEG_CLKNEGPEAK_CLK_ADC_PEAK_NEG 0x13346 3347#define IQM_AF_CLKNEG_CLKNEGDATA__B 13348#define IQM_AF_CLKNEG_CLKNEGDATA__W 13349#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x23350#define IQM_AF_CLKNEG_CLKNEGDATA__PRE 0x03351#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x03352#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x23353 3354#define IQM_AF_MON_IN_MUX__A 0x18700133355#define IQM_AF_MON_IN_MUX__W 23356#define IQM_AF_MON_IN_MUX__M 0x33357#define IQM_AF_MON_IN_MUX__PRE 0x03358 3359#define IQM_AF_MON_IN5__A 0x18700143360#define IQM_AF_MON_IN5__W 103361#define IQM_AF_MON_IN5__M 0x3FF3362#define IQM_AF_MON_IN5__PRE 0x03363 3364#define IQM_AF_MON_IN4__A 0x18700153365#define IQM_AF_MON_IN4__W 103366#define IQM_AF_MON_IN4__M 0x3FF3367#define IQM_AF_MON_IN4__PRE 0x03368 3369#define IQM_AF_MON_IN3__A 0x18700163370#define IQM_AF_MON_IN3__W 103371#define IQM_AF_MON_IN3__M 0x3FF3372#define IQM_AF_MON_IN3__PRE 0x03373 3374#define IQM_AF_MON_IN2__A 0x18700173375#define IQM_AF_MON_IN2__W 103376#define IQM_AF_MON_IN2__M 0x3FF3377#define IQM_AF_MON_IN2__PRE 0x03378 3379#define IQM_AF_MON_IN1__A 0x18700183380#define IQM_AF_MON_IN1__W 103381#define IQM_AF_MON_IN1__M 0x3FF3382#define IQM_AF_MON_IN1__PRE 0x03383 3384#define IQM_AF_MON_IN0__A 0x18700193385#define IQM_AF_MON_IN0__W 103386#define IQM_AF_MON_IN0__M 0x3FF3387#define IQM_AF_MON_IN0__PRE 0x03388 3389#define IQM_AF_MON_IN_VAL__A 0x187001A3390#define IQM_AF_MON_IN_VAL__W 13391#define IQM_AF_MON_IN_VAL__M 0x13392#define IQM_AF_MON_IN_VAL__PRE 0x03393 3394#define IQM_AF_START_LOCK__A 0x187001B3395#define IQM_AF_START_LOCK__W 13396#define IQM_AF_START_LOCK__M 0x13397#define IQM_AF_START_LOCK__PRE 0x03398 3399#define IQM_AF_PHASE0__A 0x187001C3400#define IQM_AF_PHASE0__W 73401#define IQM_AF_PHASE0__M 0x7F3402#define IQM_AF_PHASE0__PRE 0x03403 3404#define IQM_AF_PHASE1__A 0x187001D3405#define IQM_AF_PHASE1__W 73406#define IQM_AF_PHASE1__M 0x7F3407#define IQM_AF_PHASE1__PRE 0x03408 3409#define IQM_AF_PHASE2__A 0x187001E3410#define IQM_AF_PHASE2__W 73411#define IQM_AF_PHASE2__M 0x7F3412#define IQM_AF_PHASE2__PRE 0x03413 3414#define IQM_AF_SCU_PHASE__A 0x187001F3415#define IQM_AF_SCU_PHASE__W 23416#define IQM_AF_SCU_PHASE__M 0x33417#define IQM_AF_SCU_PHASE__PRE 0x03418 3419#define IQM_AF_SYNC_SEL__A 0x18700203420#define IQM_AF_SYNC_SEL__W 23421#define IQM_AF_SYNC_SEL__M 0x33422#define IQM_AF_SYNC_SEL__PRE 0x03423#define IQM_AF_ADC_CONF__A 0x18700213424#define IQM_AF_ADC_CONF__W 43425#define IQM_AF_ADC_CONF__M 0xF3426#define IQM_AF_ADC_CONF__PRE 0x03427 3428#define IQM_AF_ADC_CONF_ADC_SIGN__B 03429#define IQM_AF_ADC_CONF_ADC_SIGN__W 13430#define IQM_AF_ADC_CONF_ADC_SIGN__M 0x13431#define IQM_AF_ADC_CONF_ADC_SIGN__PRE 0x03432#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_SIGNED 0x03433#define IQM_AF_ADC_CONF_ADC_SIGN_ADC_UNSIGNED 0x13434 3435#define IQM_AF_ADC_CONF_BITREVERSE_ADC__B 13436#define IQM_AF_ADC_CONF_BITREVERSE_ADC__W 13437#define IQM_AF_ADC_CONF_BITREVERSE_ADC__M 0x23438#define IQM_AF_ADC_CONF_BITREVERSE_ADC__PRE 0x03439#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_NORMAL 0x03440#define IQM_AF_ADC_CONF_BITREVERSE_ADC_ADC_BITREVERSED 0x23441 3442#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__B 23443#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__W 13444#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__M 0x43445#define IQM_AF_ADC_CONF_BITREVERSE_NSSI__PRE 0x03446#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_NORMAL 0x03447#define IQM_AF_ADC_CONF_BITREVERSE_NSSI_IFAGC_DAC_BITREVERSED 0x43448 3449#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__B 33450#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__W 13451#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__M 0x83452#define IQM_AF_ADC_CONF_BITREVERSE_NSSR__PRE 0x03453#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_NORMAL 0x03454#define IQM_AF_ADC_CONF_BITREVERSE_NSSR_RFAGC_DAC_BITREVERSED 0x83455 3456#define IQM_AF_CLP_CLIP__A 0x18700223457#define IQM_AF_CLP_CLIP__W 163458#define IQM_AF_CLP_CLIP__M 0xFFFF3459#define IQM_AF_CLP_CLIP__PRE 0x03460 3461#define IQM_AF_CLP_LEN__A 0x18700233462#define IQM_AF_CLP_LEN__W 163463#define IQM_AF_CLP_LEN__M 0xFFFF3464#define IQM_AF_CLP_LEN__PRE 0x03465#define IQM_AF_CLP_LEN_QAM_B_64 0x4003466#define IQM_AF_CLP_LEN_QAM_B_256 0x4003467#define IQM_AF_CLP_LEN_ATV 0x03468 3469#define IQM_AF_CLP_TH__A 0x18700243470#define IQM_AF_CLP_TH__W 93471#define IQM_AF_CLP_TH__M 0x1FF3472#define IQM_AF_CLP_TH__PRE 0x03473#define IQM_AF_CLP_TH_QAM_B_64 0x803474#define IQM_AF_CLP_TH_QAM_B_256 0x803475#define IQM_AF_CLP_TH_ATV 0x1C03476 3477#define IQM_AF_DCF_BYPASS__A 0x18700253478#define IQM_AF_DCF_BYPASS__W 13479#define IQM_AF_DCF_BYPASS__M 0x13480#define IQM_AF_DCF_BYPASS__PRE 0x03481#define IQM_AF_DCF_BYPASS_ACTIVE 0x03482#define IQM_AF_DCF_BYPASS_BYPASS 0x13483 3484#define IQM_AF_SNS_LEN__A 0x18700263485#define IQM_AF_SNS_LEN__W 163486#define IQM_AF_SNS_LEN__M 0xFFFF3487#define IQM_AF_SNS_LEN__PRE 0x03488#define IQM_AF_SNS_LEN_QAM_B_64 0x4003489#define IQM_AF_SNS_LEN_QAM_B_256 0x4003490#define IQM_AF_SNS_LEN_ATV 0x03491 3492#define IQM_AF_SNS_SENSE__A 0x18700273493#define IQM_AF_SNS_SENSE__W 163494#define IQM_AF_SNS_SENSE__M 0xFFFF3495#define IQM_AF_SNS_SENSE__PRE 0x03496 3497#define IQM_AF_AGC_IF__A 0x18700283498#define IQM_AF_AGC_IF__W 153499#define IQM_AF_AGC_IF__M 0x7FFF3500#define IQM_AF_AGC_IF__PRE 0x03501 3502#define IQM_AF_AGC_RF__A 0x18700293503#define IQM_AF_AGC_RF__W 153504#define IQM_AF_AGC_RF__M 0x7FFF3505#define IQM_AF_AGC_RF__PRE 0x03506 3507#define IQM_AF_PGA_GAIN__A 0x187002A3508#define IQM_AF_PGA_GAIN__W 43509#define IQM_AF_PGA_GAIN__M 0xF3510#define IQM_AF_PGA_GAIN__PRE 0x03511 3512#define IQM_AF_PDREF__A 0x187002B3513#define IQM_AF_PDREF__W 53514#define IQM_AF_PDREF__M 0x1F3515#define IQM_AF_PDREF__PRE 0x03516#define IQM_AF_PDREF_QAM_B_64 0xF3517#define IQM_AF_PDREF_QAM_B_256 0xF3518#define IQM_AF_PDREF_ATV 0xF3519 3520#define IQM_AF_STDBY__A 0x187002C3521#define IQM_AF_STDBY__W 63522#define IQM_AF_STDBY__M 0x3F3523#define IQM_AF_STDBY__PRE 0x03524 3525#define IQM_AF_STDBY_STDBY_BIAS__B 03526#define IQM_AF_STDBY_STDBY_BIAS__W 13527#define IQM_AF_STDBY_STDBY_BIAS__M 0x13528#define IQM_AF_STDBY_STDBY_BIAS__PRE 0x03529#define IQM_AF_STDBY_STDBY_BIAS_ACTIVE 0x03530#define IQM_AF_STDBY_STDBY_BIAS_STANDBY 0x13531 3532#define IQM_AF_STDBY_STDBY_ADC__B 13533#define IQM_AF_STDBY_STDBY_ADC__W 13534#define IQM_AF_STDBY_STDBY_ADC__M 0x23535#define IQM_AF_STDBY_STDBY_ADC__PRE 0x03536#define IQM_AF_STDBY_STDBY_ADC_A1_ACTIVE 0x03537#define IQM_AF_STDBY_STDBY_ADC_A1_STANDBY 0x23538#define IQM_AF_STDBY_STDBY_ADC_A2_ACTIVE 0x23539#define IQM_AF_STDBY_STDBY_ADC_A2_STANDBY 0x03540 3541#define IQM_AF_STDBY_STDBY_AMP__B 23542#define IQM_AF_STDBY_STDBY_AMP__W 13543#define IQM_AF_STDBY_STDBY_AMP__M 0x43544#define IQM_AF_STDBY_STDBY_AMP__PRE 0x03545#define IQM_AF_STDBY_STDBY_AMP_A1_ACTIVE 0x03546#define IQM_AF_STDBY_STDBY_AMP_A1_STANDBY 0x43547#define IQM_AF_STDBY_STDBY_AMP_A2_ACTIVE 0x43548#define IQM_AF_STDBY_STDBY_AMP_A2_STANDBY 0x03549 3550#define IQM_AF_STDBY_STDBY_PD__B 33551#define IQM_AF_STDBY_STDBY_PD__W 13552#define IQM_AF_STDBY_STDBY_PD__M 0x83553#define IQM_AF_STDBY_STDBY_PD__PRE 0x03554#define IQM_AF_STDBY_STDBY_PD_A1_ACTIVE 0x03555#define IQM_AF_STDBY_STDBY_PD_A1_STANDBY 0x83556#define IQM_AF_STDBY_STDBY_PD_A2_ACTIVE 0x83557#define IQM_AF_STDBY_STDBY_PD_A2_STANDBY 0x03558 3559#define IQM_AF_STDBY_STDBY_TAGC_IF__B 43560#define IQM_AF_STDBY_STDBY_TAGC_IF__W 13561#define IQM_AF_STDBY_STDBY_TAGC_IF__M 0x103562#define IQM_AF_STDBY_STDBY_TAGC_IF__PRE 0x03563#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_ACTIVE 0x03564#define IQM_AF_STDBY_STDBY_TAGC_IF_A1_STANDBY 0x103565#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_ACTIVE 0x103566#define IQM_AF_STDBY_STDBY_TAGC_IF_A2_STANDBY 0x03567 3568#define IQM_AF_STDBY_STDBY_TAGC_RF__B 53569#define IQM_AF_STDBY_STDBY_TAGC_RF__W 13570#define IQM_AF_STDBY_STDBY_TAGC_RF__M 0x203571#define IQM_AF_STDBY_STDBY_TAGC_RF__PRE 0x03572#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_ACTIVE 0x03573#define IQM_AF_STDBY_STDBY_TAGC_RF_A1_STANDBY 0x203574#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_ACTIVE 0x203575#define IQM_AF_STDBY_STDBY_TAGC_RF_A2_STANDBY 0x03576 3577#define IQM_AF_AMUX__A 0x187002D3578#define IQM_AF_AMUX__W 23579#define IQM_AF_AMUX__M 0x33580#define IQM_AF_AMUX__PRE 0x03581 3582#define IQM_AF_TST_AFEMAIN__A 0x187002E3583#define IQM_AF_TST_AFEMAIN__W 83584#define IQM_AF_TST_AFEMAIN__M 0xFF3585#define IQM_AF_TST_AFEMAIN__PRE 0x03586 3587#define IQM_RT_RAM__A 0x18800003588 3589#define IQM_RT_RAM_DLY__B 03590#define IQM_RT_RAM_DLY__W 133591#define IQM_RT_RAM_DLY__M 0x1FFF3592#define IQM_RT_RAM_DLY__PRE 0x03593 3594#define ORX_COMM_EXEC__A 0x20000003595#define ORX_COMM_EXEC__W 23596#define ORX_COMM_EXEC__M 0x33597#define ORX_COMM_EXEC__PRE 0x03598#define ORX_COMM_EXEC_STOP 0x03599#define ORX_COMM_EXEC_ACTIVE 0x13600#define ORX_COMM_EXEC_HOLD 0x23601 3602#define ORX_COMM_STATE__A 0x20000013603#define ORX_COMM_STATE__W 163604#define ORX_COMM_STATE__M 0xFFFF3605#define ORX_COMM_STATE__PRE 0x03606#define ORX_COMM_MB__A 0x20000023607#define ORX_COMM_MB__W 163608#define ORX_COMM_MB__M 0xFFFF3609#define ORX_COMM_MB__PRE 0x03610#define ORX_COMM_INT_REQ__A 0x20000033611#define ORX_COMM_INT_REQ__W 163612#define ORX_COMM_INT_REQ__M 0xFFFF3613#define ORX_COMM_INT_REQ__PRE 0x03614#define ORX_COMM_INT_REQ_EQU_REQ__B 03615#define ORX_COMM_INT_REQ_EQU_REQ__W 13616#define ORX_COMM_INT_REQ_EQU_REQ__M 0x13617#define ORX_COMM_INT_REQ_EQU_REQ__PRE 0x03618#define ORX_COMM_INT_REQ_DDC_REQ__B 13619#define ORX_COMM_INT_REQ_DDC_REQ__W 13620#define ORX_COMM_INT_REQ_DDC_REQ__M 0x23621#define ORX_COMM_INT_REQ_DDC_REQ__PRE 0x03622#define ORX_COMM_INT_REQ_FWP_REQ__B 23623#define ORX_COMM_INT_REQ_FWP_REQ__W 13624#define ORX_COMM_INT_REQ_FWP_REQ__M 0x43625#define ORX_COMM_INT_REQ_FWP_REQ__PRE 0x03626#define ORX_COMM_INT_REQ_CON_REQ__B 33627#define ORX_COMM_INT_REQ_CON_REQ__W 13628#define ORX_COMM_INT_REQ_CON_REQ__M 0x83629#define ORX_COMM_INT_REQ_CON_REQ__PRE 0x03630#define ORX_COMM_INT_REQ_NSU_REQ__B 43631#define ORX_COMM_INT_REQ_NSU_REQ__W 13632#define ORX_COMM_INT_REQ_NSU_REQ__M 0x103633#define ORX_COMM_INT_REQ_NSU_REQ__PRE 0x03634 3635#define ORX_COMM_INT_STA__A 0x20000053636#define ORX_COMM_INT_STA__W 163637#define ORX_COMM_INT_STA__M 0xFFFF3638#define ORX_COMM_INT_STA__PRE 0x03639#define ORX_COMM_INT_MSK__A 0x20000063640#define ORX_COMM_INT_MSK__W 163641#define ORX_COMM_INT_MSK__M 0xFFFF3642#define ORX_COMM_INT_MSK__PRE 0x03643#define ORX_COMM_INT_STM__A 0x20000073644#define ORX_COMM_INT_STM__W 163645#define ORX_COMM_INT_STM__M 0xFFFF3646#define ORX_COMM_INT_STM__PRE 0x03647 3648#define ORX_TOP_COMM_EXEC__A 0x20100003649#define ORX_TOP_COMM_EXEC__W 23650#define ORX_TOP_COMM_EXEC__M 0x33651#define ORX_TOP_COMM_EXEC__PRE 0x03652#define ORX_TOP_COMM_EXEC_STOP 0x03653#define ORX_TOP_COMM_EXEC_ACTIVE 0x13654#define ORX_TOP_COMM_EXEC_HOLD 0x23655 3656#define ORX_TOP_COMM_KEY__A 0x201000F3657#define ORX_TOP_COMM_KEY__W 163658#define ORX_TOP_COMM_KEY__M 0xFFFF3659#define ORX_TOP_COMM_KEY__PRE 0x03660#define ORX_TOP_COMM_KEY_KEY 0xFABA3661 3662#define ORX_TOP_MDE_W__A 0x20100103663#define ORX_TOP_MDE_W__W 23664#define ORX_TOP_MDE_W__M 0x33665#define ORX_TOP_MDE_W__PRE 0x23666#define ORX_TOP_MDE_W_RATE_1544KBPS 0x03667#define ORX_TOP_MDE_W_RATE_3088KBPS 0x13668#define ORX_TOP_MDE_W_RATE_2048KBPS_SQRT 0x23669#define ORX_TOP_MDE_W_RATE_2048KBPS_RO 0x33670 3671#define ORX_TOP_AIF_CTRL_W__A 0x20100113672#define ORX_TOP_AIF_CTRL_W__W 33673#define ORX_TOP_AIF_CTRL_W__M 0x73674#define ORX_TOP_AIF_CTRL_W__PRE 0x03675#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__B 03676#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__W 13677#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__M 0x13678#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE__PRE 0x03679#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_POS_CLK_EDGE 0x03680#define ORX_TOP_AIF_CTRL_W_NEG_CLK_EDGE_ADC_SAMPL_ON_NEG_CLK_EDGE 0x13681#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__B 13682#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__W 13683#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__M 0x23684#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE__PRE 0x03685#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REGULAR_BIT_ORDER_ADC 0x03686#define ORX_TOP_AIF_CTRL_W_BIT_REVERSE_REVERSAL_BIT_ORDER_ADC 0x23687#define ORX_TOP_AIF_CTRL_W_INV_MSB__B 23688#define ORX_TOP_AIF_CTRL_W_INV_MSB__W 13689#define ORX_TOP_AIF_CTRL_W_INV_MSB__M 0x43690#define ORX_TOP_AIF_CTRL_W_INV_MSB__PRE 0x03691#define ORX_TOP_AIF_CTRL_W_INV_MSB_NO_MSB_INVERSION_ADC 0x03692#define ORX_TOP_AIF_CTRL_W_INV_MSB_MSB_INVERSION_ADC 0x43693 3694#define ORX_FWP_COMM_EXEC__A 0x20200003695#define ORX_FWP_COMM_EXEC__W 23696#define ORX_FWP_COMM_EXEC__M 0x33697#define ORX_FWP_COMM_EXEC__PRE 0x03698#define ORX_FWP_COMM_EXEC_STOP 0x03699#define ORX_FWP_COMM_EXEC_ACTIVE 0x13700#define ORX_FWP_COMM_EXEC_HOLD 0x23701 3702#define ORX_FWP_COMM_MB__A 0x20200023703#define ORX_FWP_COMM_MB__W 83704#define ORX_FWP_COMM_MB__M 0xFF3705#define ORX_FWP_COMM_MB__PRE 0x03706#define ORX_FWP_COMM_MB_CTL__B 03707#define ORX_FWP_COMM_MB_CTL__W 13708#define ORX_FWP_COMM_MB_CTL__M 0x13709#define ORX_FWP_COMM_MB_CTL__PRE 0x03710#define ORX_FWP_COMM_MB_CTL_OFF 0x03711#define ORX_FWP_COMM_MB_CTL_ON 0x13712#define ORX_FWP_COMM_MB_OBS__B 13713#define ORX_FWP_COMM_MB_OBS__W 13714#define ORX_FWP_COMM_MB_OBS__M 0x23715#define ORX_FWP_COMM_MB_OBS__PRE 0x03716#define ORX_FWP_COMM_MB_OBS_OFF 0x03717#define ORX_FWP_COMM_MB_OBS_ON 0x23718 3719#define ORX_FWP_COMM_MB_CTL_MUX__B 23720#define ORX_FWP_COMM_MB_CTL_MUX__W 33721#define ORX_FWP_COMM_MB_CTL_MUX__M 0x1C3722#define ORX_FWP_COMM_MB_CTL_MUX__PRE 0x03723 3724#define ORX_FWP_COMM_MB_OBS_MUX__B 53725#define ORX_FWP_COMM_MB_OBS_MUX__W 33726#define ORX_FWP_COMM_MB_OBS_MUX__M 0xE03727#define ORX_FWP_COMM_MB_OBS_MUX__PRE 0x03728 3729#define ORX_FWP_AAG_LEN_W__A 0x20200103730#define ORX_FWP_AAG_LEN_W__W 163731#define ORX_FWP_AAG_LEN_W__M 0xFFFF3732#define ORX_FWP_AAG_LEN_W__PRE 0x8003733 3734#define ORX_FWP_AAG_THR_W__A 0x20200113735#define ORX_FWP_AAG_THR_W__W 83736#define ORX_FWP_AAG_THR_W__M 0xFF3737#define ORX_FWP_AAG_THR_W__PRE 0x503738 3739#define ORX_FWP_AAG_THR_CNT_R__A 0x20200123740#define ORX_FWP_AAG_THR_CNT_R__W 163741#define ORX_FWP_AAG_THR_CNT_R__M 0xFFFF3742#define ORX_FWP_AAG_THR_CNT_R__PRE 0x03743 3744#define ORX_FWP_AAG_SNS_CNT_R__A 0x20200133745#define ORX_FWP_AAG_SNS_CNT_R__W 163746#define ORX_FWP_AAG_SNS_CNT_R__M 0xFFFF3747#define ORX_FWP_AAG_SNS_CNT_R__PRE 0x03748 3749#define ORX_FWP_PFI_A_W__A 0x20200143750#define ORX_FWP_PFI_A_W__W 83751#define ORX_FWP_PFI_A_W__M 0xFF3752#define ORX_FWP_PFI_A_W__PRE 0xB03753#define ORX_FWP_PFI_A_W_RATE_2048KBPS 0xB03754#define ORX_FWP_PFI_A_W_RATE_1544KBPS 0xA43755#define ORX_FWP_PFI_A_W_RATE_3088KBPS 0xC03756 3757#define ORX_FWP_PFI_B_W__A 0x20200153758#define ORX_FWP_PFI_B_W__W 83759#define ORX_FWP_PFI_B_W__M 0xFF3760#define ORX_FWP_PFI_B_W__PRE 0x9E3761#define ORX_FWP_PFI_B_W_RATE_2048KBPS 0x9E3762#define ORX_FWP_PFI_B_W_RATE_1544KBPS 0x943763#define ORX_FWP_PFI_B_W_RATE_3088KBPS 0xB03764 3765#define ORX_FWP_PFI_C_W__A 0x20200163766#define ORX_FWP_PFI_C_W__W 83767#define ORX_FWP_PFI_C_W__M 0xFF3768#define ORX_FWP_PFI_C_W__PRE 0x5C3769#define ORX_FWP_PFI_C_W_RATE_2048KBPS 0x5C3770#define ORX_FWP_PFI_C_W_RATE_1544KBPS 0x643771#define ORX_FWP_PFI_C_W_RATE_3088KBPS 0x503772 3773#define ORX_FWP_KR1_AMP_R__A 0x20200173774#define ORX_FWP_KR1_AMP_R__W 93775#define ORX_FWP_KR1_AMP_R__M 0x1FF3776#define ORX_FWP_KR1_AMP_R__PRE 0x03777 3778#define ORX_FWP_KR1_LDT_W__A 0x20200183779#define ORX_FWP_KR1_LDT_W__W 33780#define ORX_FWP_KR1_LDT_W__M 0x73781#define ORX_FWP_KR1_LDT_W__PRE 0x23782#define ORX_FWP_SRC_DGN_W__A 0x20200193783#define ORX_FWP_SRC_DGN_W__W 163784#define ORX_FWP_SRC_DGN_W__M 0xFFFF3785#define ORX_FWP_SRC_DGN_W__PRE 0x1FF3786 3787#define ORX_FWP_SRC_DGN_W_MANT__B 03788#define ORX_FWP_SRC_DGN_W_MANT__W 93789#define ORX_FWP_SRC_DGN_W_MANT__M 0x1FF3790#define ORX_FWP_SRC_DGN_W_MANT__PRE 0x1FF3791 3792#define ORX_FWP_SRC_DGN_W_EXP__B 123793#define ORX_FWP_SRC_DGN_W_EXP__W 43794#define ORX_FWP_SRC_DGN_W_EXP__M 0xF0003795#define ORX_FWP_SRC_DGN_W_EXP__PRE 0x03796 3797#define ORX_FWP_NYQ_ADR_W__A 0x202001A3798#define ORX_FWP_NYQ_ADR_W__W 53799#define ORX_FWP_NYQ_ADR_W__M 0x1F3800#define ORX_FWP_NYQ_ADR_W__PRE 0x1F3801 3802#define ORX_FWP_NYQ_COF_RW__A 0x202001B3803#define ORX_FWP_NYQ_COF_RW__W 103804#define ORX_FWP_NYQ_COF_RW__M 0x3FF3805#define ORX_FWP_NYQ_COF_RW__PRE 0x03806 3807#define ORX_FWP_IQM_FRQ_W__A 0x202001C3808#define ORX_FWP_IQM_FRQ_W__W 163809#define ORX_FWP_IQM_FRQ_W__M 0xFFFF3810#define ORX_FWP_IQM_FRQ_W__PRE 0x43013811 3812#define ORX_EQU_COMM_EXEC__A 0x20300003813#define ORX_EQU_COMM_EXEC__W 23814#define ORX_EQU_COMM_EXEC__M 0x33815#define ORX_EQU_COMM_EXEC__PRE 0x03816#define ORX_EQU_COMM_EXEC_STOP 0x03817#define ORX_EQU_COMM_EXEC_ACTIVE 0x13818#define ORX_EQU_COMM_EXEC_HOLD 0x23819 3820#define ORX_EQU_COMM_MB__A 0x20300023821#define ORX_EQU_COMM_MB__W 83822#define ORX_EQU_COMM_MB__M 0xFF3823#define ORX_EQU_COMM_MB__PRE 0x03824#define ORX_EQU_COMM_MB_CTL__B 03825#define ORX_EQU_COMM_MB_CTL__W 13826#define ORX_EQU_COMM_MB_CTL__M 0x13827#define ORX_EQU_COMM_MB_CTL__PRE 0x03828#define ORX_EQU_COMM_MB_CTL_OFF 0x03829#define ORX_EQU_COMM_MB_CTL_ON 0x13830#define ORX_EQU_COMM_MB_OBS__B 13831#define ORX_EQU_COMM_MB_OBS__W 13832#define ORX_EQU_COMM_MB_OBS__M 0x23833#define ORX_EQU_COMM_MB_OBS__PRE 0x03834#define ORX_EQU_COMM_MB_OBS_OFF 0x03835#define ORX_EQU_COMM_MB_OBS_ON 0x23836 3837#define ORX_EQU_COMM_MB_CTL_MUX__B 23838#define ORX_EQU_COMM_MB_CTL_MUX__W 33839#define ORX_EQU_COMM_MB_CTL_MUX__M 0x1C3840#define ORX_EQU_COMM_MB_CTL_MUX__PRE 0x03841 3842#define ORX_EQU_COMM_MB_OBS_MUX__B 53843#define ORX_EQU_COMM_MB_OBS_MUX__W 33844#define ORX_EQU_COMM_MB_OBS_MUX__M 0xE03845#define ORX_EQU_COMM_MB_OBS_MUX__PRE 0x03846 3847#define ORX_EQU_COMM_INT_REQ__A 0x20300033848#define ORX_EQU_COMM_INT_REQ__W 13849#define ORX_EQU_COMM_INT_REQ__M 0x13850#define ORX_EQU_COMM_INT_REQ__PRE 0x03851#define ORX_EQU_COMM_INT_STA__A 0x20300053852#define ORX_EQU_COMM_INT_STA__W 23853#define ORX_EQU_COMM_INT_STA__M 0x33854#define ORX_EQU_COMM_INT_STA__PRE 0x03855 3856#define ORX_EQU_COMM_INT_STA_FFF_READ__B 03857#define ORX_EQU_COMM_INT_STA_FFF_READ__W 13858#define ORX_EQU_COMM_INT_STA_FFF_READ__M 0x13859#define ORX_EQU_COMM_INT_STA_FFF_READ__PRE 0x03860 3861#define ORX_EQU_COMM_INT_STA_FBF_READ__B 13862#define ORX_EQU_COMM_INT_STA_FBF_READ__W 13863#define ORX_EQU_COMM_INT_STA_FBF_READ__M 0x23864#define ORX_EQU_COMM_INT_STA_FBF_READ__PRE 0x03865 3866#define ORX_EQU_COMM_INT_MSK__A 0x20300063867#define ORX_EQU_COMM_INT_MSK__W 23868#define ORX_EQU_COMM_INT_MSK__M 0x33869#define ORX_EQU_COMM_INT_MSK__PRE 0x03870#define ORX_EQU_COMM_INT_MSK_FFF_READ__B 03871#define ORX_EQU_COMM_INT_MSK_FFF_READ__W 13872#define ORX_EQU_COMM_INT_MSK_FFF_READ__M 0x13873#define ORX_EQU_COMM_INT_MSK_FFF_READ__PRE 0x03874#define ORX_EQU_COMM_INT_MSK_FBF_READ__B 13875#define ORX_EQU_COMM_INT_MSK_FBF_READ__W 13876#define ORX_EQU_COMM_INT_MSK_FBF_READ__M 0x23877#define ORX_EQU_COMM_INT_MSK_FBF_READ__PRE 0x03878 3879#define ORX_EQU_COMM_INT_STM__A 0x20300073880#define ORX_EQU_COMM_INT_STM__W 23881#define ORX_EQU_COMM_INT_STM__M 0x33882#define ORX_EQU_COMM_INT_STM__PRE 0x03883#define ORX_EQU_COMM_INT_STM_FFF_READ__B 03884#define ORX_EQU_COMM_INT_STM_FFF_READ__W 13885#define ORX_EQU_COMM_INT_STM_FFF_READ__M 0x13886#define ORX_EQU_COMM_INT_STM_FFF_READ__PRE 0x03887#define ORX_EQU_COMM_INT_STM_FBF_READ__B 13888#define ORX_EQU_COMM_INT_STM_FBF_READ__W 13889#define ORX_EQU_COMM_INT_STM_FBF_READ__M 0x23890#define ORX_EQU_COMM_INT_STM_FBF_READ__PRE 0x03891 3892#define ORX_EQU_FFF_SCL_W__A 0x20300103893#define ORX_EQU_FFF_SCL_W__W 13894#define ORX_EQU_FFF_SCL_W__M 0x13895#define ORX_EQU_FFF_SCL_W__PRE 0x03896#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_1 0x03897#define ORX_EQU_FFF_SCL_W_SCALE_GAIN_2 0x13898 3899#define ORX_EQU_FFF_UPD_W__A 0x20300113900#define ORX_EQU_FFF_UPD_W__W 13901#define ORX_EQU_FFF_UPD_W__M 0x13902#define ORX_EQU_FFF_UPD_W__PRE 0x03903#define ORX_EQU_FFF_UPD_W_NO_UPDATE 0x03904#define ORX_EQU_FFF_UPD_W_LMS_UPDATE 0x13905 3906#define ORX_EQU_FFF_STP_W__A 0x20300123907#define ORX_EQU_FFF_STP_W__W 33908#define ORX_EQU_FFF_STP_W__M 0x73909#define ORX_EQU_FFF_STP_W__PRE 0x23910 3911#define ORX_EQU_FFF_LEA_W__A 0x20300133912#define ORX_EQU_FFF_LEA_W__W 43913#define ORX_EQU_FFF_LEA_W__M 0xF3914#define ORX_EQU_FFF_LEA_W__PRE 0x43915 3916#define ORX_EQU_FFF_RWT_W__A 0x20300143917#define ORX_EQU_FFF_RWT_W__W 23918#define ORX_EQU_FFF_RWT_W__M 0x33919#define ORX_EQU_FFF_RWT_W__PRE 0x03920 3921#define ORX_EQU_FFF_C0RE_RW__A 0x20300153922#define ORX_EQU_FFF_C0RE_RW__W 123923#define ORX_EQU_FFF_C0RE_RW__M 0xFFF3924#define ORX_EQU_FFF_C0RE_RW__PRE 0x03925 3926#define ORX_EQU_FFF_C0IM_RW__A 0x20300163927#define ORX_EQU_FFF_C0IM_RW__W 123928#define ORX_EQU_FFF_C0IM_RW__M 0xFFF3929#define ORX_EQU_FFF_C0IM_RW__PRE 0x03930 3931#define ORX_EQU_FFF_C1RE_RW__A 0x20300173932#define ORX_EQU_FFF_C1RE_RW__W 123933#define ORX_EQU_FFF_C1RE_RW__M 0xFFF3934#define ORX_EQU_FFF_C1RE_RW__PRE 0x03935 3936#define ORX_EQU_FFF_C1IM_RW__A 0x20300183937#define ORX_EQU_FFF_C1IM_RW__W 123938#define ORX_EQU_FFF_C1IM_RW__M 0xFFF3939#define ORX_EQU_FFF_C1IM_RW__PRE 0x03940 3941#define ORX_EQU_FFF_C2RE_RW__A 0x20300193942#define ORX_EQU_FFF_C2RE_RW__W 123943#define ORX_EQU_FFF_C2RE_RW__M 0xFFF3944#define ORX_EQU_FFF_C2RE_RW__PRE 0x03945 3946#define ORX_EQU_FFF_C2IM_RW__A 0x203001A3947#define ORX_EQU_FFF_C2IM_RW__W 123948#define ORX_EQU_FFF_C2IM_RW__M 0xFFF3949#define ORX_EQU_FFF_C2IM_RW__PRE 0x03950 3951#define ORX_EQU_FFF_C3RE_RW__A 0x203001B3952#define ORX_EQU_FFF_C3RE_RW__W 123953#define ORX_EQU_FFF_C3RE_RW__M 0xFFF3954#define ORX_EQU_FFF_C3RE_RW__PRE 0x03955 3956#define ORX_EQU_FFF_C3IM_RW__A 0x203001C3957#define ORX_EQU_FFF_C3IM_RW__W 123958#define ORX_EQU_FFF_C3IM_RW__M 0xFFF3959#define ORX_EQU_FFF_C3IM_RW__PRE 0x03960 3961#define ORX_EQU_FFF_C4RE_RW__A 0x203001D3962#define ORX_EQU_FFF_C4RE_RW__W 123963#define ORX_EQU_FFF_C4RE_RW__M 0xFFF3964#define ORX_EQU_FFF_C4RE_RW__PRE 0x4003965 3966#define ORX_EQU_FFF_C4IM_RW__A 0x203001E3967#define ORX_EQU_FFF_C4IM_RW__W 123968#define ORX_EQU_FFF_C4IM_RW__M 0xFFF3969#define ORX_EQU_FFF_C4IM_RW__PRE 0x03970 3971#define ORX_EQU_FFF_C5RE_RW__A 0x203001F3972#define ORX_EQU_FFF_C5RE_RW__W 123973#define ORX_EQU_FFF_C5RE_RW__M 0xFFF3974#define ORX_EQU_FFF_C5RE_RW__PRE 0x03975 3976#define ORX_EQU_FFF_C5IM_RW__A 0x20300203977#define ORX_EQU_FFF_C5IM_RW__W 123978#define ORX_EQU_FFF_C5IM_RW__M 0xFFF3979#define ORX_EQU_FFF_C5IM_RW__PRE 0x03980 3981#define ORX_EQU_FFF_C6RE_RW__A 0x20300213982#define ORX_EQU_FFF_C6RE_RW__W 123983#define ORX_EQU_FFF_C6RE_RW__M 0xFFF3984#define ORX_EQU_FFF_C6RE_RW__PRE 0x03985 3986#define ORX_EQU_FFF_C6IM_RW__A 0x20300223987#define ORX_EQU_FFF_C6IM_RW__W 123988#define ORX_EQU_FFF_C6IM_RW__M 0xFFF3989#define ORX_EQU_FFF_C6IM_RW__PRE 0x03990 3991#define ORX_EQU_FFF_C7RE_RW__A 0x20300233992#define ORX_EQU_FFF_C7RE_RW__W 123993#define ORX_EQU_FFF_C7RE_RW__M 0xFFF3994#define ORX_EQU_FFF_C7RE_RW__PRE 0x03995 3996#define ORX_EQU_FFF_C7IM_RW__A 0x20300243997#define ORX_EQU_FFF_C7IM_RW__W 123998#define ORX_EQU_FFF_C7IM_RW__M 0xFFF3999#define ORX_EQU_FFF_C7IM_RW__PRE 0x04000 4001#define ORX_EQU_FFF_C8RE_RW__A 0x20300254002#define ORX_EQU_FFF_C8RE_RW__W 124003#define ORX_EQU_FFF_C8RE_RW__M 0xFFF4004#define ORX_EQU_FFF_C8RE_RW__PRE 0x04005 4006#define ORX_EQU_FFF_C8IM_RW__A 0x20300264007#define ORX_EQU_FFF_C8IM_RW__W 124008#define ORX_EQU_FFF_C8IM_RW__M 0xFFF4009#define ORX_EQU_FFF_C8IM_RW__PRE 0x04010 4011#define ORX_EQU_FFF_C9RE_RW__A 0x20300274012#define ORX_EQU_FFF_C9RE_RW__W 124013#define ORX_EQU_FFF_C9RE_RW__M 0xFFF4014#define ORX_EQU_FFF_C9RE_RW__PRE 0x04015 4016#define ORX_EQU_FFF_C9IM_RW__A 0x20300284017#define ORX_EQU_FFF_C9IM_RW__W 124018#define ORX_EQU_FFF_C9IM_RW__M 0xFFF4019#define ORX_EQU_FFF_C9IM_RW__PRE 0x04020 4021#define ORX_EQU_FFF_C10RE_RW__A 0x20300294022#define ORX_EQU_FFF_C10RE_RW__W 124023#define ORX_EQU_FFF_C10RE_RW__M 0xFFF4024#define ORX_EQU_FFF_C10RE_RW__PRE 0x04025 4026#define ORX_EQU_FFF_C10IM_RW__A 0x203002A4027#define ORX_EQU_FFF_C10IM_RW__W 124028#define ORX_EQU_FFF_C10IM_RW__M 0xFFF4029#define ORX_EQU_FFF_C10IM_RW__PRE 0x04030 4031#define ORX_EQU_MXB_SEL_W__A 0x203002B4032#define ORX_EQU_MXB_SEL_W__W 14033#define ORX_EQU_MXB_SEL_W__M 0x14034#define ORX_EQU_MXB_SEL_W__PRE 0x04035#define ORX_EQU_MXB_SEL_W_UNDECIDED_SYMBOLS 0x04036#define ORX_EQU_MXB_SEL_W_DECIDED_SYMBOLS 0x14037 4038#define ORX_EQU_FBF_UPD_W__A 0x203002C4039#define ORX_EQU_FBF_UPD_W__W 14040#define ORX_EQU_FBF_UPD_W__M 0x14041#define ORX_EQU_FBF_UPD_W__PRE 0x04042#define ORX_EQU_FBF_UPD_W_NO_UPDATE 0x04043#define ORX_EQU_FBF_UPD_W_LMS_UPDATE 0x14044 4045#define ORX_EQU_FBF_STP_W__A 0x203002D4046#define ORX_EQU_FBF_STP_W__W 34047#define ORX_EQU_FBF_STP_W__M 0x74048#define ORX_EQU_FBF_STP_W__PRE 0x24049 4050#define ORX_EQU_FBF_LEA_W__A 0x203002E4051#define ORX_EQU_FBF_LEA_W__W 44052#define ORX_EQU_FBF_LEA_W__M 0xF4053#define ORX_EQU_FBF_LEA_W__PRE 0x44054 4055#define ORX_EQU_FBF_RWT_W__A 0x203002F4056#define ORX_EQU_FBF_RWT_W__W 24057#define ORX_EQU_FBF_RWT_W__M 0x34058#define ORX_EQU_FBF_RWT_W__PRE 0x04059 4060#define ORX_EQU_FBF_C0RE_RW__A 0x20300304061#define ORX_EQU_FBF_C0RE_RW__W 124062#define ORX_EQU_FBF_C0RE_RW__M 0xFFF4063#define ORX_EQU_FBF_C0RE_RW__PRE 0x04064 4065#define ORX_EQU_FBF_C0IM_RW__A 0x20300314066#define ORX_EQU_FBF_C0IM_RW__W 124067#define ORX_EQU_FBF_C0IM_RW__M 0xFFF4068#define ORX_EQU_FBF_C0IM_RW__PRE 0x04069 4070#define ORX_EQU_FBF_C1RE_RW__A 0x20300324071#define ORX_EQU_FBF_C1RE_RW__W 124072#define ORX_EQU_FBF_C1RE_RW__M 0xFFF4073#define ORX_EQU_FBF_C1RE_RW__PRE 0x04074 4075#define ORX_EQU_FBF_C1IM_RW__A 0x20300334076#define ORX_EQU_FBF_C1IM_RW__W 124077#define ORX_EQU_FBF_C1IM_RW__M 0xFFF4078#define ORX_EQU_FBF_C1IM_RW__PRE 0x04079 4080#define ORX_EQU_FBF_C2RE_RW__A 0x20300344081#define ORX_EQU_FBF_C2RE_RW__W 124082#define ORX_EQU_FBF_C2RE_RW__M 0xFFF4083#define ORX_EQU_FBF_C2RE_RW__PRE 0x04084 4085#define ORX_EQU_FBF_C2IM_RW__A 0x20300354086#define ORX_EQU_FBF_C2IM_RW__W 124087#define ORX_EQU_FBF_C2IM_RW__M 0xFFF4088#define ORX_EQU_FBF_C2IM_RW__PRE 0x04089 4090#define ORX_EQU_FBF_C3RE_RW__A 0x20300364091#define ORX_EQU_FBF_C3RE_RW__W 124092#define ORX_EQU_FBF_C3RE_RW__M 0xFFF4093#define ORX_EQU_FBF_C3RE_RW__PRE 0x04094 4095#define ORX_EQU_FBF_C3IM_RW__A 0x20300374096#define ORX_EQU_FBF_C3IM_RW__W 124097#define ORX_EQU_FBF_C3IM_RW__M 0xFFF4098#define ORX_EQU_FBF_C3IM_RW__PRE 0x04099 4100#define ORX_EQU_FBF_C4RE_RW__A 0x20300384101#define ORX_EQU_FBF_C4RE_RW__W 124102#define ORX_EQU_FBF_C4RE_RW__M 0xFFF4103#define ORX_EQU_FBF_C4RE_RW__PRE 0x04104 4105#define ORX_EQU_FBF_C4IM_RW__A 0x20300394106#define ORX_EQU_FBF_C4IM_RW__W 124107#define ORX_EQU_FBF_C4IM_RW__M 0xFFF4108#define ORX_EQU_FBF_C4IM_RW__PRE 0x04109 4110#define ORX_EQU_FBF_C5RE_RW__A 0x203003A4111#define ORX_EQU_FBF_C5RE_RW__W 124112#define ORX_EQU_FBF_C5RE_RW__M 0xFFF4113#define ORX_EQU_FBF_C5RE_RW__PRE 0x04114 4115#define ORX_EQU_FBF_C5IM_RW__A 0x203003B4116#define ORX_EQU_FBF_C5IM_RW__W 124117#define ORX_EQU_FBF_C5IM_RW__M 0xFFF4118#define ORX_EQU_FBF_C5IM_RW__PRE 0x04119 4120#define ORX_EQU_ERR_SEL_W__A 0x203003C4121#define ORX_EQU_ERR_SEL_W__W 14122#define ORX_EQU_ERR_SEL_W__M 0x14123#define ORX_EQU_ERR_SEL_W__PRE 0x04124#define ORX_EQU_ERR_SEL_W_CMA_ERROR 0x04125#define ORX_EQU_ERR_SEL_W_DDA_ERROR 0x14126 4127#define ORX_EQU_ERR_TIS_W__A 0x203003D4128#define ORX_EQU_ERR_TIS_W__W 14129#define ORX_EQU_ERR_TIS_W__M 0x14130#define ORX_EQU_ERR_TIS_W__PRE 0x04131#define ORX_EQU_ERR_TIS_W_CMA_SIGNALS 0x04132#define ORX_EQU_ERR_TIS_W_DDA_SIGNALS 0x14133 4134#define ORX_EQU_ERR_EDI_R__A 0x203003E4135#define ORX_EQU_ERR_EDI_R__W 54136#define ORX_EQU_ERR_EDI_R__M 0x1F4137#define ORX_EQU_ERR_EDI_R__PRE 0xF4138 4139#define ORX_EQU_ERR_EDQ_R__A 0x203003F4140#define ORX_EQU_ERR_EDQ_R__W 54141#define ORX_EQU_ERR_EDQ_R__M 0x1F4142#define ORX_EQU_ERR_EDQ_R__PRE 0xF4143 4144#define ORX_EQU_ERR_ECI_R__A 0x20300404145#define ORX_EQU_ERR_ECI_R__W 54146#define ORX_EQU_ERR_ECI_R__M 0x1F4147#define ORX_EQU_ERR_ECI_R__PRE 0xF4148 4149#define ORX_EQU_ERR_ECQ_R__A 0x20300414150#define ORX_EQU_ERR_ECQ_R__W 54151#define ORX_EQU_ERR_ECQ_R__M 0x1F4152#define ORX_EQU_ERR_ECQ_R__PRE 0xF4153 4154#define ORX_EQU_MER_MER_R__A 0x20300424155#define ORX_EQU_MER_MER_R__W 64156#define ORX_EQU_MER_MER_R__M 0x3F4157#define ORX_EQU_MER_MER_R__PRE 0x3F4158 4159#define ORX_EQU_MER_LDT_W__A 0x20300434160#define ORX_EQU_MER_LDT_W__W 34161#define ORX_EQU_MER_LDT_W__M 0x74162#define ORX_EQU_MER_LDT_W__PRE 0x44163 4164#define ORX_EQU_SYN_LEN_W__A 0x20300444165#define ORX_EQU_SYN_LEN_W__W 164166#define ORX_EQU_SYN_LEN_W__M 0xFFFF4167#define ORX_EQU_SYN_LEN_W__PRE 0x04168 4169#define ORX_DDC_COMM_EXEC__A 0x20400004170#define ORX_DDC_COMM_EXEC__W 24171#define ORX_DDC_COMM_EXEC__M 0x34172#define ORX_DDC_COMM_EXEC__PRE 0x04173#define ORX_DDC_COMM_EXEC_STOP 0x04174#define ORX_DDC_COMM_EXEC_ACTIVE 0x14175#define ORX_DDC_COMM_EXEC_HOLD 0x24176 4177#define ORX_DDC_COMM_MB__A 0x20400024178#define ORX_DDC_COMM_MB__W 64179#define ORX_DDC_COMM_MB__M 0x3F4180#define ORX_DDC_COMM_MB__PRE 0x04181#define ORX_DDC_COMM_MB_CTL__B 04182#define ORX_DDC_COMM_MB_CTL__W 14183#define ORX_DDC_COMM_MB_CTL__M 0x14184#define ORX_DDC_COMM_MB_CTL__PRE 0x04185#define ORX_DDC_COMM_MB_CTL_OFF 0x04186#define ORX_DDC_COMM_MB_CTL_ON 0x14187#define ORX_DDC_COMM_MB_OBS__B 14188#define ORX_DDC_COMM_MB_OBS__W 14189#define ORX_DDC_COMM_MB_OBS__M 0x24190#define ORX_DDC_COMM_MB_OBS__PRE 0x04191#define ORX_DDC_COMM_MB_OBS_OFF 0x04192#define ORX_DDC_COMM_MB_OBS_ON 0x24193 4194#define ORX_DDC_COMM_MB_CTL_MUX__B 24195#define ORX_DDC_COMM_MB_CTL_MUX__W 24196#define ORX_DDC_COMM_MB_CTL_MUX__M 0xC4197#define ORX_DDC_COMM_MB_CTL_MUX__PRE 0x04198 4199#define ORX_DDC_COMM_MB_OBS_MUX__B 44200#define ORX_DDC_COMM_MB_OBS_MUX__W 24201#define ORX_DDC_COMM_MB_OBS_MUX__M 0x304202#define ORX_DDC_COMM_MB_OBS_MUX__PRE 0x04203 4204#define ORX_DDC_COMM_INT_REQ__A 0x20400034205#define ORX_DDC_COMM_INT_REQ__W 14206#define ORX_DDC_COMM_INT_REQ__M 0x14207#define ORX_DDC_COMM_INT_REQ__PRE 0x04208#define ORX_DDC_COMM_INT_STA__A 0x20400054209#define ORX_DDC_COMM_INT_STA__W 14210#define ORX_DDC_COMM_INT_STA__M 0x14211#define ORX_DDC_COMM_INT_STA__PRE 0x04212#define ORX_DDC_COMM_INT_MSK__A 0x20400064213#define ORX_DDC_COMM_INT_MSK__W 14214#define ORX_DDC_COMM_INT_MSK__M 0x14215#define ORX_DDC_COMM_INT_MSK__PRE 0x04216#define ORX_DDC_COMM_INT_STM__A 0x20400074217#define ORX_DDC_COMM_INT_STM__W 14218#define ORX_DDC_COMM_INT_STM__M 0x14219#define ORX_DDC_COMM_INT_STM__PRE 0x04220#define ORX_DDC_DEC_MAP_W__A 0x20400104221#define ORX_DDC_DEC_MAP_W__W 94222#define ORX_DDC_DEC_MAP_W__M 0x1FF4223#define ORX_DDC_DEC_MAP_W__PRE 0x1784224 4225#define ORX_DDC_DEC_MAP_W_QUADR0__B 04226#define ORX_DDC_DEC_MAP_W_QUADR0__W 24227#define ORX_DDC_DEC_MAP_W_QUADR0__M 0x34228#define ORX_DDC_DEC_MAP_W_QUADR0__PRE 0x04229#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_DEFAULT 0x04230#define ORX_DDC_DEC_MAP_W_QUADR0_ROTATE_ALTERNATE 0x04231 4232#define ORX_DDC_DEC_MAP_W_QUADR1__B 24233#define ORX_DDC_DEC_MAP_W_QUADR1__W 24234#define ORX_DDC_DEC_MAP_W_QUADR1__M 0xC4235#define ORX_DDC_DEC_MAP_W_QUADR1__PRE 0x84236#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_DEFAULT 0x84237#define ORX_DDC_DEC_MAP_W_QUADR1_ROTATE_ALTERNATE 0x44238 4239#define ORX_DDC_DEC_MAP_W_QUADR2__B 44240#define ORX_DDC_DEC_MAP_W_QUADR2__W 24241#define ORX_DDC_DEC_MAP_W_QUADR2__M 0x304242#define ORX_DDC_DEC_MAP_W_QUADR2__PRE 0x304243#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_DEFAULT 0x304244#define ORX_DDC_DEC_MAP_W_QUADR2_ROTATE_ALTERNATE 0x304245 4246#define ORX_DDC_DEC_MAP_W_QUADR3__B 64247#define ORX_DDC_DEC_MAP_W_QUADR3__W 24248#define ORX_DDC_DEC_MAP_W_QUADR3__M 0xC04249#define ORX_DDC_DEC_MAP_W_QUADR3__PRE 0x404250#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_DEFAULT 0x404251#define ORX_DDC_DEC_MAP_W_QUADR3_ROTATE_ALTERNATE 0x804252#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__B 84253#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__W 14254#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__M 0x1004255#define ORX_DDC_DEC_MAP_W_DIFF_DECOD__PRE 0x1004256#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_COHERENT_DECODING 0x04257#define ORX_DDC_DEC_MAP_W_DIFF_DECOD_DIFF_DECODING 0x1004258 4259#define ORX_DDC_OFO_SET_W__A 0x20400114260#define ORX_DDC_OFO_SET_W__W 164261#define ORX_DDC_OFO_SET_W__M 0xFFFF4262#define ORX_DDC_OFO_SET_W__PRE 0x14024263 4264#define ORX_DDC_OFO_SET_W_PHASE__B 04265#define ORX_DDC_OFO_SET_W_PHASE__W 74266#define ORX_DDC_OFO_SET_W_PHASE__M 0x7F4267#define ORX_DDC_OFO_SET_W_PHASE__PRE 0x24268 4269#define ORX_DDC_OFO_SET_W_CRXHITIME__B 74270#define ORX_DDC_OFO_SET_W_CRXHITIME__W 74271#define ORX_DDC_OFO_SET_W_CRXHITIME__M 0x3F804272#define ORX_DDC_OFO_SET_W_CRXHITIME__PRE 0x14004273 4274#define ORX_DDC_OFO_SET_W_CRXINV__B 144275#define ORX_DDC_OFO_SET_W_CRXINV__W 14276#define ORX_DDC_OFO_SET_W_CRXINV__M 0x40004277#define ORX_DDC_OFO_SET_W_CRXINV__PRE 0x04278 4279#define ORX_DDC_OFO_SET_W_DISABLE__B 154280#define ORX_DDC_OFO_SET_W_DISABLE__W 14281#define ORX_DDC_OFO_SET_W_DISABLE__M 0x80004282#define ORX_DDC_OFO_SET_W_DISABLE__PRE 0x04283 4284#define ORX_CON_COMM_EXEC__A 0x20500004285#define ORX_CON_COMM_EXEC__W 24286#define ORX_CON_COMM_EXEC__M 0x34287#define ORX_CON_COMM_EXEC__PRE 0x04288#define ORX_CON_COMM_EXEC_STOP 0x04289#define ORX_CON_COMM_EXEC_ACTIVE 0x14290#define ORX_CON_COMM_EXEC_HOLD 0x24291 4292#define ORX_CON_LDT_W__A 0x20500104293#define ORX_CON_LDT_W__W 34294#define ORX_CON_LDT_W__M 0x74295#define ORX_CON_LDT_W__PRE 0x34296 4297#define ORX_CON_LDT_W_CON_LDT_W__B 04298#define ORX_CON_LDT_W_CON_LDT_W__W 34299#define ORX_CON_LDT_W_CON_LDT_W__M 0x74300#define ORX_CON_LDT_W_CON_LDT_W__PRE 0x34301 4302#define ORX_CON_RST_W__A 0x20500114303#define ORX_CON_RST_W__W 44304#define ORX_CON_RST_W__M 0xF4305#define ORX_CON_RST_W__PRE 0x04306 4307#define ORX_CON_RST_W_CPH__B 04308#define ORX_CON_RST_W_CPH__W 14309#define ORX_CON_RST_W_CPH__M 0x14310#define ORX_CON_RST_W_CPH__PRE 0x04311 4312#define ORX_CON_RST_W_CTI__B 14313#define ORX_CON_RST_W_CTI__W 14314#define ORX_CON_RST_W_CTI__M 0x24315#define ORX_CON_RST_W_CTI__PRE 0x04316 4317#define ORX_CON_RST_W_KRN__B 24318#define ORX_CON_RST_W_KRN__W 14319#define ORX_CON_RST_W_KRN__M 0x44320#define ORX_CON_RST_W_KRN__PRE 0x04321 4322#define ORX_CON_RST_W_KRP__B 34323#define ORX_CON_RST_W_KRP__W 14324#define ORX_CON_RST_W_KRP__M 0x84325#define ORX_CON_RST_W_KRP__PRE 0x04326 4327#define ORX_CON_CPH_PHI_R__A 0x20500124328#define ORX_CON_CPH_PHI_R__W 164329#define ORX_CON_CPH_PHI_R__M 0xFFFF4330#define ORX_CON_CPH_PHI_R__PRE 0x04331 4332#define ORX_CON_CPH_FRQ_R__A 0x20500134333#define ORX_CON_CPH_FRQ_R__W 164334#define ORX_CON_CPH_FRQ_R__M 0xFFFF4335#define ORX_CON_CPH_FRQ_R__PRE 0x04336 4337#define ORX_CON_CPH_AMP_R__A 0x20500144338#define ORX_CON_CPH_AMP_R__W 164339#define ORX_CON_CPH_AMP_R__M 0xFFFF4340#define ORX_CON_CPH_AMP_R__PRE 0x04341 4342#define ORX_CON_CPH_KDF_W__A 0x20500154343#define ORX_CON_CPH_KDF_W__W 44344#define ORX_CON_CPH_KDF_W__M 0xF4345#define ORX_CON_CPH_KDF_W__PRE 0x04346 4347#define ORX_CON_CPH_KPF_W__A 0x20500164348#define ORX_CON_CPH_KPF_W__W 44349#define ORX_CON_CPH_KPF_W__M 0xF4350#define ORX_CON_CPH_KPF_W__PRE 0x04351 4352#define ORX_CON_CPH_KIF_W__A 0x20500174353#define ORX_CON_CPH_KIF_W__W 44354#define ORX_CON_CPH_KIF_W__M 0xF4355#define ORX_CON_CPH_KIF_W__PRE 0x04356#define ORX_CON_CPH_APT_W__A 0x20500184357#define ORX_CON_CPH_APT_W__W 164358#define ORX_CON_CPH_APT_W__M 0xFFFF4359#define ORX_CON_CPH_APT_W__PRE 0x8044360 4361#define ORX_CON_CPH_APT_W_PTH__B 04362#define ORX_CON_CPH_APT_W_PTH__W 84363#define ORX_CON_CPH_APT_W_PTH__M 0xFF4364#define ORX_CON_CPH_APT_W_PTH__PRE 0x44365 4366#define ORX_CON_CPH_APT_W_ATH__B 84367#define ORX_CON_CPH_APT_W_ATH__W 84368#define ORX_CON_CPH_APT_W_ATH__M 0xFF004369#define ORX_CON_CPH_APT_W_ATH__PRE 0x8004370 4371#define ORX_CON_CPH_WLC_W__A 0x20500194372#define ORX_CON_CPH_WLC_W__W 84373#define ORX_CON_CPH_WLC_W__M 0xFF4374#define ORX_CON_CPH_WLC_W__PRE 0x814375 4376#define ORX_CON_CPH_WLC_W_LATC__B 04377#define ORX_CON_CPH_WLC_W_LATC__W 44378#define ORX_CON_CPH_WLC_W_LATC__M 0xF4379#define ORX_CON_CPH_WLC_W_LATC__PRE 0x14380 4381#define ORX_CON_CPH_WLC_W_WLIM__B 44382#define ORX_CON_CPH_WLC_W_WLIM__W 44383#define ORX_CON_CPH_WLC_W_WLIM__M 0xF04384#define ORX_CON_CPH_WLC_W_WLIM__PRE 0x804385 4386#define ORX_CON_CPH_DLY_W__A 0x205001A4387#define ORX_CON_CPH_DLY_W__W 34388#define ORX_CON_CPH_DLY_W__M 0x74389#define ORX_CON_CPH_DLY_W__PRE 0x44390 4391#define ORX_CON_CPH_TCL_W__A 0x205001B4392#define ORX_CON_CPH_TCL_W__W 34393#define ORX_CON_CPH_TCL_W__M 0x74394#define ORX_CON_CPH_TCL_W__PRE 0x34395 4396#define ORX_CON_KRP_AMP_R__A 0x205001C4397#define ORX_CON_KRP_AMP_R__W 94398#define ORX_CON_KRP_AMP_R__M 0x1FF4399#define ORX_CON_KRP_AMP_R__PRE 0x04400 4401#define ORX_CON_KRN_AMP_R__A 0x205001D4402#define ORX_CON_KRN_AMP_R__W 94403#define ORX_CON_KRN_AMP_R__M 0x1FF4404#define ORX_CON_KRN_AMP_R__PRE 0x04405 4406#define ORX_CON_CTI_DTI_R__A 0x205001E4407#define ORX_CON_CTI_DTI_R__W 164408#define ORX_CON_CTI_DTI_R__M 0xFFFF4409#define ORX_CON_CTI_DTI_R__PRE 0x04410 4411#define ORX_CON_CTI_KDT_W__A 0x205001F4412#define ORX_CON_CTI_KDT_W__W 44413#define ORX_CON_CTI_KDT_W__M 0xF4414#define ORX_CON_CTI_KDT_W__PRE 0x44415 4416#define ORX_CON_CTI_KPT_W__A 0x20500204417#define ORX_CON_CTI_KPT_W__W 44418#define ORX_CON_CTI_KPT_W__M 0xF4419#define ORX_CON_CTI_KPT_W__PRE 0x34420 4421#define ORX_CON_CTI_KIT_W__A 0x20500214422#define ORX_CON_CTI_KIT_W__W 44423#define ORX_CON_CTI_KIT_W__M 0xF4424#define ORX_CON_CTI_KIT_W__PRE 0xB4425 4426#define ORX_CON_CTI_TAT_W__A 0x20500224427#define ORX_CON_CTI_TAT_W__W 44428#define ORX_CON_CTI_TAT_W__M 0xF4429#define ORX_CON_CTI_TAT_W__PRE 0x34430 4431#define ORX_NSU_COMM_EXEC__A 0x20600004432#define ORX_NSU_COMM_EXEC__W 24433#define ORX_NSU_COMM_EXEC__M 0x34434#define ORX_NSU_COMM_EXEC__PRE 0x04435#define ORX_NSU_COMM_EXEC_STOP 0x04436#define ORX_NSU_COMM_EXEC_ACTIVE 0x14437#define ORX_NSU_COMM_EXEC_HOLD 0x24438 4439#define ORX_NSU_AOX_STDBY_W__A 0x20600104440#define ORX_NSU_AOX_STDBY_W__W 84441#define ORX_NSU_AOX_STDBY_W__M 0xFF4442#define ORX_NSU_AOX_STDBY_W__PRE 0x04443 4444#define ORX_NSU_AOX_STDBY_W_STDBYADC__B 04445#define ORX_NSU_AOX_STDBY_W_STDBYADC__W 14446#define ORX_NSU_AOX_STDBY_W_STDBYADC__M 0x14447#define ORX_NSU_AOX_STDBY_W_STDBYADC__PRE 0x04448#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_ON 0x04449#define ORX_NSU_AOX_STDBY_W_STDBYADC_A1_OFF 0x14450#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_OFF 0x04451#define ORX_NSU_AOX_STDBY_W_STDBYADC_A2_ON 0x14452 4453#define ORX_NSU_AOX_STDBY_W_STDBYAMP__B 14454#define ORX_NSU_AOX_STDBY_W_STDBYAMP__W 14455#define ORX_NSU_AOX_STDBY_W_STDBYAMP__M 0x24456#define ORX_NSU_AOX_STDBY_W_STDBYAMP__PRE 0x04457#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_ON 0x04458#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A1_OFF 0x24459#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_OFF 0x04460#define ORX_NSU_AOX_STDBY_W_STDBYAMP_A2_ON 0x24461 4462#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__B 24463#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__W 14464#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__M 0x44465#define ORX_NSU_AOX_STDBY_W_STDBYBIAS__PRE 0x04466#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_ON 0x04467#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A1_OFF 0x44468#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_OFF 0x04469#define ORX_NSU_AOX_STDBY_W_STDBYBIAS_A2_ON 0x44470 4471#define ORX_NSU_AOX_STDBY_W_STDBYPLL__B 34472#define ORX_NSU_AOX_STDBY_W_STDBYPLL__W 14473#define ORX_NSU_AOX_STDBY_W_STDBYPLL__M 0x84474#define ORX_NSU_AOX_STDBY_W_STDBYPLL__PRE 0x04475#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_ON 0x04476#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A1_OFF 0x84477#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_OFF 0x04478#define ORX_NSU_AOX_STDBY_W_STDBYPLL_A2_ON 0x84479 4480#define ORX_NSU_AOX_STDBY_W_STDBYPD__B 44481#define ORX_NSU_AOX_STDBY_W_STDBYPD__W 14482#define ORX_NSU_AOX_STDBY_W_STDBYPD__M 0x104483#define ORX_NSU_AOX_STDBY_W_STDBYPD__PRE 0x04484#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_ON 0x04485#define ORX_NSU_AOX_STDBY_W_STDBYPD_A1_OFF 0x104486#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_OFF 0x04487#define ORX_NSU_AOX_STDBY_W_STDBYPD_A2_ON 0x104488 4489#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__B 54490#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__W 14491#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__M 0x204492#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF__PRE 0x04493#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_ON 0x04494#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A1_OFF 0x204495#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_OFF 0x04496#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_IF_A2_ON 0x204497 4498#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__B 64499#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__W 14500#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__M 0x404501#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF__PRE 0x04502#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_ON 0x04503#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A1_OFF 0x404504#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_OFF 0x04505#define ORX_NSU_AOX_STDBY_W_STDBYTAGC_RF_A2_ON 0x404506 4507#define ORX_NSU_AOX_STDBY_W_STDBYFLT__B 74508#define ORX_NSU_AOX_STDBY_W_STDBYFLT__W 14509#define ORX_NSU_AOX_STDBY_W_STDBYFLT__M 0x804510#define ORX_NSU_AOX_STDBY_W_STDBYFLT__PRE 0x04511#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_ON 0x04512#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A1_OFF 0x804513#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_OFF 0x04514#define ORX_NSU_AOX_STDBY_W_STDBYFLT_A2_ON 0x804515 4516#define ORX_NSU_AOX_LOFRQ_W__A 0x20600114517#define ORX_NSU_AOX_LOFRQ_W__W 164518#define ORX_NSU_AOX_LOFRQ_W__M 0xFFFF4519#define ORX_NSU_AOX_LOFRQ_W__PRE 0x04520#define ORX_NSU_AOX_LOMDE_W__A 0x20600124521#define ORX_NSU_AOX_LOMDE_W__W 164522#define ORX_NSU_AOX_LOMDE_W__M 0xFFFF4523#define ORX_NSU_AOX_LOMDE_W__PRE 0x04524 4525#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__B 04526#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__W 84527#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__M 0xFF4528#define ORX_NSU_AOX_LOMDE_W_AOX_LOFRQ_EXT__PRE 0x04529 4530#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__B 134531#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__W 14532#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__M 0x20004533#define ORX_NSU_AOX_LOMDE_W_RESET_VCO__PRE 0x04534 4535#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__B 144536#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__W 24537#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__M 0xC0004538#define ORX_NSU_AOX_LOMDE_W_PLL_DIV__PRE 0x04539 4540#define ORX_NSU_AOX_LOPOW_W__A 0x20600134541#define ORX_NSU_AOX_LOPOW_W__W 24542#define ORX_NSU_AOX_LOPOW_W__M 0x34543#define ORX_NSU_AOX_LOPOW_W__PRE 0x04544#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS0DB 0x04545#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS5DB 0x14546#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS10DB 0x24547#define ORX_NSU_AOX_LOPOW_W_POWER_MINUS15DB 0x34548 4549#define ORX_NSU_AOX_STHR_W__A 0x20600144550#define ORX_NSU_AOX_STHR_W__W 54551#define ORX_NSU_AOX_STHR_W__M 0x1F4552#define ORX_NSU_AOX_STHR_W__PRE 0x04553 4554#define ORX_NSU_TUN_RFGAIN_W__A 0x20600154555#define ORX_NSU_TUN_RFGAIN_W__W 154556#define ORX_NSU_TUN_RFGAIN_W__M 0x7FFF4557#define ORX_NSU_TUN_RFGAIN_W__PRE 0x04558 4559#define ORX_NSU_TUN_IFGAIN_W__A 0x20600164560#define ORX_NSU_TUN_IFGAIN_W__W 154561#define ORX_NSU_TUN_IFGAIN_W__M 0x7FFF4562#define ORX_NSU_TUN_IFGAIN_W__PRE 0x04563 4564#define ORX_NSU_TUN_BPF_W__A 0x20600174565#define ORX_NSU_TUN_BPF_W__W 154566#define ORX_NSU_TUN_BPF_W__M 0x7FFF4567#define ORX_NSU_TUN_BPF_W__PRE 0x1F94568#define ORX_NSU_NSS_BITSWAP_W__A 0x20600184569#define ORX_NSU_NSS_BITSWAP_W__W 34570#define ORX_NSU_NSS_BITSWAP_W__M 0x74571#define ORX_NSU_NSS_BITSWAP_W__PRE 0x04572 4573#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__B 04574#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__W 14575#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__M 0x14576#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS0_RF__PRE 0x04577 4578#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__B 14579#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__W 14580#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__M 0x24581#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS1_IF__PRE 0x04582 4583#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__B 24584#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__W 14585#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__M 0x44586#define ORX_NSU_NSS_BITSWAP_W_BITSWAP_NS2_BP__PRE 0x04587 4588#define ORX_TST_COMM_EXEC__A 0x23F00004589#define ORX_TST_COMM_EXEC__W 24590#define ORX_TST_COMM_EXEC__M 0x34591#define ORX_TST_COMM_EXEC__PRE 0x04592#define ORX_TST_COMM_EXEC_STOP 0x04593#define ORX_TST_COMM_EXEC_ACTIVE 0x14594#define ORX_TST_COMM_EXEC_HOLD 0x24595 4596#define ORX_TST_AOX_TST_W__A 0x23F00104597#define ORX_TST_AOX_TST_W__W 84598#define ORX_TST_AOX_TST_W__M 0xFF4599#define ORX_TST_AOX_TST_W__PRE 0x04600 4601#define QAM_COMM_EXEC__A 0x14000004602#define QAM_COMM_EXEC__W 24603#define QAM_COMM_EXEC__M 0x34604#define QAM_COMM_EXEC__PRE 0x04605#define QAM_COMM_EXEC_STOP 0x04606#define QAM_COMM_EXEC_ACTIVE 0x14607#define QAM_COMM_EXEC_HOLD 0x24608 4609#define QAM_COMM_MB__A 0x14000024610#define QAM_COMM_MB__W 164611#define QAM_COMM_MB__M 0xFFFF4612#define QAM_COMM_MB__PRE 0x04613#define QAM_COMM_INT_REQ__A 0x14000034614#define QAM_COMM_INT_REQ__W 164615#define QAM_COMM_INT_REQ__M 0xFFFF4616#define QAM_COMM_INT_REQ__PRE 0x04617 4618#define QAM_COMM_INT_REQ_SL_REQ__B 04619#define QAM_COMM_INT_REQ_SL_REQ__W 14620#define QAM_COMM_INT_REQ_SL_REQ__M 0x14621#define QAM_COMM_INT_REQ_SL_REQ__PRE 0x04622 4623#define QAM_COMM_INT_REQ_LC_REQ__B 14624#define QAM_COMM_INT_REQ_LC_REQ__W 14625#define QAM_COMM_INT_REQ_LC_REQ__M 0x24626#define QAM_COMM_INT_REQ_LC_REQ__PRE 0x04627 4628#define QAM_COMM_INT_REQ_VD_REQ__B 24629#define QAM_COMM_INT_REQ_VD_REQ__W 14630#define QAM_COMM_INT_REQ_VD_REQ__M 0x44631#define QAM_COMM_INT_REQ_VD_REQ__PRE 0x04632 4633#define QAM_COMM_INT_REQ_SY_REQ__B 34634#define QAM_COMM_INT_REQ_SY_REQ__W 14635#define QAM_COMM_INT_REQ_SY_REQ__M 0x84636#define QAM_COMM_INT_REQ_SY_REQ__PRE 0x04637 4638#define QAM_COMM_INT_STA__A 0x14000054639#define QAM_COMM_INT_STA__W 164640#define QAM_COMM_INT_STA__M 0xFFFF4641#define QAM_COMM_INT_STA__PRE 0x04642#define QAM_COMM_INT_MSK__A 0x14000064643#define QAM_COMM_INT_MSK__W 164644#define QAM_COMM_INT_MSK__M 0xFFFF4645#define QAM_COMM_INT_MSK__PRE 0x04646#define QAM_COMM_INT_STM__A 0x14000074647#define QAM_COMM_INT_STM__W 164648#define QAM_COMM_INT_STM__M 0xFFFF4649#define QAM_COMM_INT_STM__PRE 0x04650 4651#define QAM_TOP_COMM_EXEC__A 0x14100004652#define QAM_TOP_COMM_EXEC__W 24653#define QAM_TOP_COMM_EXEC__M 0x34654#define QAM_TOP_COMM_EXEC__PRE 0x04655#define QAM_TOP_COMM_EXEC_STOP 0x04656#define QAM_TOP_COMM_EXEC_ACTIVE 0x14657#define QAM_TOP_COMM_EXEC_HOLD 0x24658 4659#define QAM_TOP_ANNEX__A 0x14100104660#define QAM_TOP_ANNEX__W 24661#define QAM_TOP_ANNEX__M 0x34662#define QAM_TOP_ANNEX__PRE 0x14663#define QAM_TOP_ANNEX_A 0x04664#define QAM_TOP_ANNEX_B 0x14665#define QAM_TOP_ANNEX_C 0x24666#define QAM_TOP_ANNEX_D 0x34667 4668#define QAM_TOP_CONSTELLATION__A 0x14100114669#define QAM_TOP_CONSTELLATION__W 34670#define QAM_TOP_CONSTELLATION__M 0x74671#define QAM_TOP_CONSTELLATION__PRE 0x54672#define QAM_TOP_CONSTELLATION_NONE 0x04673#define QAM_TOP_CONSTELLATION_QPSK 0x14674#define QAM_TOP_CONSTELLATION_QAM8 0x24675#define QAM_TOP_CONSTELLATION_QAM16 0x34676#define QAM_TOP_CONSTELLATION_QAM32 0x44677#define QAM_TOP_CONSTELLATION_QAM64 0x54678#define QAM_TOP_CONSTELLATION_QAM128 0x64679#define QAM_TOP_CONSTELLATION_QAM256 0x74680 4681#define QAM_FQ_COMM_EXEC__A 0x14200004682#define QAM_FQ_COMM_EXEC__W 24683#define QAM_FQ_COMM_EXEC__M 0x34684#define QAM_FQ_COMM_EXEC__PRE 0x04685#define QAM_FQ_COMM_EXEC_STOP 0x04686#define QAM_FQ_COMM_EXEC_ACTIVE 0x14687#define QAM_FQ_COMM_EXEC_HOLD 0x24688 4689#define QAM_FQ_MODE__A 0x14200104690#define QAM_FQ_MODE__W 34691#define QAM_FQ_MODE__M 0x74692#define QAM_FQ_MODE__PRE 0x04693 4694#define QAM_FQ_MODE_TAPRESET__B 04695#define QAM_FQ_MODE_TAPRESET__W 14696#define QAM_FQ_MODE_TAPRESET__M 0x14697#define QAM_FQ_MODE_TAPRESET__PRE 0x04698#define QAM_FQ_MODE_TAPRESET_RST 0x14699 4700#define QAM_FQ_MODE_TAPLMS__B 14701#define QAM_FQ_MODE_TAPLMS__W 14702#define QAM_FQ_MODE_TAPLMS__M 0x24703#define QAM_FQ_MODE_TAPLMS__PRE 0x04704#define QAM_FQ_MODE_TAPLMS_UPD 0x24705 4706#define QAM_FQ_MODE_TAPDRAIN__B 24707#define QAM_FQ_MODE_TAPDRAIN__W 14708#define QAM_FQ_MODE_TAPDRAIN__M 0x44709#define QAM_FQ_MODE_TAPDRAIN__PRE 0x04710#define QAM_FQ_MODE_TAPDRAIN_DRAIN 0x44711 4712#define QAM_FQ_MU_FACTOR__A 0x14200114713#define QAM_FQ_MU_FACTOR__W 34714#define QAM_FQ_MU_FACTOR__M 0x74715#define QAM_FQ_MU_FACTOR__PRE 0x04716 4717#define QAM_FQ_LA_FACTOR__A 0x14200124718#define QAM_FQ_LA_FACTOR__W 44719#define QAM_FQ_LA_FACTOR__M 0xF4720#define QAM_FQ_LA_FACTOR__PRE 0xC4721#define QAM_FQ_CENTTAP_IDX__A 0x14200164722#define QAM_FQ_CENTTAP_IDX__W 54723#define QAM_FQ_CENTTAP_IDX__M 0x1F4724#define QAM_FQ_CENTTAP_IDX__PRE 0x134725 4726#define QAM_FQ_CENTTAP_IDX_IDX__B 04727#define QAM_FQ_CENTTAP_IDX_IDX__W 54728#define QAM_FQ_CENTTAP_IDX_IDX__M 0x1F4729#define QAM_FQ_CENTTAP_IDX_IDX__PRE 0x134730 4731#define QAM_FQ_CENTTAP_VALUE__A 0x14200174732#define QAM_FQ_CENTTAP_VALUE__W 124733#define QAM_FQ_CENTTAP_VALUE__M 0xFFF4734#define QAM_FQ_CENTTAP_VALUE__PRE 0x6004735 4736#define QAM_FQ_CENTTAP_VALUE_TAP__B 04737#define QAM_FQ_CENTTAP_VALUE_TAP__W 124738#define QAM_FQ_CENTTAP_VALUE_TAP__M 0xFFF4739#define QAM_FQ_CENTTAP_VALUE_TAP__PRE 0x6004740 4741#define QAM_FQ_TAP_RE_EL0__A 0x14200204742#define QAM_FQ_TAP_RE_EL0__W 124743#define QAM_FQ_TAP_RE_EL0__M 0xFFF4744#define QAM_FQ_TAP_RE_EL0__PRE 0x24745 4746#define QAM_FQ_TAP_RE_EL0_TAP__B 04747#define QAM_FQ_TAP_RE_EL0_TAP__W 124748#define QAM_FQ_TAP_RE_EL0_TAP__M 0xFFF4749#define QAM_FQ_TAP_RE_EL0_TAP__PRE 0x24750 4751#define QAM_FQ_TAP_IM_EL0__A 0x14200214752#define QAM_FQ_TAP_IM_EL0__W 124753#define QAM_FQ_TAP_IM_EL0__M 0xFFF4754#define QAM_FQ_TAP_IM_EL0__PRE 0x24755 4756#define QAM_FQ_TAP_IM_EL0_TAP__B 04757#define QAM_FQ_TAP_IM_EL0_TAP__W 124758#define QAM_FQ_TAP_IM_EL0_TAP__M 0xFFF4759#define QAM_FQ_TAP_IM_EL0_TAP__PRE 0x24760 4761#define QAM_FQ_TAP_RE_EL1__A 0x14200224762#define QAM_FQ_TAP_RE_EL1__W 124763#define QAM_FQ_TAP_RE_EL1__M 0xFFF4764#define QAM_FQ_TAP_RE_EL1__PRE 0x24765 4766#define QAM_FQ_TAP_RE_EL1_TAP__B 04767#define QAM_FQ_TAP_RE_EL1_TAP__W 124768#define QAM_FQ_TAP_RE_EL1_TAP__M 0xFFF4769#define QAM_FQ_TAP_RE_EL1_TAP__PRE 0x24770 4771#define QAM_FQ_TAP_IM_EL1__A 0x14200234772#define QAM_FQ_TAP_IM_EL1__W 124773#define QAM_FQ_TAP_IM_EL1__M 0xFFF4774#define QAM_FQ_TAP_IM_EL1__PRE 0x24775 4776#define QAM_FQ_TAP_IM_EL1_TAP__B 04777#define QAM_FQ_TAP_IM_EL1_TAP__W 124778#define QAM_FQ_TAP_IM_EL1_TAP__M 0xFFF4779#define QAM_FQ_TAP_IM_EL1_TAP__PRE 0x24780 4781#define QAM_FQ_TAP_RE_EL2__A 0x14200244782#define QAM_FQ_TAP_RE_EL2__W 124783#define QAM_FQ_TAP_RE_EL2__M 0xFFF4784#define QAM_FQ_TAP_RE_EL2__PRE 0x24785 4786#define QAM_FQ_TAP_RE_EL2_TAP__B 04787#define QAM_FQ_TAP_RE_EL2_TAP__W 124788#define QAM_FQ_TAP_RE_EL2_TAP__M 0xFFF4789#define QAM_FQ_TAP_RE_EL2_TAP__PRE 0x24790 4791#define QAM_FQ_TAP_IM_EL2__A 0x14200254792#define QAM_FQ_TAP_IM_EL2__W 124793#define QAM_FQ_TAP_IM_EL2__M 0xFFF4794#define QAM_FQ_TAP_IM_EL2__PRE 0x24795 4796#define QAM_FQ_TAP_IM_EL2_TAP__B 04797#define QAM_FQ_TAP_IM_EL2_TAP__W 124798#define QAM_FQ_TAP_IM_EL2_TAP__M 0xFFF4799#define QAM_FQ_TAP_IM_EL2_TAP__PRE 0x24800 4801#define QAM_FQ_TAP_RE_EL3__A 0x14200264802#define QAM_FQ_TAP_RE_EL3__W 124803#define QAM_FQ_TAP_RE_EL3__M 0xFFF4804#define QAM_FQ_TAP_RE_EL3__PRE 0x24805 4806#define QAM_FQ_TAP_RE_EL3_TAP__B 04807#define QAM_FQ_TAP_RE_EL3_TAP__W 124808#define QAM_FQ_TAP_RE_EL3_TAP__M 0xFFF4809#define QAM_FQ_TAP_RE_EL3_TAP__PRE 0x24810 4811#define QAM_FQ_TAP_IM_EL3__A 0x14200274812#define QAM_FQ_TAP_IM_EL3__W 124813#define QAM_FQ_TAP_IM_EL3__M 0xFFF4814#define QAM_FQ_TAP_IM_EL3__PRE 0x24815 4816#define QAM_FQ_TAP_IM_EL3_TAP__B 04817#define QAM_FQ_TAP_IM_EL3_TAP__W 124818#define QAM_FQ_TAP_IM_EL3_TAP__M 0xFFF4819#define QAM_FQ_TAP_IM_EL3_TAP__PRE 0x24820 4821#define QAM_FQ_TAP_RE_EL4__A 0x14200284822#define QAM_FQ_TAP_RE_EL4__W 124823#define QAM_FQ_TAP_RE_EL4__M 0xFFF4824#define QAM_FQ_TAP_RE_EL4__PRE 0x24825 4826#define QAM_FQ_TAP_RE_EL4_TAP__B 04827#define QAM_FQ_TAP_RE_EL4_TAP__W 124828#define QAM_FQ_TAP_RE_EL4_TAP__M 0xFFF4829#define QAM_FQ_TAP_RE_EL4_TAP__PRE 0x24830 4831#define QAM_FQ_TAP_IM_EL4__A 0x14200294832#define QAM_FQ_TAP_IM_EL4__W 124833#define QAM_FQ_TAP_IM_EL4__M 0xFFF4834#define QAM_FQ_TAP_IM_EL4__PRE 0x24835 4836#define QAM_FQ_TAP_IM_EL4_TAP__B 04837#define QAM_FQ_TAP_IM_EL4_TAP__W 124838#define QAM_FQ_TAP_IM_EL4_TAP__M 0xFFF4839#define QAM_FQ_TAP_IM_EL4_TAP__PRE 0x24840 4841#define QAM_FQ_TAP_RE_EL5__A 0x142002A4842#define QAM_FQ_TAP_RE_EL5__W 124843#define QAM_FQ_TAP_RE_EL5__M 0xFFF4844#define QAM_FQ_TAP_RE_EL5__PRE 0x24845 4846#define QAM_FQ_TAP_RE_EL5_TAP__B 04847#define QAM_FQ_TAP_RE_EL5_TAP__W 124848#define QAM_FQ_TAP_RE_EL5_TAP__M 0xFFF4849#define QAM_FQ_TAP_RE_EL5_TAP__PRE 0x24850 4851#define QAM_FQ_TAP_IM_EL5__A 0x142002B4852#define QAM_FQ_TAP_IM_EL5__W 124853#define QAM_FQ_TAP_IM_EL5__M 0xFFF4854#define QAM_FQ_TAP_IM_EL5__PRE 0x24855 4856#define QAM_FQ_TAP_IM_EL5_TAP__B 04857#define QAM_FQ_TAP_IM_EL5_TAP__W 124858#define QAM_FQ_TAP_IM_EL5_TAP__M 0xFFF4859#define QAM_FQ_TAP_IM_EL5_TAP__PRE 0x24860 4861#define QAM_FQ_TAP_RE_EL6__A 0x142002C4862#define QAM_FQ_TAP_RE_EL6__W 124863#define QAM_FQ_TAP_RE_EL6__M 0xFFF4864#define QAM_FQ_TAP_RE_EL6__PRE 0x24865 4866#define QAM_FQ_TAP_RE_EL6_TAP__B 04867#define QAM_FQ_TAP_RE_EL6_TAP__W 124868#define QAM_FQ_TAP_RE_EL6_TAP__M 0xFFF4869#define QAM_FQ_TAP_RE_EL6_TAP__PRE 0x24870 4871#define QAM_FQ_TAP_IM_EL6__A 0x142002D4872#define QAM_FQ_TAP_IM_EL6__W 124873#define QAM_FQ_TAP_IM_EL6__M 0xFFF4874#define QAM_FQ_TAP_IM_EL6__PRE 0x24875 4876#define QAM_FQ_TAP_IM_EL6_TAP__B 04877#define QAM_FQ_TAP_IM_EL6_TAP__W 124878#define QAM_FQ_TAP_IM_EL6_TAP__M 0xFFF4879#define QAM_FQ_TAP_IM_EL6_TAP__PRE 0x24880 4881#define QAM_FQ_TAP_RE_EL7__A 0x142002E4882#define QAM_FQ_TAP_RE_EL7__W 124883#define QAM_FQ_TAP_RE_EL7__M 0xFFF4884#define QAM_FQ_TAP_RE_EL7__PRE 0x24885 4886#define QAM_FQ_TAP_RE_EL7_TAP__B 04887#define QAM_FQ_TAP_RE_EL7_TAP__W 124888#define QAM_FQ_TAP_RE_EL7_TAP__M 0xFFF4889#define QAM_FQ_TAP_RE_EL7_TAP__PRE 0x24890 4891#define QAM_FQ_TAP_IM_EL7__A 0x142002F4892#define QAM_FQ_TAP_IM_EL7__W 124893#define QAM_FQ_TAP_IM_EL7__M 0xFFF4894#define QAM_FQ_TAP_IM_EL7__PRE 0x24895 4896#define QAM_FQ_TAP_IM_EL7_TAP__B 04897#define QAM_FQ_TAP_IM_EL7_TAP__W 124898#define QAM_FQ_TAP_IM_EL7_TAP__M 0xFFF4899#define QAM_FQ_TAP_IM_EL7_TAP__PRE 0x24900 4901#define QAM_FQ_TAP_RE_EL8__A 0x14200304902#define QAM_FQ_TAP_RE_EL8__W 124903#define QAM_FQ_TAP_RE_EL8__M 0xFFF4904#define QAM_FQ_TAP_RE_EL8__PRE 0x24905 4906#define QAM_FQ_TAP_RE_EL8_TAP__B 04907#define QAM_FQ_TAP_RE_EL8_TAP__W 124908#define QAM_FQ_TAP_RE_EL8_TAP__M 0xFFF4909#define QAM_FQ_TAP_RE_EL8_TAP__PRE 0x24910 4911#define QAM_FQ_TAP_IM_EL8__A 0x14200314912#define QAM_FQ_TAP_IM_EL8__W 124913#define QAM_FQ_TAP_IM_EL8__M 0xFFF4914#define QAM_FQ_TAP_IM_EL8__PRE 0x24915 4916#define QAM_FQ_TAP_IM_EL8_TAP__B 04917#define QAM_FQ_TAP_IM_EL8_TAP__W 124918#define QAM_FQ_TAP_IM_EL8_TAP__M 0xFFF4919#define QAM_FQ_TAP_IM_EL8_TAP__PRE 0x24920 4921#define QAM_FQ_TAP_RE_EL9__A 0x14200324922#define QAM_FQ_TAP_RE_EL9__W 124923#define QAM_FQ_TAP_RE_EL9__M 0xFFF4924#define QAM_FQ_TAP_RE_EL9__PRE 0x24925 4926#define QAM_FQ_TAP_RE_EL9_TAP__B 04927#define QAM_FQ_TAP_RE_EL9_TAP__W 124928#define QAM_FQ_TAP_RE_EL9_TAP__M 0xFFF4929#define QAM_FQ_TAP_RE_EL9_TAP__PRE 0x24930 4931#define QAM_FQ_TAP_IM_EL9__A 0x14200334932#define QAM_FQ_TAP_IM_EL9__W 124933#define QAM_FQ_TAP_IM_EL9__M 0xFFF4934#define QAM_FQ_TAP_IM_EL9__PRE 0x24935 4936#define QAM_FQ_TAP_IM_EL9_TAP__B 04937#define QAM_FQ_TAP_IM_EL9_TAP__W 124938#define QAM_FQ_TAP_IM_EL9_TAP__M 0xFFF4939#define QAM_FQ_TAP_IM_EL9_TAP__PRE 0x24940 4941#define QAM_FQ_TAP_RE_EL10__A 0x14200344942#define QAM_FQ_TAP_RE_EL10__W 124943#define QAM_FQ_TAP_RE_EL10__M 0xFFF4944#define QAM_FQ_TAP_RE_EL10__PRE 0x24945 4946#define QAM_FQ_TAP_RE_EL10_TAP__B 04947#define QAM_FQ_TAP_RE_EL10_TAP__W 124948#define QAM_FQ_TAP_RE_EL10_TAP__M 0xFFF4949#define QAM_FQ_TAP_RE_EL10_TAP__PRE 0x24950 4951#define QAM_FQ_TAP_IM_EL10__A 0x14200354952#define QAM_FQ_TAP_IM_EL10__W 124953#define QAM_FQ_TAP_IM_EL10__M 0xFFF4954#define QAM_FQ_TAP_IM_EL10__PRE 0x24955 4956#define QAM_FQ_TAP_IM_EL10_TAP__B 04957#define QAM_FQ_TAP_IM_EL10_TAP__W 124958#define QAM_FQ_TAP_IM_EL10_TAP__M 0xFFF4959#define QAM_FQ_TAP_IM_EL10_TAP__PRE 0x24960 4961#define QAM_FQ_TAP_RE_EL11__A 0x14200364962#define QAM_FQ_TAP_RE_EL11__W 124963#define QAM_FQ_TAP_RE_EL11__M 0xFFF4964#define QAM_FQ_TAP_RE_EL11__PRE 0x24965 4966#define QAM_FQ_TAP_RE_EL11_TAP__B 04967#define QAM_FQ_TAP_RE_EL11_TAP__W 124968#define QAM_FQ_TAP_RE_EL11_TAP__M 0xFFF4969#define QAM_FQ_TAP_RE_EL11_TAP__PRE 0x24970 4971#define QAM_FQ_TAP_IM_EL11__A 0x14200374972#define QAM_FQ_TAP_IM_EL11__W 124973#define QAM_FQ_TAP_IM_EL11__M 0xFFF4974#define QAM_FQ_TAP_IM_EL11__PRE 0x24975 4976#define QAM_FQ_TAP_IM_EL11_TAP__B 04977#define QAM_FQ_TAP_IM_EL11_TAP__W 124978#define QAM_FQ_TAP_IM_EL11_TAP__M 0xFFF4979#define QAM_FQ_TAP_IM_EL11_TAP__PRE 0x24980 4981#define QAM_FQ_TAP_RE_EL12__A 0x14200384982#define QAM_FQ_TAP_RE_EL12__W 124983#define QAM_FQ_TAP_RE_EL12__M 0xFFF4984#define QAM_FQ_TAP_RE_EL12__PRE 0x24985 4986#define QAM_FQ_TAP_RE_EL12_TAP__B 04987#define QAM_FQ_TAP_RE_EL12_TAP__W 124988#define QAM_FQ_TAP_RE_EL12_TAP__M 0xFFF4989#define QAM_FQ_TAP_RE_EL12_TAP__PRE 0x24990 4991#define QAM_FQ_TAP_IM_EL12__A 0x14200394992#define QAM_FQ_TAP_IM_EL12__W 124993#define QAM_FQ_TAP_IM_EL12__M 0xFFF4994#define QAM_FQ_TAP_IM_EL12__PRE 0x24995 4996#define QAM_FQ_TAP_IM_EL12_TAP__B 04997#define QAM_FQ_TAP_IM_EL12_TAP__W 124998#define QAM_FQ_TAP_IM_EL12_TAP__M 0xFFF4999#define QAM_FQ_TAP_IM_EL12_TAP__PRE 0x25000 5001#define QAM_FQ_TAP_RE_EL13__A 0x142003A5002#define QAM_FQ_TAP_RE_EL13__W 125003#define QAM_FQ_TAP_RE_EL13__M 0xFFF5004#define QAM_FQ_TAP_RE_EL13__PRE 0x25005 5006#define QAM_FQ_TAP_RE_EL13_TAP__B 05007#define QAM_FQ_TAP_RE_EL13_TAP__W 125008#define QAM_FQ_TAP_RE_EL13_TAP__M 0xFFF5009#define QAM_FQ_TAP_RE_EL13_TAP__PRE 0x25010 5011#define QAM_FQ_TAP_IM_EL13__A 0x142003B5012#define QAM_FQ_TAP_IM_EL13__W 125013#define QAM_FQ_TAP_IM_EL13__M 0xFFF5014#define QAM_FQ_TAP_IM_EL13__PRE 0x25015 5016#define QAM_FQ_TAP_IM_EL13_TAP__B 05017#define QAM_FQ_TAP_IM_EL13_TAP__W 125018#define QAM_FQ_TAP_IM_EL13_TAP__M 0xFFF5019#define QAM_FQ_TAP_IM_EL13_TAP__PRE 0x25020 5021#define QAM_FQ_TAP_RE_EL14__A 0x142003C5022#define QAM_FQ_TAP_RE_EL14__W 125023#define QAM_FQ_TAP_RE_EL14__M 0xFFF5024#define QAM_FQ_TAP_RE_EL14__PRE 0x25025 5026#define QAM_FQ_TAP_RE_EL14_TAP__B 05027#define QAM_FQ_TAP_RE_EL14_TAP__W 125028#define QAM_FQ_TAP_RE_EL14_TAP__M 0xFFF5029#define QAM_FQ_TAP_RE_EL14_TAP__PRE 0x25030 5031#define QAM_FQ_TAP_IM_EL14__A 0x142003D5032#define QAM_FQ_TAP_IM_EL14__W 125033#define QAM_FQ_TAP_IM_EL14__M 0xFFF5034#define QAM_FQ_TAP_IM_EL14__PRE 0x25035 5036#define QAM_FQ_TAP_IM_EL14_TAP__B 05037#define QAM_FQ_TAP_IM_EL14_TAP__W 125038#define QAM_FQ_TAP_IM_EL14_TAP__M 0xFFF5039#define QAM_FQ_TAP_IM_EL14_TAP__PRE 0x25040 5041#define QAM_FQ_TAP_RE_EL15__A 0x142003E5042#define QAM_FQ_TAP_RE_EL15__W 125043#define QAM_FQ_TAP_RE_EL15__M 0xFFF5044#define QAM_FQ_TAP_RE_EL15__PRE 0x25045 5046#define QAM_FQ_TAP_RE_EL15_TAP__B 05047#define QAM_FQ_TAP_RE_EL15_TAP__W 125048#define QAM_FQ_TAP_RE_EL15_TAP__M 0xFFF5049#define QAM_FQ_TAP_RE_EL15_TAP__PRE 0x25050 5051#define QAM_FQ_TAP_IM_EL15__A 0x142003F5052#define QAM_FQ_TAP_IM_EL15__W 125053#define QAM_FQ_TAP_IM_EL15__M 0xFFF5054#define QAM_FQ_TAP_IM_EL15__PRE 0x25055 5056#define QAM_FQ_TAP_IM_EL15_TAP__B 05057#define QAM_FQ_TAP_IM_EL15_TAP__W 125058#define QAM_FQ_TAP_IM_EL15_TAP__M 0xFFF5059#define QAM_FQ_TAP_IM_EL15_TAP__PRE 0x25060 5061#define QAM_FQ_TAP_RE_EL16__A 0x14200405062#define QAM_FQ_TAP_RE_EL16__W 125063#define QAM_FQ_TAP_RE_EL16__M 0xFFF5064#define QAM_FQ_TAP_RE_EL16__PRE 0x25065 5066#define QAM_FQ_TAP_RE_EL16_TAP__B 05067#define QAM_FQ_TAP_RE_EL16_TAP__W 125068#define QAM_FQ_TAP_RE_EL16_TAP__M 0xFFF5069#define QAM_FQ_TAP_RE_EL16_TAP__PRE 0x25070 5071#define QAM_FQ_TAP_IM_EL16__A 0x14200415072#define QAM_FQ_TAP_IM_EL16__W 125073#define QAM_FQ_TAP_IM_EL16__M 0xFFF5074#define QAM_FQ_TAP_IM_EL16__PRE 0x25075 5076#define QAM_FQ_TAP_IM_EL16_TAP__B 05077#define QAM_FQ_TAP_IM_EL16_TAP__W 125078#define QAM_FQ_TAP_IM_EL16_TAP__M 0xFFF5079#define QAM_FQ_TAP_IM_EL16_TAP__PRE 0x25080 5081#define QAM_FQ_TAP_RE_EL17__A 0x14200425082#define QAM_FQ_TAP_RE_EL17__W 125083#define QAM_FQ_TAP_RE_EL17__M 0xFFF5084#define QAM_FQ_TAP_RE_EL17__PRE 0x25085 5086#define QAM_FQ_TAP_RE_EL17_TAP__B 05087#define QAM_FQ_TAP_RE_EL17_TAP__W 125088#define QAM_FQ_TAP_RE_EL17_TAP__M 0xFFF5089#define QAM_FQ_TAP_RE_EL17_TAP__PRE 0x25090 5091#define QAM_FQ_TAP_IM_EL17__A 0x14200435092#define QAM_FQ_TAP_IM_EL17__W 125093#define QAM_FQ_TAP_IM_EL17__M 0xFFF5094#define QAM_FQ_TAP_IM_EL17__PRE 0x25095 5096#define QAM_FQ_TAP_IM_EL17_TAP__B 05097#define QAM_FQ_TAP_IM_EL17_TAP__W 125098#define QAM_FQ_TAP_IM_EL17_TAP__M 0xFFF5099#define QAM_FQ_TAP_IM_EL17_TAP__PRE 0x25100 5101#define QAM_FQ_TAP_RE_EL18__A 0x14200445102#define QAM_FQ_TAP_RE_EL18__W 125103#define QAM_FQ_TAP_RE_EL18__M 0xFFF5104#define QAM_FQ_TAP_RE_EL18__PRE 0x25105 5106#define QAM_FQ_TAP_RE_EL18_TAP__B 05107#define QAM_FQ_TAP_RE_EL18_TAP__W 125108#define QAM_FQ_TAP_RE_EL18_TAP__M 0xFFF5109#define QAM_FQ_TAP_RE_EL18_TAP__PRE 0x25110 5111#define QAM_FQ_TAP_IM_EL18__A 0x14200455112#define QAM_FQ_TAP_IM_EL18__W 125113#define QAM_FQ_TAP_IM_EL18__M 0xFFF5114#define QAM_FQ_TAP_IM_EL18__PRE 0x25115 5116#define QAM_FQ_TAP_IM_EL18_TAP__B 05117#define QAM_FQ_TAP_IM_EL18_TAP__W 125118#define QAM_FQ_TAP_IM_EL18_TAP__M 0xFFF5119#define QAM_FQ_TAP_IM_EL18_TAP__PRE 0x25120 5121#define QAM_FQ_TAP_RE_EL19__A 0x14200465122#define QAM_FQ_TAP_RE_EL19__W 125123#define QAM_FQ_TAP_RE_EL19__M 0xFFF5124#define QAM_FQ_TAP_RE_EL19__PRE 0x6005125 5126#define QAM_FQ_TAP_RE_EL19_TAP__B 05127#define QAM_FQ_TAP_RE_EL19_TAP__W 125128#define QAM_FQ_TAP_RE_EL19_TAP__M 0xFFF5129#define QAM_FQ_TAP_RE_EL19_TAP__PRE 0x6005130 5131#define QAM_FQ_TAP_IM_EL19__A 0x14200475132#define QAM_FQ_TAP_IM_EL19__W 125133#define QAM_FQ_TAP_IM_EL19__M 0xFFF5134#define QAM_FQ_TAP_IM_EL19__PRE 0x25135 5136#define QAM_FQ_TAP_IM_EL19_TAP__B 05137#define QAM_FQ_TAP_IM_EL19_TAP__W 125138#define QAM_FQ_TAP_IM_EL19_TAP__M 0xFFF5139#define QAM_FQ_TAP_IM_EL19_TAP__PRE 0x25140 5141#define QAM_FQ_TAP_RE_EL20__A 0x14200485142#define QAM_FQ_TAP_RE_EL20__W 125143#define QAM_FQ_TAP_RE_EL20__M 0xFFF5144#define QAM_FQ_TAP_RE_EL20__PRE 0x25145 5146#define QAM_FQ_TAP_RE_EL20_TAP__B 05147#define QAM_FQ_TAP_RE_EL20_TAP__W 125148#define QAM_FQ_TAP_RE_EL20_TAP__M 0xFFF5149#define QAM_FQ_TAP_RE_EL20_TAP__PRE 0x25150 5151#define QAM_FQ_TAP_IM_EL20__A 0x14200495152#define QAM_FQ_TAP_IM_EL20__W 125153#define QAM_FQ_TAP_IM_EL20__M 0xFFF5154#define QAM_FQ_TAP_IM_EL20__PRE 0x25155 5156#define QAM_FQ_TAP_IM_EL20_TAP__B 05157#define QAM_FQ_TAP_IM_EL20_TAP__W 125158#define QAM_FQ_TAP_IM_EL20_TAP__M 0xFFF5159#define QAM_FQ_TAP_IM_EL20_TAP__PRE 0x25160 5161#define QAM_FQ_TAP_RE_EL21__A 0x142004A5162#define QAM_FQ_TAP_RE_EL21__W 125163#define QAM_FQ_TAP_RE_EL21__M 0xFFF5164#define QAM_FQ_TAP_RE_EL21__PRE 0x25165 5166#define QAM_FQ_TAP_RE_EL21_TAP__B 05167#define QAM_FQ_TAP_RE_EL21_TAP__W 125168#define QAM_FQ_TAP_RE_EL21_TAP__M 0xFFF5169#define QAM_FQ_TAP_RE_EL21_TAP__PRE 0x25170 5171#define QAM_FQ_TAP_IM_EL21__A 0x142004B5172#define QAM_FQ_TAP_IM_EL21__W 125173#define QAM_FQ_TAP_IM_EL21__M 0xFFF5174#define QAM_FQ_TAP_IM_EL21__PRE 0x25175 5176#define QAM_FQ_TAP_IM_EL21_TAP__B 05177#define QAM_FQ_TAP_IM_EL21_TAP__W 125178#define QAM_FQ_TAP_IM_EL21_TAP__M 0xFFF5179#define QAM_FQ_TAP_IM_EL21_TAP__PRE 0x25180 5181#define QAM_FQ_TAP_RE_EL22__A 0x142004C5182#define QAM_FQ_TAP_RE_EL22__W 125183#define QAM_FQ_TAP_RE_EL22__M 0xFFF5184#define QAM_FQ_TAP_RE_EL22__PRE 0x25185 5186#define QAM_FQ_TAP_RE_EL22_TAP__B 05187#define QAM_FQ_TAP_RE_EL22_TAP__W 125188#define QAM_FQ_TAP_RE_EL22_TAP__M 0xFFF5189#define QAM_FQ_TAP_RE_EL22_TAP__PRE 0x25190 5191#define QAM_FQ_TAP_IM_EL22__A 0x142004D5192#define QAM_FQ_TAP_IM_EL22__W 125193#define QAM_FQ_TAP_IM_EL22__M 0xFFF5194#define QAM_FQ_TAP_IM_EL22__PRE 0x25195 5196#define QAM_FQ_TAP_IM_EL22_TAP__B 05197#define QAM_FQ_TAP_IM_EL22_TAP__W 125198#define QAM_FQ_TAP_IM_EL22_TAP__M 0xFFF5199#define QAM_FQ_TAP_IM_EL22_TAP__PRE 0x25200 5201#define QAM_FQ_TAP_RE_EL23__A 0x142004E5202#define QAM_FQ_TAP_RE_EL23__W 125203#define QAM_FQ_TAP_RE_EL23__M 0xFFF5204#define QAM_FQ_TAP_RE_EL23__PRE 0x25205 5206#define QAM_FQ_TAP_RE_EL23_TAP__B 05207#define QAM_FQ_TAP_RE_EL23_TAP__W 125208#define QAM_FQ_TAP_RE_EL23_TAP__M 0xFFF5209#define QAM_FQ_TAP_RE_EL23_TAP__PRE 0x25210 5211#define QAM_FQ_TAP_IM_EL23__A 0x142004F5212#define QAM_FQ_TAP_IM_EL23__W 125213#define QAM_FQ_TAP_IM_EL23__M 0xFFF5214#define QAM_FQ_TAP_IM_EL23__PRE 0x25215 5216#define QAM_FQ_TAP_IM_EL23_TAP__B 05217#define QAM_FQ_TAP_IM_EL23_TAP__W 125218#define QAM_FQ_TAP_IM_EL23_TAP__M 0xFFF5219#define QAM_FQ_TAP_IM_EL23_TAP__PRE 0x25220 5221#define QAM_SL_COMM_EXEC__A 0x14300005222#define QAM_SL_COMM_EXEC__W 25223#define QAM_SL_COMM_EXEC__M 0x35224#define QAM_SL_COMM_EXEC__PRE 0x05225#define QAM_SL_COMM_EXEC_STOP 0x05226#define QAM_SL_COMM_EXEC_ACTIVE 0x15227#define QAM_SL_COMM_EXEC_HOLD 0x25228 5229#define QAM_SL_COMM_MB__A 0x14300025230#define QAM_SL_COMM_MB__W 45231#define QAM_SL_COMM_MB__M 0xF5232#define QAM_SL_COMM_MB__PRE 0x05233#define QAM_SL_COMM_MB_CTL__B 05234#define QAM_SL_COMM_MB_CTL__W 15235#define QAM_SL_COMM_MB_CTL__M 0x15236#define QAM_SL_COMM_MB_CTL__PRE 0x05237#define QAM_SL_COMM_MB_CTL_OFF 0x05238#define QAM_SL_COMM_MB_CTL_ON 0x15239#define QAM_SL_COMM_MB_OBS__B 15240#define QAM_SL_COMM_MB_OBS__W 15241#define QAM_SL_COMM_MB_OBS__M 0x25242#define QAM_SL_COMM_MB_OBS__PRE 0x05243#define QAM_SL_COMM_MB_OBS_OFF 0x05244#define QAM_SL_COMM_MB_OBS_ON 0x25245#define QAM_SL_COMM_MB_MUX_OBS__B 25246#define QAM_SL_COMM_MB_MUX_OBS__W 25247#define QAM_SL_COMM_MB_MUX_OBS__M 0xC5248#define QAM_SL_COMM_MB_MUX_OBS__PRE 0x05249#define QAM_SL_COMM_MB_MUX_OBS_CONST_CORR 0x05250#define QAM_SL_COMM_MB_MUX_OBS_CONST2LC_O 0x45251#define QAM_SL_COMM_MB_MUX_OBS_CONST2DQ_O 0x85252#define QAM_SL_COMM_MB_MUX_OBS_VDEC_O 0xC5253 5254#define QAM_SL_COMM_INT_REQ__A 0x14300035255#define QAM_SL_COMM_INT_REQ__W 15256#define QAM_SL_COMM_INT_REQ__M 0x15257#define QAM_SL_COMM_INT_REQ__PRE 0x05258#define QAM_SL_COMM_INT_STA__A 0x14300055259#define QAM_SL_COMM_INT_STA__W 25260#define QAM_SL_COMM_INT_STA__M 0x35261#define QAM_SL_COMM_INT_STA__PRE 0x05262 5263#define QAM_SL_COMM_INT_STA_MED_ERR_INT__B 05264#define QAM_SL_COMM_INT_STA_MED_ERR_INT__W 15265#define QAM_SL_COMM_INT_STA_MED_ERR_INT__M 0x15266#define QAM_SL_COMM_INT_STA_MED_ERR_INT__PRE 0x05267 5268#define QAM_SL_COMM_INT_STA_MER_INT__B 15269#define QAM_SL_COMM_INT_STA_MER_INT__W 15270#define QAM_SL_COMM_INT_STA_MER_INT__M 0x25271#define QAM_SL_COMM_INT_STA_MER_INT__PRE 0x05272 5273#define QAM_SL_COMM_INT_MSK__A 0x14300065274#define QAM_SL_COMM_INT_MSK__W 25275#define QAM_SL_COMM_INT_MSK__M 0x35276#define QAM_SL_COMM_INT_MSK__PRE 0x05277#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__B 05278#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__W 15279#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__M 0x15280#define QAM_SL_COMM_INT_MSK_MED_ERR_MSK__PRE 0x05281#define QAM_SL_COMM_INT_MSK_MER_MSK__B 15282#define QAM_SL_COMM_INT_MSK_MER_MSK__W 15283#define QAM_SL_COMM_INT_MSK_MER_MSK__M 0x25284#define QAM_SL_COMM_INT_MSK_MER_MSK__PRE 0x05285 5286#define QAM_SL_COMM_INT_STM__A 0x14300075287#define QAM_SL_COMM_INT_STM__W 25288#define QAM_SL_COMM_INT_STM__M 0x35289#define QAM_SL_COMM_INT_STM__PRE 0x05290#define QAM_SL_COMM_INT_STM_MED_ERR_STM__B 05291#define QAM_SL_COMM_INT_STM_MED_ERR_STM__W 15292#define QAM_SL_COMM_INT_STM_MED_ERR_STM__M 0x15293#define QAM_SL_COMM_INT_STM_MED_ERR_STM__PRE 0x05294#define QAM_SL_COMM_INT_STM_MER_STM__B 15295#define QAM_SL_COMM_INT_STM_MER_STM__W 15296#define QAM_SL_COMM_INT_STM_MER_STM__M 0x25297#define QAM_SL_COMM_INT_STM_MER_STM__PRE 0x05298 5299#define QAM_SL_MODE__A 0x14300105300#define QAM_SL_MODE__W 115301#define QAM_SL_MODE__M 0x7FF5302#define QAM_SL_MODE__PRE 0x05303 5304#define QAM_SL_MODE_SLICER4LC__B 05305#define QAM_SL_MODE_SLICER4LC__W 25306#define QAM_SL_MODE_SLICER4LC__M 0x35307#define QAM_SL_MODE_SLICER4LC__PRE 0x05308#define QAM_SL_MODE_SLICER4LC_RECT 0x05309#define QAM_SL_MODE_SLICER4LC_ONET 0x15310#define QAM_SL_MODE_SLICER4LC_RAD 0x25311 5312#define QAM_SL_MODE_SLICER4DQ__B 25313#define QAM_SL_MODE_SLICER4DQ__W 25314#define QAM_SL_MODE_SLICER4DQ__M 0xC5315#define QAM_SL_MODE_SLICER4DQ__PRE 0x05316#define QAM_SL_MODE_SLICER4DQ_RECT 0x05317#define QAM_SL_MODE_SLICER4DQ_ONET 0x45318#define QAM_SL_MODE_SLICER4DQ_RAD 0x85319 5320#define QAM_SL_MODE_SLICER4VD__B 45321#define QAM_SL_MODE_SLICER4VD__W 25322#define QAM_SL_MODE_SLICER4VD__M 0x305323#define QAM_SL_MODE_SLICER4VD__PRE 0x05324#define QAM_SL_MODE_SLICER4VD_RECT 0x05325#define QAM_SL_MODE_SLICER4VD_ONET 0x105326#define QAM_SL_MODE_SLICER4VD_RAD 0x205327 5328#define QAM_SL_MODE_ROT_DIS__B 65329#define QAM_SL_MODE_ROT_DIS__W 15330#define QAM_SL_MODE_ROT_DIS__M 0x405331#define QAM_SL_MODE_ROT_DIS__PRE 0x05332 5333#define QAM_SL_MODE_DQROT_DIS__B 75334#define QAM_SL_MODE_DQROT_DIS__W 15335#define QAM_SL_MODE_DQROT_DIS__M 0x805336#define QAM_SL_MODE_DQROT_DIS__PRE 0x05337 5338#define QAM_SL_MODE_DFE_DIS__B 85339#define QAM_SL_MODE_DFE_DIS__W 15340#define QAM_SL_MODE_DFE_DIS__M 0x1005341#define QAM_SL_MODE_DFE_DIS__PRE 0x05342 5343#define QAM_SL_MODE_RADIUS_MIX__B 95344#define QAM_SL_MODE_RADIUS_MIX__W 15345#define QAM_SL_MODE_RADIUS_MIX__M 0x2005346#define QAM_SL_MODE_RADIUS_MIX__PRE 0x05347 5348#define QAM_SL_MODE_TILT_COMP__B 105349#define QAM_SL_MODE_TILT_COMP__W 15350#define QAM_SL_MODE_TILT_COMP__M 0x4005351#define QAM_SL_MODE_TILT_COMP__PRE 0x05352 5353#define QAM_SL_K_FACTOR__A 0x14300115354#define QAM_SL_K_FACTOR__W 45355#define QAM_SL_K_FACTOR__M 0xF5356#define QAM_SL_K_FACTOR__PRE 0x05357#define QAM_SL_MEDIAN__A 0x14300125358#define QAM_SL_MEDIAN__W 145359#define QAM_SL_MEDIAN__M 0x3FFF5360#define QAM_SL_MEDIAN__PRE 0x05361 5362#define QAM_SL_MEDIAN_LENGTH__B 05363#define QAM_SL_MEDIAN_LENGTH__W 25364#define QAM_SL_MEDIAN_LENGTH__M 0x35365#define QAM_SL_MEDIAN_LENGTH__PRE 0x05366 5367#define QAM_SL_MEDIAN_CORRECT__B 25368#define QAM_SL_MEDIAN_CORRECT__W 45369#define QAM_SL_MEDIAN_CORRECT__M 0x3C5370#define QAM_SL_MEDIAN_CORRECT__PRE 0x05371 5372#define QAM_SL_MEDIAN_TOLERANCE__B 65373#define QAM_SL_MEDIAN_TOLERANCE__W 75374#define QAM_SL_MEDIAN_TOLERANCE__M 0x1FC05375#define QAM_SL_MEDIAN_TOLERANCE__PRE 0x05376 5377#define QAM_SL_MEDIAN_FAST__B 135378#define QAM_SL_MEDIAN_FAST__W 15379#define QAM_SL_MEDIAN_FAST__M 0x20005380#define QAM_SL_MEDIAN_FAST__PRE 0x05381 5382#define QAM_SL_ALPHA__A 0x14300135383#define QAM_SL_ALPHA__W 35384#define QAM_SL_ALPHA__M 0x75385#define QAM_SL_ALPHA__PRE 0x05386 5387#define QAM_SL_PHASELIMIT__A 0x14300145388#define QAM_SL_PHASELIMIT__W 95389#define QAM_SL_PHASELIMIT__M 0x1FF5390#define QAM_SL_PHASELIMIT__PRE 0x05391#define QAM_SL_MTA_LENGTH__A 0x14300155392#define QAM_SL_MTA_LENGTH__W 25393#define QAM_SL_MTA_LENGTH__M 0x35394#define QAM_SL_MTA_LENGTH__PRE 0x15395 5396#define QAM_SL_MTA_LENGTH_LENGTH__B 05397#define QAM_SL_MTA_LENGTH_LENGTH__W 25398#define QAM_SL_MTA_LENGTH_LENGTH__M 0x35399#define QAM_SL_MTA_LENGTH_LENGTH__PRE 0x15400 5401#define QAM_SL_MEDIAN_ERROR__A 0x14300165402#define QAM_SL_MEDIAN_ERROR__W 105403#define QAM_SL_MEDIAN_ERROR__M 0x3FF5404#define QAM_SL_MEDIAN_ERROR__PRE 0x05405 5406#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__B 05407#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__W 105408#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__M 0x3FF5409#define QAM_SL_MEDIAN_ERROR_MEDIAN_ERR__PRE 0x05410 5411#define QAM_SL_ERR_POWER__A 0x14300175412#define QAM_SL_ERR_POWER__W 165413#define QAM_SL_ERR_POWER__M 0xFFFF5414#define QAM_SL_ERR_POWER__PRE 0x05415 5416#define QAM_DQ_COMM_EXEC__A 0x14400005417#define QAM_DQ_COMM_EXEC__W 25418#define QAM_DQ_COMM_EXEC__M 0x35419#define QAM_DQ_COMM_EXEC__PRE 0x05420#define QAM_DQ_COMM_EXEC_STOP 0x05421#define QAM_DQ_COMM_EXEC_ACTIVE 0x15422#define QAM_DQ_COMM_EXEC_HOLD 0x25423 5424#define QAM_DQ_MODE__A 0x14400105425#define QAM_DQ_MODE__W 55426#define QAM_DQ_MODE__M 0x1F5427#define QAM_DQ_MODE__PRE 0x05428 5429#define QAM_DQ_MODE_TAPRESET__B 05430#define QAM_DQ_MODE_TAPRESET__W 15431#define QAM_DQ_MODE_TAPRESET__M 0x15432#define QAM_DQ_MODE_TAPRESET__PRE 0x05433#define QAM_DQ_MODE_TAPRESET_RST 0x15434 5435#define QAM_DQ_MODE_TAPLMS__B 15436#define QAM_DQ_MODE_TAPLMS__W 15437#define QAM_DQ_MODE_TAPLMS__M 0x25438#define QAM_DQ_MODE_TAPLMS__PRE 0x05439#define QAM_DQ_MODE_TAPLMS_UPD 0x25440 5441#define QAM_DQ_MODE_TAPDRAIN__B 25442#define QAM_DQ_MODE_TAPDRAIN__W 15443#define QAM_DQ_MODE_TAPDRAIN__M 0x45444#define QAM_DQ_MODE_TAPDRAIN__PRE 0x05445#define QAM_DQ_MODE_TAPDRAIN_DRAIN 0x45446 5447#define QAM_DQ_MODE_FB__B 35448#define QAM_DQ_MODE_FB__W 25449#define QAM_DQ_MODE_FB__M 0x185450#define QAM_DQ_MODE_FB__PRE 0x05451#define QAM_DQ_MODE_FB_CMA 0x05452#define QAM_DQ_MODE_FB_RADIUS 0x85453#define QAM_DQ_MODE_FB_DFB 0x105454#define QAM_DQ_MODE_FB_TRELLIS 0x185455 5456#define QAM_DQ_MU_FACTOR__A 0x14400115457#define QAM_DQ_MU_FACTOR__W 35458#define QAM_DQ_MU_FACTOR__M 0x75459#define QAM_DQ_MU_FACTOR__PRE 0x05460 5461#define QAM_DQ_LA_FACTOR__A 0x14400125462#define QAM_DQ_LA_FACTOR__W 45463#define QAM_DQ_LA_FACTOR__M 0xF5464#define QAM_DQ_LA_FACTOR__PRE 0xC5465 5466#define QAM_DQ_CMA_RATIO__A 0x14400135467#define QAM_DQ_CMA_RATIO__W 145468#define QAM_DQ_CMA_RATIO__M 0x3FFF5469#define QAM_DQ_CMA_RATIO__PRE 0x3CF95470#define QAM_DQ_CMA_RATIO_QPSK 0x20005471#define QAM_DQ_CMA_RATIO_QAM16 0x34CD5472#define QAM_DQ_CMA_RATIO_QAM64 0x3A005473#define QAM_DQ_CMA_RATIO_QAM256 0x3B4D5474#define QAM_DQ_CMA_RATIO_QAM1024 0x3BA05475 5476#define QAM_DQ_QUAL_RADSEL__A 0x14400145477#define QAM_DQ_QUAL_RADSEL__W 35478#define QAM_DQ_QUAL_RADSEL__M 0x75479#define QAM_DQ_QUAL_RADSEL__PRE 0x05480 5481#define QAM_DQ_QUAL_RADSEL_BIT__B 05482#define QAM_DQ_QUAL_RADSEL_BIT__W 35483#define QAM_DQ_QUAL_RADSEL_BIT__M 0x75484#define QAM_DQ_QUAL_RADSEL_BIT__PRE 0x05485#define QAM_DQ_QUAL_RADSEL_BIT_PURE_RADIUS 0x05486#define QAM_DQ_QUAL_RADSEL_BIT_PURE_CMA 0x65487 5488#define QAM_DQ_QUAL_ENA__A 0x14400155489#define QAM_DQ_QUAL_ENA__W 15490#define QAM_DQ_QUAL_ENA__M 0x15491#define QAM_DQ_QUAL_ENA__PRE 0x05492 5493#define QAM_DQ_QUAL_ENA_ENA__B 05494#define QAM_DQ_QUAL_ENA_ENA__W 15495#define QAM_DQ_QUAL_ENA_ENA__M 0x15496#define QAM_DQ_QUAL_ENA_ENA__PRE 0x05497#define QAM_DQ_QUAL_ENA_ENA_QUAL_WEIGHTING 0x15498 5499#define QAM_DQ_QUAL_FUN0__A 0x14400185500#define QAM_DQ_QUAL_FUN0__W 65501#define QAM_DQ_QUAL_FUN0__M 0x3F5502#define QAM_DQ_QUAL_FUN0__PRE 0x45503 5504#define QAM_DQ_QUAL_FUN0_BIT__B 05505#define QAM_DQ_QUAL_FUN0_BIT__W 65506#define QAM_DQ_QUAL_FUN0_BIT__M 0x3F5507#define QAM_DQ_QUAL_FUN0_BIT__PRE 0x45508 5509#define QAM_DQ_QUAL_FUN1__A 0x14400195510#define QAM_DQ_QUAL_FUN1__W 65511#define QAM_DQ_QUAL_FUN1__M 0x3F5512#define QAM_DQ_QUAL_FUN1__PRE 0x45513 5514#define QAM_DQ_QUAL_FUN1_BIT__B 05515#define QAM_DQ_QUAL_FUN1_BIT__W 65516#define QAM_DQ_QUAL_FUN1_BIT__M 0x3F5517#define QAM_DQ_QUAL_FUN1_BIT__PRE 0x45518 5519#define QAM_DQ_QUAL_FUN2__A 0x144001A5520#define QAM_DQ_QUAL_FUN2__W 65521#define QAM_DQ_QUAL_FUN2__M 0x3F5522#define QAM_DQ_QUAL_FUN2__PRE 0x45523 5524#define QAM_DQ_QUAL_FUN2_BIT__B 05525#define QAM_DQ_QUAL_FUN2_BIT__W 65526#define QAM_DQ_QUAL_FUN2_BIT__M 0x3F5527#define QAM_DQ_QUAL_FUN2_BIT__PRE 0x45528 5529#define QAM_DQ_QUAL_FUN3__A 0x144001B5530#define QAM_DQ_QUAL_FUN3__W 65531#define QAM_DQ_QUAL_FUN3__M 0x3F5532#define QAM_DQ_QUAL_FUN3__PRE 0x45533 5534#define QAM_DQ_QUAL_FUN3_BIT__B 05535#define QAM_DQ_QUAL_FUN3_BIT__W 65536#define QAM_DQ_QUAL_FUN3_BIT__M 0x3F5537#define QAM_DQ_QUAL_FUN3_BIT__PRE 0x45538 5539#define QAM_DQ_QUAL_FUN4__A 0x144001C5540#define QAM_DQ_QUAL_FUN4__W 65541#define QAM_DQ_QUAL_FUN4__M 0x3F5542#define QAM_DQ_QUAL_FUN4__PRE 0x65543 5544#define QAM_DQ_QUAL_FUN4_BIT__B 05545#define QAM_DQ_QUAL_FUN4_BIT__W 65546#define QAM_DQ_QUAL_FUN4_BIT__M 0x3F5547#define QAM_DQ_QUAL_FUN4_BIT__PRE 0x65548 5549#define QAM_DQ_QUAL_FUN5__A 0x144001D5550#define QAM_DQ_QUAL_FUN5__W 65551#define QAM_DQ_QUAL_FUN5__M 0x3F5552#define QAM_DQ_QUAL_FUN5__PRE 0x65553 5554#define QAM_DQ_QUAL_FUN5_BIT__B 05555#define QAM_DQ_QUAL_FUN5_BIT__W 65556#define QAM_DQ_QUAL_FUN5_BIT__M 0x3F5557#define QAM_DQ_QUAL_FUN5_BIT__PRE 0x65558 5559#define QAM_DQ_RAW_LIM__A 0x144001E5560#define QAM_DQ_RAW_LIM__W 55561#define QAM_DQ_RAW_LIM__M 0x1F5562#define QAM_DQ_RAW_LIM__PRE 0x1F5563 5564#define QAM_DQ_RAW_LIM_BIT__B 05565#define QAM_DQ_RAW_LIM_BIT__W 55566#define QAM_DQ_RAW_LIM_BIT__M 0x1F5567#define QAM_DQ_RAW_LIM_BIT__PRE 0x1F5568 5569#define QAM_DQ_TAP_RE_EL0__A 0x14400205570#define QAM_DQ_TAP_RE_EL0__W 125571#define QAM_DQ_TAP_RE_EL0__M 0xFFF5572#define QAM_DQ_TAP_RE_EL0__PRE 0x25573 5574#define QAM_DQ_TAP_RE_EL0_TAP__B 05575#define QAM_DQ_TAP_RE_EL0_TAP__W 125576#define QAM_DQ_TAP_RE_EL0_TAP__M 0xFFF5577#define QAM_DQ_TAP_RE_EL0_TAP__PRE 0x25578 5579#define QAM_DQ_TAP_IM_EL0__A 0x14400215580#define QAM_DQ_TAP_IM_EL0__W 125581#define QAM_DQ_TAP_IM_EL0__M 0xFFF5582#define QAM_DQ_TAP_IM_EL0__PRE 0x25583 5584#define QAM_DQ_TAP_IM_EL0_TAP__B 05585#define QAM_DQ_TAP_IM_EL0_TAP__W 125586#define QAM_DQ_TAP_IM_EL0_TAP__M 0xFFF5587#define QAM_DQ_TAP_IM_EL0_TAP__PRE 0x25588 5589#define QAM_DQ_TAP_RE_EL1__A 0x14400225590#define QAM_DQ_TAP_RE_EL1__W 125591#define QAM_DQ_TAP_RE_EL1__M 0xFFF5592#define QAM_DQ_TAP_RE_EL1__PRE 0x25593 5594#define QAM_DQ_TAP_RE_EL1_TAP__B 05595#define QAM_DQ_TAP_RE_EL1_TAP__W 125596#define QAM_DQ_TAP_RE_EL1_TAP__M 0xFFF5597#define QAM_DQ_TAP_RE_EL1_TAP__PRE 0x25598 5599#define QAM_DQ_TAP_IM_EL1__A 0x14400235600#define QAM_DQ_TAP_IM_EL1__W 125601#define QAM_DQ_TAP_IM_EL1__M 0xFFF5602#define QAM_DQ_TAP_IM_EL1__PRE 0x25603 5604#define QAM_DQ_TAP_IM_EL1_TAP__B 05605#define QAM_DQ_TAP_IM_EL1_TAP__W 125606#define QAM_DQ_TAP_IM_EL1_TAP__M 0xFFF5607#define QAM_DQ_TAP_IM_EL1_TAP__PRE 0x25608 5609#define QAM_DQ_TAP_RE_EL2__A 0x14400245610#define QAM_DQ_TAP_RE_EL2__W 125611#define QAM_DQ_TAP_RE_EL2__M 0xFFF5612#define QAM_DQ_TAP_RE_EL2__PRE 0x25613 5614#define QAM_DQ_TAP_RE_EL2_TAP__B 05615#define QAM_DQ_TAP_RE_EL2_TAP__W 125616#define QAM_DQ_TAP_RE_EL2_TAP__M 0xFFF5617#define QAM_DQ_TAP_RE_EL2_TAP__PRE 0x25618 5619#define QAM_DQ_TAP_IM_EL2__A 0x14400255620#define QAM_DQ_TAP_IM_EL2__W 125621#define QAM_DQ_TAP_IM_EL2__M 0xFFF5622#define QAM_DQ_TAP_IM_EL2__PRE 0x25623 5624#define QAM_DQ_TAP_IM_EL2_TAP__B 05625#define QAM_DQ_TAP_IM_EL2_TAP__W 125626#define QAM_DQ_TAP_IM_EL2_TAP__M 0xFFF5627#define QAM_DQ_TAP_IM_EL2_TAP__PRE 0x25628 5629#define QAM_DQ_TAP_RE_EL3__A 0x14400265630#define QAM_DQ_TAP_RE_EL3__W 125631#define QAM_DQ_TAP_RE_EL3__M 0xFFF5632#define QAM_DQ_TAP_RE_EL3__PRE 0x25633 5634#define QAM_DQ_TAP_RE_EL3_TAP__B 05635#define QAM_DQ_TAP_RE_EL3_TAP__W 125636#define QAM_DQ_TAP_RE_EL3_TAP__M 0xFFF5637#define QAM_DQ_TAP_RE_EL3_TAP__PRE 0x25638 5639#define QAM_DQ_TAP_IM_EL3__A 0x14400275640#define QAM_DQ_TAP_IM_EL3__W 125641#define QAM_DQ_TAP_IM_EL3__M 0xFFF5642#define QAM_DQ_TAP_IM_EL3__PRE 0x25643 5644#define QAM_DQ_TAP_IM_EL3_TAP__B 05645#define QAM_DQ_TAP_IM_EL3_TAP__W 125646#define QAM_DQ_TAP_IM_EL3_TAP__M 0xFFF5647#define QAM_DQ_TAP_IM_EL3_TAP__PRE 0x25648 5649#define QAM_DQ_TAP_RE_EL4__A 0x14400285650#define QAM_DQ_TAP_RE_EL4__W 125651#define QAM_DQ_TAP_RE_EL4__M 0xFFF5652#define QAM_DQ_TAP_RE_EL4__PRE 0x25653 5654#define QAM_DQ_TAP_RE_EL4_TAP__B 05655#define QAM_DQ_TAP_RE_EL4_TAP__W 125656#define QAM_DQ_TAP_RE_EL4_TAP__M 0xFFF5657#define QAM_DQ_TAP_RE_EL4_TAP__PRE 0x25658 5659#define QAM_DQ_TAP_IM_EL4__A 0x14400295660#define QAM_DQ_TAP_IM_EL4__W 125661#define QAM_DQ_TAP_IM_EL4__M 0xFFF5662#define QAM_DQ_TAP_IM_EL4__PRE 0x25663 5664#define QAM_DQ_TAP_IM_EL4_TAP__B 05665#define QAM_DQ_TAP_IM_EL4_TAP__W 125666#define QAM_DQ_TAP_IM_EL4_TAP__M 0xFFF5667#define QAM_DQ_TAP_IM_EL4_TAP__PRE 0x25668 5669#define QAM_DQ_TAP_RE_EL5__A 0x144002A5670#define QAM_DQ_TAP_RE_EL5__W 125671#define QAM_DQ_TAP_RE_EL5__M 0xFFF5672#define QAM_DQ_TAP_RE_EL5__PRE 0x25673 5674#define QAM_DQ_TAP_RE_EL5_TAP__B 05675#define QAM_DQ_TAP_RE_EL5_TAP__W 125676#define QAM_DQ_TAP_RE_EL5_TAP__M 0xFFF5677#define QAM_DQ_TAP_RE_EL5_TAP__PRE 0x25678 5679#define QAM_DQ_TAP_IM_EL5__A 0x144002B5680#define QAM_DQ_TAP_IM_EL5__W 125681#define QAM_DQ_TAP_IM_EL5__M 0xFFF5682#define QAM_DQ_TAP_IM_EL5__PRE 0x25683 5684#define QAM_DQ_TAP_IM_EL5_TAP__B 05685#define QAM_DQ_TAP_IM_EL5_TAP__W 125686#define QAM_DQ_TAP_IM_EL5_TAP__M 0xFFF5687#define QAM_DQ_TAP_IM_EL5_TAP__PRE 0x25688 5689#define QAM_DQ_TAP_RE_EL6__A 0x144002C5690#define QAM_DQ_TAP_RE_EL6__W 125691#define QAM_DQ_TAP_RE_EL6__M 0xFFF5692#define QAM_DQ_TAP_RE_EL6__PRE 0x25693 5694#define QAM_DQ_TAP_RE_EL6_TAP__B 05695#define QAM_DQ_TAP_RE_EL6_TAP__W 125696#define QAM_DQ_TAP_RE_EL6_TAP__M 0xFFF5697#define QAM_DQ_TAP_RE_EL6_TAP__PRE 0x25698 5699#define QAM_DQ_TAP_IM_EL6__A 0x144002D5700#define QAM_DQ_TAP_IM_EL6__W 125701#define QAM_DQ_TAP_IM_EL6__M 0xFFF5702#define QAM_DQ_TAP_IM_EL6__PRE 0x25703 5704#define QAM_DQ_TAP_IM_EL6_TAP__B 05705#define QAM_DQ_TAP_IM_EL6_TAP__W 125706#define QAM_DQ_TAP_IM_EL6_TAP__M 0xFFF5707#define QAM_DQ_TAP_IM_EL6_TAP__PRE 0x25708 5709#define QAM_DQ_TAP_RE_EL7__A 0x144002E5710#define QAM_DQ_TAP_RE_EL7__W 125711#define QAM_DQ_TAP_RE_EL7__M 0xFFF5712#define QAM_DQ_TAP_RE_EL7__PRE 0x25713 5714#define QAM_DQ_TAP_RE_EL7_TAP__B 05715#define QAM_DQ_TAP_RE_EL7_TAP__W 125716#define QAM_DQ_TAP_RE_EL7_TAP__M 0xFFF5717#define QAM_DQ_TAP_RE_EL7_TAP__PRE 0x25718 5719#define QAM_DQ_TAP_IM_EL7__A 0x144002F5720#define QAM_DQ_TAP_IM_EL7__W 125721#define QAM_DQ_TAP_IM_EL7__M 0xFFF5722#define QAM_DQ_TAP_IM_EL7__PRE 0x25723 5724#define QAM_DQ_TAP_IM_EL7_TAP__B 05725#define QAM_DQ_TAP_IM_EL7_TAP__W 125726#define QAM_DQ_TAP_IM_EL7_TAP__M 0xFFF5727#define QAM_DQ_TAP_IM_EL7_TAP__PRE 0x25728 5729#define QAM_DQ_TAP_RE_EL8__A 0x14400305730#define QAM_DQ_TAP_RE_EL8__W 125731#define QAM_DQ_TAP_RE_EL8__M 0xFFF5732#define QAM_DQ_TAP_RE_EL8__PRE 0x25733 5734#define QAM_DQ_TAP_RE_EL8_TAP__B 05735#define QAM_DQ_TAP_RE_EL8_TAP__W 125736#define QAM_DQ_TAP_RE_EL8_TAP__M 0xFFF5737#define QAM_DQ_TAP_RE_EL8_TAP__PRE 0x25738 5739#define QAM_DQ_TAP_IM_EL8__A 0x14400315740#define QAM_DQ_TAP_IM_EL8__W 125741#define QAM_DQ_TAP_IM_EL8__M 0xFFF5742#define QAM_DQ_TAP_IM_EL8__PRE 0x25743 5744#define QAM_DQ_TAP_IM_EL8_TAP__B 05745#define QAM_DQ_TAP_IM_EL8_TAP__W 125746#define QAM_DQ_TAP_IM_EL8_TAP__M 0xFFF5747#define QAM_DQ_TAP_IM_EL8_TAP__PRE 0x25748 5749#define QAM_DQ_TAP_RE_EL9__A 0x14400325750#define QAM_DQ_TAP_RE_EL9__W 125751#define QAM_DQ_TAP_RE_EL9__M 0xFFF5752#define QAM_DQ_TAP_RE_EL9__PRE 0x25753 5754#define QAM_DQ_TAP_RE_EL9_TAP__B 05755#define QAM_DQ_TAP_RE_EL9_TAP__W 125756#define QAM_DQ_TAP_RE_EL9_TAP__M 0xFFF5757#define QAM_DQ_TAP_RE_EL9_TAP__PRE 0x25758 5759#define QAM_DQ_TAP_IM_EL9__A 0x14400335760#define QAM_DQ_TAP_IM_EL9__W 125761#define QAM_DQ_TAP_IM_EL9__M 0xFFF5762#define QAM_DQ_TAP_IM_EL9__PRE 0x25763 5764#define QAM_DQ_TAP_IM_EL9_TAP__B 05765#define QAM_DQ_TAP_IM_EL9_TAP__W 125766#define QAM_DQ_TAP_IM_EL9_TAP__M 0xFFF5767#define QAM_DQ_TAP_IM_EL9_TAP__PRE 0x25768 5769#define QAM_DQ_TAP_RE_EL10__A 0x14400345770#define QAM_DQ_TAP_RE_EL10__W 125771#define QAM_DQ_TAP_RE_EL10__M 0xFFF5772#define QAM_DQ_TAP_RE_EL10__PRE 0x25773 5774#define QAM_DQ_TAP_RE_EL10_TAP__B 05775#define QAM_DQ_TAP_RE_EL10_TAP__W 125776#define QAM_DQ_TAP_RE_EL10_TAP__M 0xFFF5777#define QAM_DQ_TAP_RE_EL10_TAP__PRE 0x25778 5779#define QAM_DQ_TAP_IM_EL10__A 0x14400355780#define QAM_DQ_TAP_IM_EL10__W 125781#define QAM_DQ_TAP_IM_EL10__M 0xFFF5782#define QAM_DQ_TAP_IM_EL10__PRE 0x25783 5784#define QAM_DQ_TAP_IM_EL10_TAP__B 05785#define QAM_DQ_TAP_IM_EL10_TAP__W 125786#define QAM_DQ_TAP_IM_EL10_TAP__M 0xFFF5787#define QAM_DQ_TAP_IM_EL10_TAP__PRE 0x25788 5789#define QAM_DQ_TAP_RE_EL11__A 0x14400365790#define QAM_DQ_TAP_RE_EL11__W 125791#define QAM_DQ_TAP_RE_EL11__M 0xFFF5792#define QAM_DQ_TAP_RE_EL11__PRE 0x25793 5794#define QAM_DQ_TAP_RE_EL11_TAP__B 05795#define QAM_DQ_TAP_RE_EL11_TAP__W 125796#define QAM_DQ_TAP_RE_EL11_TAP__M 0xFFF5797#define QAM_DQ_TAP_RE_EL11_TAP__PRE 0x25798 5799#define QAM_DQ_TAP_IM_EL11__A 0x14400375800#define QAM_DQ_TAP_IM_EL11__W 125801#define QAM_DQ_TAP_IM_EL11__M 0xFFF5802#define QAM_DQ_TAP_IM_EL11__PRE 0x25803 5804#define QAM_DQ_TAP_IM_EL11_TAP__B 05805#define QAM_DQ_TAP_IM_EL11_TAP__W 125806#define QAM_DQ_TAP_IM_EL11_TAP__M 0xFFF5807#define QAM_DQ_TAP_IM_EL11_TAP__PRE 0x25808 5809#define QAM_DQ_TAP_RE_EL12__A 0x14400385810#define QAM_DQ_TAP_RE_EL12__W 125811#define QAM_DQ_TAP_RE_EL12__M 0xFFF5812#define QAM_DQ_TAP_RE_EL12__PRE 0x25813 5814#define QAM_DQ_TAP_RE_EL12_TAP__B 05815#define QAM_DQ_TAP_RE_EL12_TAP__W 125816#define QAM_DQ_TAP_RE_EL12_TAP__M 0xFFF5817#define QAM_DQ_TAP_RE_EL12_TAP__PRE 0x25818 5819#define QAM_DQ_TAP_IM_EL12__A 0x14400395820#define QAM_DQ_TAP_IM_EL12__W 125821#define QAM_DQ_TAP_IM_EL12__M 0xFFF5822#define QAM_DQ_TAP_IM_EL12__PRE 0x25823 5824#define QAM_DQ_TAP_IM_EL12_TAP__B 05825#define QAM_DQ_TAP_IM_EL12_TAP__W 125826#define QAM_DQ_TAP_IM_EL12_TAP__M 0xFFF5827#define QAM_DQ_TAP_IM_EL12_TAP__PRE 0x25828 5829#define QAM_DQ_TAP_RE_EL13__A 0x144003A5830#define QAM_DQ_TAP_RE_EL13__W 125831#define QAM_DQ_TAP_RE_EL13__M 0xFFF5832#define QAM_DQ_TAP_RE_EL13__PRE 0x25833 5834#define QAM_DQ_TAP_RE_EL13_TAP__B 05835#define QAM_DQ_TAP_RE_EL13_TAP__W 125836#define QAM_DQ_TAP_RE_EL13_TAP__M 0xFFF5837#define QAM_DQ_TAP_RE_EL13_TAP__PRE 0x25838 5839#define QAM_DQ_TAP_IM_EL13__A 0x144003B5840#define QAM_DQ_TAP_IM_EL13__W 125841#define QAM_DQ_TAP_IM_EL13__M 0xFFF5842#define QAM_DQ_TAP_IM_EL13__PRE 0x25843 5844#define QAM_DQ_TAP_IM_EL13_TAP__B 05845#define QAM_DQ_TAP_IM_EL13_TAP__W 125846#define QAM_DQ_TAP_IM_EL13_TAP__M 0xFFF5847#define QAM_DQ_TAP_IM_EL13_TAP__PRE 0x25848 5849#define QAM_DQ_TAP_RE_EL14__A 0x144003C5850#define QAM_DQ_TAP_RE_EL14__W 125851#define QAM_DQ_TAP_RE_EL14__M 0xFFF5852#define QAM_DQ_TAP_RE_EL14__PRE 0x25853 5854#define QAM_DQ_TAP_RE_EL14_TAP__B 05855#define QAM_DQ_TAP_RE_EL14_TAP__W 125856#define QAM_DQ_TAP_RE_EL14_TAP__M 0xFFF5857#define QAM_DQ_TAP_RE_EL14_TAP__PRE 0x25858 5859#define QAM_DQ_TAP_IM_EL14__A 0x144003D5860#define QAM_DQ_TAP_IM_EL14__W 125861#define QAM_DQ_TAP_IM_EL14__M 0xFFF5862#define QAM_DQ_TAP_IM_EL14__PRE 0x25863 5864#define QAM_DQ_TAP_IM_EL14_TAP__B 05865#define QAM_DQ_TAP_IM_EL14_TAP__W 125866#define QAM_DQ_TAP_IM_EL14_TAP__M 0xFFF5867#define QAM_DQ_TAP_IM_EL14_TAP__PRE 0x25868 5869#define QAM_DQ_TAP_RE_EL15__A 0x144003E5870#define QAM_DQ_TAP_RE_EL15__W 125871#define QAM_DQ_TAP_RE_EL15__M 0xFFF5872#define QAM_DQ_TAP_RE_EL15__PRE 0x25873 5874#define QAM_DQ_TAP_RE_EL15_TAP__B 05875#define QAM_DQ_TAP_RE_EL15_TAP__W 125876#define QAM_DQ_TAP_RE_EL15_TAP__M 0xFFF5877#define QAM_DQ_TAP_RE_EL15_TAP__PRE 0x25878 5879#define QAM_DQ_TAP_IM_EL15__A 0x144003F5880#define QAM_DQ_TAP_IM_EL15__W 125881#define QAM_DQ_TAP_IM_EL15__M 0xFFF5882#define QAM_DQ_TAP_IM_EL15__PRE 0x25883 5884#define QAM_DQ_TAP_IM_EL15_TAP__B 05885#define QAM_DQ_TAP_IM_EL15_TAP__W 125886#define QAM_DQ_TAP_IM_EL15_TAP__M 0xFFF5887#define QAM_DQ_TAP_IM_EL15_TAP__PRE 0x25888 5889#define QAM_DQ_TAP_RE_EL16__A 0x14400405890#define QAM_DQ_TAP_RE_EL16__W 125891#define QAM_DQ_TAP_RE_EL16__M 0xFFF5892#define QAM_DQ_TAP_RE_EL16__PRE 0x25893 5894#define QAM_DQ_TAP_RE_EL16_TAP__B 05895#define QAM_DQ_TAP_RE_EL16_TAP__W 125896#define QAM_DQ_TAP_RE_EL16_TAP__M 0xFFF5897#define QAM_DQ_TAP_RE_EL16_TAP__PRE 0x25898 5899#define QAM_DQ_TAP_IM_EL16__A 0x14400415900#define QAM_DQ_TAP_IM_EL16__W 125901#define QAM_DQ_TAP_IM_EL16__M 0xFFF5902#define QAM_DQ_TAP_IM_EL16__PRE 0x25903 5904#define QAM_DQ_TAP_IM_EL16_TAP__B 05905#define QAM_DQ_TAP_IM_EL16_TAP__W 125906#define QAM_DQ_TAP_IM_EL16_TAP__M 0xFFF5907#define QAM_DQ_TAP_IM_EL16_TAP__PRE 0x25908 5909#define QAM_DQ_TAP_RE_EL17__A 0x14400425910#define QAM_DQ_TAP_RE_EL17__W 125911#define QAM_DQ_TAP_RE_EL17__M 0xFFF5912#define QAM_DQ_TAP_RE_EL17__PRE 0x25913 5914#define QAM_DQ_TAP_RE_EL17_TAP__B 05915#define QAM_DQ_TAP_RE_EL17_TAP__W 125916#define QAM_DQ_TAP_RE_EL17_TAP__M 0xFFF5917#define QAM_DQ_TAP_RE_EL17_TAP__PRE 0x25918 5919#define QAM_DQ_TAP_IM_EL17__A 0x14400435920#define QAM_DQ_TAP_IM_EL17__W 125921#define QAM_DQ_TAP_IM_EL17__M 0xFFF5922#define QAM_DQ_TAP_IM_EL17__PRE 0x25923 5924#define QAM_DQ_TAP_IM_EL17_TAP__B 05925#define QAM_DQ_TAP_IM_EL17_TAP__W 125926#define QAM_DQ_TAP_IM_EL17_TAP__M 0xFFF5927#define QAM_DQ_TAP_IM_EL17_TAP__PRE 0x25928 5929#define QAM_DQ_TAP_RE_EL18__A 0x14400445930#define QAM_DQ_TAP_RE_EL18__W 125931#define QAM_DQ_TAP_RE_EL18__M 0xFFF5932#define QAM_DQ_TAP_RE_EL18__PRE 0x25933 5934#define QAM_DQ_TAP_RE_EL18_TAP__B 05935#define QAM_DQ_TAP_RE_EL18_TAP__W 125936#define QAM_DQ_TAP_RE_EL18_TAP__M 0xFFF5937#define QAM_DQ_TAP_RE_EL18_TAP__PRE 0x25938 5939#define QAM_DQ_TAP_IM_EL18__A 0x14400455940#define QAM_DQ_TAP_IM_EL18__W 125941#define QAM_DQ_TAP_IM_EL18__M 0xFFF5942#define QAM_DQ_TAP_IM_EL18__PRE 0x25943 5944#define QAM_DQ_TAP_IM_EL18_TAP__B 05945#define QAM_DQ_TAP_IM_EL18_TAP__W 125946#define QAM_DQ_TAP_IM_EL18_TAP__M 0xFFF5947#define QAM_DQ_TAP_IM_EL18_TAP__PRE 0x25948 5949#define QAM_DQ_TAP_RE_EL19__A 0x14400465950#define QAM_DQ_TAP_RE_EL19__W 125951#define QAM_DQ_TAP_RE_EL19__M 0xFFF5952#define QAM_DQ_TAP_RE_EL19__PRE 0x25953 5954#define QAM_DQ_TAP_RE_EL19_TAP__B 05955#define QAM_DQ_TAP_RE_EL19_TAP__W 125956#define QAM_DQ_TAP_RE_EL19_TAP__M 0xFFF5957#define QAM_DQ_TAP_RE_EL19_TAP__PRE 0x25958 5959#define QAM_DQ_TAP_IM_EL19__A 0x14400475960#define QAM_DQ_TAP_IM_EL19__W 125961#define QAM_DQ_TAP_IM_EL19__M 0xFFF5962#define QAM_DQ_TAP_IM_EL19__PRE 0x25963 5964#define QAM_DQ_TAP_IM_EL19_TAP__B 05965#define QAM_DQ_TAP_IM_EL19_TAP__W 125966#define QAM_DQ_TAP_IM_EL19_TAP__M 0xFFF5967#define QAM_DQ_TAP_IM_EL19_TAP__PRE 0x25968 5969#define QAM_DQ_TAP_RE_EL20__A 0x14400485970#define QAM_DQ_TAP_RE_EL20__W 125971#define QAM_DQ_TAP_RE_EL20__M 0xFFF5972#define QAM_DQ_TAP_RE_EL20__PRE 0x25973 5974#define QAM_DQ_TAP_RE_EL20_TAP__B 05975#define QAM_DQ_TAP_RE_EL20_TAP__W 125976#define QAM_DQ_TAP_RE_EL20_TAP__M 0xFFF5977#define QAM_DQ_TAP_RE_EL20_TAP__PRE 0x25978 5979#define QAM_DQ_TAP_IM_EL20__A 0x14400495980#define QAM_DQ_TAP_IM_EL20__W 125981#define QAM_DQ_TAP_IM_EL20__M 0xFFF5982#define QAM_DQ_TAP_IM_EL20__PRE 0x25983 5984#define QAM_DQ_TAP_IM_EL20_TAP__B 05985#define QAM_DQ_TAP_IM_EL20_TAP__W 125986#define QAM_DQ_TAP_IM_EL20_TAP__M 0xFFF5987#define QAM_DQ_TAP_IM_EL20_TAP__PRE 0x25988 5989#define QAM_DQ_TAP_RE_EL21__A 0x144004A5990#define QAM_DQ_TAP_RE_EL21__W 125991#define QAM_DQ_TAP_RE_EL21__M 0xFFF5992#define QAM_DQ_TAP_RE_EL21__PRE 0x25993 5994#define QAM_DQ_TAP_RE_EL21_TAP__B 05995#define QAM_DQ_TAP_RE_EL21_TAP__W 125996#define QAM_DQ_TAP_RE_EL21_TAP__M 0xFFF5997#define QAM_DQ_TAP_RE_EL21_TAP__PRE 0x25998 5999#define QAM_DQ_TAP_IM_EL21__A 0x144004B6000#define QAM_DQ_TAP_IM_EL21__W 126001#define QAM_DQ_TAP_IM_EL21__M 0xFFF6002#define QAM_DQ_TAP_IM_EL21__PRE 0x26003 6004#define QAM_DQ_TAP_IM_EL21_TAP__B 06005#define QAM_DQ_TAP_IM_EL21_TAP__W 126006#define QAM_DQ_TAP_IM_EL21_TAP__M 0xFFF6007#define QAM_DQ_TAP_IM_EL21_TAP__PRE 0x26008 6009#define QAM_DQ_TAP_RE_EL22__A 0x144004C6010#define QAM_DQ_TAP_RE_EL22__W 126011#define QAM_DQ_TAP_RE_EL22__M 0xFFF6012#define QAM_DQ_TAP_RE_EL22__PRE 0x26013 6014#define QAM_DQ_TAP_RE_EL22_TAP__B 06015#define QAM_DQ_TAP_RE_EL22_TAP__W 126016#define QAM_DQ_TAP_RE_EL22_TAP__M 0xFFF6017#define QAM_DQ_TAP_RE_EL22_TAP__PRE 0x26018 6019#define QAM_DQ_TAP_IM_EL22__A 0x144004D6020#define QAM_DQ_TAP_IM_EL22__W 126021#define QAM_DQ_TAP_IM_EL22__M 0xFFF6022#define QAM_DQ_TAP_IM_EL22__PRE 0x26023 6024#define QAM_DQ_TAP_IM_EL22_TAP__B 06025#define QAM_DQ_TAP_IM_EL22_TAP__W 126026#define QAM_DQ_TAP_IM_EL22_TAP__M 0xFFF6027#define QAM_DQ_TAP_IM_EL22_TAP__PRE 0x26028 6029#define QAM_DQ_TAP_RE_EL23__A 0x144004E6030#define QAM_DQ_TAP_RE_EL23__W 126031#define QAM_DQ_TAP_RE_EL23__M 0xFFF6032#define QAM_DQ_TAP_RE_EL23__PRE 0x26033 6034#define QAM_DQ_TAP_RE_EL23_TAP__B 06035#define QAM_DQ_TAP_RE_EL23_TAP__W 126036#define QAM_DQ_TAP_RE_EL23_TAP__M 0xFFF6037#define QAM_DQ_TAP_RE_EL23_TAP__PRE 0x26038 6039#define QAM_DQ_TAP_IM_EL23__A 0x144004F6040#define QAM_DQ_TAP_IM_EL23__W 126041#define QAM_DQ_TAP_IM_EL23__M 0xFFF6042#define QAM_DQ_TAP_IM_EL23__PRE 0x26043 6044#define QAM_DQ_TAP_IM_EL23_TAP__B 06045#define QAM_DQ_TAP_IM_EL23_TAP__W 126046#define QAM_DQ_TAP_IM_EL23_TAP__M 0xFFF6047#define QAM_DQ_TAP_IM_EL23_TAP__PRE 0x26048 6049#define QAM_DQ_TAP_RE_EL24__A 0x14400506050#define QAM_DQ_TAP_RE_EL24__W 126051#define QAM_DQ_TAP_RE_EL24__M 0xFFF6052#define QAM_DQ_TAP_RE_EL24__PRE 0x26053 6054#define QAM_DQ_TAP_RE_EL24_TAP__B 06055#define QAM_DQ_TAP_RE_EL24_TAP__W 126056#define QAM_DQ_TAP_RE_EL24_TAP__M 0xFFF6057#define QAM_DQ_TAP_RE_EL24_TAP__PRE 0x26058 6059#define QAM_DQ_TAP_IM_EL24__A 0x14400516060#define QAM_DQ_TAP_IM_EL24__W 126061#define QAM_DQ_TAP_IM_EL24__M 0xFFF6062#define QAM_DQ_TAP_IM_EL24__PRE 0x26063 6064#define QAM_DQ_TAP_IM_EL24_TAP__B 06065#define QAM_DQ_TAP_IM_EL24_TAP__W 126066#define QAM_DQ_TAP_IM_EL24_TAP__M 0xFFF6067#define QAM_DQ_TAP_IM_EL24_TAP__PRE 0x26068 6069#define QAM_DQ_TAP_RE_EL25__A 0x14400526070#define QAM_DQ_TAP_RE_EL25__W 126071#define QAM_DQ_TAP_RE_EL25__M 0xFFF6072#define QAM_DQ_TAP_RE_EL25__PRE 0x26073 6074#define QAM_DQ_TAP_RE_EL25_TAP__B 06075#define QAM_DQ_TAP_RE_EL25_TAP__W 126076#define QAM_DQ_TAP_RE_EL25_TAP__M 0xFFF6077#define QAM_DQ_TAP_RE_EL25_TAP__PRE 0x26078 6079#define QAM_DQ_TAP_IM_EL25__A 0x14400536080#define QAM_DQ_TAP_IM_EL25__W 126081#define QAM_DQ_TAP_IM_EL25__M 0xFFF6082#define QAM_DQ_TAP_IM_EL25__PRE 0x26083 6084#define QAM_DQ_TAP_IM_EL25_TAP__B 06085#define QAM_DQ_TAP_IM_EL25_TAP__W 126086#define QAM_DQ_TAP_IM_EL25_TAP__M 0xFFF6087#define QAM_DQ_TAP_IM_EL25_TAP__PRE 0x26088 6089#define QAM_DQ_TAP_RE_EL26__A 0x14400546090#define QAM_DQ_TAP_RE_EL26__W 126091#define QAM_DQ_TAP_RE_EL26__M 0xFFF6092#define QAM_DQ_TAP_RE_EL26__PRE 0x26093 6094#define QAM_DQ_TAP_RE_EL26_TAP__B 06095#define QAM_DQ_TAP_RE_EL26_TAP__W 126096#define QAM_DQ_TAP_RE_EL26_TAP__M 0xFFF6097#define QAM_DQ_TAP_RE_EL26_TAP__PRE 0x26098 6099#define QAM_DQ_TAP_IM_EL26__A 0x14400556100#define QAM_DQ_TAP_IM_EL26__W 126101#define QAM_DQ_TAP_IM_EL26__M 0xFFF6102#define QAM_DQ_TAP_IM_EL26__PRE 0x26103 6104#define QAM_DQ_TAP_IM_EL26_TAP__B 06105#define QAM_DQ_TAP_IM_EL26_TAP__W 126106#define QAM_DQ_TAP_IM_EL26_TAP__M 0xFFF6107#define QAM_DQ_TAP_IM_EL26_TAP__PRE 0x26108 6109#define QAM_DQ_TAP_RE_EL27__A 0x14400566110#define QAM_DQ_TAP_RE_EL27__W 126111#define QAM_DQ_TAP_RE_EL27__M 0xFFF6112#define QAM_DQ_TAP_RE_EL27__PRE 0x26113 6114#define QAM_DQ_TAP_RE_EL27_TAP__B 06115#define QAM_DQ_TAP_RE_EL27_TAP__W 126116#define QAM_DQ_TAP_RE_EL27_TAP__M 0xFFF6117#define QAM_DQ_TAP_RE_EL27_TAP__PRE 0x26118 6119#define QAM_DQ_TAP_IM_EL27__A 0x14400576120#define QAM_DQ_TAP_IM_EL27__W 126121#define QAM_DQ_TAP_IM_EL27__M 0xFFF6122#define QAM_DQ_TAP_IM_EL27__PRE 0x26123 6124#define QAM_DQ_TAP_IM_EL27_TAP__B 06125#define QAM_DQ_TAP_IM_EL27_TAP__W 126126#define QAM_DQ_TAP_IM_EL27_TAP__M 0xFFF6127#define QAM_DQ_TAP_IM_EL27_TAP__PRE 0x26128 6129#define QAM_LC_COMM_EXEC__A 0x14500006130#define QAM_LC_COMM_EXEC__W 26131#define QAM_LC_COMM_EXEC__M 0x36132#define QAM_LC_COMM_EXEC__PRE 0x06133#define QAM_LC_COMM_EXEC_STOP 0x06134#define QAM_LC_COMM_EXEC_ACTIVE 0x16135#define QAM_LC_COMM_EXEC_HOLD 0x26136 6137#define QAM_LC_COMM_MB__A 0x14500026138#define QAM_LC_COMM_MB__W 26139#define QAM_LC_COMM_MB__M 0x36140#define QAM_LC_COMM_MB__PRE 0x06141#define QAM_LC_COMM_MB_CTL__B 06142#define QAM_LC_COMM_MB_CTL__W 16143#define QAM_LC_COMM_MB_CTL__M 0x16144#define QAM_LC_COMM_MB_CTL__PRE 0x06145#define QAM_LC_COMM_MB_CTL_OFF 0x06146#define QAM_LC_COMM_MB_CTL_ON 0x16147#define QAM_LC_COMM_MB_OBS__B 16148#define QAM_LC_COMM_MB_OBS__W 16149#define QAM_LC_COMM_MB_OBS__M 0x26150#define QAM_LC_COMM_MB_OBS__PRE 0x06151#define QAM_LC_COMM_MB_OBS_OFF 0x06152#define QAM_LC_COMM_MB_OBS_ON 0x26153 6154#define QAM_LC_COMM_INT_REQ__A 0x14500036155#define QAM_LC_COMM_INT_REQ__W 16156#define QAM_LC_COMM_INT_REQ__M 0x16157#define QAM_LC_COMM_INT_REQ__PRE 0x06158#define QAM_LC_COMM_INT_STA__A 0x14500056159#define QAM_LC_COMM_INT_STA__W 36160#define QAM_LC_COMM_INT_STA__M 0x76161#define QAM_LC_COMM_INT_STA__PRE 0x06162 6163#define QAM_LC_COMM_INT_STA_READY__B 06164#define QAM_LC_COMM_INT_STA_READY__W 16165#define QAM_LC_COMM_INT_STA_READY__M 0x16166#define QAM_LC_COMM_INT_STA_READY__PRE 0x06167 6168#define QAM_LC_COMM_INT_STA_OVERFLOW__B 16169#define QAM_LC_COMM_INT_STA_OVERFLOW__W 16170#define QAM_LC_COMM_INT_STA_OVERFLOW__M 0x26171#define QAM_LC_COMM_INT_STA_OVERFLOW__PRE 0x06172 6173#define QAM_LC_COMM_INT_STA_FREQ_WRAP__B 26174#define QAM_LC_COMM_INT_STA_FREQ_WRAP__W 16175#define QAM_LC_COMM_INT_STA_FREQ_WRAP__M 0x46176#define QAM_LC_COMM_INT_STA_FREQ_WRAP__PRE 0x06177 6178#define QAM_LC_COMM_INT_MSK__A 0x14500066179#define QAM_LC_COMM_INT_MSK__W 36180#define QAM_LC_COMM_INT_MSK__M 0x76181#define QAM_LC_COMM_INT_MSK__PRE 0x06182#define QAM_LC_COMM_INT_MSK_READY__B 06183#define QAM_LC_COMM_INT_MSK_READY__W 16184#define QAM_LC_COMM_INT_MSK_READY__M 0x16185#define QAM_LC_COMM_INT_MSK_READY__PRE 0x06186#define QAM_LC_COMM_INT_MSK_OVERFLOW__B 16187#define QAM_LC_COMM_INT_MSK_OVERFLOW__W 16188#define QAM_LC_COMM_INT_MSK_OVERFLOW__M 0x26189#define QAM_LC_COMM_INT_MSK_OVERFLOW__PRE 0x06190#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__B 26191#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__W 16192#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__M 0x46193#define QAM_LC_COMM_INT_MSK_FREQ_WRAP__PRE 0x06194 6195#define QAM_LC_COMM_INT_STM__A 0x14500076196#define QAM_LC_COMM_INT_STM__W 36197#define QAM_LC_COMM_INT_STM__M 0x76198#define QAM_LC_COMM_INT_STM__PRE 0x06199#define QAM_LC_COMM_INT_STM_READY__B 06200#define QAM_LC_COMM_INT_STM_READY__W 16201#define QAM_LC_COMM_INT_STM_READY__M 0x16202#define QAM_LC_COMM_INT_STM_READY__PRE 0x06203#define QAM_LC_COMM_INT_STM_OVERFLOW__B 16204#define QAM_LC_COMM_INT_STM_OVERFLOW__W 16205#define QAM_LC_COMM_INT_STM_OVERFLOW__M 0x26206#define QAM_LC_COMM_INT_STM_OVERFLOW__PRE 0x06207#define QAM_LC_COMM_INT_STM_FREQ_WRAP__B 26208#define QAM_LC_COMM_INT_STM_FREQ_WRAP__W 16209#define QAM_LC_COMM_INT_STM_FREQ_WRAP__M 0x46210#define QAM_LC_COMM_INT_STM_FREQ_WRAP__PRE 0x06211 6212#define QAM_LC_MODE__A 0x14500106213#define QAM_LC_MODE__W 36214#define QAM_LC_MODE__M 0x76215#define QAM_LC_MODE__PRE 0x76216 6217#define QAM_LC_MODE_ENABLE_A__B 06218#define QAM_LC_MODE_ENABLE_A__W 16219#define QAM_LC_MODE_ENABLE_A__M 0x16220#define QAM_LC_MODE_ENABLE_A__PRE 0x16221 6222#define QAM_LC_MODE_ENABLE_F__B 16223#define QAM_LC_MODE_ENABLE_F__W 16224#define QAM_LC_MODE_ENABLE_F__M 0x26225#define QAM_LC_MODE_ENABLE_F__PRE 0x26226 6227#define QAM_LC_MODE_ENABLE_R__B 26228#define QAM_LC_MODE_ENABLE_R__W 16229#define QAM_LC_MODE_ENABLE_R__M 0x46230#define QAM_LC_MODE_ENABLE_R__PRE 0x46231 6232#define QAM_LC_CA__A 0x14500116233#define QAM_LC_CA__W 66234#define QAM_LC_CA__M 0x3F6235#define QAM_LC_CA__PRE 0x286236 6237#define QAM_LC_CA_COEF__B 06238#define QAM_LC_CA_COEF__W 66239#define QAM_LC_CA_COEF__M 0x3F6240#define QAM_LC_CA_COEF__PRE 0x286241 6242#define QAM_LC_CF__A 0x14500126243#define QAM_LC_CF__W 86244#define QAM_LC_CF__M 0xFF6245#define QAM_LC_CF__PRE 0x8C6246 6247#define QAM_LC_CF_COEF__B 06248#define QAM_LC_CF_COEF__W 86249#define QAM_LC_CF_COEF__M 0xFF6250#define QAM_LC_CF_COEF__PRE 0x8C6251 6252#define QAM_LC_CF1__A 0x14500136253#define QAM_LC_CF1__W 86254#define QAM_LC_CF1__M 0xFF6255#define QAM_LC_CF1__PRE 0x1E6256 6257#define QAM_LC_CF1_COEF__B 06258#define QAM_LC_CF1_COEF__W 86259#define QAM_LC_CF1_COEF__M 0xFF6260#define QAM_LC_CF1_COEF__PRE 0x1E6261 6262#define QAM_LC_CP__A 0x14500146263#define QAM_LC_CP__W 86264#define QAM_LC_CP__M 0xFF6265#define QAM_LC_CP__PRE 0x786266 6267#define QAM_LC_CP_COEF__B 06268#define QAM_LC_CP_COEF__W 86269#define QAM_LC_CP_COEF__M 0xFF6270#define QAM_LC_CP_COEF__PRE 0x786271 6272#define QAM_LC_CI__A 0x14500156273#define QAM_LC_CI__W 86274#define QAM_LC_CI__M 0xFF6275#define QAM_LC_CI__PRE 0x466276 6277#define QAM_LC_CI_COEF__B 06278#define QAM_LC_CI_COEF__W 86279#define QAM_LC_CI_COEF__M 0xFF6280#define QAM_LC_CI_COEF__PRE 0x466281 6282#define QAM_LC_EP__A 0x14500166283#define QAM_LC_EP__W 66284#define QAM_LC_EP__M 0x3F6285#define QAM_LC_EP__PRE 0x06286 6287#define QAM_LC_EP_COEF__B 06288#define QAM_LC_EP_COEF__W 66289#define QAM_LC_EP_COEF__M 0x3F6290#define QAM_LC_EP_COEF__PRE 0x06291 6292#define QAM_LC_EI__A 0x14500176293#define QAM_LC_EI__W 66294#define QAM_LC_EI__M 0x3F6295#define QAM_LC_EI__PRE 0x06296 6297#define QAM_LC_EI_COEF__B 06298#define QAM_LC_EI_COEF__W 66299#define QAM_LC_EI_COEF__M 0x3F6300#define QAM_LC_EI_COEF__PRE 0x06301 6302#define QAM_LC_QUAL_TAB0__A 0x14500186303#define QAM_LC_QUAL_TAB0__W 56304#define QAM_LC_QUAL_TAB0__M 0x1F6305#define QAM_LC_QUAL_TAB0__PRE 0x16306 6307#define QAM_LC_QUAL_TAB0_VALUE__B 06308#define QAM_LC_QUAL_TAB0_VALUE__W 56309#define QAM_LC_QUAL_TAB0_VALUE__M 0x1F6310#define QAM_LC_QUAL_TAB0_VALUE__PRE 0x16311 6312#define QAM_LC_QUAL_TAB1__A 0x14500196313#define QAM_LC_QUAL_TAB1__W 56314#define QAM_LC_QUAL_TAB1__M 0x1F6315#define QAM_LC_QUAL_TAB1__PRE 0x16316 6317#define QAM_LC_QUAL_TAB1_VALUE__B 06318#define QAM_LC_QUAL_TAB1_VALUE__W 56319#define QAM_LC_QUAL_TAB1_VALUE__M 0x1F6320#define QAM_LC_QUAL_TAB1_VALUE__PRE 0x16321 6322#define QAM_LC_QUAL_TAB2__A 0x145001A6323#define QAM_LC_QUAL_TAB2__W 56324#define QAM_LC_QUAL_TAB2__M 0x1F6325#define QAM_LC_QUAL_TAB2__PRE 0x16326 6327#define QAM_LC_QUAL_TAB2_VALUE__B 06328#define QAM_LC_QUAL_TAB2_VALUE__W 56329#define QAM_LC_QUAL_TAB2_VALUE__M 0x1F6330#define QAM_LC_QUAL_TAB2_VALUE__PRE 0x16331 6332#define QAM_LC_QUAL_TAB3__A 0x145001B6333#define QAM_LC_QUAL_TAB3__W 56334#define QAM_LC_QUAL_TAB3__M 0x1F6335#define QAM_LC_QUAL_TAB3__PRE 0x16336 6337#define QAM_LC_QUAL_TAB3_VALUE__B 06338#define QAM_LC_QUAL_TAB3_VALUE__W 56339#define QAM_LC_QUAL_TAB3_VALUE__M 0x1F6340#define QAM_LC_QUAL_TAB3_VALUE__PRE 0x16341 6342#define QAM_LC_QUAL_TAB4__A 0x145001C6343#define QAM_LC_QUAL_TAB4__W 56344#define QAM_LC_QUAL_TAB4__M 0x1F6345#define QAM_LC_QUAL_TAB4__PRE 0x16346 6347#define QAM_LC_QUAL_TAB4_VALUE__B 06348#define QAM_LC_QUAL_TAB4_VALUE__W 56349#define QAM_LC_QUAL_TAB4_VALUE__M 0x1F6350#define QAM_LC_QUAL_TAB4_VALUE__PRE 0x16351 6352#define QAM_LC_QUAL_TAB5__A 0x145001D6353#define QAM_LC_QUAL_TAB5__W 56354#define QAM_LC_QUAL_TAB5__M 0x1F6355#define QAM_LC_QUAL_TAB5__PRE 0x16356 6357#define QAM_LC_QUAL_TAB5_VALUE__B 06358#define QAM_LC_QUAL_TAB5_VALUE__W 56359#define QAM_LC_QUAL_TAB5_VALUE__M 0x1F6360#define QAM_LC_QUAL_TAB5_VALUE__PRE 0x16361 6362#define QAM_LC_QUAL_TAB6__A 0x145001E6363#define QAM_LC_QUAL_TAB6__W 56364#define QAM_LC_QUAL_TAB6__M 0x1F6365#define QAM_LC_QUAL_TAB6__PRE 0x16366 6367#define QAM_LC_QUAL_TAB6_VALUE__B 06368#define QAM_LC_QUAL_TAB6_VALUE__W 56369#define QAM_LC_QUAL_TAB6_VALUE__M 0x1F6370#define QAM_LC_QUAL_TAB6_VALUE__PRE 0x16371 6372#define QAM_LC_QUAL_TAB8__A 0x145001F6373#define QAM_LC_QUAL_TAB8__W 56374#define QAM_LC_QUAL_TAB8__M 0x1F6375#define QAM_LC_QUAL_TAB8__PRE 0x16376 6377#define QAM_LC_QUAL_TAB8_VALUE__B 06378#define QAM_LC_QUAL_TAB8_VALUE__W 56379#define QAM_LC_QUAL_TAB8_VALUE__M 0x1F6380#define QAM_LC_QUAL_TAB8_VALUE__PRE 0x16381 6382#define QAM_LC_QUAL_TAB9__A 0x14500206383#define QAM_LC_QUAL_TAB9__W 56384#define QAM_LC_QUAL_TAB9__M 0x1F6385#define QAM_LC_QUAL_TAB9__PRE 0x16386 6387#define QAM_LC_QUAL_TAB9_VALUE__B 06388#define QAM_LC_QUAL_TAB9_VALUE__W 56389#define QAM_LC_QUAL_TAB9_VALUE__M 0x1F6390#define QAM_LC_QUAL_TAB9_VALUE__PRE 0x16391 6392#define QAM_LC_QUAL_TAB10__A 0x14500216393#define QAM_LC_QUAL_TAB10__W 56394#define QAM_LC_QUAL_TAB10__M 0x1F6395#define QAM_LC_QUAL_TAB10__PRE 0x16396 6397#define QAM_LC_QUAL_TAB10_VALUE__B 06398#define QAM_LC_QUAL_TAB10_VALUE__W 56399#define QAM_LC_QUAL_TAB10_VALUE__M 0x1F6400#define QAM_LC_QUAL_TAB10_VALUE__PRE 0x16401 6402#define QAM_LC_QUAL_TAB12__A 0x14500226403#define QAM_LC_QUAL_TAB12__W 56404#define QAM_LC_QUAL_TAB12__M 0x1F6405#define QAM_LC_QUAL_TAB12__PRE 0x16406 6407#define QAM_LC_QUAL_TAB12_VALUE__B 06408#define QAM_LC_QUAL_TAB12_VALUE__W 56409#define QAM_LC_QUAL_TAB12_VALUE__M 0x1F6410#define QAM_LC_QUAL_TAB12_VALUE__PRE 0x16411 6412#define QAM_LC_QUAL_TAB15__A 0x14500236413#define QAM_LC_QUAL_TAB15__W 56414#define QAM_LC_QUAL_TAB15__M 0x1F6415#define QAM_LC_QUAL_TAB15__PRE 0x16416 6417#define QAM_LC_QUAL_TAB15_VALUE__B 06418#define QAM_LC_QUAL_TAB15_VALUE__W 56419#define QAM_LC_QUAL_TAB15_VALUE__M 0x1F6420#define QAM_LC_QUAL_TAB15_VALUE__PRE 0x16421 6422#define QAM_LC_QUAL_TAB16__A 0x14500246423#define QAM_LC_QUAL_TAB16__W 56424#define QAM_LC_QUAL_TAB16__M 0x1F6425#define QAM_LC_QUAL_TAB16__PRE 0x16426 6427#define QAM_LC_QUAL_TAB16_VALUE__B 06428#define QAM_LC_QUAL_TAB16_VALUE__W 56429#define QAM_LC_QUAL_TAB16_VALUE__M 0x1F6430#define QAM_LC_QUAL_TAB16_VALUE__PRE 0x16431 6432#define QAM_LC_QUAL_TAB20__A 0x14500256433#define QAM_LC_QUAL_TAB20__W 56434#define QAM_LC_QUAL_TAB20__M 0x1F6435#define QAM_LC_QUAL_TAB20__PRE 0x16436 6437#define QAM_LC_QUAL_TAB20_VALUE__B 06438#define QAM_LC_QUAL_TAB20_VALUE__W 56439#define QAM_LC_QUAL_TAB20_VALUE__M 0x1F6440#define QAM_LC_QUAL_TAB20_VALUE__PRE 0x16441 6442#define QAM_LC_QUAL_TAB25__A 0x14500266443#define QAM_LC_QUAL_TAB25__W 56444#define QAM_LC_QUAL_TAB25__M 0x1F6445#define QAM_LC_QUAL_TAB25__PRE 0x16446 6447#define QAM_LC_QUAL_TAB25_VALUE__B 06448#define QAM_LC_QUAL_TAB25_VALUE__W 56449#define QAM_LC_QUAL_TAB25_VALUE__M 0x1F6450#define QAM_LC_QUAL_TAB25_VALUE__PRE 0x16451 6452#define QAM_LC_EQ_TIMING__A 0x14500276453#define QAM_LC_EQ_TIMING__W 106454#define QAM_LC_EQ_TIMING__M 0x3FF6455#define QAM_LC_EQ_TIMING__PRE 0x06456 6457#define QAM_LC_EQ_TIMING_OFFS__B 06458#define QAM_LC_EQ_TIMING_OFFS__W 106459#define QAM_LC_EQ_TIMING_OFFS__M 0x3FF6460#define QAM_LC_EQ_TIMING_OFFS__PRE 0x06461 6462#define QAM_LC_LPF_FACTORP__A 0x14500286463#define QAM_LC_LPF_FACTORP__W 36464#define QAM_LC_LPF_FACTORP__M 0x76465#define QAM_LC_LPF_FACTORP__PRE 0x36466 6467#define QAM_LC_LPF_FACTORP_FACTOR__B 06468#define QAM_LC_LPF_FACTORP_FACTOR__W 36469#define QAM_LC_LPF_FACTORP_FACTOR__M 0x76470#define QAM_LC_LPF_FACTORP_FACTOR__PRE 0x36471 6472#define QAM_LC_LPF_FACTORI__A 0x14500296473#define QAM_LC_LPF_FACTORI__W 36474#define QAM_LC_LPF_FACTORI__M 0x76475#define QAM_LC_LPF_FACTORI__PRE 0x36476 6477#define QAM_LC_LPF_FACTORI_FACTOR__B 06478#define QAM_LC_LPF_FACTORI_FACTOR__W 36479#define QAM_LC_LPF_FACTORI_FACTOR__M 0x76480#define QAM_LC_LPF_FACTORI_FACTOR__PRE 0x36481 6482#define QAM_LC_RATE_LIMIT__A 0x145002A6483#define QAM_LC_RATE_LIMIT__W 26484#define QAM_LC_RATE_LIMIT__M 0x36485#define QAM_LC_RATE_LIMIT__PRE 0x36486 6487#define QAM_LC_RATE_LIMIT_LIMIT__B 06488#define QAM_LC_RATE_LIMIT_LIMIT__W 26489#define QAM_LC_RATE_LIMIT_LIMIT__M 0x36490#define QAM_LC_RATE_LIMIT_LIMIT__PRE 0x36491 6492#define QAM_LC_SYMBOL_FREQ__A 0x145002B6493#define QAM_LC_SYMBOL_FREQ__W 106494#define QAM_LC_SYMBOL_FREQ__M 0x3FF6495#define QAM_LC_SYMBOL_FREQ__PRE 0x1996496 6497#define QAM_LC_SYMBOL_FREQ_FREQ__B 06498#define QAM_LC_SYMBOL_FREQ_FREQ__W 106499#define QAM_LC_SYMBOL_FREQ_FREQ__M 0x3FF6500#define QAM_LC_SYMBOL_FREQ_FREQ__PRE 0x1996501#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_64 0x1976502#define QAM_LC_SYMBOL_FREQ_FREQ_QAM_B_256 0x1B26503 6504#define QAM_LC_MTA_LENGTH__A 0x145002C6505#define QAM_LC_MTA_LENGTH__W 26506#define QAM_LC_MTA_LENGTH__M 0x36507#define QAM_LC_MTA_LENGTH__PRE 0x26508 6509#define QAM_LC_MTA_LENGTH_LENGTH__B 06510#define QAM_LC_MTA_LENGTH_LENGTH__W 26511#define QAM_LC_MTA_LENGTH_LENGTH__M 0x36512#define QAM_LC_MTA_LENGTH_LENGTH__PRE 0x26513 6514#define QAM_LC_AMP_ACCU__A 0x145002D6515#define QAM_LC_AMP_ACCU__W 146516#define QAM_LC_AMP_ACCU__M 0x3FFF6517#define QAM_LC_AMP_ACCU__PRE 0x6006518 6519#define QAM_LC_AMP_ACCU_ACCU__B 06520#define QAM_LC_AMP_ACCU_ACCU__W 146521#define QAM_LC_AMP_ACCU_ACCU__M 0x3FFF6522#define QAM_LC_AMP_ACCU_ACCU__PRE 0x6006523 6524#define QAM_LC_FREQ_ACCU__A 0x145002E6525#define QAM_LC_FREQ_ACCU__W 106526#define QAM_LC_FREQ_ACCU__M 0x3FF6527#define QAM_LC_FREQ_ACCU__PRE 0x06528 6529#define QAM_LC_FREQ_ACCU_ACCU__B 06530#define QAM_LC_FREQ_ACCU_ACCU__W 106531#define QAM_LC_FREQ_ACCU_ACCU__M 0x3FF6532#define QAM_LC_FREQ_ACCU_ACCU__PRE 0x06533 6534#define QAM_LC_RATE_ACCU__A 0x145002F6535#define QAM_LC_RATE_ACCU__W 106536#define QAM_LC_RATE_ACCU__M 0x3FF6537#define QAM_LC_RATE_ACCU__PRE 0x06538 6539#define QAM_LC_RATE_ACCU_ACCU__B 06540#define QAM_LC_RATE_ACCU_ACCU__W 106541#define QAM_LC_RATE_ACCU_ACCU__M 0x3FF6542#define QAM_LC_RATE_ACCU_ACCU__PRE 0x06543 6544#define QAM_LC_AMPLITUDE__A 0x14500306545#define QAM_LC_AMPLITUDE__W 106546#define QAM_LC_AMPLITUDE__M 0x3FF6547#define QAM_LC_AMPLITUDE__PRE 0x06548 6549#define QAM_LC_AMPLITUDE_SIZE__B 06550#define QAM_LC_AMPLITUDE_SIZE__W 106551#define QAM_LC_AMPLITUDE_SIZE__M 0x3FF6552#define QAM_LC_AMPLITUDE_SIZE__PRE 0x06553 6554#define QAM_LC_RAD_ERROR__A 0x14500316555#define QAM_LC_RAD_ERROR__W 106556#define QAM_LC_RAD_ERROR__M 0x3FF6557#define QAM_LC_RAD_ERROR__PRE 0x06558 6559#define QAM_LC_RAD_ERROR_SIZE__B 06560#define QAM_LC_RAD_ERROR_SIZE__W 106561#define QAM_LC_RAD_ERROR_SIZE__M 0x3FF6562#define QAM_LC_RAD_ERROR_SIZE__PRE 0x06563 6564#define QAM_LC_FREQ_OFFS__A 0x14500326565#define QAM_LC_FREQ_OFFS__W 106566#define QAM_LC_FREQ_OFFS__M 0x3FF6567#define QAM_LC_FREQ_OFFS__PRE 0x06568 6569#define QAM_LC_FREQ_OFFS_OFFS__B 06570#define QAM_LC_FREQ_OFFS_OFFS__W 106571#define QAM_LC_FREQ_OFFS_OFFS__M 0x3FF6572#define QAM_LC_FREQ_OFFS_OFFS__PRE 0x06573 6574#define QAM_LC_PHASE_ERROR__A 0x14500336575#define QAM_LC_PHASE_ERROR__W 106576#define QAM_LC_PHASE_ERROR__M 0x3FF6577#define QAM_LC_PHASE_ERROR__PRE 0x06578 6579#define QAM_LC_PHASE_ERROR_SIZE__B 06580#define QAM_LC_PHASE_ERROR_SIZE__W 106581#define QAM_LC_PHASE_ERROR_SIZE__M 0x3FF6582#define QAM_LC_PHASE_ERROR_SIZE__PRE 0x06583 6584#define QAM_VD_COMM_EXEC__A 0x14600006585#define QAM_VD_COMM_EXEC__W 26586#define QAM_VD_COMM_EXEC__M 0x36587#define QAM_VD_COMM_EXEC__PRE 0x06588#define QAM_VD_COMM_EXEC_STOP 0x06589#define QAM_VD_COMM_EXEC_ACTIVE 0x16590#define QAM_VD_COMM_EXEC_HOLD 0x26591 6592#define QAM_VD_COMM_MB__A 0x14600026593#define QAM_VD_COMM_MB__W 26594#define QAM_VD_COMM_MB__M 0x36595#define QAM_VD_COMM_MB__PRE 0x06596#define QAM_VD_COMM_MB_CTL__B 06597#define QAM_VD_COMM_MB_CTL__W 16598#define QAM_VD_COMM_MB_CTL__M 0x16599#define QAM_VD_COMM_MB_CTL__PRE 0x06600#define QAM_VD_COMM_MB_CTL_OFF 0x06601#define QAM_VD_COMM_MB_CTL_ON 0x16602#define QAM_VD_COMM_MB_OBS__B 16603#define QAM_VD_COMM_MB_OBS__W 16604#define QAM_VD_COMM_MB_OBS__M 0x26605#define QAM_VD_COMM_MB_OBS__PRE 0x06606#define QAM_VD_COMM_MB_OBS_OFF 0x06607#define QAM_VD_COMM_MB_OBS_ON 0x26608 6609#define QAM_VD_COMM_INT_REQ__A 0x14600036610#define QAM_VD_COMM_INT_REQ__W 16611#define QAM_VD_COMM_INT_REQ__M 0x16612#define QAM_VD_COMM_INT_REQ__PRE 0x06613#define QAM_VD_COMM_INT_STA__A 0x14600056614#define QAM_VD_COMM_INT_STA__W 26615#define QAM_VD_COMM_INT_STA__M 0x36616#define QAM_VD_COMM_INT_STA__PRE 0x06617 6618#define QAM_VD_COMM_INT_STA_LOCK_INT__B 06619#define QAM_VD_COMM_INT_STA_LOCK_INT__W 16620#define QAM_VD_COMM_INT_STA_LOCK_INT__M 0x16621#define QAM_VD_COMM_INT_STA_LOCK_INT__PRE 0x06622 6623#define QAM_VD_COMM_INT_STA_PERIOD_INT__B 16624#define QAM_VD_COMM_INT_STA_PERIOD_INT__W 16625#define QAM_VD_COMM_INT_STA_PERIOD_INT__M 0x26626#define QAM_VD_COMM_INT_STA_PERIOD_INT__PRE 0x06627 6628#define QAM_VD_COMM_INT_MSK__A 0x14600066629#define QAM_VD_COMM_INT_MSK__W 26630#define QAM_VD_COMM_INT_MSK__M 0x36631#define QAM_VD_COMM_INT_MSK__PRE 0x06632#define QAM_VD_COMM_INT_MSK_LOCK_INT__B 06633#define QAM_VD_COMM_INT_MSK_LOCK_INT__W 16634#define QAM_VD_COMM_INT_MSK_LOCK_INT__M 0x16635#define QAM_VD_COMM_INT_MSK_LOCK_INT__PRE 0x06636#define QAM_VD_COMM_INT_MSK_PERIOD_INT__B 16637#define QAM_VD_COMM_INT_MSK_PERIOD_INT__W 16638#define QAM_VD_COMM_INT_MSK_PERIOD_INT__M 0x26639#define QAM_VD_COMM_INT_MSK_PERIOD_INT__PRE 0x06640 6641#define QAM_VD_COMM_INT_STM__A 0x14600076642#define QAM_VD_COMM_INT_STM__W 26643#define QAM_VD_COMM_INT_STM__M 0x36644#define QAM_VD_COMM_INT_STM__PRE 0x06645#define QAM_VD_COMM_INT_STM_LOCK_INT__B 06646#define QAM_VD_COMM_INT_STM_LOCK_INT__W 16647#define QAM_VD_COMM_INT_STM_LOCK_INT__M 0x16648#define QAM_VD_COMM_INT_STM_LOCK_INT__PRE 0x06649#define QAM_VD_COMM_INT_STM_PERIOD_INT__B 16650#define QAM_VD_COMM_INT_STM_PERIOD_INT__W 16651#define QAM_VD_COMM_INT_STM_PERIOD_INT__M 0x26652#define QAM_VD_COMM_INT_STM_PERIOD_INT__PRE 0x06653 6654#define QAM_VD_STATUS__A 0x14600106655#define QAM_VD_STATUS__W 16656#define QAM_VD_STATUS__M 0x16657#define QAM_VD_STATUS__PRE 0x06658 6659#define QAM_VD_STATUS_LOCK__B 06660#define QAM_VD_STATUS_LOCK__W 16661#define QAM_VD_STATUS_LOCK__M 0x16662#define QAM_VD_STATUS_LOCK__PRE 0x06663 6664#define QAM_VD_UNLOCK_CONTROL__A 0x14600116665#define QAM_VD_UNLOCK_CONTROL__W 16666#define QAM_VD_UNLOCK_CONTROL__M 0x16667#define QAM_VD_UNLOCK_CONTROL__PRE 0x06668 6669#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__B 06670#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__W 16671#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__M 0x16672#define QAM_VD_UNLOCK_CONTROL_UNLOCK_CTRL__PRE 0x06673 6674#define QAM_VD_MIN_VOTING_ROUNDS__A 0x14600126675#define QAM_VD_MIN_VOTING_ROUNDS__W 66676#define QAM_VD_MIN_VOTING_ROUNDS__M 0x3F6677#define QAM_VD_MIN_VOTING_ROUNDS__PRE 0x106678 6679#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__B 06680#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__W 66681#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__M 0x3F6682#define QAM_VD_MIN_VOTING_ROUNDS_ROUNDS__PRE 0x106683 6684#define QAM_VD_MAX_VOTING_ROUNDS__A 0x14600136685#define QAM_VD_MAX_VOTING_ROUNDS__W 66686#define QAM_VD_MAX_VOTING_ROUNDS__M 0x3F6687#define QAM_VD_MAX_VOTING_ROUNDS__PRE 0x106688 6689#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__B 06690#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__W 66691#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__M 0x3F6692#define QAM_VD_MAX_VOTING_ROUNDS_ROUNDS__PRE 0x106693 6694#define QAM_VD_TRACEBACK_DEPTH__A 0x14600146695#define QAM_VD_TRACEBACK_DEPTH__W 56696#define QAM_VD_TRACEBACK_DEPTH__M 0x1F6697#define QAM_VD_TRACEBACK_DEPTH__PRE 0x106698 6699#define QAM_VD_TRACEBACK_DEPTH_LENGTH__B 06700#define QAM_VD_TRACEBACK_DEPTH_LENGTH__W 56701#define QAM_VD_TRACEBACK_DEPTH_LENGTH__M 0x1F6702#define QAM_VD_TRACEBACK_DEPTH_LENGTH__PRE 0x106703 6704#define QAM_VD_UNLOCK__A 0x14600156705#define QAM_VD_UNLOCK__W 16706#define QAM_VD_UNLOCK__M 0x16707#define QAM_VD_UNLOCK__PRE 0x06708#define QAM_VD_MEASUREMENT_PERIOD__A 0x14600166709#define QAM_VD_MEASUREMENT_PERIOD__W 166710#define QAM_VD_MEASUREMENT_PERIOD__M 0xFFFF6711#define QAM_VD_MEASUREMENT_PERIOD__PRE 0x82366712 6713#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__B 06714#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__W 166715#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__M 0xFFFF6716#define QAM_VD_MEASUREMENT_PERIOD_PERIOD__PRE 0x82366717 6718#define QAM_VD_MEASUREMENT_PRESCALE__A 0x14600176719#define QAM_VD_MEASUREMENT_PRESCALE__W 166720#define QAM_VD_MEASUREMENT_PRESCALE__M 0xFFFF6721#define QAM_VD_MEASUREMENT_PRESCALE__PRE 0x46722 6723#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__B 06724#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__W 166725#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__M 0xFFFF6726#define QAM_VD_MEASUREMENT_PRESCALE_PRESCALE__PRE 0x46727 6728#define QAM_VD_DELTA_PATH_METRIC__A 0x14600186729#define QAM_VD_DELTA_PATH_METRIC__W 166730#define QAM_VD_DELTA_PATH_METRIC__M 0xFFFF6731#define QAM_VD_DELTA_PATH_METRIC__PRE 0xFFFF6732 6733#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__B 06734#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__W 126735#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__M 0xFFF6736#define QAM_VD_DELTA_PATH_METRIC_FIXED_MANT__PRE 0xFFF6737 6738#define QAM_VD_DELTA_PATH_METRIC_EXP__B 126739#define QAM_VD_DELTA_PATH_METRIC_EXP__W 46740#define QAM_VD_DELTA_PATH_METRIC_EXP__M 0xF0006741#define QAM_VD_DELTA_PATH_METRIC_EXP__PRE 0xF0006742 6743#define QAM_VD_NR_QSYM_ERRORS__A 0x14600196744#define QAM_VD_NR_QSYM_ERRORS__W 166745#define QAM_VD_NR_QSYM_ERRORS__M 0xFFFF6746#define QAM_VD_NR_QSYM_ERRORS__PRE 0xFFFF6747 6748#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__B 06749#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__W 126750#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__M 0xFFF6751#define QAM_VD_NR_QSYM_ERRORS_FIXED_MANT__PRE 0xFFF6752 6753#define QAM_VD_NR_QSYM_ERRORS_EXP__B 126754#define QAM_VD_NR_QSYM_ERRORS_EXP__W 46755#define QAM_VD_NR_QSYM_ERRORS_EXP__M 0xF0006756#define QAM_VD_NR_QSYM_ERRORS_EXP__PRE 0xF0006757 6758#define QAM_VD_NR_SYMBOL_ERRORS__A 0x146001A6759#define QAM_VD_NR_SYMBOL_ERRORS__W 166760#define QAM_VD_NR_SYMBOL_ERRORS__M 0xFFFF6761#define QAM_VD_NR_SYMBOL_ERRORS__PRE 0xFFFF6762 6763#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__B 06764#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__W 126765#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__M 0xFFF6766#define QAM_VD_NR_SYMBOL_ERRORS_FIXED_MANT__PRE 0xFFF6767 6768#define QAM_VD_NR_SYMBOL_ERRORS_EXP__B 126769#define QAM_VD_NR_SYMBOL_ERRORS_EXP__W 46770#define QAM_VD_NR_SYMBOL_ERRORS_EXP__M 0xF0006771#define QAM_VD_NR_SYMBOL_ERRORS_EXP__PRE 0xF0006772 6773#define QAM_VD_RELOCK_COUNT__A 0x146001B6774#define QAM_VD_RELOCK_COUNT__W 166775#define QAM_VD_RELOCK_COUNT__M 0xFFFF6776#define QAM_VD_RELOCK_COUNT__PRE 0x06777 6778#define QAM_VD_RELOCK_COUNT_COUNT__B 06779#define QAM_VD_RELOCK_COUNT_COUNT__W 86780#define QAM_VD_RELOCK_COUNT_COUNT__M 0xFF6781#define QAM_VD_RELOCK_COUNT_COUNT__PRE 0x06782 6783#define QAM_SY_COMM_EXEC__A 0x14700006784#define QAM_SY_COMM_EXEC__W 26785#define QAM_SY_COMM_EXEC__M 0x36786#define QAM_SY_COMM_EXEC__PRE 0x06787#define QAM_SY_COMM_EXEC_STOP 0x06788#define QAM_SY_COMM_EXEC_ACTIVE 0x16789#define QAM_SY_COMM_EXEC_HOLD 0x26790 6791#define QAM_SY_COMM_MB__A 0x14700026792#define QAM_SY_COMM_MB__W 26793#define QAM_SY_COMM_MB__M 0x36794#define QAM_SY_COMM_MB__PRE 0x06795#define QAM_SY_COMM_MB_CTL__B 06796#define QAM_SY_COMM_MB_CTL__W 16797#define QAM_SY_COMM_MB_CTL__M 0x16798#define QAM_SY_COMM_MB_CTL__PRE 0x06799#define QAM_SY_COMM_MB_CTL_OFF 0x06800#define QAM_SY_COMM_MB_CTL_ON 0x16801#define QAM_SY_COMM_MB_OBS__B 16802#define QAM_SY_COMM_MB_OBS__W 16803#define QAM_SY_COMM_MB_OBS__M 0x26804#define QAM_SY_COMM_MB_OBS__PRE 0x06805#define QAM_SY_COMM_MB_OBS_OFF 0x06806#define QAM_SY_COMM_MB_OBS_ON 0x26807 6808#define QAM_SY_COMM_INT_REQ__A 0x14700036809#define QAM_SY_COMM_INT_REQ__W 16810#define QAM_SY_COMM_INT_REQ__M 0x16811#define QAM_SY_COMM_INT_REQ__PRE 0x06812#define QAM_SY_COMM_INT_STA__A 0x14700056813#define QAM_SY_COMM_INT_STA__W 46814#define QAM_SY_COMM_INT_STA__M 0xF6815#define QAM_SY_COMM_INT_STA__PRE 0x06816 6817#define QAM_SY_COMM_INT_STA_LOCK_INT__B 06818#define QAM_SY_COMM_INT_STA_LOCK_INT__W 16819#define QAM_SY_COMM_INT_STA_LOCK_INT__M 0x16820#define QAM_SY_COMM_INT_STA_LOCK_INT__PRE 0x06821 6822#define QAM_SY_COMM_INT_STA_UNLOCK_INT__B 16823#define QAM_SY_COMM_INT_STA_UNLOCK_INT__W 16824#define QAM_SY_COMM_INT_STA_UNLOCK_INT__M 0x26825#define QAM_SY_COMM_INT_STA_UNLOCK_INT__PRE 0x06826 6827#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__B 26828#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__W 16829#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__M 0x46830#define QAM_SY_COMM_INT_STA_TIMEOUT_INT__PRE 0x06831 6832#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__B 36833#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__W 16834#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__M 0x86835#define QAM_SY_COMM_INT_STA_CTL_WORD_INT__PRE 0x06836 6837#define QAM_SY_COMM_INT_MSK__A 0x14700066838#define QAM_SY_COMM_INT_MSK__W 46839#define QAM_SY_COMM_INT_MSK__M 0xF6840#define QAM_SY_COMM_INT_MSK__PRE 0x06841#define QAM_SY_COMM_INT_MSK_LOCK_MSK__B 06842#define QAM_SY_COMM_INT_MSK_LOCK_MSK__W 16843#define QAM_SY_COMM_INT_MSK_LOCK_MSK__M 0x16844#define QAM_SY_COMM_INT_MSK_LOCK_MSK__PRE 0x06845#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__B 16846#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__W 16847#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__M 0x26848#define QAM_SY_COMM_INT_MSK_UNLOCK_MSK__PRE 0x06849#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__B 26850#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__W 16851#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__M 0x46852#define QAM_SY_COMM_INT_MSK_TIMEOUT_MSK__PRE 0x06853#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__B 36854#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__W 16855#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__M 0x86856#define QAM_SY_COMM_INT_MSK_CTL_WORD_MSK__PRE 0x06857 6858#define QAM_SY_COMM_INT_STM__A 0x14700076859#define QAM_SY_COMM_INT_STM__W 46860#define QAM_SY_COMM_INT_STM__M 0xF6861#define QAM_SY_COMM_INT_STM__PRE 0x06862#define QAM_SY_COMM_INT_STM_LOCK_MSK__B 06863#define QAM_SY_COMM_INT_STM_LOCK_MSK__W 16864#define QAM_SY_COMM_INT_STM_LOCK_MSK__M 0x16865#define QAM_SY_COMM_INT_STM_LOCK_MSK__PRE 0x06866#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__B 16867#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__W 16868#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__M 0x26869#define QAM_SY_COMM_INT_STM_UNLOCK_MSK__PRE 0x06870#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__B 26871#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__W 16872#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__M 0x46873#define QAM_SY_COMM_INT_STM_TIMEOUT_MSK__PRE 0x06874#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__B 36875#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__W 16876#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__M 0x86877#define QAM_SY_COMM_INT_STM_CTL_WORD_MSK__PRE 0x06878 6879#define QAM_SY_STATUS__A 0x14700106880#define QAM_SY_STATUS__W 26881#define QAM_SY_STATUS__M 0x36882#define QAM_SY_STATUS__PRE 0x06883 6884#define QAM_SY_STATUS_SYNC_STATE__B 06885#define QAM_SY_STATUS_SYNC_STATE__W 26886#define QAM_SY_STATUS_SYNC_STATE__M 0x36887#define QAM_SY_STATUS_SYNC_STATE__PRE 0x06888 6889#define QAM_SY_TIMEOUT__A 0x14700116890#define QAM_SY_TIMEOUT__W 166891#define QAM_SY_TIMEOUT__M 0xFFFF6892#define QAM_SY_TIMEOUT__PRE 0x3A986893 6894#define QAM_SY_SYNC_LWM__A 0x14700126895#define QAM_SY_SYNC_LWM__W 46896#define QAM_SY_SYNC_LWM__M 0xF6897#define QAM_SY_SYNC_LWM__PRE 0x26898 6899#define QAM_SY_SYNC_AWM__A 0x14700136900#define QAM_SY_SYNC_AWM__W 46901#define QAM_SY_SYNC_AWM__M 0xF6902#define QAM_SY_SYNC_AWM__PRE 0x36903 6904#define QAM_SY_SYNC_HWM__A 0x14700146905#define QAM_SY_SYNC_HWM__W 46906#define QAM_SY_SYNC_HWM__M 0xF6907#define QAM_SY_SYNC_HWM__PRE 0x56908 6909#define QAM_SY_UNLOCK__A 0x14700156910#define QAM_SY_UNLOCK__W 16911#define QAM_SY_UNLOCK__M 0x16912#define QAM_SY_UNLOCK__PRE 0x06913#define QAM_SY_CONTROL_WORD__A 0x14700166914#define QAM_SY_CONTROL_WORD__W 46915#define QAM_SY_CONTROL_WORD__M 0xF6916#define QAM_SY_CONTROL_WORD__PRE 0x06917 6918#define QAM_SY_CONTROL_WORD_CTRL_WORD__B 06919#define QAM_SY_CONTROL_WORD_CTRL_WORD__W 46920#define QAM_SY_CONTROL_WORD_CTRL_WORD__M 0xF6921#define QAM_SY_CONTROL_WORD_CTRL_WORD__PRE 0x06922 6923#define QAM_VD_ISS_RAM__A 0x14800006924 6925#define QAM_VD_QSS_RAM__A 0x14900006926 6927#define QAM_VD_SYM_RAM__A 0x14A00006928 6929#define SCU_COMM_EXEC__A 0x8000006930#define SCU_COMM_EXEC__W 26931#define SCU_COMM_EXEC__M 0x36932#define SCU_COMM_EXEC__PRE 0x06933#define SCU_COMM_EXEC_STOP 0x06934#define SCU_COMM_EXEC_ACTIVE 0x16935#define SCU_COMM_EXEC_HOLD 0x26936 6937#define SCU_COMM_STATE__A 0x8000016938#define SCU_COMM_STATE__W 166939#define SCU_COMM_STATE__M 0xFFFF6940#define SCU_COMM_STATE__PRE 0x06941 6942#define SCU_COMM_STATE_COMM_STATE__B 06943#define SCU_COMM_STATE_COMM_STATE__W 166944#define SCU_COMM_STATE_COMM_STATE__M 0xFFFF6945#define SCU_COMM_STATE_COMM_STATE__PRE 0x06946 6947#define SCU_TOP_COMM_EXEC__A 0x8100006948#define SCU_TOP_COMM_EXEC__W 26949#define SCU_TOP_COMM_EXEC__M 0x36950#define SCU_TOP_COMM_EXEC__PRE 0x06951#define SCU_TOP_COMM_EXEC_STOP 0x06952#define SCU_TOP_COMM_EXEC_ACTIVE 0x16953#define SCU_TOP_COMM_EXEC_HOLD 0x26954 6955#define SCU_TOP_COMM_STATE__A 0x8100016956#define SCU_TOP_COMM_STATE__W 166957#define SCU_TOP_COMM_STATE__M 0xFFFF6958#define SCU_TOP_COMM_STATE__PRE 0x06959#define SCU_TOP_MWAIT_CTR__A 0x8100106960#define SCU_TOP_MWAIT_CTR__W 26961#define SCU_TOP_MWAIT_CTR__M 0x36962#define SCU_TOP_MWAIT_CTR__PRE 0x06963 6964#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__B 06965#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__W 16966#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__M 0x16967#define SCU_TOP_MWAIT_CTR_MWAIT_SEL__PRE 0x06968#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_OFF 0x06969#define SCU_TOP_MWAIT_CTR_MWAIT_SEL_TR_MW_ON 0x16970 6971#define SCU_TOP_MWAIT_CTR_READY_DIS__B 16972#define SCU_TOP_MWAIT_CTR_READY_DIS__W 16973#define SCU_TOP_MWAIT_CTR_READY_DIS__M 0x26974#define SCU_TOP_MWAIT_CTR_READY_DIS__PRE 0x06975#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_ON 0x06976#define SCU_TOP_MWAIT_CTR_READY_DIS_NMI_OFF 0x26977 6978#define SCU_LOW_RAM__A 0x8200006979 6980#define SCU_LOW_RAM_LOW__B 06981#define SCU_LOW_RAM_LOW__W 166982#define SCU_LOW_RAM_LOW__M 0xFFFF6983#define SCU_LOW_RAM_LOW__PRE 0x06984 6985#define SCU_HIGH_RAM__A 0x8300006986 6987#define SCU_HIGH_RAM_HIGH__B 06988#define SCU_HIGH_RAM_HIGH__W 166989#define SCU_HIGH_RAM_HIGH__M 0xFFFF6990#define SCU_HIGH_RAM_HIGH__PRE 0x06991 6992#define SCU_RAM_AGC_RF_MAX__A 0x831E966993#define SCU_RAM_AGC_RF_MAX__W 156994#define SCU_RAM_AGC_RF_MAX__M 0x7FFF6995#define SCU_RAM_AGC_RF_MAX__PRE 0x06996 6997#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831E976998#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__W 166999#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__M 0xFFFF7000#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__PRE 0x07001 7002#define SCU_RAM_AGC_KI_CYCCNT__A 0x831E987003#define SCU_RAM_AGC_KI_CYCCNT__W 167004#define SCU_RAM_AGC_KI_CYCCNT__M 0xFFFF7005#define SCU_RAM_AGC_KI_CYCCNT__PRE 0x07006 7007#define SCU_RAM_AGC_KI_CYCLEN__A 0x831E997008#define SCU_RAM_AGC_KI_CYCLEN__W 167009#define SCU_RAM_AGC_KI_CYCLEN__M 0xFFFF7010#define SCU_RAM_AGC_KI_CYCLEN__PRE 0x07011 7012#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831E9A7013#define SCU_RAM_AGC_SNS_CYCLEN__W 167014#define SCU_RAM_AGC_SNS_CYCLEN__M 0xFFFF7015#define SCU_RAM_AGC_SNS_CYCLEN__PRE 0x07016 7017#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831E9B7018#define SCU_RAM_AGC_RF_SNS_DEV_MAX__W 167019#define SCU_RAM_AGC_RF_SNS_DEV_MAX__M 0xFFFF7020#define SCU_RAM_AGC_RF_SNS_DEV_MAX__PRE 0x07021 7022#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831E9C7023#define SCU_RAM_AGC_RF_SNS_DEV_MIN__W 167024#define SCU_RAM_AGC_RF_SNS_DEV_MIN__M 0xFFFF7025#define SCU_RAM_AGC_RF_SNS_DEV_MIN__PRE 0x07026#define SCU_RAM_AGC_KI__A 0x831E9D7027#define SCU_RAM_AGC_KI__W 157028#define SCU_RAM_AGC_KI__M 0x7FFF7029#define SCU_RAM_AGC_KI__PRE 0x07030 7031#define SCU_RAM_AGC_KI_DGAIN__B 07032#define SCU_RAM_AGC_KI_DGAIN__W 47033#define SCU_RAM_AGC_KI_DGAIN__M 0xF7034#define SCU_RAM_AGC_KI_DGAIN__PRE 0x07035 7036#define SCU_RAM_AGC_KI_RF__B 47037#define SCU_RAM_AGC_KI_RF__W 47038#define SCU_RAM_AGC_KI_RF__M 0xF07039#define SCU_RAM_AGC_KI_RF__PRE 0x07040 7041#define SCU_RAM_AGC_KI_IF__B 87042#define SCU_RAM_AGC_KI_IF__W 47043#define SCU_RAM_AGC_KI_IF__M 0xF007044#define SCU_RAM_AGC_KI_IF__PRE 0x07045 7046#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__B 127047#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__W 17048#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__M 0x10007049#define SCU_RAM_AGC_KI_IF_AGC_DISABLE__PRE 0x07050 7051#define SCU_RAM_AGC_KI_INV_IF_POL__B 137052#define SCU_RAM_AGC_KI_INV_IF_POL__W 17053#define SCU_RAM_AGC_KI_INV_IF_POL__M 0x20007054#define SCU_RAM_AGC_KI_INV_IF_POL__PRE 0x07055 7056#define SCU_RAM_AGC_KI_INV_RF_POL__B 147057#define SCU_RAM_AGC_KI_INV_RF_POL__W 17058#define SCU_RAM_AGC_KI_INV_RF_POL__M 0x40007059#define SCU_RAM_AGC_KI_INV_RF_POL__PRE 0x07060 7061#define SCU_RAM_AGC_KI_RED__A 0x831E9E7062#define SCU_RAM_AGC_KI_RED__W 67063#define SCU_RAM_AGC_KI_RED__M 0x3F7064#define SCU_RAM_AGC_KI_RED__PRE 0x07065 7066#define SCU_RAM_AGC_KI_RED_INNER_RED__B 07067#define SCU_RAM_AGC_KI_RED_INNER_RED__W 27068#define SCU_RAM_AGC_KI_RED_INNER_RED__M 0x37069#define SCU_RAM_AGC_KI_RED_INNER_RED__PRE 0x07070 7071#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 27072#define SCU_RAM_AGC_KI_RED_RAGC_RED__W 27073#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC7074#define SCU_RAM_AGC_KI_RED_RAGC_RED__PRE 0x07075 7076#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 47077#define SCU_RAM_AGC_KI_RED_IAGC_RED__W 27078#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x307079#define SCU_RAM_AGC_KI_RED_IAGC_RED__PRE 0x07080 7081#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831E9F7082#define SCU_RAM_AGC_KI_INNERGAIN_MIN__W 167083#define SCU_RAM_AGC_KI_INNERGAIN_MIN__M 0xFFFF7084#define SCU_RAM_AGC_KI_INNERGAIN_MIN__PRE 0x07085 7086#define SCU_RAM_AGC_KI_MINGAIN__A 0x831EA07087#define SCU_RAM_AGC_KI_MINGAIN__W 167088#define SCU_RAM_AGC_KI_MINGAIN__M 0xFFFF7089#define SCU_RAM_AGC_KI_MINGAIN__PRE 0x07090 7091#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831EA17092#define SCU_RAM_AGC_KI_MAXGAIN__W 167093#define SCU_RAM_AGC_KI_MAXGAIN__M 0xFFFF7094#define SCU_RAM_AGC_KI_MAXGAIN__PRE 0x07095 7096#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831EA27097#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__W 167098#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__M 0xFFFF7099#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__PRE 0x07100#define SCU_RAM_AGC_KI_MIN__A 0x831EA37101#define SCU_RAM_AGC_KI_MIN__W 127102#define SCU_RAM_AGC_KI_MIN__M 0xFFF7103#define SCU_RAM_AGC_KI_MIN__PRE 0x07104 7105#define SCU_RAM_AGC_KI_MIN_DGAIN__B 07106#define SCU_RAM_AGC_KI_MIN_DGAIN__W 47107#define SCU_RAM_AGC_KI_MIN_DGAIN__M 0xF7108#define SCU_RAM_AGC_KI_MIN_DGAIN__PRE 0x07109 7110#define SCU_RAM_AGC_KI_MIN_RF__B 47111#define SCU_RAM_AGC_KI_MIN_RF__W 47112#define SCU_RAM_AGC_KI_MIN_RF__M 0xF07113#define SCU_RAM_AGC_KI_MIN_RF__PRE 0x07114 7115#define SCU_RAM_AGC_KI_MIN_IF__B 87116#define SCU_RAM_AGC_KI_MIN_IF__W 47117#define SCU_RAM_AGC_KI_MIN_IF__M 0xF007118#define SCU_RAM_AGC_KI_MIN_IF__PRE 0x07119 7120#define SCU_RAM_AGC_KI_MAX__A 0x831EA47121#define SCU_RAM_AGC_KI_MAX__W 127122#define SCU_RAM_AGC_KI_MAX__M 0xFFF7123#define SCU_RAM_AGC_KI_MAX__PRE 0x07124 7125#define SCU_RAM_AGC_KI_MAX_DGAIN__B 07126#define SCU_RAM_AGC_KI_MAX_DGAIN__W 47127#define SCU_RAM_AGC_KI_MAX_DGAIN__M 0xF7128#define SCU_RAM_AGC_KI_MAX_DGAIN__PRE 0x07129 7130#define SCU_RAM_AGC_KI_MAX_RF__B 47131#define SCU_RAM_AGC_KI_MAX_RF__W 47132#define SCU_RAM_AGC_KI_MAX_RF__M 0xF07133#define SCU_RAM_AGC_KI_MAX_RF__PRE 0x07134 7135#define SCU_RAM_AGC_KI_MAX_IF__B 87136#define SCU_RAM_AGC_KI_MAX_IF__W 47137#define SCU_RAM_AGC_KI_MAX_IF__M 0xF007138#define SCU_RAM_AGC_KI_MAX_IF__PRE 0x07139 7140#define SCU_RAM_AGC_CLP_SUM__A 0x831EA57141#define SCU_RAM_AGC_CLP_SUM__W 167142#define SCU_RAM_AGC_CLP_SUM__M 0xFFFF7143#define SCU_RAM_AGC_CLP_SUM__PRE 0x07144 7145#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831EA67146#define SCU_RAM_AGC_CLP_SUM_MIN__W 167147#define SCU_RAM_AGC_CLP_SUM_MIN__M 0xFFFF7148#define SCU_RAM_AGC_CLP_SUM_MIN__PRE 0x07149 7150#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831EA77151#define SCU_RAM_AGC_CLP_SUM_MAX__W 167152#define SCU_RAM_AGC_CLP_SUM_MAX__M 0xFFFF7153#define SCU_RAM_AGC_CLP_SUM_MAX__PRE 0x07154 7155#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831EA87156#define SCU_RAM_AGC_CLP_CYCLEN__W 167157#define SCU_RAM_AGC_CLP_CYCLEN__M 0xFFFF7158#define SCU_RAM_AGC_CLP_CYCLEN__PRE 0x07159 7160#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831EA97161#define SCU_RAM_AGC_CLP_CYCCNT__W 167162#define SCU_RAM_AGC_CLP_CYCCNT__M 0xFFFF7163#define SCU_RAM_AGC_CLP_CYCCNT__PRE 0x07164 7165#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831EAA7166#define SCU_RAM_AGC_CLP_DIR_TO__W 87167#define SCU_RAM_AGC_CLP_DIR_TO__M 0xFF7168#define SCU_RAM_AGC_CLP_DIR_TO__PRE 0x07169 7170#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831EAB7171#define SCU_RAM_AGC_CLP_DIR_WD__W 87172#define SCU_RAM_AGC_CLP_DIR_WD__M 0xFF7173#define SCU_RAM_AGC_CLP_DIR_WD__PRE 0x07174 7175#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831EAC7176#define SCU_RAM_AGC_CLP_DIR_STP__W 167177#define SCU_RAM_AGC_CLP_DIR_STP__M 0xFFFF7178#define SCU_RAM_AGC_CLP_DIR_STP__PRE 0x07179 7180#define SCU_RAM_AGC_SNS_SUM__A 0x831EAD7181#define SCU_RAM_AGC_SNS_SUM__W 167182#define SCU_RAM_AGC_SNS_SUM__M 0xFFFF7183#define SCU_RAM_AGC_SNS_SUM__PRE 0x07184 7185#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831EAE7186#define SCU_RAM_AGC_SNS_SUM_MIN__W 167187#define SCU_RAM_AGC_SNS_SUM_MIN__M 0xFFFF7188#define SCU_RAM_AGC_SNS_SUM_MIN__PRE 0x07189 7190#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831EAF7191#define SCU_RAM_AGC_SNS_SUM_MAX__W 167192#define SCU_RAM_AGC_SNS_SUM_MAX__M 0xFFFF7193#define SCU_RAM_AGC_SNS_SUM_MAX__PRE 0x07194 7195#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831EB07196#define SCU_RAM_AGC_SNS_CYCCNT__W 167197#define SCU_RAM_AGC_SNS_CYCCNT__M 0xFFFF7198#define SCU_RAM_AGC_SNS_CYCCNT__PRE 0x07199 7200#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831EB17201#define SCU_RAM_AGC_SNS_DIR_TO__W 87202#define SCU_RAM_AGC_SNS_DIR_TO__M 0xFF7203#define SCU_RAM_AGC_SNS_DIR_TO__PRE 0x07204 7205#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831EB27206#define SCU_RAM_AGC_SNS_DIR_WD__W 87207#define SCU_RAM_AGC_SNS_DIR_WD__M 0xFF7208#define SCU_RAM_AGC_SNS_DIR_WD__PRE 0x07209 7210#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831EB37211#define SCU_RAM_AGC_SNS_DIR_STP__W 167212#define SCU_RAM_AGC_SNS_DIR_STP__M 0xFFFF7213#define SCU_RAM_AGC_SNS_DIR_STP__PRE 0x07214 7215#define SCU_RAM_AGC_INGAIN__A 0x831EB47216#define SCU_RAM_AGC_INGAIN__W 167217#define SCU_RAM_AGC_INGAIN__M 0xFFFF7218#define SCU_RAM_AGC_INGAIN__PRE 0x07219 7220#define SCU_RAM_AGC_INGAIN_TGT__A 0x831EB57221#define SCU_RAM_AGC_INGAIN_TGT__W 157222#define SCU_RAM_AGC_INGAIN_TGT__M 0x7FFF7223#define SCU_RAM_AGC_INGAIN_TGT__PRE 0x07224 7225#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831EB67226#define SCU_RAM_AGC_INGAIN_TGT_MIN__W 157227#define SCU_RAM_AGC_INGAIN_TGT_MIN__M 0x7FFF7228#define SCU_RAM_AGC_INGAIN_TGT_MIN__PRE 0x07229 7230#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831EB77231#define SCU_RAM_AGC_INGAIN_TGT_MAX__W 157232#define SCU_RAM_AGC_INGAIN_TGT_MAX__M 0x7FFF7233#define SCU_RAM_AGC_INGAIN_TGT_MAX__PRE 0x07234 7235#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831EB87236#define SCU_RAM_AGC_IF_IACCU_HI__W 167237#define SCU_RAM_AGC_IF_IACCU_HI__M 0xFFFF7238#define SCU_RAM_AGC_IF_IACCU_HI__PRE 0x07239 7240#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831EB97241#define SCU_RAM_AGC_IF_IACCU_LO__W 87242#define SCU_RAM_AGC_IF_IACCU_LO__M 0xFF7243#define SCU_RAM_AGC_IF_IACCU_LO__PRE 0x07244 7245#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831EBA7246#define SCU_RAM_AGC_IF_IACCU_HI_TGT__W 157247#define SCU_RAM_AGC_IF_IACCU_HI_TGT__M 0x7FFF7248#define SCU_RAM_AGC_IF_IACCU_HI_TGT__PRE 0x07249 7250#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831EBB7251#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__W 157252#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__M 0x7FFF7253#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__PRE 0x07254 7255#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831EBC7256#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__W 157257#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__M 0x7FFF7258#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__PRE 0x07259 7260#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831EBD7261#define SCU_RAM_AGC_RF_IACCU_HI__W 167262#define SCU_RAM_AGC_RF_IACCU_HI__M 0xFFFF7263#define SCU_RAM_AGC_RF_IACCU_HI__PRE 0x07264 7265#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831EBE7266#define SCU_RAM_AGC_RF_IACCU_LO__W 87267#define SCU_RAM_AGC_RF_IACCU_LO__M 0xFF7268#define SCU_RAM_AGC_RF_IACCU_LO__PRE 0x07269 7270#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831EBF7271#define SCU_RAM_AGC_RF_IACCU_HI_CO__W 167272#define SCU_RAM_AGC_RF_IACCU_HI_CO__M 0xFFFF7273#define SCU_RAM_AGC_RF_IACCU_HI_CO__PRE 0x07274 7275#define SCU_RAM_SP__A 0x831EC07276#define SCU_RAM_SP__W 167277#define SCU_RAM_SP__M 0xFFFF7278#define SCU_RAM_SP__PRE 0x07279 7280#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831EC17281#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__W 167282#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__M 0xFFFF7283#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__PRE 0x07284 7285#define SCU_RAM_AGC_KI_MIN_IFGAIN__A 0x831EC27286#define SCU_RAM_AGC_KI_MIN_IFGAIN__W 167287#define SCU_RAM_AGC_KI_MIN_IFGAIN__M 0xFFFF7288#define SCU_RAM_AGC_KI_MIN_IFGAIN__PRE 0x07289 7290#define SCU_RAM_AGC_KI_MAX_IFGAIN__A 0x831EC37291#define SCU_RAM_AGC_KI_MAX_IFGAIN__W 167292#define SCU_RAM_AGC_KI_MAX_IFGAIN__M 0xFFFF7293#define SCU_RAM_AGC_KI_MAX_IFGAIN__PRE 0x07294 7295#define SCU_RAM_FEC_MEAS_COUNT__A 0x831EC47296#define SCU_RAM_FEC_MEAS_COUNT__W 167297#define SCU_RAM_FEC_MEAS_COUNT__M 0xFFFF7298#define SCU_RAM_FEC_MEAS_COUNT__PRE 0x07299 7300#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A 0x831EC57301#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__W 167302#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__M 0xFFFF7303#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__PRE 0x07304 7305#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__A 0x831EC67306#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__W 167307#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__M 0xFFFF7308#define SCU_RAM_FEC_ACCUM_CW_CORRECTED_HI__PRE 0x07309#define SCU_RAM_GPIO__A 0x831EC77310#define SCU_RAM_GPIO__W 17311#define SCU_RAM_GPIO__M 0x17312#define SCU_RAM_GPIO__PRE 0x07313 7314#define SCU_RAM_GPIO_HW_LOCK_IND__B 07315#define SCU_RAM_GPIO_HW_LOCK_IND__W 17316#define SCU_RAM_GPIO_HW_LOCK_IND__M 0x17317#define SCU_RAM_GPIO_HW_LOCK_IND__PRE 0x07318#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x07319#define SCU_RAM_GPIO_HW_LOCK_IND_ENABLE 0x17320 7321#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC87322#define SCU_RAM_AGC_CLP_CTRL_MODE__W 87323#define SCU_RAM_AGC_CLP_CTRL_MODE__M 0xFF7324#define SCU_RAM_AGC_CLP_CTRL_MODE__PRE 0x07325 7326#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__B 07327#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__W 17328#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__M 0x17329#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW__PRE 0x07330#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_false 0x07331#define SCU_RAM_AGC_CLP_CTRL_MODE_NARROW_POW_true 0x17332 7333#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__B 17334#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__W 17335#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__M 0x27336#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP__PRE 0x07337#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_ENABLE 0x07338#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_BP_FCC_DISABLE 0x27339 7340#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__B 27341#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__W 17342#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__M 0x47343#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC__PRE 0x07344#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_DISABLE 0x07345#define SCU_RAM_AGC_CLP_CTRL_MODE_FAST_CLP_DEC_DEC_ENABLE 0x47346 7347#define SCU_RAM_AGC_KI_MIN_RFGAIN__A 0x831EC97348#define SCU_RAM_AGC_KI_MIN_RFGAIN__W 167349#define SCU_RAM_AGC_KI_MIN_RFGAIN__M 0xFFFF7350#define SCU_RAM_AGC_KI_MIN_RFGAIN__PRE 0x07351 7352#define SCU_RAM_AGC_KI_MAX_RFGAIN__A 0x831ECA7353#define SCU_RAM_AGC_KI_MAX_RFGAIN__W 167354#define SCU_RAM_AGC_KI_MAX_RFGAIN__M 0xFFFF7355#define SCU_RAM_AGC_KI_MAX_RFGAIN__PRE 0x07356 7357#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB7358#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__W 167359#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__M 0xFFFF7360#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__PRE 0x07361 7362#define SCU_RAM_INHIBIT_1__A 0x831ECC7363#define SCU_RAM_INHIBIT_1__W 167364#define SCU_RAM_INHIBIT_1__M 0xFFFF7365#define SCU_RAM_INHIBIT_1__PRE 0x07366 7367#define SCU_RAM_HTOL_BUF_0__A 0x831ECD7368#define SCU_RAM_HTOL_BUF_0__W 167369#define SCU_RAM_HTOL_BUF_0__M 0xFFFF7370#define SCU_RAM_HTOL_BUF_0__PRE 0x07371 7372#define SCU_RAM_HTOL_BUF_1__A 0x831ECE7373#define SCU_RAM_HTOL_BUF_1__W 167374#define SCU_RAM_HTOL_BUF_1__M 0xFFFF7375#define SCU_RAM_HTOL_BUF_1__PRE 0x07376 7377#define SCU_RAM_INHIBIT_2__A 0x831ECF7378#define SCU_RAM_INHIBIT_2__W 167379#define SCU_RAM_INHIBIT_2__M 0xFFFF7380#define SCU_RAM_INHIBIT_2__PRE 0x07381 7382#define SCU_RAM_TR_SHORT_BUF_0__A 0x831ED07383#define SCU_RAM_TR_SHORT_BUF_0__W 167384#define SCU_RAM_TR_SHORT_BUF_0__M 0xFFFF7385#define SCU_RAM_TR_SHORT_BUF_0__PRE 0x07386 7387#define SCU_RAM_TR_SHORT_BUF_1__A 0x831ED17388#define SCU_RAM_TR_SHORT_BUF_1__W 167389#define SCU_RAM_TR_SHORT_BUF_1__M 0xFFFF7390#define SCU_RAM_TR_SHORT_BUF_1__PRE 0x07391 7392#define SCU_RAM_TR_LONG_BUF_0__A 0x831ED27393#define SCU_RAM_TR_LONG_BUF_0__W 167394#define SCU_RAM_TR_LONG_BUF_0__M 0xFFFF7395#define SCU_RAM_TR_LONG_BUF_0__PRE 0x07396 7397#define SCU_RAM_TR_LONG_BUF_1__A 0x831ED37398#define SCU_RAM_TR_LONG_BUF_1__W 167399#define SCU_RAM_TR_LONG_BUF_1__M 0xFFFF7400#define SCU_RAM_TR_LONG_BUF_1__PRE 0x07401 7402#define SCU_RAM_TR_LONG_BUF_2__A 0x831ED47403#define SCU_RAM_TR_LONG_BUF_2__W 167404#define SCU_RAM_TR_LONG_BUF_2__M 0xFFFF7405#define SCU_RAM_TR_LONG_BUF_2__PRE 0x07406 7407#define SCU_RAM_TR_LONG_BUF_3__A 0x831ED57408#define SCU_RAM_TR_LONG_BUF_3__W 167409#define SCU_RAM_TR_LONG_BUF_3__M 0xFFFF7410#define SCU_RAM_TR_LONG_BUF_3__PRE 0x07411 7412#define SCU_RAM_TR_LONG_BUF_4__A 0x831ED67413#define SCU_RAM_TR_LONG_BUF_4__W 167414#define SCU_RAM_TR_LONG_BUF_4__M 0xFFFF7415#define SCU_RAM_TR_LONG_BUF_4__PRE 0x07416 7417#define SCU_RAM_TR_LONG_BUF_5__A 0x831ED77418#define SCU_RAM_TR_LONG_BUF_5__W 167419#define SCU_RAM_TR_LONG_BUF_5__M 0xFFFF7420#define SCU_RAM_TR_LONG_BUF_5__PRE 0x07421 7422#define SCU_RAM_TR_LONG_BUF_6__A 0x831ED87423#define SCU_RAM_TR_LONG_BUF_6__W 167424#define SCU_RAM_TR_LONG_BUF_6__M 0xFFFF7425#define SCU_RAM_TR_LONG_BUF_6__PRE 0x07426 7427#define SCU_RAM_TR_LONG_BUF_7__A 0x831ED97428#define SCU_RAM_TR_LONG_BUF_7__W 167429#define SCU_RAM_TR_LONG_BUF_7__M 0xFFFF7430#define SCU_RAM_TR_LONG_BUF_7__PRE 0x07431 7432#define SCU_RAM_TR_LONG_BUF_8__A 0x831EDA7433#define SCU_RAM_TR_LONG_BUF_8__W 167434#define SCU_RAM_TR_LONG_BUF_8__M 0xFFFF7435#define SCU_RAM_TR_LONG_BUF_8__PRE 0x07436 7437#define SCU_RAM_TR_LONG_BUF_9__A 0x831EDB7438#define SCU_RAM_TR_LONG_BUF_9__W 167439#define SCU_RAM_TR_LONG_BUF_9__M 0xFFFF7440#define SCU_RAM_TR_LONG_BUF_9__PRE 0x07441 7442#define SCU_RAM_TR_LONG_BUF_10__A 0x831EDC7443#define SCU_RAM_TR_LONG_BUF_10__W 167444#define SCU_RAM_TR_LONG_BUF_10__M 0xFFFF7445#define SCU_RAM_TR_LONG_BUF_10__PRE 0x07446 7447#define SCU_RAM_TR_LONG_BUF_11__A 0x831EDD7448#define SCU_RAM_TR_LONG_BUF_11__W 167449#define SCU_RAM_TR_LONG_BUF_11__M 0xFFFF7450#define SCU_RAM_TR_LONG_BUF_11__PRE 0x07451 7452#define SCU_RAM_TR_LONG_BUF_12__A 0x831EDE7453#define SCU_RAM_TR_LONG_BUF_12__W 167454#define SCU_RAM_TR_LONG_BUF_12__M 0xFFFF7455#define SCU_RAM_TR_LONG_BUF_12__PRE 0x07456 7457#define SCU_RAM_TR_LONG_BUF_13__A 0x831EDF7458#define SCU_RAM_TR_LONG_BUF_13__W 167459#define SCU_RAM_TR_LONG_BUF_13__M 0xFFFF7460#define SCU_RAM_TR_LONG_BUF_13__PRE 0x07461 7462#define SCU_RAM_TR_LONG_BUF_14__A 0x831EE07463#define SCU_RAM_TR_LONG_BUF_14__W 167464#define SCU_RAM_TR_LONG_BUF_14__M 0xFFFF7465#define SCU_RAM_TR_LONG_BUF_14__PRE 0x07466 7467#define SCU_RAM_TR_LONG_BUF_15__A 0x831EE17468#define SCU_RAM_TR_LONG_BUF_15__W 167469#define SCU_RAM_TR_LONG_BUF_15__M 0xFFFF7470#define SCU_RAM_TR_LONG_BUF_15__PRE 0x07471 7472#define SCU_RAM_TR_LONG_BUF_16__A 0x831EE27473#define SCU_RAM_TR_LONG_BUF_16__W 167474#define SCU_RAM_TR_LONG_BUF_16__M 0xFFFF7475#define SCU_RAM_TR_LONG_BUF_16__PRE 0x07476 7477#define SCU_RAM_TR_LONG_BUF_17__A 0x831EE37478#define SCU_RAM_TR_LONG_BUF_17__W 167479#define SCU_RAM_TR_LONG_BUF_17__M 0xFFFF7480#define SCU_RAM_TR_LONG_BUF_17__PRE 0x07481 7482#define SCU_RAM_TR_LONG_BUF_18__A 0x831EE47483#define SCU_RAM_TR_LONG_BUF_18__W 167484#define SCU_RAM_TR_LONG_BUF_18__M 0xFFFF7485#define SCU_RAM_TR_LONG_BUF_18__PRE 0x07486 7487#define SCU_RAM_TR_LONG_BUF_19__A 0x831EE57488#define SCU_RAM_TR_LONG_BUF_19__W 167489#define SCU_RAM_TR_LONG_BUF_19__M 0xFFFF7490#define SCU_RAM_TR_LONG_BUF_19__PRE 0x07491 7492#define SCU_RAM_TR_LONG_BUF_20__A 0x831EE67493#define SCU_RAM_TR_LONG_BUF_20__W 167494#define SCU_RAM_TR_LONG_BUF_20__M 0xFFFF7495#define SCU_RAM_TR_LONG_BUF_20__PRE 0x07496 7497#define SCU_RAM_TR_LONG_BUF_21__A 0x831EE77498#define SCU_RAM_TR_LONG_BUF_21__W 167499#define SCU_RAM_TR_LONG_BUF_21__M 0xFFFF7500#define SCU_RAM_TR_LONG_BUF_21__PRE 0x07501 7502#define SCU_RAM_TR_LONG_BUF_22__A 0x831EE87503#define SCU_RAM_TR_LONG_BUF_22__W 167504#define SCU_RAM_TR_LONG_BUF_22__M 0xFFFF7505#define SCU_RAM_TR_LONG_BUF_22__PRE 0x07506 7507#define SCU_RAM_TR_LONG_BUF_23__A 0x831EE97508#define SCU_RAM_TR_LONG_BUF_23__W 167509#define SCU_RAM_TR_LONG_BUF_23__M 0xFFFF7510#define SCU_RAM_TR_LONG_BUF_23__PRE 0x07511 7512#define SCU_RAM_TR_LONG_BUF_24__A 0x831EEA7513#define SCU_RAM_TR_LONG_BUF_24__W 167514#define SCU_RAM_TR_LONG_BUF_24__M 0xFFFF7515#define SCU_RAM_TR_LONG_BUF_24__PRE 0x07516 7517#define SCU_RAM_TR_LONG_BUF_25__A 0x831EEB7518#define SCU_RAM_TR_LONG_BUF_25__W 167519#define SCU_RAM_TR_LONG_BUF_25__M 0xFFFF7520#define SCU_RAM_TR_LONG_BUF_25__PRE 0x07521 7522#define SCU_RAM_TR_LONG_BUF_26__A 0x831EEC7523#define SCU_RAM_TR_LONG_BUF_26__W 167524#define SCU_RAM_TR_LONG_BUF_26__M 0xFFFF7525#define SCU_RAM_TR_LONG_BUF_26__PRE 0x07526 7527#define SCU_RAM_TR_LONG_BUF_27__A 0x831EED7528#define SCU_RAM_TR_LONG_BUF_27__W 167529#define SCU_RAM_TR_LONG_BUF_27__M 0xFFFF7530#define SCU_RAM_TR_LONG_BUF_27__PRE 0x07531 7532#define SCU_RAM_TR_LONG_BUF_28__A 0x831EEE7533#define SCU_RAM_TR_LONG_BUF_28__W 167534#define SCU_RAM_TR_LONG_BUF_28__M 0xFFFF7535#define SCU_RAM_TR_LONG_BUF_28__PRE 0x07536 7537#define SCU_RAM_TR_LONG_BUF_29__A 0x831EEF7538#define SCU_RAM_TR_LONG_BUF_29__W 167539#define SCU_RAM_TR_LONG_BUF_29__M 0xFFFF7540#define SCU_RAM_TR_LONG_BUF_29__PRE 0x07541 7542#define SCU_RAM_TR_LONG_BUF_30__A 0x831EF07543#define SCU_RAM_TR_LONG_BUF_30__W 167544#define SCU_RAM_TR_LONG_BUF_30__M 0xFFFF7545#define SCU_RAM_TR_LONG_BUF_30__PRE 0x07546 7547#define SCU_RAM_TR_LONG_BUF_31__A 0x831EF17548#define SCU_RAM_TR_LONG_BUF_31__W 167549#define SCU_RAM_TR_LONG_BUF_31__M 0xFFFF7550#define SCU_RAM_TR_LONG_BUF_31__PRE 0x07551#define SCU_RAM_ATV_AMS_MAX__A 0x831EF27552#define SCU_RAM_ATV_AMS_MAX__W 117553#define SCU_RAM_ATV_AMS_MAX__M 0x7FF7554#define SCU_RAM_ATV_AMS_MAX__PRE 0x07555 7556#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__B 07557#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__W 117558#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__M 0x7FF7559#define SCU_RAM_ATV_AMS_MAX_AMS_MAX__PRE 0x07560 7561#define SCU_RAM_ATV_AMS_MIN__A 0x831EF37562#define SCU_RAM_ATV_AMS_MIN__W 117563#define SCU_RAM_ATV_AMS_MIN__M 0x7FF7564#define SCU_RAM_ATV_AMS_MIN__PRE 0x07565 7566#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__B 07567#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__W 117568#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__M 0x7FF7569#define SCU_RAM_ATV_AMS_MIN_AMS_MIN__PRE 0x07570 7571#define SCU_RAM_ATV_FIELD_CNT__A 0x831EF47572#define SCU_RAM_ATV_FIELD_CNT__W 97573#define SCU_RAM_ATV_FIELD_CNT__M 0x1FF7574#define SCU_RAM_ATV_FIELD_CNT__PRE 0x07575 7576#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__B 07577#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__W 97578#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__M 0x1FF7579#define SCU_RAM_ATV_FIELD_CNT_FIELD_CNT__PRE 0x07580 7581#define SCU_RAM_ATV_AAGC_FAST__A 0x831EF57582#define SCU_RAM_ATV_AAGC_FAST__W 17583#define SCU_RAM_ATV_AAGC_FAST__M 0x17584#define SCU_RAM_ATV_AAGC_FAST__PRE 0x07585 7586#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__B 07587#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__W 17588#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__M 0x17589#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST__PRE 0x07590#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_OFF 0x07591#define SCU_RAM_ATV_AAGC_FAST_AAGC_FAST_ON 0x17592 7593#define SCU_RAM_ATV_AAGC_LP2__A 0x831EF67594#define SCU_RAM_ATV_AAGC_LP2__W 167595#define SCU_RAM_ATV_AAGC_LP2__M 0xFFFF7596#define SCU_RAM_ATV_AAGC_LP2__PRE 0x07597 7598#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__B 07599#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__W 167600#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__M 0xFFFF7601#define SCU_RAM_ATV_AAGC_LP2_AAGC_LP2__PRE 0x07602 7603#define SCU_RAM_ATV_BP_LVL__A 0x831EF77604#define SCU_RAM_ATV_BP_LVL__W 117605#define SCU_RAM_ATV_BP_LVL__M 0x7FF7606#define SCU_RAM_ATV_BP_LVL__PRE 0x07607 7608#define SCU_RAM_ATV_BP_LVL_BP_LVL__B 07609#define SCU_RAM_ATV_BP_LVL_BP_LVL__W 117610#define SCU_RAM_ATV_BP_LVL_BP_LVL__M 0x7FF7611#define SCU_RAM_ATV_BP_LVL_BP_LVL__PRE 0x07612 7613#define SCU_RAM_ATV_BP_RELY__A 0x831EF87614#define SCU_RAM_ATV_BP_RELY__W 87615#define SCU_RAM_ATV_BP_RELY__M 0xFF7616#define SCU_RAM_ATV_BP_RELY__PRE 0x07617 7618#define SCU_RAM_ATV_BP_RELY_BP_RELY__B 07619#define SCU_RAM_ATV_BP_RELY_BP_RELY__W 87620#define SCU_RAM_ATV_BP_RELY_BP_RELY__M 0xFF7621#define SCU_RAM_ATV_BP_RELY_BP_RELY__PRE 0x07622 7623#define SCU_RAM_ATV_BP_MTA__A 0x831EF97624#define SCU_RAM_ATV_BP_MTA__W 147625#define SCU_RAM_ATV_BP_MTA__M 0x3FFF7626#define SCU_RAM_ATV_BP_MTA__PRE 0x07627 7628#define SCU_RAM_ATV_BP_MTA_BP_MTA__B 07629#define SCU_RAM_ATV_BP_MTA_BP_MTA__W 147630#define SCU_RAM_ATV_BP_MTA_BP_MTA__M 0x3FFF7631#define SCU_RAM_ATV_BP_MTA_BP_MTA__PRE 0x07632 7633#define SCU_RAM_ATV_BP_REF__A 0x831EFA7634#define SCU_RAM_ATV_BP_REF__W 117635#define SCU_RAM_ATV_BP_REF__M 0x7FF7636#define SCU_RAM_ATV_BP_REF__PRE 0x07637 7638#define SCU_RAM_ATV_BP_REF_BP_REF__B 07639#define SCU_RAM_ATV_BP_REF_BP_REF__W 117640#define SCU_RAM_ATV_BP_REF_BP_REF__M 0x7FF7641#define SCU_RAM_ATV_BP_REF_BP_REF__PRE 0x07642 7643#define SCU_RAM_ATV_BP_REF_MIN__A 0x831EFB7644#define SCU_RAM_ATV_BP_REF_MIN__W 117645#define SCU_RAM_ATV_BP_REF_MIN__M 0x7FF7646#define SCU_RAM_ATV_BP_REF_MIN__PRE 0x07647 7648#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__B 07649#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__W 117650#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__M 0x7FF7651#define SCU_RAM_ATV_BP_REF_MIN_BP_REF_MIN__PRE 0x07652 7653#define SCU_RAM_ATV_BP_REF_MAX__A 0x831EFC7654#define SCU_RAM_ATV_BP_REF_MAX__W 117655#define SCU_RAM_ATV_BP_REF_MAX__M 0x7FF7656#define SCU_RAM_ATV_BP_REF_MAX__PRE 0x07657 7658#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__B 07659#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__W 117660#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__M 0x7FF7661#define SCU_RAM_ATV_BP_REF_MAX_BP_REF_MAX__PRE 0x07662 7663#define SCU_RAM_ATV_BP_CNT__A 0x831EFD7664#define SCU_RAM_ATV_BP_CNT__W 87665#define SCU_RAM_ATV_BP_CNT__M 0xFF7666#define SCU_RAM_ATV_BP_CNT__PRE 0x07667 7668#define SCU_RAM_ATV_BP_CNT_BP_CNT__B 07669#define SCU_RAM_ATV_BP_CNT_BP_CNT__W 87670#define SCU_RAM_ATV_BP_CNT_BP_CNT__M 0xFF7671#define SCU_RAM_ATV_BP_CNT_BP_CNT__PRE 0x07672 7673#define SCU_RAM_ATV_BP_XD_CNT__A 0x831EFE7674#define SCU_RAM_ATV_BP_XD_CNT__W 127675#define SCU_RAM_ATV_BP_XD_CNT__M 0xFFF7676#define SCU_RAM_ATV_BP_XD_CNT__PRE 0x07677 7678#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__B 07679#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__W 127680#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__M 0xFFF7681#define SCU_RAM_ATV_BP_XD_CNT_BP_XD_CNT__PRE 0x07682 7683#define SCU_RAM_ATV_PAGC_KI_MIN__A 0x831EFF7684#define SCU_RAM_ATV_PAGC_KI_MIN__W 127685#define SCU_RAM_ATV_PAGC_KI_MIN__M 0xFFF7686#define SCU_RAM_ATV_PAGC_KI_MIN__PRE 0x07687 7688#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__B 07689#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__W 127690#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__M 0xFFF7691#define SCU_RAM_ATV_PAGC_KI_MIN_PAGC_KI_MIN__PRE 0x07692 7693#define SCU_RAM_ATV_BPC_KI_MIN__A 0x831F007694#define SCU_RAM_ATV_BPC_KI_MIN__W 127695#define SCU_RAM_ATV_BPC_KI_MIN__M 0xFFF7696#define SCU_RAM_ATV_BPC_KI_MIN__PRE 0x07697 7698#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__B 07699#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__W 127700#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__M 0xFFF7701#define SCU_RAM_ATV_BPC_KI_MIN_BPC_KI_MIN__PRE 0x07702 7703#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__A 0x831F017704#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__W 167705#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__M 0xFFFF7706#define SCU_RAM_ORX_RF_RX_FREQUENCY_VALUE__PRE 0x07707 7708#define SCU_RAM_ORX_RF_RX_DATA_RATE__A 0x831F027709#define SCU_RAM_ORX_RF_RX_DATA_RATE__W 87710#define SCU_RAM_ORX_RF_RX_DATA_RATE__M 0xFF7711#define SCU_RAM_ORX_RF_RX_DATA_RATE__PRE 0x07712#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC 0x07713#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC 0x17714#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_REGSPEC_ALT 0x407715#define SCU_RAM_ORX_RF_RX_DATA_RATE_2048KBPS_INVSPEC_ALT 0x417716#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_REGSPEC 0x807717#define SCU_RAM_ORX_RF_RX_DATA_RATE_1544KBPS_INVSPEC 0x817718#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_REGSPEC 0xC07719#define SCU_RAM_ORX_RF_RX_DATA_RATE_3088KBPS_INVSPEC 0xC17720 7721#define SCU_RAM_ORX_SCU_STATE__A 0x831F037722#define SCU_RAM_ORX_SCU_STATE__W 87723#define SCU_RAM_ORX_SCU_STATE__M 0xFF7724#define SCU_RAM_ORX_SCU_STATE__PRE 0x07725#define SCU_RAM_ORX_SCU_STATE_RESET 0x07726#define SCU_RAM_ORX_SCU_STATE_AGN_HUNT 0x17727#define SCU_RAM_ORX_SCU_STATE_DGN_HUNT 0x27728#define SCU_RAM_ORX_SCU_STATE_AGC_HUNT 0x37729#define SCU_RAM_ORX_SCU_STATE_FRQ_HUNT 0x47730#define SCU_RAM_ORX_SCU_STATE_PHA_HUNT 0x87731#define SCU_RAM_ORX_SCU_STATE_TIM_HUNT 0x107732#define SCU_RAM_ORX_SCU_STATE_EQU_HUNT 0x207733#define SCU_RAM_ORX_SCU_STATE_EQT_HUNT 0x307734#define SCU_RAM_ORX_SCU_STATE_SYNC 0x407735 7736#define SCU_RAM_ORX_SCU_LOCK__A 0x831F047737#define SCU_RAM_ORX_SCU_LOCK__W 167738#define SCU_RAM_ORX_SCU_LOCK__M 0xFFFF7739#define SCU_RAM_ORX_SCU_LOCK__PRE 0x07740 7741#define SCU_RAM_ORX_TARGET_MODE__A 0x831F057742#define SCU_RAM_ORX_TARGET_MODE__W 27743#define SCU_RAM_ORX_TARGET_MODE__M 0x37744#define SCU_RAM_ORX_TARGET_MODE__PRE 0x07745#define SCU_RAM_ORX_TARGET_MODE_1544KBPS 0x07746#define SCU_RAM_ORX_TARGET_MODE_3088KBPS 0x17747#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_SQRT 0x27748#define SCU_RAM_ORX_TARGET_MODE_2048KBPS_RO 0x37749 7750#define SCU_RAM_ORX_MER_MIN_DB__A 0x831F067751#define SCU_RAM_ORX_MER_MIN_DB__W 87752#define SCU_RAM_ORX_MER_MIN_DB__M 0xFF7753#define SCU_RAM_ORX_MER_MIN_DB__PRE 0x07754 7755#define SCU_RAM_ORX_RF_GAIN__A 0x831F077756#define SCU_RAM_ORX_RF_GAIN__W 167757#define SCU_RAM_ORX_RF_GAIN__M 0xFFFF7758#define SCU_RAM_ORX_RF_GAIN__PRE 0x07759 7760#define SCU_RAM_ORX_RF_GAIN_MIN__A 0x831F087761#define SCU_RAM_ORX_RF_GAIN_MIN__W 167762#define SCU_RAM_ORX_RF_GAIN_MIN__M 0xFFFF7763#define SCU_RAM_ORX_RF_GAIN_MIN__PRE 0x07764 7765#define SCU_RAM_ORX_RF_GAIN_MAX__A 0x831F097766#define SCU_RAM_ORX_RF_GAIN_MAX__W 167767#define SCU_RAM_ORX_RF_GAIN_MAX__M 0xFFFF7768#define SCU_RAM_ORX_RF_GAIN_MAX__PRE 0x07769 7770#define SCU_RAM_ORX_IF_GAIN__A 0x831F0A7771#define SCU_RAM_ORX_IF_GAIN__W 167772#define SCU_RAM_ORX_IF_GAIN__M 0xFFFF7773#define SCU_RAM_ORX_IF_GAIN__PRE 0x07774 7775#define SCU_RAM_ORX_IF_GAIN_MIN__A 0x831F0B7776#define SCU_RAM_ORX_IF_GAIN_MIN__W 167777#define SCU_RAM_ORX_IF_GAIN_MIN__M 0xFFFF7778#define SCU_RAM_ORX_IF_GAIN_MIN__PRE 0x07779 7780#define SCU_RAM_ORX_IF_GAIN_MAX__A 0x831F0C7781#define SCU_RAM_ORX_IF_GAIN_MAX__W 167782#define SCU_RAM_ORX_IF_GAIN_MAX__M 0xFFFF7783#define SCU_RAM_ORX_IF_GAIN_MAX__PRE 0x07784 7785#define SCU_RAM_ORX_AGN_HEADR__A 0x831F0D7786#define SCU_RAM_ORX_AGN_HEADR__W 167787#define SCU_RAM_ORX_AGN_HEADR__M 0xFFFF7788#define SCU_RAM_ORX_AGN_HEADR__PRE 0x07789 7790#define SCU_RAM_ORX_AGN_HEADR_STP__A 0x831F0E7791#define SCU_RAM_ORX_AGN_HEADR_STP__W 87792#define SCU_RAM_ORX_AGN_HEADR_STP__M 0xFF7793#define SCU_RAM_ORX_AGN_HEADR_STP__PRE 0x07794 7795#define SCU_RAM_ORX_AGN_KI__A 0x831F0F7796#define SCU_RAM_ORX_AGN_KI__W 87797#define SCU_RAM_ORX_AGN_KI__M 0xFF7798#define SCU_RAM_ORX_AGN_KI__PRE 0x07799 7800#define SCU_RAM_ORX_AGN_LOCK_TH__A 0x831F107801#define SCU_RAM_ORX_AGN_LOCK_TH__W 167802#define SCU_RAM_ORX_AGN_LOCK_TH__M 0xFFFF7803#define SCU_RAM_ORX_AGN_LOCK_TH__PRE 0x07804 7805#define SCU_RAM_ORX_AGN_LOCK_WD__A 0x831F117806#define SCU_RAM_ORX_AGN_LOCK_WD__W 167807#define SCU_RAM_ORX_AGN_LOCK_WD__M 0xFFFF7808#define SCU_RAM_ORX_AGN_LOCK_WD__PRE 0x07809 7810#define SCU_RAM_ORX_AGN_ONLOCK_TTH__A 0x831F127811#define SCU_RAM_ORX_AGN_ONLOCK_TTH__W 167812#define SCU_RAM_ORX_AGN_ONLOCK_TTH__M 0xFFFF7813#define SCU_RAM_ORX_AGN_ONLOCK_TTH__PRE 0x07814 7815#define SCU_RAM_ORX_AGN_UNLOCK_TTH__A 0x831F137816#define SCU_RAM_ORX_AGN_UNLOCK_TTH__W 167817#define SCU_RAM_ORX_AGN_UNLOCK_TTH__M 0xFFFF7818#define SCU_RAM_ORX_AGN_UNLOCK_TTH__PRE 0x07819 7820#define SCU_RAM_ORX_AGN_LOCK_TOTH__A 0x831F147821#define SCU_RAM_ORX_AGN_LOCK_TOTH__W 167822#define SCU_RAM_ORX_AGN_LOCK_TOTH__M 0xFFFF7823#define SCU_RAM_ORX_AGN_LOCK_TOTH__PRE 0x07824 7825#define SCU_RAM_ORX_AGN_LOCK_MASK__A 0x831F157826#define SCU_RAM_ORX_AGN_LOCK_MASK__W 87827#define SCU_RAM_ORX_AGN_LOCK_MASK__M 0xFF7828#define SCU_RAM_ORX_AGN_LOCK_MASK__PRE 0x07829 7830#define SCU_RAM_ORX_DGN__A 0x831F167831#define SCU_RAM_ORX_DGN__W 167832#define SCU_RAM_ORX_DGN__M 0xFFFF7833#define SCU_RAM_ORX_DGN__PRE 0x07834 7835#define SCU_RAM_ORX_DGN_MIN__A 0x831F177836#define SCU_RAM_ORX_DGN_MIN__W 167837#define SCU_RAM_ORX_DGN_MIN__M 0xFFFF7838#define SCU_RAM_ORX_DGN_MIN__PRE 0x07839 7840#define SCU_RAM_ORX_DGN_MAX__A 0x831F187841#define SCU_RAM_ORX_DGN_MAX__W 167842#define SCU_RAM_ORX_DGN_MAX__M 0xFFFF7843#define SCU_RAM_ORX_DGN_MAX__PRE 0x07844 7845#define SCU_RAM_ORX_DGN_AMP__A 0x831F197846#define SCU_RAM_ORX_DGN_AMP__W 167847#define SCU_RAM_ORX_DGN_AMP__M 0xFFFF7848#define SCU_RAM_ORX_DGN_AMP__PRE 0x07849 7850#define SCU_RAM_ORX_DGN_AMPTARGET__A 0x831F1A7851#define SCU_RAM_ORX_DGN_AMPTARGET__W 167852#define SCU_RAM_ORX_DGN_AMPTARGET__M 0xFFFF7853#define SCU_RAM_ORX_DGN_AMPTARGET__PRE 0x07854 7855#define SCU_RAM_ORX_DGN_KI__A 0x831F1B7856#define SCU_RAM_ORX_DGN_KI__W 87857#define SCU_RAM_ORX_DGN_KI__M 0xFF7858#define SCU_RAM_ORX_DGN_KI__PRE 0x07859 7860#define SCU_RAM_ORX_DGN_LOCK_TH__A 0x831F1C7861#define SCU_RAM_ORX_DGN_LOCK_TH__W 167862#define SCU_RAM_ORX_DGN_LOCK_TH__M 0xFFFF7863#define SCU_RAM_ORX_DGN_LOCK_TH__PRE 0x07864 7865#define SCU_RAM_ORX_DGN_LOCK_WD__A 0x831F1D7866#define SCU_RAM_ORX_DGN_LOCK_WD__W 167867#define SCU_RAM_ORX_DGN_LOCK_WD__M 0xFFFF7868#define SCU_RAM_ORX_DGN_LOCK_WD__PRE 0x07869 7870#define SCU_RAM_ORX_DGN_ONLOCK_TTH__A 0x831F1E7871#define SCU_RAM_ORX_DGN_ONLOCK_TTH__W 167872#define SCU_RAM_ORX_DGN_ONLOCK_TTH__M 0xFFFF7873#define SCU_RAM_ORX_DGN_ONLOCK_TTH__PRE 0x07874 7875#define SCU_RAM_ORX_DGN_UNLOCK_TTH__A 0x831F1F7876#define SCU_RAM_ORX_DGN_UNLOCK_TTH__W 167877#define SCU_RAM_ORX_DGN_UNLOCK_TTH__M 0xFFFF7878#define SCU_RAM_ORX_DGN_UNLOCK_TTH__PRE 0x07879 7880#define SCU_RAM_ORX_DGN_LOCK_TOTH__A 0x831F207881#define SCU_RAM_ORX_DGN_LOCK_TOTH__W 167882#define SCU_RAM_ORX_DGN_LOCK_TOTH__M 0xFFFF7883#define SCU_RAM_ORX_DGN_LOCK_TOTH__PRE 0x07884 7885#define SCU_RAM_ORX_DGN_LOCK_MASK__A 0x831F217886#define SCU_RAM_ORX_DGN_LOCK_MASK__W 87887#define SCU_RAM_ORX_DGN_LOCK_MASK__M 0xFF7888#define SCU_RAM_ORX_DGN_LOCK_MASK__PRE 0x07889 7890#define SCU_RAM_ORX_FREQ_GAIN_CORR__A 0x831F227891#define SCU_RAM_ORX_FREQ_GAIN_CORR__W 87892#define SCU_RAM_ORX_FREQ_GAIN_CORR__M 0xFF7893#define SCU_RAM_ORX_FREQ_GAIN_CORR__PRE 0x07894#define SCU_RAM_ORX_FREQ_GAIN_CORR_1544KBPS 0x607895#define SCU_RAM_ORX_FREQ_GAIN_CORR_2048KBPS 0x807896#define SCU_RAM_ORX_FREQ_GAIN_CORR_3088KBPS 0xC07897 7898#define SCU_RAM_ORX_FRQ_OFFSET__A 0x831F237899#define SCU_RAM_ORX_FRQ_OFFSET__W 167900#define SCU_RAM_ORX_FRQ_OFFSET__M 0xFFFF7901#define SCU_RAM_ORX_FRQ_OFFSET__PRE 0x07902 7903#define SCU_RAM_ORX_FRQ_OFFSET_MAX__A 0x831F247904#define SCU_RAM_ORX_FRQ_OFFSET_MAX__W 157905#define SCU_RAM_ORX_FRQ_OFFSET_MAX__M 0x7FFF7906#define SCU_RAM_ORX_FRQ_OFFSET_MAX__PRE 0x07907 7908#define SCU_RAM_ORX_FRQ_KI__A 0x831F257909#define SCU_RAM_ORX_FRQ_KI__W 87910#define SCU_RAM_ORX_FRQ_KI__M 0xFF7911#define SCU_RAM_ORX_FRQ_KI__PRE 0x07912 7913#define SCU_RAM_ORX_FRQ_DIFF__A 0x831F267914#define SCU_RAM_ORX_FRQ_DIFF__W 167915#define SCU_RAM_ORX_FRQ_DIFF__M 0xFFFF7916#define SCU_RAM_ORX_FRQ_DIFF__PRE 0x07917 7918#define SCU_RAM_ORX_FRQ_LOCK_TH__A 0x831F277919#define SCU_RAM_ORX_FRQ_LOCK_TH__W 167920#define SCU_RAM_ORX_FRQ_LOCK_TH__M 0xFFFF7921#define SCU_RAM_ORX_FRQ_LOCK_TH__PRE 0x07922 7923#define SCU_RAM_ORX_FRQ_LOCK_WD__A 0x831F287924#define SCU_RAM_ORX_FRQ_LOCK_WD__W 167925#define SCU_RAM_ORX_FRQ_LOCK_WD__M 0xFFFF7926#define SCU_RAM_ORX_FRQ_LOCK_WD__PRE 0x07927 7928#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__A 0x831F297929#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__W 167930#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__M 0xFFFF7931#define SCU_RAM_ORX_FRQ_ONLOCK_TTH__PRE 0x07932 7933#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__A 0x831F2A7934#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__W 167935#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__M 0xFFFF7936#define SCU_RAM_ORX_FRQ_UNLOCK_TTH__PRE 0x07937 7938#define SCU_RAM_ORX_FRQ_LOCK_TOTH__A 0x831F2B7939#define SCU_RAM_ORX_FRQ_LOCK_TOTH__W 167940#define SCU_RAM_ORX_FRQ_LOCK_TOTH__M 0xFFFF7941#define SCU_RAM_ORX_FRQ_LOCK_TOTH__PRE 0x07942 7943#define SCU_RAM_ORX_FRQ_LOCK_MASK__A 0x831F2C7944#define SCU_RAM_ORX_FRQ_LOCK_MASK__W 87945#define SCU_RAM_ORX_FRQ_LOCK_MASK__M 0xFF7946#define SCU_RAM_ORX_FRQ_LOCK_MASK__PRE 0x07947 7948#define SCU_RAM_ORX_PHA_DIFF__A 0x831F2D7949#define SCU_RAM_ORX_PHA_DIFF__W 167950#define SCU_RAM_ORX_PHA_DIFF__M 0xFFFF7951#define SCU_RAM_ORX_PHA_DIFF__PRE 0x07952 7953#define SCU_RAM_ORX_PHA_LOCK_TH__A 0x831F2E7954#define SCU_RAM_ORX_PHA_LOCK_TH__W 167955#define SCU_RAM_ORX_PHA_LOCK_TH__M 0xFFFF7956#define SCU_RAM_ORX_PHA_LOCK_TH__PRE 0x07957 7958#define SCU_RAM_ORX_PHA_LOCK_WD__A 0x831F2F7959#define SCU_RAM_ORX_PHA_LOCK_WD__W 167960#define SCU_RAM_ORX_PHA_LOCK_WD__M 0xFFFF7961#define SCU_RAM_ORX_PHA_LOCK_WD__PRE 0x07962 7963#define SCU_RAM_ORX_PHA_ONLOCK_TTH__A 0x831F307964#define SCU_RAM_ORX_PHA_ONLOCK_TTH__W 167965#define SCU_RAM_ORX_PHA_ONLOCK_TTH__M 0xFFFF7966#define SCU_RAM_ORX_PHA_ONLOCK_TTH__PRE 0x07967 7968#define SCU_RAM_ORX_PHA_UNLOCK_TTH__A 0x831F317969#define SCU_RAM_ORX_PHA_UNLOCK_TTH__W 167970#define SCU_RAM_ORX_PHA_UNLOCK_TTH__M 0xFFFF7971#define SCU_RAM_ORX_PHA_UNLOCK_TTH__PRE 0x07972 7973#define SCU_RAM_ORX_PHA_LOCK_TOTH__A 0x831F327974#define SCU_RAM_ORX_PHA_LOCK_TOTH__W 167975#define SCU_RAM_ORX_PHA_LOCK_TOTH__M 0xFFFF7976#define SCU_RAM_ORX_PHA_LOCK_TOTH__PRE 0x07977 7978#define SCU_RAM_ORX_PHA_LOCK_MASK__A 0x831F337979#define SCU_RAM_ORX_PHA_LOCK_MASK__W 87980#define SCU_RAM_ORX_PHA_LOCK_MASK__M 0xFF7981#define SCU_RAM_ORX_PHA_LOCK_MASK__PRE 0x07982 7983#define SCU_RAM_ORX_TIM_OFFSET__A 0x831F347984#define SCU_RAM_ORX_TIM_OFFSET__W 167985#define SCU_RAM_ORX_TIM_OFFSET__M 0xFFFF7986#define SCU_RAM_ORX_TIM_OFFSET__PRE 0x07987 7988#define SCU_RAM_ORX_TIM_DIFF__A 0x831F357989#define SCU_RAM_ORX_TIM_DIFF__W 167990#define SCU_RAM_ORX_TIM_DIFF__M 0xFFFF7991#define SCU_RAM_ORX_TIM_DIFF__PRE 0x07992 7993#define SCU_RAM_ORX_TIM_LOCK_TH__A 0x831F367994#define SCU_RAM_ORX_TIM_LOCK_TH__W 167995#define SCU_RAM_ORX_TIM_LOCK_TH__M 0xFFFF7996#define SCU_RAM_ORX_TIM_LOCK_TH__PRE 0x07997 7998#define SCU_RAM_ORX_TIM_LOCK_WD__A 0x831F377999#define SCU_RAM_ORX_TIM_LOCK_WD__W 168000#define SCU_RAM_ORX_TIM_LOCK_WD__M 0xFFFF8001#define SCU_RAM_ORX_TIM_LOCK_WD__PRE 0x08002 8003#define SCU_RAM_ORX_TIM_ONLOCK_TTH__A 0x831F388004#define SCU_RAM_ORX_TIM_ONLOCK_TTH__W 168005#define SCU_RAM_ORX_TIM_ONLOCK_TTH__M 0xFFFF8006#define SCU_RAM_ORX_TIM_ONLOCK_TTH__PRE 0x08007 8008#define SCU_RAM_ORX_TIM_UNLOCK_TTH__A 0x831F398009#define SCU_RAM_ORX_TIM_UNLOCK_TTH__W 168010#define SCU_RAM_ORX_TIM_UNLOCK_TTH__M 0xFFFF8011#define SCU_RAM_ORX_TIM_UNLOCK_TTH__PRE 0x08012 8013#define SCU_RAM_ORX_TIM_LOCK_TOTH__A 0x831F3A8014#define SCU_RAM_ORX_TIM_LOCK_TOTH__W 168015#define SCU_RAM_ORX_TIM_LOCK_TOTH__M 0xFFFF8016#define SCU_RAM_ORX_TIM_LOCK_TOTH__PRE 0x08017 8018#define SCU_RAM_ORX_TIM_LOCK_MASK__A 0x831F3B8019#define SCU_RAM_ORX_TIM_LOCK_MASK__W 88020#define SCU_RAM_ORX_TIM_LOCK_MASK__M 0xFF8021#define SCU_RAM_ORX_TIM_LOCK_MASK__PRE 0x08022 8023#define SCU_RAM_ORX_EQU_DIFF__A 0x831F3C8024#define SCU_RAM_ORX_EQU_DIFF__W 168025#define SCU_RAM_ORX_EQU_DIFF__M 0xFFFF8026#define SCU_RAM_ORX_EQU_DIFF__PRE 0x08027 8028#define SCU_RAM_ORX_EQU_LOCK_TH__A 0x831F3D8029#define SCU_RAM_ORX_EQU_LOCK_TH__W 168030#define SCU_RAM_ORX_EQU_LOCK_TH__M 0xFFFF8031#define SCU_RAM_ORX_EQU_LOCK_TH__PRE 0x08032 8033#define SCU_RAM_ORX_EQU_LOCK_WD__A 0x831F3E8034#define SCU_RAM_ORX_EQU_LOCK_WD__W 168035#define SCU_RAM_ORX_EQU_LOCK_WD__M 0xFFFF8036#define SCU_RAM_ORX_EQU_LOCK_WD__PRE 0x08037 8038#define SCU_RAM_ORX_EQU_ONLOCK_TTH__A 0x831F3F8039#define SCU_RAM_ORX_EQU_ONLOCK_TTH__W 168040#define SCU_RAM_ORX_EQU_ONLOCK_TTH__M 0xFFFF8041#define SCU_RAM_ORX_EQU_ONLOCK_TTH__PRE 0x08042 8043#define SCU_RAM_ORX_EQU_UNLOCK_TTH__A 0x831F408044#define SCU_RAM_ORX_EQU_UNLOCK_TTH__W 168045#define SCU_RAM_ORX_EQU_UNLOCK_TTH__M 0xFFFF8046#define SCU_RAM_ORX_EQU_UNLOCK_TTH__PRE 0x08047 8048#define SCU_RAM_ORX_EQU_LOCK_TOTH__A 0x831F418049#define SCU_RAM_ORX_EQU_LOCK_TOTH__W 168050#define SCU_RAM_ORX_EQU_LOCK_TOTH__M 0xFFFF8051#define SCU_RAM_ORX_EQU_LOCK_TOTH__PRE 0x08052 8053#define SCU_RAM_ORX_EQU_LOCK_MASK__A 0x831F428054#define SCU_RAM_ORX_EQU_LOCK_MASK__W 88055#define SCU_RAM_ORX_EQU_LOCK_MASK__M 0xFF8056#define SCU_RAM_ORX_EQU_LOCK_MASK__PRE 0x08057 8058#define SCU_RAM_ORX_FLT_FRQ__A 0x831F438059#define SCU_RAM_ORX_FLT_FRQ__W 168060#define SCU_RAM_ORX_FLT_FRQ__M 0xFFFF8061#define SCU_RAM_ORX_FLT_FRQ__PRE 0x08062#define SCU_RAM_ORX_RST_CPH__A 0x831F448063#define SCU_RAM_ORX_RST_CPH__W 48064#define SCU_RAM_ORX_RST_CPH__M 0xF8065#define SCU_RAM_ORX_RST_CPH__PRE 0x08066 8067#define SCU_RAM_ORX_RST_CPH_RST_CPH__B 08068#define SCU_RAM_ORX_RST_CPH_RST_CPH__W 48069#define SCU_RAM_ORX_RST_CPH_RST_CPH__M 0xF8070#define SCU_RAM_ORX_RST_CPH_RST_CPH__PRE 0x08071 8072#define SCU_RAM_ORX_RST_CTI__A 0x831F458073#define SCU_RAM_ORX_RST_CTI__W 48074#define SCU_RAM_ORX_RST_CTI__M 0xF8075#define SCU_RAM_ORX_RST_CTI__PRE 0x08076 8077#define SCU_RAM_ORX_RST_CTI_RST_CTI__B 08078#define SCU_RAM_ORX_RST_CTI_RST_CTI__W 48079#define SCU_RAM_ORX_RST_CTI_RST_CTI__M 0xF8080#define SCU_RAM_ORX_RST_CTI_RST_CTI__PRE 0x08081 8082#define SCU_RAM_ORX_RST_KRN__A 0x831F468083#define SCU_RAM_ORX_RST_KRN__W 48084#define SCU_RAM_ORX_RST_KRN__M 0xF8085#define SCU_RAM_ORX_RST_KRN__PRE 0x08086 8087#define SCU_RAM_ORX_RST_KRN_RST_KRN__B 08088#define SCU_RAM_ORX_RST_KRN_RST_KRN__W 48089#define SCU_RAM_ORX_RST_KRN_RST_KRN__M 0xF8090#define SCU_RAM_ORX_RST_KRN_RST_KRN__PRE 0x08091 8092#define SCU_RAM_ORX_RST_KRP__A 0x831F478093#define SCU_RAM_ORX_RST_KRP__W 48094#define SCU_RAM_ORX_RST_KRP__M 0xF8095#define SCU_RAM_ORX_RST_KRP__PRE 0x08096 8097#define SCU_RAM_ORX_RST_KRP_RST_KRP__B 08098#define SCU_RAM_ORX_RST_KRP_RST_KRP__W 48099#define SCU_RAM_ORX_RST_KRP_RST_KRP__M 0xF8100#define SCU_RAM_ORX_RST_KRP_RST_KRP__PRE 0x08101 8102#define SCU_RAM_ATV_STANDARD__A 0x831F488103#define SCU_RAM_ATV_STANDARD__W 128104#define SCU_RAM_ATV_STANDARD__M 0xFFF8105#define SCU_RAM_ATV_STANDARD__PRE 0x08106 8107#define SCU_RAM_ATV_STANDARD_STANDARD__B 08108#define SCU_RAM_ATV_STANDARD_STANDARD__W 128109#define SCU_RAM_ATV_STANDARD_STANDARD__M 0xFFF8110#define SCU_RAM_ATV_STANDARD_STANDARD__PRE 0x08111#define SCU_RAM_ATV_STANDARD_STANDARD_MN 0x28112#define SCU_RAM_ATV_STANDARD_STANDARD_B 0x1038113#define SCU_RAM_ATV_STANDARD_STANDARD_G 0x38114#define SCU_RAM_ATV_STANDARD_STANDARD_DK 0x48115#define SCU_RAM_ATV_STANDARD_STANDARD_L 0x98116#define SCU_RAM_ATV_STANDARD_STANDARD_LP 0x1098117#define SCU_RAM_ATV_STANDARD_STANDARD_I 0xA8118#define SCU_RAM_ATV_STANDARD_STANDARD_FM 0x408119 8120#define SCU_RAM_ATV_DETECT__A 0x831F498121#define SCU_RAM_ATV_DETECT__W 18122#define SCU_RAM_ATV_DETECT__M 0x18123#define SCU_RAM_ATV_DETECT__PRE 0x08124 8125#define SCU_RAM_ATV_DETECT_DETECT__B 08126#define SCU_RAM_ATV_DETECT_DETECT__W 18127#define SCU_RAM_ATV_DETECT_DETECT__M 0x18128#define SCU_RAM_ATV_DETECT_DETECT__PRE 0x08129#define SCU_RAM_ATV_DETECT_DETECT_false 0x08130#define SCU_RAM_ATV_DETECT_DETECT_true 0x18131 8132#define SCU_RAM_ATV_DETECT_TH__A 0x831F4A8133#define SCU_RAM_ATV_DETECT_TH__W 88134#define SCU_RAM_ATV_DETECT_TH__M 0xFF8135#define SCU_RAM_ATV_DETECT_TH__PRE 0x08136 8137#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__B 08138#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__W 88139#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__M 0xFF8140#define SCU_RAM_ATV_DETECT_TH_DETECT_TH__PRE 0x08141 8142#define SCU_RAM_ATV_LOCK__A 0x831F4B8143#define SCU_RAM_ATV_LOCK__W 28144#define SCU_RAM_ATV_LOCK__M 0x38145#define SCU_RAM_ATV_LOCK__PRE 0x08146 8147#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__B 08148#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__W 18149#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__M 0x18150#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT__PRE 0x08151#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_NO_LOCK 0x08152#define SCU_RAM_ATV_LOCK_CR_LOCK_BIT_LOCK 0x18153 8154#define SCU_RAM_ATV_LOCK_SYNC_FLAG__B 18155#define SCU_RAM_ATV_LOCK_SYNC_FLAG__W 18156#define SCU_RAM_ATV_LOCK_SYNC_FLAG__M 0x28157#define SCU_RAM_ATV_LOCK_SYNC_FLAG__PRE 0x08158#define SCU_RAM_ATV_LOCK_SYNC_FLAG_NO_SYNC 0x08159#define SCU_RAM_ATV_LOCK_SYNC_FLAG_SYNC 0x28160 8161#define SCU_RAM_ATV_CR_LOCK__A 0x831F4C8162#define SCU_RAM_ATV_CR_LOCK__W 118163#define SCU_RAM_ATV_CR_LOCK__M 0x7FF8164#define SCU_RAM_ATV_CR_LOCK__PRE 0x08165 8166#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__B 08167#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__W 118168#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__M 0x7FF8169#define SCU_RAM_ATV_CR_LOCK_CR_LOCK__PRE 0x08170 8171#define SCU_RAM_ATV_AGC_MODE__A 0x831F4D8172#define SCU_RAM_ATV_AGC_MODE__W 88173#define SCU_RAM_ATV_AGC_MODE__M 0xFF8174#define SCU_RAM_ATV_AGC_MODE__PRE 0x08175 8176#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__B 28177#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__W 18178#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__M 0x48179#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL__PRE 0x08180#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_FAST 0x08181#define SCU_RAM_ATV_AGC_MODE_VAGC_VEL_AGC_SLOW 0x48182 8183#define SCU_RAM_ATV_AGC_MODE_BP_EN__B 38184#define SCU_RAM_ATV_AGC_MODE_BP_EN__W 18185#define SCU_RAM_ATV_AGC_MODE_BP_EN__M 0x88186#define SCU_RAM_ATV_AGC_MODE_BP_EN__PRE 0x08187#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_DISABLE 0x08188#define SCU_RAM_ATV_AGC_MODE_BP_EN_BPC_ENABLE 0x88189 8190#define SCU_RAM_ATV_AGC_MODE_SIF_STD__B 48191#define SCU_RAM_ATV_AGC_MODE_SIF_STD__W 28192#define SCU_RAM_ATV_AGC_MODE_SIF_STD__M 0x308193#define SCU_RAM_ATV_AGC_MODE_SIF_STD__PRE 0x08194#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_OFF 0x08195#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_FM 0x108196#define SCU_RAM_ATV_AGC_MODE_SIF_STD_SIF_AGC_AM 0x208197 8198#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__B 68199#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__W 18200#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__M 0x408201#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN__PRE 0x08202#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_DISABLE 0x08203#define SCU_RAM_ATV_AGC_MODE_FAST_VAGC_EN_FAGC_ENABLE 0x408204 8205#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__B 78206#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__W 18207#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__M 0x808208#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP__PRE 0x08209#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_ENABLE 0x08210#define SCU_RAM_ATV_AGC_MODE_MOD_WA_BP_MWA_DISABLE 0x808211 8212#define SCU_RAM_ATV_RSV_01__A 0x831F4E8213#define SCU_RAM_ATV_RSV_01__W 168214#define SCU_RAM_ATV_RSV_01__M 0xFFFF8215#define SCU_RAM_ATV_RSV_01__PRE 0x08216 8217#define SCU_RAM_ATV_RSV_02__A 0x831F4F8218#define SCU_RAM_ATV_RSV_02__W 168219#define SCU_RAM_ATV_RSV_02__M 0xFFFF8220#define SCU_RAM_ATV_RSV_02__PRE 0x08221 8222#define SCU_RAM_ATV_RSV_03__A 0x831F508223#define SCU_RAM_ATV_RSV_03__W 168224#define SCU_RAM_ATV_RSV_03__M 0xFFFF8225#define SCU_RAM_ATV_RSV_03__PRE 0x08226 8227#define SCU_RAM_ATV_RSV_04__A 0x831F518228#define SCU_RAM_ATV_RSV_04__W 168229#define SCU_RAM_ATV_RSV_04__M 0xFFFF8230#define SCU_RAM_ATV_RSV_04__PRE 0x08231#define SCU_RAM_ATV_FAGC_TH_RED__A 0x831F528232#define SCU_RAM_ATV_FAGC_TH_RED__W 88233#define SCU_RAM_ATV_FAGC_TH_RED__M 0xFF8234#define SCU_RAM_ATV_FAGC_TH_RED__PRE 0x08235 8236#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__B 08237#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__W 88238#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__M 0xFF8239#define SCU_RAM_ATV_FAGC_TH_RED_FAGC_TH_RED__PRE 0x08240 8241#define SCU_RAM_ATV_AMS_MAX_REF__A 0x831F538242#define SCU_RAM_ATV_AMS_MAX_REF__W 118243#define SCU_RAM_ATV_AMS_MAX_REF__M 0x7FF8244#define SCU_RAM_ATV_AMS_MAX_REF__PRE 0x08245 8246#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__B 08247#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__W 118248#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__M 0x7FF8249#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF__PRE 0x08250#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_BG_MN 0x2BC8251#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_DK 0x2D08252#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_I 0x3148253#define SCU_RAM_ATV_AMS_MAX_REF_AMS_MAX_REF_LLP 0x28A8254 8255#define SCU_RAM_ATV_ACT_AMX__A 0x831F548256#define SCU_RAM_ATV_ACT_AMX__W 118257#define SCU_RAM_ATV_ACT_AMX__M 0x7FF8258#define SCU_RAM_ATV_ACT_AMX__PRE 0x08259 8260#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__B 08261#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__W 118262#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__M 0x7FF8263#define SCU_RAM_ATV_ACT_AMX_ACT_AMX__PRE 0x08264 8265#define SCU_RAM_ATV_ACT_AMI__A 0x831F558266#define SCU_RAM_ATV_ACT_AMI__W 118267#define SCU_RAM_ATV_ACT_AMI__M 0x7FF8268#define SCU_RAM_ATV_ACT_AMI__PRE 0x08269 8270#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__B 08271#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__W 118272#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__M 0x7FF8273#define SCU_RAM_ATV_ACT_AMI_ACT_AMI__PRE 0x08274 8275#define SCU_RAM_ATV_RSV_05__A 0x831F568276#define SCU_RAM_ATV_RSV_05__W 168277#define SCU_RAM_ATV_RSV_05__M 0xFFFF8278#define SCU_RAM_ATV_RSV_05__PRE 0x08279 8280#define SCU_RAM_ATV_RSV_06__A 0x831F578281#define SCU_RAM_ATV_RSV_06__W 168282#define SCU_RAM_ATV_RSV_06__M 0xFFFF8283#define SCU_RAM_ATV_RSV_06__PRE 0x08284 8285#define SCU_RAM_ATV_RSV_07__A 0x831F588286#define SCU_RAM_ATV_RSV_07__W 168287#define SCU_RAM_ATV_RSV_07__M 0xFFFF8288#define SCU_RAM_ATV_RSV_07__PRE 0x08289 8290#define SCU_RAM_ATV_RSV_08__A 0x831F598291#define SCU_RAM_ATV_RSV_08__W 168292#define SCU_RAM_ATV_RSV_08__M 0xFFFF8293#define SCU_RAM_ATV_RSV_08__PRE 0x08294 8295#define SCU_RAM_ATV_RSV_09__A 0x831F5A8296#define SCU_RAM_ATV_RSV_09__W 168297#define SCU_RAM_ATV_RSV_09__M 0xFFFF8298#define SCU_RAM_ATV_RSV_09__PRE 0x08299 8300#define SCU_RAM_ATV_RSV_10__A 0x831F5B8301#define SCU_RAM_ATV_RSV_10__W 168302#define SCU_RAM_ATV_RSV_10__M 0xFFFF8303#define SCU_RAM_ATV_RSV_10__PRE 0x08304 8305#define SCU_RAM_ATV_RSV_11__A 0x831F5C8306#define SCU_RAM_ATV_RSV_11__W 168307#define SCU_RAM_ATV_RSV_11__M 0xFFFF8308#define SCU_RAM_ATV_RSV_11__PRE 0x08309 8310#define SCU_RAM_ATV_RSV_12__A 0x831F5D8311#define SCU_RAM_ATV_RSV_12__W 168312#define SCU_RAM_ATV_RSV_12__M 0xFFFF8313#define SCU_RAM_ATV_RSV_12__PRE 0x08314#define SCU_RAM_ATV_VID_GAIN_HI__A 0x831F5E8315#define SCU_RAM_ATV_VID_GAIN_HI__W 168316#define SCU_RAM_ATV_VID_GAIN_HI__M 0xFFFF8317#define SCU_RAM_ATV_VID_GAIN_HI__PRE 0x08318 8319#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__B 08320#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__W 168321#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__M 0xFFFF8322#define SCU_RAM_ATV_VID_GAIN_HI_VID_GAIN_HI__PRE 0x08323 8324#define SCU_RAM_ATV_VID_GAIN_LO__A 0x831F5F8325#define SCU_RAM_ATV_VID_GAIN_LO__W 88326#define SCU_RAM_ATV_VID_GAIN_LO__M 0xFF8327#define SCU_RAM_ATV_VID_GAIN_LO__PRE 0x08328 8329#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__B 08330#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__W 88331#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__M 0xFF8332#define SCU_RAM_ATV_VID_GAIN_LO_VID_GAIN_LO__PRE 0x08333 8334#define SCU_RAM_ATV_RSV_13__A 0x831F608335#define SCU_RAM_ATV_RSV_13__W 168336#define SCU_RAM_ATV_RSV_13__M 0xFFFF8337#define SCU_RAM_ATV_RSV_13__PRE 0x08338 8339#define SCU_RAM_ATV_RSV_14__A 0x831F618340#define SCU_RAM_ATV_RSV_14__W 168341#define SCU_RAM_ATV_RSV_14__M 0xFFFF8342#define SCU_RAM_ATV_RSV_14__PRE 0x08343 8344#define SCU_RAM_ATV_RSV_15__A 0x831F628345#define SCU_RAM_ATV_RSV_15__W 168346#define SCU_RAM_ATV_RSV_15__M 0xFFFF8347#define SCU_RAM_ATV_RSV_15__PRE 0x08348 8349#define SCU_RAM_ATV_RSV_16__A 0x831F638350#define SCU_RAM_ATV_RSV_16__W 168351#define SCU_RAM_ATV_RSV_16__M 0xFFFF8352#define SCU_RAM_ATV_RSV_16__PRE 0x08353#define SCU_RAM_ATV_AAGC_CNT__A 0x831F648354#define SCU_RAM_ATV_AAGC_CNT__W 88355#define SCU_RAM_ATV_AAGC_CNT__M 0xFF8356#define SCU_RAM_ATV_AAGC_CNT__PRE 0x08357 8358#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__B 08359#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__W 88360#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__M 0xFF8361#define SCU_RAM_ATV_AAGC_CNT_AAGC_CNT__PRE 0x08362 8363#define SCU_RAM_ATV_SIF_GAIN__A 0x831F658364#define SCU_RAM_ATV_SIF_GAIN__W 118365#define SCU_RAM_ATV_SIF_GAIN__M 0x7FF8366#define SCU_RAM_ATV_SIF_GAIN__PRE 0x08367 8368#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__B 08369#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__W 118370#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__M 0x7FF8371#define SCU_RAM_ATV_SIF_GAIN_SIF_GAIN__PRE 0x08372 8373#define SCU_RAM_ATV_RSV_17__A 0x831F668374#define SCU_RAM_ATV_RSV_17__W 168375#define SCU_RAM_ATV_RSV_17__M 0xFFFF8376#define SCU_RAM_ATV_RSV_17__PRE 0x08377 8378#define SCU_RAM_ATV_RSV_18__A 0x831F678379#define SCU_RAM_ATV_RSV_18__W 168380#define SCU_RAM_ATV_RSV_18__M 0xFFFF8381#define SCU_RAM_ATV_RSV_18__PRE 0x08382 8383#define SCU_RAM_ATV_RATE_OFS__A 0x831F688384#define SCU_RAM_ATV_RATE_OFS__W 128385#define SCU_RAM_ATV_RATE_OFS__M 0xFFF8386#define SCU_RAM_ATV_RATE_OFS__PRE 0x08387 8388#define SCU_RAM_ATV_LO_INCR__A 0x831F698389#define SCU_RAM_ATV_LO_INCR__W 128390#define SCU_RAM_ATV_LO_INCR__M 0xFFF8391#define SCU_RAM_ATV_LO_INCR__PRE 0x08392 8393#define SCU_RAM_ATV_IIR_CRIT__A 0x831F6A8394#define SCU_RAM_ATV_IIR_CRIT__W 128395#define SCU_RAM_ATV_IIR_CRIT__M 0xFFF8396#define SCU_RAM_ATV_IIR_CRIT__PRE 0x08397 8398#define SCU_RAM_ATV_DEF_RATE_OFS__A 0x831F6B8399#define SCU_RAM_ATV_DEF_RATE_OFS__W 128400#define SCU_RAM_ATV_DEF_RATE_OFS__M 0xFFF8401#define SCU_RAM_ATV_DEF_RATE_OFS__PRE 0x08402 8403#define SCU_RAM_ATV_DEF_LO_INCR__A 0x831F6C8404#define SCU_RAM_ATV_DEF_LO_INCR__W 128405#define SCU_RAM_ATV_DEF_LO_INCR__M 0xFFF8406#define SCU_RAM_ATV_DEF_LO_INCR__PRE 0x08407 8408#define SCU_RAM_ATV_ENABLE_IIR_WA__A 0x831F6D8409#define SCU_RAM_ATV_ENABLE_IIR_WA__W 18410#define SCU_RAM_ATV_ENABLE_IIR_WA__M 0x18411#define SCU_RAM_ATV_ENABLE_IIR_WA__PRE 0x08412 8413#define SCU_RAM_ATV_MOD_CONTROL__A 0x831F6E8414#define SCU_RAM_ATV_MOD_CONTROL__W 128415#define SCU_RAM_ATV_MOD_CONTROL__M 0xFFF8416#define SCU_RAM_ATV_MOD_CONTROL__PRE 0x08417 8418#define SCU_RAM_ATV_PAGC_KI_MAX__A 0x831F6F8419#define SCU_RAM_ATV_PAGC_KI_MAX__W 128420#define SCU_RAM_ATV_PAGC_KI_MAX__M 0xFFF8421#define SCU_RAM_ATV_PAGC_KI_MAX__PRE 0x08422 8423#define SCU_RAM_ATV_BPC_KI_MAX__A 0x831F708424#define SCU_RAM_ATV_BPC_KI_MAX__W 128425#define SCU_RAM_ATV_BPC_KI_MAX__M 0xFFF8426#define SCU_RAM_ATV_BPC_KI_MAX__PRE 0x08427 8428#define SCU_RAM_ATV_NAGC_KI_MAX__A 0x831F718429#define SCU_RAM_ATV_NAGC_KI_MAX__W 128430#define SCU_RAM_ATV_NAGC_KI_MAX__M 0xFFF8431#define SCU_RAM_ATV_NAGC_KI_MAX__PRE 0x08432#define SCU_RAM_ATV_NAGC_KI_MIN__A 0x831F728433#define SCU_RAM_ATV_NAGC_KI_MIN__W 128434#define SCU_RAM_ATV_NAGC_KI_MIN__M 0xFFF8435#define SCU_RAM_ATV_NAGC_KI_MIN__PRE 0x08436 8437#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__B 08438#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__W 128439#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__M 0xFFF8440#define SCU_RAM_ATV_NAGC_KI_MIN_NAGC_KI_MIN__PRE 0x08441 8442#define SCU_RAM_ATV_KI_CHANGE_TH__A 0x831F738443#define SCU_RAM_ATV_KI_CHANGE_TH__W 88444#define SCU_RAM_ATV_KI_CHANGE_TH__M 0xFF8445#define SCU_RAM_ATV_KI_CHANGE_TH__PRE 0x08446 8447#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__B 08448#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__W 88449#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__M 0xFF8450#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH__PRE 0x08451#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_NEG_MOD 0x148452#define SCU_RAM_ATV_KI_CHANGE_TH_KI_CHANGE_TH_POS_MOD 0x288453 8454#define SCU_RAM_QAM_PARAM_ANNEX__A 0x831F748455#define SCU_RAM_QAM_PARAM_ANNEX__W 28456#define SCU_RAM_QAM_PARAM_ANNEX__M 0x38457#define SCU_RAM_QAM_PARAM_ANNEX__PRE 0x08458 8459#define SCU_RAM_QAM_PARAM_ANNEX_BIT__B 08460#define SCU_RAM_QAM_PARAM_ANNEX_BIT__W 28461#define SCU_RAM_QAM_PARAM_ANNEX_BIT__M 0x38462#define SCU_RAM_QAM_PARAM_ANNEX_BIT__PRE 0x08463#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_A 0x08464#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_B 0x18465#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_C 0x28466#define SCU_RAM_QAM_PARAM_ANNEX_BIT_ANNEX_D 0x38467 8468#define SCU_RAM_QAM_PARAM_CONSTELLATION__A 0x831F758469#define SCU_RAM_QAM_PARAM_CONSTELLATION__W 38470#define SCU_RAM_QAM_PARAM_CONSTELLATION__M 0x78471#define SCU_RAM_QAM_PARAM_CONSTELLATION__PRE 0x08472 8473#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__B 08474#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__W 38475#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__M 0x78476#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT__PRE 0x08477#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_UNKNOWN 0x08478#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_16 0x38479#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_32 0x48480#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_64 0x58481#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_128 0x68482#define SCU_RAM_QAM_PARAM_CONSTELLATION_BIT_QAM_256 0x78483 8484#define SCU_RAM_QAM_PARAM_INTERLEAVE__A 0x831F768485#define SCU_RAM_QAM_PARAM_INTERLEAVE__W 88486#define SCU_RAM_QAM_PARAM_INTERLEAVE__M 0xFF8487#define SCU_RAM_QAM_PARAM_INTERLEAVE__PRE 0x08488 8489#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__B 08490#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__W 88491#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__M 0xFF8492#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT__PRE 0x08493#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1 0x08494#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J1_V2 0x18495#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J2 0x28496#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I64_J2 0x38497#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J3 0x48498#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I32_J4 0x58499#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J4 0x68500#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I16_J8 0x78501#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J5 0x88502#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I8_J16 0x98503#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J6 0xA8504#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J7 0xC8505#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I128_J8 0xE8506#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I12_J17 0x108507#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_I5_J4 0x118508#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_UNKNOWN 0xFE8509#define SCU_RAM_QAM_PARAM_INTERLEAVE_BIT_AUTO 0xFF8510 8511#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__A 0x831F778512#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__W 168513#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__M 0xFFFF8514#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI__PRE 0x08515 8516#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__B 08517#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__W 168518#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__M 0xFFFF8519#define SCU_RAM_QAM_PARAM_SYM_RCRATE_HI_BIT__PRE 0x08520 8521#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__A 0x831F788522#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__W 168523#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__M 0xFFFF8524#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO__PRE 0x08525 8526#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__B 08527#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__W 168528#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__M 0xFFFF8529#define SCU_RAM_QAM_PARAM_SYM_RCRATE_LO_BIT__PRE 0x08530 8531#define SCU_RAM_QAM_EQ_CENTERTAP__A 0x831F798532#define SCU_RAM_QAM_EQ_CENTERTAP__W 168533#define SCU_RAM_QAM_EQ_CENTERTAP__M 0xFFFF8534#define SCU_RAM_QAM_EQ_CENTERTAP__PRE 0x08535 8536#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__B 08537#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__W 88538#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__M 0xFF8539#define SCU_RAM_QAM_EQ_CENTERTAP_BIT__PRE 0x08540 8541#define SCU_RAM_QAM_WR_RSV_0__A 0x831F7A8542#define SCU_RAM_QAM_WR_RSV_0__W 168543#define SCU_RAM_QAM_WR_RSV_0__M 0xFFFF8544#define SCU_RAM_QAM_WR_RSV_0__PRE 0x08545 8546#define SCU_RAM_QAM_WR_RSV_0_BIT__B 08547#define SCU_RAM_QAM_WR_RSV_0_BIT__W 168548#define SCU_RAM_QAM_WR_RSV_0_BIT__M 0xFFFF8549#define SCU_RAM_QAM_WR_RSV_0_BIT__PRE 0x08550 8551#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__A 0x831F7B8552#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__W 168553#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__M 0xFFFF8554#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI__PRE 0x08555 8556#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__B 08557#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__W 168558#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__M 0xFFFF8559#define SCU_RAM_QAM_PARAM_ALT_RCRATE_HI_BIT__PRE 0x08560 8561#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__A 0x831F7C8562#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__W 168563#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__M 0xFFFF8564#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO__PRE 0x08565 8566#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__B 08567#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__W 168568#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__M 0xFFFF8569#define SCU_RAM_QAM_PARAM_ALT_RCRATE_LO_BIT__PRE 0x08570 8571#define SCU_RAM_QAM_WR_RSV_5__A 0x831F7D8572#define SCU_RAM_QAM_WR_RSV_5__W 168573#define SCU_RAM_QAM_WR_RSV_5__M 0xFFFF8574#define SCU_RAM_QAM_WR_RSV_5__PRE 0x08575 8576#define SCU_RAM_QAM_WR_RSV_5_BIT__B 08577#define SCU_RAM_QAM_WR_RSV_5_BIT__W 168578#define SCU_RAM_QAM_WR_RSV_5_BIT__M 0xFFFF8579#define SCU_RAM_QAM_WR_RSV_5_BIT__PRE 0x08580 8581#define SCU_RAM_QAM_WR_RSV_6__A 0x831F7E8582#define SCU_RAM_QAM_WR_RSV_6__W 168583#define SCU_RAM_QAM_WR_RSV_6__M 0xFFFF8584#define SCU_RAM_QAM_WR_RSV_6__PRE 0x08585 8586#define SCU_RAM_QAM_WR_RSV_6_BIT__B 08587#define SCU_RAM_QAM_WR_RSV_6_BIT__W 168588#define SCU_RAM_QAM_WR_RSV_6_BIT__M 0xFFFF8589#define SCU_RAM_QAM_WR_RSV_6_BIT__PRE 0x08590 8591#define SCU_RAM_QAM_WR_RSV_7__A 0x831F7F8592#define SCU_RAM_QAM_WR_RSV_7__W 168593#define SCU_RAM_QAM_WR_RSV_7__M 0xFFFF8594#define SCU_RAM_QAM_WR_RSV_7__PRE 0x08595 8596#define SCU_RAM_QAM_WR_RSV_7_BIT__B 08597#define SCU_RAM_QAM_WR_RSV_7_BIT__W 168598#define SCU_RAM_QAM_WR_RSV_7_BIT__M 0xFFFF8599#define SCU_RAM_QAM_WR_RSV_7_BIT__PRE 0x08600 8601#define SCU_RAM_QAM_WR_RSV_8__A 0x831F808602#define SCU_RAM_QAM_WR_RSV_8__W 168603#define SCU_RAM_QAM_WR_RSV_8__M 0xFFFF8604#define SCU_RAM_QAM_WR_RSV_8__PRE 0x08605 8606#define SCU_RAM_QAM_WR_RSV_8_BIT__B 08607#define SCU_RAM_QAM_WR_RSV_8_BIT__W 168608#define SCU_RAM_QAM_WR_RSV_8_BIT__M 0xFFFF8609#define SCU_RAM_QAM_WR_RSV_8_BIT__PRE 0x08610 8611#define SCU_RAM_QAM_WR_RSV_9__A 0x831F818612#define SCU_RAM_QAM_WR_RSV_9__W 168613#define SCU_RAM_QAM_WR_RSV_9__M 0xFFFF8614#define SCU_RAM_QAM_WR_RSV_9__PRE 0x08615 8616#define SCU_RAM_QAM_WR_RSV_9_BIT__B 08617#define SCU_RAM_QAM_WR_RSV_9_BIT__W 168618#define SCU_RAM_QAM_WR_RSV_9_BIT__M 0xFFFF8619#define SCU_RAM_QAM_WR_RSV_9_BIT__PRE 0x08620 8621#define SCU_RAM_QAM_WR_RSV_10__A 0x831F828622#define SCU_RAM_QAM_WR_RSV_10__W 168623#define SCU_RAM_QAM_WR_RSV_10__M 0xFFFF8624#define SCU_RAM_QAM_WR_RSV_10__PRE 0x08625 8626#define SCU_RAM_QAM_WR_RSV_10_BIT__B 08627#define SCU_RAM_QAM_WR_RSV_10_BIT__W 168628#define SCU_RAM_QAM_WR_RSV_10_BIT__M 0xFFFF8629#define SCU_RAM_QAM_WR_RSV_10_BIT__PRE 0x08630 8631#define SCU_RAM_QAM_FSM_FMHUM_TO__A 0x831F838632#define SCU_RAM_QAM_FSM_FMHUM_TO__W 168633#define SCU_RAM_QAM_FSM_FMHUM_TO__M 0xFFFF8634#define SCU_RAM_QAM_FSM_FMHUM_TO__PRE 0x08635 8636#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__B 08637#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__W 168638#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__M 0xFFFF8639#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT__PRE 0x08640#define SCU_RAM_QAM_FSM_FMHUM_TO_BIT_NO_FMHUM_TO 0x08641 8642#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F848643#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__W 168644#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__M 0xFFFF8645#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__PRE 0x08646 8647#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__B 08648#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__W 168649#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__M 0xFFFF8650#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT_BIT__PRE 0x08651 8652#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F858653#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__W 168654#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__M 0xFFFF8655#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__PRE 0x08656 8657#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__B 08658#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__W 168659#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__M 0xFFFF8660#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT_BIT__PRE 0x08661 8662#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F868663#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__W 168664#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__M 0xFFFF8665#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__PRE 0x08666 8667#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__B 08668#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__W 168669#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__M 0xFFFF8670#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1_BIT__PRE 0x08671 8672#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F878673#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__W 168674#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__M 0xFFFF8675#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__PRE 0x08676 8677#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__B 08678#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__W 168679#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__M 0xFFFF8680#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2_BIT__PRE 0x08681 8682#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F888683#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__W 168684#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__M 0xFFFF8685#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__PRE 0x08686 8687#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__B 08688#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__W 168689#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__M 0xFFFF8690#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3_BIT__PRE 0x08691 8692#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F898693#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__W 168694#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__M 0xFFFF8695#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__PRE 0x08696 8697#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__B 08698#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__W 168699#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__M 0xFFFF8700#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4_BIT__PRE 0x08701 8702#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A8703#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__W 168704#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__M 0xFFFF8705#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__PRE 0x08706 8707#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__B 08708#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__W 168709#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__M 0xFFFF8710#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5_BIT__PRE 0x08711 8712#define SCU_RAM_QAM_FSM_STATE_TGT__A 0x831F8B8713#define SCU_RAM_QAM_FSM_STATE_TGT__W 48714#define SCU_RAM_QAM_FSM_STATE_TGT__M 0xF8715#define SCU_RAM_QAM_FSM_STATE_TGT__PRE 0x08716 8717#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__B 08718#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__W 48719#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__M 0xF8720#define SCU_RAM_QAM_FSM_STATE_TGT_BIT__PRE 0x08721#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_AMP 0x08722#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_RATE 0x18723#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_FREQ 0x28724#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_UPRIGHT 0x38725#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_HUNTING_PHASE 0x48726#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_PHNOISE 0x58727#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING 0x68728#define SCU_RAM_QAM_FSM_STATE_TGT_BIT_TRACKING_BURST 0x78729 8730#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__A 0x831F8C8731#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__W 98732#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__M 0x1FF8733#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE__PRE 0x08734 8735#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__B 08736#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__W 18737#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__M 0x18738#define SCU_RAM_QAM_FSM_LOCK_OVERRIDE_LCK_AMP__PRE 0x08739 8740#define SCU_RAM_QAM_FSM_ATH__A 0x831F8D8741#define SCU_RAM_QAM_FSM_ATH__W 168742#define SCU_RAM_QAM_FSM_ATH__M 0xFFFF8743#define SCU_RAM_QAM_FSM_ATH__PRE 0x08744 8745#define SCU_RAM_QAM_FSM_ATH_BIT__B 08746#define SCU_RAM_QAM_FSM_ATH_BIT__W 168747#define SCU_RAM_QAM_FSM_ATH_BIT__M 0xFFFF8748#define SCU_RAM_QAM_FSM_ATH_BIT__PRE 0x08749 8750#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E8751#define SCU_RAM_QAM_FSM_RTH__W 168752#define SCU_RAM_QAM_FSM_RTH__M 0xFFFF8753#define SCU_RAM_QAM_FSM_RTH__PRE 0x08754 8755#define SCU_RAM_QAM_FSM_RTH_BIT__B 08756#define SCU_RAM_QAM_FSM_RTH_BIT__W 168757#define SCU_RAM_QAM_FSM_RTH_BIT__M 0xFFFF8758#define SCU_RAM_QAM_FSM_RTH_BIT__PRE 0x08759#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_16 0x8C8760#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_32 0x508761#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_64 0x4E8762#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_128 0x328763#define SCU_RAM_QAM_FSM_RTH_BIT_QAM_256 0x2D8764 8765#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F8766#define SCU_RAM_QAM_FSM_FTH__W 168767#define SCU_RAM_QAM_FSM_FTH__M 0xFFFF8768#define SCU_RAM_QAM_FSM_FTH__PRE 0x08769 8770#define SCU_RAM_QAM_FSM_FTH_BIT__B 08771#define SCU_RAM_QAM_FSM_FTH_BIT__W 168772#define SCU_RAM_QAM_FSM_FTH_BIT__M 0xFFFF8773#define SCU_RAM_QAM_FSM_FTH_BIT__PRE 0x08774#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_16 0x328775#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_32 0x1E8776#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_64 0x1E8777#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_128 0x148778#define SCU_RAM_QAM_FSM_FTH_BIT_QAM_256 0x148779 8780#define SCU_RAM_QAM_FSM_PTH__A 0x831F908781#define SCU_RAM_QAM_FSM_PTH__W 168782#define SCU_RAM_QAM_FSM_PTH__M 0xFFFF8783#define SCU_RAM_QAM_FSM_PTH__PRE 0x08784 8785#define SCU_RAM_QAM_FSM_PTH_BIT__B 08786#define SCU_RAM_QAM_FSM_PTH_BIT__W 168787#define SCU_RAM_QAM_FSM_PTH_BIT__M 0xFFFF8788#define SCU_RAM_QAM_FSM_PTH_BIT__PRE 0x08789#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_16 0xC88790#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_32 0x968791#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_64 0x8C8792#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_128 0x648793#define SCU_RAM_QAM_FSM_PTH_BIT_QAM_256 0x648794 8795#define SCU_RAM_QAM_FSM_MTH__A 0x831F918796#define SCU_RAM_QAM_FSM_MTH__W 168797#define SCU_RAM_QAM_FSM_MTH__M 0xFFFF8798#define SCU_RAM_QAM_FSM_MTH__PRE 0x08799 8800#define SCU_RAM_QAM_FSM_MTH_BIT__B 08801#define SCU_RAM_QAM_FSM_MTH_BIT__W 168802#define SCU_RAM_QAM_FSM_MTH_BIT__M 0xFFFF8803#define SCU_RAM_QAM_FSM_MTH_BIT__PRE 0x08804#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_16 0x5A8805#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_32 0x508806#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_64 0x468807#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_128 0x3C8808#define SCU_RAM_QAM_FSM_MTH_BIT_QAM_256 0x508809 8810#define SCU_RAM_QAM_FSM_CTH__A 0x831F928811#define SCU_RAM_QAM_FSM_CTH__W 168812#define SCU_RAM_QAM_FSM_CTH__M 0xFFFF8813#define SCU_RAM_QAM_FSM_CTH__PRE 0x08814 8815#define SCU_RAM_QAM_FSM_CTH_BIT__B 08816#define SCU_RAM_QAM_FSM_CTH_BIT__W 168817#define SCU_RAM_QAM_FSM_CTH_BIT__M 0xFFFF8818#define SCU_RAM_QAM_FSM_CTH_BIT__PRE 0x08819#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_16 0xA08820#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_32 0x8C8821#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_64 0x8C8822#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_128 0x8C8823#define SCU_RAM_QAM_FSM_CTH_BIT_QAM_256 0x8C8824 8825#define SCU_RAM_QAM_FSM_QTH__A 0x831F938826#define SCU_RAM_QAM_FSM_QTH__W 168827#define SCU_RAM_QAM_FSM_QTH__M 0xFFFF8828#define SCU_RAM_QAM_FSM_QTH__PRE 0x08829 8830#define SCU_RAM_QAM_FSM_QTH_BIT__B 08831#define SCU_RAM_QAM_FSM_QTH_BIT__W 168832#define SCU_RAM_QAM_FSM_QTH_BIT__M 0xFFFF8833#define SCU_RAM_QAM_FSM_QTH_BIT__PRE 0x08834#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_16 0xE68835#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_32 0xAA8836#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_64 0xC38837#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_128 0x8C8838#define SCU_RAM_QAM_FSM_QTH_BIT_QAM_256 0x968839 8840#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F948841#define SCU_RAM_QAM_FSM_RATE_LIM__W 168842#define SCU_RAM_QAM_FSM_RATE_LIM__M 0xFFFF8843#define SCU_RAM_QAM_FSM_RATE_LIM__PRE 0x08844 8845#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__B 08846#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__W 168847#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__M 0xFFFF8848#define SCU_RAM_QAM_FSM_RATE_LIM_BIT__PRE 0x08849#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_16 0x468850#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_32 0x468851#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_64 0x468852#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_128 0x468853#define SCU_RAM_QAM_FSM_RATE_LIM_BIT_QAM_256 0x468854 8855#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F958856#define SCU_RAM_QAM_FSM_FREQ_LIM__W 168857#define SCU_RAM_QAM_FSM_FREQ_LIM__M 0xFFFF8858#define SCU_RAM_QAM_FSM_FREQ_LIM__PRE 0x08859 8860#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__B 08861#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__W 168862#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__M 0xFFFF8863#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT__PRE 0x08864#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_16 0x1E8865#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_32 0x148866#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_64 0x288867#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_128 0x88868#define SCU_RAM_QAM_FSM_FREQ_LIM_BIT_QAM_256 0x288869 8870#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F968871#define SCU_RAM_QAM_FSM_COUNT_LIM__W 168872#define SCU_RAM_QAM_FSM_COUNT_LIM__M 0xFFFF8873#define SCU_RAM_QAM_FSM_COUNT_LIM__PRE 0x08874 8875#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__B 08876#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__W 168877#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__M 0xFFFF8878#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT__PRE 0x08879#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_16 0x48880#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_32 0x68881#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_64 0x68882#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_128 0x78883#define SCU_RAM_QAM_FSM_COUNT_LIM_BIT_QAM_256 0x68884 8885#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F978886#define SCU_RAM_QAM_LC_CA_COARSE__W 168887#define SCU_RAM_QAM_LC_CA_COARSE__M 0xFFFF8888#define SCU_RAM_QAM_LC_CA_COARSE__PRE 0x08889 8890#define SCU_RAM_QAM_LC_CA_COARSE_BIT__B 08891#define SCU_RAM_QAM_LC_CA_COARSE_BIT__W 88892#define SCU_RAM_QAM_LC_CA_COARSE_BIT__M 0xFF8893#define SCU_RAM_QAM_LC_CA_COARSE_BIT__PRE 0x08894 8895#define SCU_RAM_QAM_LC_CA_MEDIUM__A 0x831F988896#define SCU_RAM_QAM_LC_CA_MEDIUM__W 168897#define SCU_RAM_QAM_LC_CA_MEDIUM__M 0xFFFF8898#define SCU_RAM_QAM_LC_CA_MEDIUM__PRE 0x08899 8900#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__B 08901#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__W 88902#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__M 0xFF8903#define SCU_RAM_QAM_LC_CA_MEDIUM_BIT__PRE 0x08904 8905#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F998906#define SCU_RAM_QAM_LC_CA_FINE__W 168907#define SCU_RAM_QAM_LC_CA_FINE__M 0xFFFF8908#define SCU_RAM_QAM_LC_CA_FINE__PRE 0x08909 8910#define SCU_RAM_QAM_LC_CA_FINE_BIT__B 08911#define SCU_RAM_QAM_LC_CA_FINE_BIT__W 88912#define SCU_RAM_QAM_LC_CA_FINE_BIT__M 0xFF8913#define SCU_RAM_QAM_LC_CA_FINE_BIT__PRE 0x08914 8915#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A8916#define SCU_RAM_QAM_LC_CP_COARSE__W 168917#define SCU_RAM_QAM_LC_CP_COARSE__M 0xFFFF8918#define SCU_RAM_QAM_LC_CP_COARSE__PRE 0x08919 8920#define SCU_RAM_QAM_LC_CP_COARSE_BIT__B 08921#define SCU_RAM_QAM_LC_CP_COARSE_BIT__W 88922#define SCU_RAM_QAM_LC_CP_COARSE_BIT__M 0xFF8923#define SCU_RAM_QAM_LC_CP_COARSE_BIT__PRE 0x08924 8925#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B8926#define SCU_RAM_QAM_LC_CP_MEDIUM__W 168927#define SCU_RAM_QAM_LC_CP_MEDIUM__M 0xFFFF8928#define SCU_RAM_QAM_LC_CP_MEDIUM__PRE 0x08929 8930#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__B 08931#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__W 88932#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__M 0xFF8933#define SCU_RAM_QAM_LC_CP_MEDIUM_BIT__PRE 0x08934 8935#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C8936#define SCU_RAM_QAM_LC_CP_FINE__W 168937#define SCU_RAM_QAM_LC_CP_FINE__M 0xFFFF8938#define SCU_RAM_QAM_LC_CP_FINE__PRE 0x08939 8940#define SCU_RAM_QAM_LC_CP_FINE_BIT__B 08941#define SCU_RAM_QAM_LC_CP_FINE_BIT__W 88942#define SCU_RAM_QAM_LC_CP_FINE_BIT__M 0xFF8943#define SCU_RAM_QAM_LC_CP_FINE_BIT__PRE 0x08944 8945#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D8946#define SCU_RAM_QAM_LC_CI_COARSE__W 168947#define SCU_RAM_QAM_LC_CI_COARSE__M 0xFFFF8948#define SCU_RAM_QAM_LC_CI_COARSE__PRE 0x08949 8950#define SCU_RAM_QAM_LC_CI_COARSE_BIT__B 08951#define SCU_RAM_QAM_LC_CI_COARSE_BIT__W 88952#define SCU_RAM_QAM_LC_CI_COARSE_BIT__M 0xFF8953#define SCU_RAM_QAM_LC_CI_COARSE_BIT__PRE 0x08954 8955#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E8956#define SCU_RAM_QAM_LC_CI_MEDIUM__W 168957#define SCU_RAM_QAM_LC_CI_MEDIUM__M 0xFFFF8958#define SCU_RAM_QAM_LC_CI_MEDIUM__PRE 0x08959 8960#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__B 08961#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__W 88962#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__M 0xFF8963#define SCU_RAM_QAM_LC_CI_MEDIUM_BIT__PRE 0x08964 8965#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F8966#define SCU_RAM_QAM_LC_CI_FINE__W 168967#define SCU_RAM_QAM_LC_CI_FINE__M 0xFFFF8968#define SCU_RAM_QAM_LC_CI_FINE__PRE 0x08969 8970#define SCU_RAM_QAM_LC_CI_FINE_BIT__B 08971#define SCU_RAM_QAM_LC_CI_FINE_BIT__W 88972#define SCU_RAM_QAM_LC_CI_FINE_BIT__M 0xFF8973#define SCU_RAM_QAM_LC_CI_FINE_BIT__PRE 0x08974 8975#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA08976#define SCU_RAM_QAM_LC_EP_COARSE__W 168977#define SCU_RAM_QAM_LC_EP_COARSE__M 0xFFFF8978#define SCU_RAM_QAM_LC_EP_COARSE__PRE 0x08979 8980#define SCU_RAM_QAM_LC_EP_COARSE_BIT__B 08981#define SCU_RAM_QAM_LC_EP_COARSE_BIT__W 88982#define SCU_RAM_QAM_LC_EP_COARSE_BIT__M 0xFF8983#define SCU_RAM_QAM_LC_EP_COARSE_BIT__PRE 0x08984 8985#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA18986#define SCU_RAM_QAM_LC_EP_MEDIUM__W 168987#define SCU_RAM_QAM_LC_EP_MEDIUM__M 0xFFFF8988#define SCU_RAM_QAM_LC_EP_MEDIUM__PRE 0x08989 8990#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__B 08991#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__W 88992#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__M 0xFF8993#define SCU_RAM_QAM_LC_EP_MEDIUM_BIT__PRE 0x08994 8995#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA28996#define SCU_RAM_QAM_LC_EP_FINE__W 168997#define SCU_RAM_QAM_LC_EP_FINE__M 0xFFFF8998#define SCU_RAM_QAM_LC_EP_FINE__PRE 0x08999 9000#define SCU_RAM_QAM_LC_EP_FINE_BIT__B 09001#define SCU_RAM_QAM_LC_EP_FINE_BIT__W 89002#define SCU_RAM_QAM_LC_EP_FINE_BIT__M 0xFF9003#define SCU_RAM_QAM_LC_EP_FINE_BIT__PRE 0x09004 9005#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA39006#define SCU_RAM_QAM_LC_EI_COARSE__W 169007#define SCU_RAM_QAM_LC_EI_COARSE__M 0xFFFF9008#define SCU_RAM_QAM_LC_EI_COARSE__PRE 0x09009 9010#define SCU_RAM_QAM_LC_EI_COARSE_BIT__B 09011#define SCU_RAM_QAM_LC_EI_COARSE_BIT__W 89012#define SCU_RAM_QAM_LC_EI_COARSE_BIT__M 0xFF9013#define SCU_RAM_QAM_LC_EI_COARSE_BIT__PRE 0x09014 9015#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA49016#define SCU_RAM_QAM_LC_EI_MEDIUM__W 169017#define SCU_RAM_QAM_LC_EI_MEDIUM__M 0xFFFF9018#define SCU_RAM_QAM_LC_EI_MEDIUM__PRE 0x09019 9020#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__B 09021#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__W 89022#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__M 0xFF9023#define SCU_RAM_QAM_LC_EI_MEDIUM_BIT__PRE 0x09024 9025#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA59026#define SCU_RAM_QAM_LC_EI_FINE__W 169027#define SCU_RAM_QAM_LC_EI_FINE__M 0xFFFF9028#define SCU_RAM_QAM_LC_EI_FINE__PRE 0x09029 9030#define SCU_RAM_QAM_LC_EI_FINE_BIT__B 09031#define SCU_RAM_QAM_LC_EI_FINE_BIT__W 89032#define SCU_RAM_QAM_LC_EI_FINE_BIT__M 0xFF9033#define SCU_RAM_QAM_LC_EI_FINE_BIT__PRE 0x09034 9035#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA69036#define SCU_RAM_QAM_LC_CF_COARSE__W 169037#define SCU_RAM_QAM_LC_CF_COARSE__M 0xFFFF9038#define SCU_RAM_QAM_LC_CF_COARSE__PRE 0x09039 9040#define SCU_RAM_QAM_LC_CF_COARSE_BIT__B 09041#define SCU_RAM_QAM_LC_CF_COARSE_BIT__W 89042#define SCU_RAM_QAM_LC_CF_COARSE_BIT__M 0xFF9043#define SCU_RAM_QAM_LC_CF_COARSE_BIT__PRE 0x09044 9045#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA79046#define SCU_RAM_QAM_LC_CF_MEDIUM__W 169047#define SCU_RAM_QAM_LC_CF_MEDIUM__M 0xFFFF9048#define SCU_RAM_QAM_LC_CF_MEDIUM__PRE 0x09049 9050#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__B 09051#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__W 89052#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__M 0xFF9053#define SCU_RAM_QAM_LC_CF_MEDIUM_BIT__PRE 0x09054 9055#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA89056#define SCU_RAM_QAM_LC_CF_FINE__W 169057#define SCU_RAM_QAM_LC_CF_FINE__M 0xFFFF9058#define SCU_RAM_QAM_LC_CF_FINE__PRE 0x09059 9060#define SCU_RAM_QAM_LC_CF_FINE_BIT__B 09061#define SCU_RAM_QAM_LC_CF_FINE_BIT__W 89062#define SCU_RAM_QAM_LC_CF_FINE_BIT__M 0xFF9063#define SCU_RAM_QAM_LC_CF_FINE_BIT__PRE 0x09064 9065#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA99066#define SCU_RAM_QAM_LC_CF1_COARSE__W 169067#define SCU_RAM_QAM_LC_CF1_COARSE__M 0xFFFF9068#define SCU_RAM_QAM_LC_CF1_COARSE__PRE 0x09069 9070#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__B 09071#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__W 89072#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__M 0xFF9073#define SCU_RAM_QAM_LC_CF1_COARSE_BIT__PRE 0x09074 9075#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA9076#define SCU_RAM_QAM_LC_CF1_MEDIUM__W 169077#define SCU_RAM_QAM_LC_CF1_MEDIUM__M 0xFFFF9078#define SCU_RAM_QAM_LC_CF1_MEDIUM__PRE 0x09079 9080#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__B 09081#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__W 89082#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__M 0xFF9083#define SCU_RAM_QAM_LC_CF1_MEDIUM_BIT__PRE 0x09084 9085#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB9086#define SCU_RAM_QAM_LC_CF1_FINE__W 169087#define SCU_RAM_QAM_LC_CF1_FINE__M 0xFFFF9088#define SCU_RAM_QAM_LC_CF1_FINE__PRE 0x09089 9090#define SCU_RAM_QAM_LC_CF1_FINE_BIT__B 09091#define SCU_RAM_QAM_LC_CF1_FINE_BIT__W 89092#define SCU_RAM_QAM_LC_CF1_FINE_BIT__M 0xFF9093#define SCU_RAM_QAM_LC_CF1_FINE_BIT__PRE 0x09094 9095#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC9096#define SCU_RAM_QAM_SL_SIG_POWER__W 169097#define SCU_RAM_QAM_SL_SIG_POWER__M 0xFFFF9098#define SCU_RAM_QAM_SL_SIG_POWER__PRE 0x09099 9100#define SCU_RAM_QAM_SL_SIG_POWER_BIT__B 09101#define SCU_RAM_QAM_SL_SIG_POWER_BIT__W 169102#define SCU_RAM_QAM_SL_SIG_POWER_BIT__M 0xFFFF9103#define SCU_RAM_QAM_SL_SIG_POWER_BIT__PRE 0x09104 9105#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD9106#define SCU_RAM_QAM_EQ_CMA_RAD0__W 149107#define SCU_RAM_QAM_EQ_CMA_RAD0__M 0x3FFF9108#define SCU_RAM_QAM_EQ_CMA_RAD0__PRE 0x09109 9110#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__B 09111#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__W 149112#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__M 0x3FFF9113#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT__PRE 0x09114#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_16 0x34CD9115#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_32 0x1A339116#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_64 0x34189117#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_128 0x18149118#define SCU_RAM_QAM_EQ_CMA_RAD0_BIT_QAM_256 0x2CEE9119 9120#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE9121#define SCU_RAM_QAM_EQ_CMA_RAD1__W 149122#define SCU_RAM_QAM_EQ_CMA_RAD1__M 0x3FFF9123#define SCU_RAM_QAM_EQ_CMA_RAD1__PRE 0x09124 9125#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__B 09126#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__W 149127#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__M 0x3FFF9128#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT__PRE 0x09129#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_16 0x34CD9130#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_32 0x1A339131#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_64 0x314A9132#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_128 0x19C69133#define SCU_RAM_QAM_EQ_CMA_RAD1_BIT_QAM_256 0x2F349134 9135#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF9136#define SCU_RAM_QAM_EQ_CMA_RAD2__W 149137#define SCU_RAM_QAM_EQ_CMA_RAD2__M 0x3FFF9138#define SCU_RAM_QAM_EQ_CMA_RAD2__PRE 0x09139 9140#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__B 09141#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__W 149142#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__M 0x3FFF9143#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT__PRE 0x09144#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_16 0x34CD9145#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_32 0x1A339146#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_64 0x2ED49147#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_128 0x18FA9148#define SCU_RAM_QAM_EQ_CMA_RAD2_BIT_QAM_256 0x30FF9149 9150#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB09151#define SCU_RAM_QAM_EQ_CMA_RAD3__W 149152#define SCU_RAM_QAM_EQ_CMA_RAD3__M 0x3FFF9153#define SCU_RAM_QAM_EQ_CMA_RAD3__PRE 0x09154 9155#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__B 09156#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__W 149157#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__M 0x3FFF9158#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT__PRE 0x09159#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_16 0x34CD9160#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_32 0x1A339161#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_64 0x35F19162#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_128 0x19099163#define SCU_RAM_QAM_EQ_CMA_RAD3_BIT_QAM_256 0x32839164 9165#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB19166#define SCU_RAM_QAM_EQ_CMA_RAD4__W 149167#define SCU_RAM_QAM_EQ_CMA_RAD4__M 0x3FFF9168#define SCU_RAM_QAM_EQ_CMA_RAD4__PRE 0x09169 9170#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__B 09171#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__W 149172#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__M 0x3FFF9173#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT__PRE 0x09174#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_16 0x34CD9175#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_32 0x1A339176#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_64 0x35F19177#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_128 0x1A009178#define SCU_RAM_QAM_EQ_CMA_RAD4_BIT_QAM_256 0x353D9179 9180#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB29181#define SCU_RAM_QAM_EQ_CMA_RAD5__W 149182#define SCU_RAM_QAM_EQ_CMA_RAD5__M 0x3FFF9183#define SCU_RAM_QAM_EQ_CMA_RAD5__PRE 0x09184 9185#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__B 09186#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__W 149187#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__M 0x3FFF9188#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT__PRE 0x09189#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_16 0x34CD9190#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_32 0x1A339191#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_64 0x3CF99192#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_128 0x1C469193#define SCU_RAM_QAM_EQ_CMA_RAD5_BIT_QAM_256 0x3C199194 9195#define SCU_RAM_QAM_CTL_ENA__A 0x831FB39196#define SCU_RAM_QAM_CTL_ENA__W 169197#define SCU_RAM_QAM_CTL_ENA__M 0xFFFF9198#define SCU_RAM_QAM_CTL_ENA__PRE 0x09199 9200#define SCU_RAM_QAM_CTL_ENA_AMP__B 09201#define SCU_RAM_QAM_CTL_ENA_AMP__W 19202#define SCU_RAM_QAM_CTL_ENA_AMP__M 0x19203#define SCU_RAM_QAM_CTL_ENA_AMP__PRE 0x09204 9205#define SCU_RAM_QAM_CTL_ENA_ACQ__B 19206#define SCU_RAM_QAM_CTL_ENA_ACQ__W 19207#define SCU_RAM_QAM_CTL_ENA_ACQ__M 0x29208#define SCU_RAM_QAM_CTL_ENA_ACQ__PRE 0x09209 9210#define SCU_RAM_QAM_CTL_ENA_EQU__B 29211#define SCU_RAM_QAM_CTL_ENA_EQU__W 19212#define SCU_RAM_QAM_CTL_ENA_EQU__M 0x49213#define SCU_RAM_QAM_CTL_ENA_EQU__PRE 0x09214 9215#define SCU_RAM_QAM_CTL_ENA_SLC__B 39216#define SCU_RAM_QAM_CTL_ENA_SLC__W 19217#define SCU_RAM_QAM_CTL_ENA_SLC__M 0x89218#define SCU_RAM_QAM_CTL_ENA_SLC__PRE 0x09219 9220#define SCU_RAM_QAM_CTL_ENA_LC__B 49221#define SCU_RAM_QAM_CTL_ENA_LC__W 19222#define SCU_RAM_QAM_CTL_ENA_LC__M 0x109223#define SCU_RAM_QAM_CTL_ENA_LC__PRE 0x09224 9225#define SCU_RAM_QAM_CTL_ENA_AGC__B 59226#define SCU_RAM_QAM_CTL_ENA_AGC__W 19227#define SCU_RAM_QAM_CTL_ENA_AGC__M 0x209228#define SCU_RAM_QAM_CTL_ENA_AGC__PRE 0x09229 9230#define SCU_RAM_QAM_CTL_ENA_FEC__B 69231#define SCU_RAM_QAM_CTL_ENA_FEC__W 19232#define SCU_RAM_QAM_CTL_ENA_FEC__M 0x409233#define SCU_RAM_QAM_CTL_ENA_FEC__PRE 0x09234 9235#define SCU_RAM_QAM_CTL_ENA_AXIS__B 79236#define SCU_RAM_QAM_CTL_ENA_AXIS__W 19237#define SCU_RAM_QAM_CTL_ENA_AXIS__M 0x809238#define SCU_RAM_QAM_CTL_ENA_AXIS__PRE 0x09239 9240#define SCU_RAM_QAM_CTL_ENA_FMHUM__B 89241#define SCU_RAM_QAM_CTL_ENA_FMHUM__W 19242#define SCU_RAM_QAM_CTL_ENA_FMHUM__M 0x1009243#define SCU_RAM_QAM_CTL_ENA_FMHUM__PRE 0x09244 9245#define SCU_RAM_QAM_CTL_ENA_EQTIME__B 99246#define SCU_RAM_QAM_CTL_ENA_EQTIME__W 19247#define SCU_RAM_QAM_CTL_ENA_EQTIME__M 0x2009248#define SCU_RAM_QAM_CTL_ENA_EQTIME__PRE 0x09249 9250#define SCU_RAM_QAM_CTL_ENA_EXTLCK__B 109251#define SCU_RAM_QAM_CTL_ENA_EXTLCK__W 19252#define SCU_RAM_QAM_CTL_ENA_EXTLCK__M 0x4009253#define SCU_RAM_QAM_CTL_ENA_EXTLCK__PRE 0x09254 9255#define SCU_RAM_QAM_WR_RSV_1__A 0x831FB49256#define SCU_RAM_QAM_WR_RSV_1__W 169257#define SCU_RAM_QAM_WR_RSV_1__M 0xFFFF9258#define SCU_RAM_QAM_WR_RSV_1__PRE 0x09259 9260#define SCU_RAM_QAM_WR_RSV_1_BIT__B 09261#define SCU_RAM_QAM_WR_RSV_1_BIT__W 169262#define SCU_RAM_QAM_WR_RSV_1_BIT__M 0xFFFF9263#define SCU_RAM_QAM_WR_RSV_1_BIT__PRE 0x09264 9265#define SCU_RAM_QAM_WR_RSV_2__A 0x831FB59266#define SCU_RAM_QAM_WR_RSV_2__W 169267#define SCU_RAM_QAM_WR_RSV_2__M 0xFFFF9268#define SCU_RAM_QAM_WR_RSV_2__PRE 0x09269 9270#define SCU_RAM_QAM_WR_RSV_2_BIT__B 09271#define SCU_RAM_QAM_WR_RSV_2_BIT__W 169272#define SCU_RAM_QAM_WR_RSV_2_BIT__M 0xFFFF9273#define SCU_RAM_QAM_WR_RSV_2_BIT__PRE 0x09274 9275#define SCU_RAM_QAM_WR_RSV_3__A 0x831FB69276#define SCU_RAM_QAM_WR_RSV_3__W 169277#define SCU_RAM_QAM_WR_RSV_3__M 0xFFFF9278#define SCU_RAM_QAM_WR_RSV_3__PRE 0x09279 9280#define SCU_RAM_QAM_WR_RSV_3_BIT__B 09281#define SCU_RAM_QAM_WR_RSV_3_BIT__W 169282#define SCU_RAM_QAM_WR_RSV_3_BIT__M 0xFFFF9283#define SCU_RAM_QAM_WR_RSV_3_BIT__PRE 0x09284 9285#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__A 0x831FB79286#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__W 39287#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__M 0x79288#define SCU_RAM_QAM_ACTIVE_CONSTELLATION__PRE 0x09289 9290#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__B 09291#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__W 39292#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__M 0x79293#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT__PRE 0x09294#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_UNKNOWN 0x09295#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_16 0x39296#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_32 0x49297#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_64 0x59298#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_128 0x69299#define SCU_RAM_QAM_ACTIVE_CONSTELLATION_BIT_QAM_256 0x79300 9301#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__A 0x831FB89302#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__W 89303#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__M 0xFF9304#define SCU_RAM_QAM_ACTIVE_INTERLEAVE__PRE 0x09305 9306#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__B 09307#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__W 89308#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__M 0xFF9309#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT__PRE 0x09310#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1 0x09311#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J1_V2 0x19312#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J2 0x29313#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I64_J2 0x39314#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J3 0x49315#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I32_J4 0x59316#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J4 0x69317#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I16_J8 0x79318#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J5 0x89319#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I8_J16 0x99320#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J6 0xA9321#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J7 0xC9322#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I128_J8 0xE9323#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I12_J17 0x109324#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_I5_J4 0x119325#define SCU_RAM_QAM_ACTIVE_INTERLEAVE_BIT_UNKNOWN 0xFE9326 9327#define SCU_RAM_QAM_RD_RSV_4__A 0x831FB99328#define SCU_RAM_QAM_RD_RSV_4__W 169329#define SCU_RAM_QAM_RD_RSV_4__M 0xFFFF9330#define SCU_RAM_QAM_RD_RSV_4__PRE 0x09331 9332#define SCU_RAM_QAM_RD_RSV_4_BIT__B 09333#define SCU_RAM_QAM_RD_RSV_4_BIT__W 169334#define SCU_RAM_QAM_RD_RSV_4_BIT__M 0xFFFF9335#define SCU_RAM_QAM_RD_RSV_4_BIT__PRE 0x09336 9337#define SCU_RAM_QAM_LOCKED__A 0x831FBA9338#define SCU_RAM_QAM_LOCKED__W 169339#define SCU_RAM_QAM_LOCKED__M 0xFFFF9340#define SCU_RAM_QAM_LOCKED__PRE 0x09341 9342#define SCU_RAM_QAM_LOCKED_INTLEVEL__B 09343#define SCU_RAM_QAM_LOCKED_INTLEVEL__W 89344#define SCU_RAM_QAM_LOCKED_INTLEVEL__M 0xFF9345#define SCU_RAM_QAM_LOCKED_INTLEVEL__PRE 0x09346#define SCU_RAM_QAM_LOCKED_INTLEVEL_NOT_LOCKED 0x09347#define SCU_RAM_QAM_LOCKED_INTLEVEL_AMP_OK 0x19348#define SCU_RAM_QAM_LOCKED_INTLEVEL_RATE_OK 0x29349#define SCU_RAM_QAM_LOCKED_INTLEVEL_FREQ_OK 0x39350#define SCU_RAM_QAM_LOCKED_INTLEVEL_UPRIGHT_OK 0x49351#define SCU_RAM_QAM_LOCKED_INTLEVEL_PHNOISE_OK 0x59352#define SCU_RAM_QAM_LOCKED_INTLEVEL_TRACK_OK 0x69353#define SCU_RAM_QAM_LOCKED_INTLEVEL_IMPNOISE_OK 0x79354 9355#define SCU_RAM_QAM_LOCKED_LOCKED__B 89356#define SCU_RAM_QAM_LOCKED_LOCKED__W 89357#define SCU_RAM_QAM_LOCKED_LOCKED__M 0xFF009358#define SCU_RAM_QAM_LOCKED_LOCKED__PRE 0x09359#define SCU_RAM_QAM_LOCKED_LOCKED_NOT_LOCKED 0x09360#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x40009361#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x80009362#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC0009363 9364#define SCU_RAM_QAM_EVENTS_OCC_HI__A 0x831FBB9365#define SCU_RAM_QAM_EVENTS_OCC_HI__W 169366#define SCU_RAM_QAM_EVENTS_OCC_HI__M 0xFFFF9367#define SCU_RAM_QAM_EVENTS_OCC_HI__PRE 0x09368 9369#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__B 09370#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__W 19371#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__M 0x19372#define SCU_RAM_QAM_EVENTS_OCC_HI_PREBER__PRE 0x09373 9374#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__B 19375#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__W 19376#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__M 0x29377#define SCU_RAM_QAM_EVENTS_OCC_HI_PACKET_FAIL__PRE 0x09378 9379#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__B 29380#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__W 19381#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__M 0x49382#define SCU_RAM_QAM_EVENTS_OCC_HI_PRBS__PRE 0x09383 9384#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__B 39385#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__W 19386#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__M 0x89387#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_IN__PRE 0x09388 9389#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__B 49390#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__W 19391#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__M 0x109392#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_LOCK_OUT__PRE 0x09393 9394#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__B 59395#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__W 19396#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__M 0x209397#define SCU_RAM_QAM_EVENTS_OCC_HI_POSTBER__PRE 0x09398 9399#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__B 69400#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__W 19401#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__M 0x409402#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_FULL__PRE 0x09403 9404#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__B 79405#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__W 19406#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__M 0x809407#define SCU_RAM_QAM_EVENTS_OCC_HI_FIFO_EMPTY__PRE 0x09408 9409#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__B 89410#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__W 19411#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__M 0x1009412#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_GRAB__PRE 0x09413 9414#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__B 99415#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__W 19416#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__M 0x2009417#define SCU_RAM_QAM_EVENTS_OCC_HI_OC_CHANGE__PRE 0x09418 9419#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__B 109420#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__W 19421#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__M 0x4009422#define SCU_RAM_QAM_EVENTS_OCC_HI_LCK_CHG__PRE 0x09423 9424#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__B 119425#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__W 19426#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__M 0x8009427#define SCU_RAM_QAM_EVENTS_OCC_HI_FSM_CHG__PRE 0x09428 9429#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__B 129430#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__W 49431#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__M 0xF0009432#define SCU_RAM_QAM_EVENTS_OCC_HI_RSV__PRE 0x09433 9434#define SCU_RAM_QAM_EVENTS_OCC_LO__A 0x831FBC9435#define SCU_RAM_QAM_EVENTS_OCC_LO__W 169436#define SCU_RAM_QAM_EVENTS_OCC_LO__M 0xFFFF9437#define SCU_RAM_QAM_EVENTS_OCC_LO__PRE 0x09438 9439#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__B 09440#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__W 19441#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__M 0x19442#define SCU_RAM_QAM_EVENTS_OCC_LO_TIMER__PRE 0x09443 9444#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__B 19445#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__W 19446#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__M 0x29447#define SCU_RAM_QAM_EVENTS_OCC_LO_CLIP__PRE 0x09448 9449#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__B 29450#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__W 19451#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__M 0x49452#define SCU_RAM_QAM_EVENTS_OCC_LO_SENSE__PRE 0x09453 9454#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__B 39455#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__W 19456#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__M 0x89457#define SCU_RAM_QAM_EVENTS_OCC_LO_POWER__PRE 0x09458 9459#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__B 49460#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__W 19461#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__M 0x109462#define SCU_RAM_QAM_EVENTS_OCC_LO_MEDIAN__PRE 0x09463 9464#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__B 59465#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__W 19466#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__M 0x209467#define SCU_RAM_QAM_EVENTS_OCC_LO_MER__PRE 0x09468 9469#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__B 69470#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__W 19471#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__M 0x409472#define SCU_RAM_QAM_EVENTS_OCC_LO_LOOP__PRE 0x09473 9474#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__B 79475#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__W 19476#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__M 0x809477#define SCU_RAM_QAM_EVENTS_OCC_LO_FREQWRAP__PRE 0x09478 9479#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__B 89480#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__W 19481#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__M 0x1009482#define SCU_RAM_QAM_EVENTS_OCC_LO_SER__PRE 0x09483 9484#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__B 99485#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__W 19486#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__M 0x2009487#define SCU_RAM_QAM_EVENTS_OCC_LO_VD_LOCK_IN__PRE 0x09488 9489#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__B 109490#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__W 19491#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__M 0x4009492#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_IN__PRE 0x09493 9494#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__B 119495#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__W 19496#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__M 0x8009497#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_LOCK_OUT__PRE 0x09498 9499#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__B 129500#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__W 19501#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__M 0x10009502#define SCU_RAM_QAM_EVENTS_OCC_LO_SY_TIME_OUT__PRE 0x09503 9504#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__B 139505#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__W 19506#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__M 0x20009507#define SCU_RAM_QAM_EVENTS_OCC_LO_SYNCWORD__PRE 0x09508 9509#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__B 149510#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__W 19511#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__M 0x40009512#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_IN__PRE 0x09513 9514#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__B 159515#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__W 19516#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__M 0x80009517#define SCU_RAM_QAM_EVENTS_OCC_LO_DI_LOCK_OUT__PRE 0x09518 9519#define SCU_RAM_QAM_EVENTS_SCHED_HI__A 0x831FBD9520#define SCU_RAM_QAM_EVENTS_SCHED_HI__W 169521#define SCU_RAM_QAM_EVENTS_SCHED_HI__M 0xFFFF9522#define SCU_RAM_QAM_EVENTS_SCHED_HI__PRE 0x09523 9524#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__B 09525#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__W 169526#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__M 0xFFFF9527#define SCU_RAM_QAM_EVENTS_SCHED_HI_BIT__PRE 0x09528 9529#define SCU_RAM_QAM_EVENTS_SCHED_LO__A 0x831FBE9530#define SCU_RAM_QAM_EVENTS_SCHED_LO__W 169531#define SCU_RAM_QAM_EVENTS_SCHED_LO__M 0xFFFF9532#define SCU_RAM_QAM_EVENTS_SCHED_LO__PRE 0x09533 9534#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__B 09535#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__W 169536#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__M 0xFFFF9537#define SCU_RAM_QAM_EVENTS_SCHED_LO_BIT__PRE 0x09538 9539#define SCU_RAM_QAM_TASKLETS_SCHED__A 0x831FBF9540#define SCU_RAM_QAM_TASKLETS_SCHED__W 169541#define SCU_RAM_QAM_TASKLETS_SCHED__M 0xFFFF9542#define SCU_RAM_QAM_TASKLETS_SCHED__PRE 0x09543 9544#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__B 09545#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__W 169546#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__M 0xFFFF9547#define SCU_RAM_QAM_TASKLETS_SCHED_BIT__PRE 0x09548 9549#define SCU_RAM_QAM_TASKLETS_RUN__A 0x831FC09550#define SCU_RAM_QAM_TASKLETS_RUN__W 169551#define SCU_RAM_QAM_TASKLETS_RUN__M 0xFFFF9552#define SCU_RAM_QAM_TASKLETS_RUN__PRE 0x09553 9554#define SCU_RAM_QAM_TASKLETS_RUN_BIT__B 09555#define SCU_RAM_QAM_TASKLETS_RUN_BIT__W 169556#define SCU_RAM_QAM_TASKLETS_RUN_BIT__M 0xFFFF9557#define SCU_RAM_QAM_TASKLETS_RUN_BIT__PRE 0x09558 9559#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__A 0x831FC19560#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__W 169561#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__M 0xFFFF9562#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI__PRE 0x09563 9564#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__B 09565#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__W 169566#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__M 0xFFFF9567#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_HI_BIT__PRE 0x09568 9569#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__A 0x831FC29570#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__W 169571#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__M 0xFFFF9572#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO__PRE 0x09573 9574#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__B 09575#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__W 169576#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__M 0xFFFF9577#define SCU_RAM_QAM_ACTIVE_SYM_RCRATE_LO_BIT__PRE 0x09578 9579#define SCU_RAM_QAM_RD_RSV_5__A 0x831FC39580#define SCU_RAM_QAM_RD_RSV_5__W 169581#define SCU_RAM_QAM_RD_RSV_5__M 0xFFFF9582#define SCU_RAM_QAM_RD_RSV_5__PRE 0x09583 9584#define SCU_RAM_QAM_RD_RSV_5_BIT__B 09585#define SCU_RAM_QAM_RD_RSV_5_BIT__W 169586#define SCU_RAM_QAM_RD_RSV_5_BIT__M 0xFFFF9587#define SCU_RAM_QAM_RD_RSV_5_BIT__PRE 0x09588 9589#define SCU_RAM_QAM_RD_RSV_6__A 0x831FC49590#define SCU_RAM_QAM_RD_RSV_6__W 169591#define SCU_RAM_QAM_RD_RSV_6__M 0xFFFF9592#define SCU_RAM_QAM_RD_RSV_6__PRE 0x09593 9594#define SCU_RAM_QAM_RD_RSV_6_BIT__B 09595#define SCU_RAM_QAM_RD_RSV_6_BIT__W 169596#define SCU_RAM_QAM_RD_RSV_6_BIT__M 0xFFFF9597#define SCU_RAM_QAM_RD_RSV_6_BIT__PRE 0x09598 9599#define SCU_RAM_QAM_RD_RSV_7__A 0x831FC59600#define SCU_RAM_QAM_RD_RSV_7__W 169601#define SCU_RAM_QAM_RD_RSV_7__M 0xFFFF9602#define SCU_RAM_QAM_RD_RSV_7__PRE 0x09603 9604#define SCU_RAM_QAM_RD_RSV_7_BIT__B 09605#define SCU_RAM_QAM_RD_RSV_7_BIT__W 169606#define SCU_RAM_QAM_RD_RSV_7_BIT__M 0xFFFF9607#define SCU_RAM_QAM_RD_RSV_7_BIT__PRE 0x09608 9609#define SCU_RAM_QAM_RD_RSV_8__A 0x831FC69610#define SCU_RAM_QAM_RD_RSV_8__W 169611#define SCU_RAM_QAM_RD_RSV_8__M 0xFFFF9612#define SCU_RAM_QAM_RD_RSV_8__PRE 0x09613 9614#define SCU_RAM_QAM_RD_RSV_8_BIT__B 09615#define SCU_RAM_QAM_RD_RSV_8_BIT__W 169616#define SCU_RAM_QAM_RD_RSV_8_BIT__M 0xFFFF9617#define SCU_RAM_QAM_RD_RSV_8_BIT__PRE 0x09618 9619#define SCU_RAM_QAM_RD_RSV_9__A 0x831FC79620#define SCU_RAM_QAM_RD_RSV_9__W 169621#define SCU_RAM_QAM_RD_RSV_9__M 0xFFFF9622#define SCU_RAM_QAM_RD_RSV_9__PRE 0x09623 9624#define SCU_RAM_QAM_RD_RSV_9_BIT__B 09625#define SCU_RAM_QAM_RD_RSV_9_BIT__W 169626#define SCU_RAM_QAM_RD_RSV_9_BIT__M 0xFFFF9627#define SCU_RAM_QAM_RD_RSV_9_BIT__PRE 0x09628 9629#define SCU_RAM_QAM_RD_RSV_10__A 0x831FC89630#define SCU_RAM_QAM_RD_RSV_10__W 169631#define SCU_RAM_QAM_RD_RSV_10__M 0xFFFF9632#define SCU_RAM_QAM_RD_RSV_10__PRE 0x09633 9634#define SCU_RAM_QAM_RD_RSV_10_BIT__B 09635#define SCU_RAM_QAM_RD_RSV_10_BIT__W 169636#define SCU_RAM_QAM_RD_RSV_10_BIT__M 0xFFFF9637#define SCU_RAM_QAM_RD_RSV_10_BIT__PRE 0x09638 9639#define SCU_RAM_QAM_AGC_TPOW_OFFS__A 0x831FC99640#define SCU_RAM_QAM_AGC_TPOW_OFFS__W 169641#define SCU_RAM_QAM_AGC_TPOW_OFFS__M 0xFFFF9642#define SCU_RAM_QAM_AGC_TPOW_OFFS__PRE 0x09643 9644#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__B 09645#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__W 169646#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__M 0xFFFF9647#define SCU_RAM_QAM_AGC_TPOW_OFFS_BIT__PRE 0x09648 9649#define SCU_RAM_QAM_FSM_STATE__A 0x831FCA9650#define SCU_RAM_QAM_FSM_STATE__W 49651#define SCU_RAM_QAM_FSM_STATE__M 0xF9652#define SCU_RAM_QAM_FSM_STATE__PRE 0x09653 9654#define SCU_RAM_QAM_FSM_STATE_BIT__B 09655#define SCU_RAM_QAM_FSM_STATE_BIT__W 49656#define SCU_RAM_QAM_FSM_STATE_BIT__M 0xF9657#define SCU_RAM_QAM_FSM_STATE_BIT__PRE 0x09658#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_AMP 0x09659#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_RATE 0x19660#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_FREQ 0x29661#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_UPRIGHT 0x39662#define SCU_RAM_QAM_FSM_STATE_BIT_HUNTING_PHASE 0x49663#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_PHNOISE 0x59664#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING 0x69665#define SCU_RAM_QAM_FSM_STATE_BIT_TRACKING_BURST 0x79666 9667#define SCU_RAM_QAM_FSM_STATE_NEW__A 0x831FCB9668#define SCU_RAM_QAM_FSM_STATE_NEW__W 49669#define SCU_RAM_QAM_FSM_STATE_NEW__M 0xF9670#define SCU_RAM_QAM_FSM_STATE_NEW__PRE 0x09671 9672#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__B 09673#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__W 49674#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__M 0xF9675#define SCU_RAM_QAM_FSM_STATE_NEW_BIT__PRE 0x09676#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_AMP 0x09677#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_RATE 0x19678#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_FREQ 0x29679#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_UPRIGHT 0x39680#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_HUNTING_PHASE 0x49681#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_PHNOISE 0x59682#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING 0x69683#define SCU_RAM_QAM_FSM_STATE_NEW_BIT_TRACKING_BURST 0x79684 9685#define SCU_RAM_QAM_FSM_LOCK_FLAGS__A 0x831FCC9686#define SCU_RAM_QAM_FSM_LOCK_FLAGS__W 99687#define SCU_RAM_QAM_FSM_LOCK_FLAGS__M 0x1FF9688#define SCU_RAM_QAM_FSM_LOCK_FLAGS__PRE 0x09689 9690#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__B 09691#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__W 19692#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__M 0x19693#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_AMP__PRE 0x09694 9695#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__B 19696#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__W 19697#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__M 0x29698#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RATEVAR__PRE 0x09699 9700#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__B 29701#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__W 19702#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__M 0x49703#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_RADIUS__PRE 0x09704 9705#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__B 39706#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__W 19707#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__M 0x89708#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQ__PRE 0x09709 9710#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__B 49711#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__W 19712#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__M 0x109713#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_FREQVAR__PRE 0x09714 9715#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__B 59716#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__W 19717#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__M 0x209718#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_CPHASE__PRE 0x09719 9720#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__B 69721#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__W 19722#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__M 0x409723#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_UPRIGHT__PRE 0x09724 9725#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__B 79726#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__W 19727#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__M 0x809728#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_PHASE__PRE 0x09729 9730#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__B 89731#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__W 19732#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__M 0x1009733#define SCU_RAM_QAM_FSM_LOCK_FLAGS_LCK_MEDIAN__PRE 0x09734 9735#define SCU_RAM_QAM_FSM_RATE_VARIATION__A 0x831FCD9736#define SCU_RAM_QAM_FSM_RATE_VARIATION__W 169737#define SCU_RAM_QAM_FSM_RATE_VARIATION__M 0xFFFF9738#define SCU_RAM_QAM_FSM_RATE_VARIATION__PRE 0x09739 9740#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__B 09741#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__W 169742#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__M 0xFFFF9743#define SCU_RAM_QAM_FSM_RATE_VARIATION_BIT__PRE 0x09744 9745#define SCU_RAM_QAM_FSM_FREQ_VARIATION__A 0x831FCE9746#define SCU_RAM_QAM_FSM_FREQ_VARIATION__W 169747#define SCU_RAM_QAM_FSM_FREQ_VARIATION__M 0xFFFF9748#define SCU_RAM_QAM_FSM_FREQ_VARIATION__PRE 0x09749 9750#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__B 09751#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__W 169752#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__M 0xFFFF9753#define SCU_RAM_QAM_FSM_FREQ_VARIATION_BIT__PRE 0x09754 9755#define SCU_RAM_QAM_ERR_STATE__A 0x831FCF9756#define SCU_RAM_QAM_ERR_STATE__W 49757#define SCU_RAM_QAM_ERR_STATE__M 0xF9758#define SCU_RAM_QAM_ERR_STATE__PRE 0x09759 9760#define SCU_RAM_QAM_ERR_STATE_BIT__B 09761#define SCU_RAM_QAM_ERR_STATE_BIT__W 49762#define SCU_RAM_QAM_ERR_STATE_BIT__M 0xF9763#define SCU_RAM_QAM_ERR_STATE_BIT__PRE 0x09764#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_AMP 0x09765#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_RATE 0x19766#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_FREQ 0x29767#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_UPRIGHT 0x39768#define SCU_RAM_QAM_ERR_STATE_BIT_HUNTING_PHASE 0x49769#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_PHNOISE 0x59770#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING 0x69771#define SCU_RAM_QAM_ERR_STATE_BIT_TRACKING_BURST 0x79772 9773#define SCU_RAM_QAM_ERR_LOCK_FLAGS__A 0x831FD09774#define SCU_RAM_QAM_ERR_LOCK_FLAGS__W 99775#define SCU_RAM_QAM_ERR_LOCK_FLAGS__M 0x1FF9776#define SCU_RAM_QAM_ERR_LOCK_FLAGS__PRE 0x09777 9778#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__B 09779#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__W 19780#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__M 0x19781#define SCU_RAM_QAM_ERR_LOCK_FLAGS_LCK_AMP__PRE 0x09782 9783#define SCU_RAM_QAM_EQ_LOCK__A 0x831FD19784#define SCU_RAM_QAM_EQ_LOCK__W 19785#define SCU_RAM_QAM_EQ_LOCK__M 0x19786#define SCU_RAM_QAM_EQ_LOCK__PRE 0x09787 9788#define SCU_RAM_QAM_EQ_LOCK_BIT__B 09789#define SCU_RAM_QAM_EQ_LOCK_BIT__W 19790#define SCU_RAM_QAM_EQ_LOCK_BIT__M 0x19791#define SCU_RAM_QAM_EQ_LOCK_BIT__PRE 0x09792 9793#define SCU_RAM_QAM_EQ_STATE__A 0x831FD29794#define SCU_RAM_QAM_EQ_STATE__W 169795#define SCU_RAM_QAM_EQ_STATE__M 0xFFFF9796#define SCU_RAM_QAM_EQ_STATE__PRE 0x09797 9798#define SCU_RAM_QAM_EQ_STATE_BIT__B 09799#define SCU_RAM_QAM_EQ_STATE_BIT__W 169800#define SCU_RAM_QAM_EQ_STATE_BIT__M 0xFFFF9801#define SCU_RAM_QAM_EQ_STATE_BIT__PRE 0x09802 9803#define SCU_RAM_QAM_RD_RSV_0__A 0x831FD39804#define SCU_RAM_QAM_RD_RSV_0__W 169805#define SCU_RAM_QAM_RD_RSV_0__M 0xFFFF9806#define SCU_RAM_QAM_RD_RSV_0__PRE 0x09807 9808#define SCU_RAM_QAM_RD_RSV_0_BIT__B 09809#define SCU_RAM_QAM_RD_RSV_0_BIT__W 169810#define SCU_RAM_QAM_RD_RSV_0_BIT__M 0xFFFF9811#define SCU_RAM_QAM_RD_RSV_0_BIT__PRE 0x09812 9813#define SCU_RAM_QAM_RD_RSV_1__A 0x831FD49814#define SCU_RAM_QAM_RD_RSV_1__W 169815#define SCU_RAM_QAM_RD_RSV_1__M 0xFFFF9816#define SCU_RAM_QAM_RD_RSV_1__PRE 0x09817 9818#define SCU_RAM_QAM_RD_RSV_1_BIT__B 09819#define SCU_RAM_QAM_RD_RSV_1_BIT__W 169820#define SCU_RAM_QAM_RD_RSV_1_BIT__M 0xFFFF9821#define SCU_RAM_QAM_RD_RSV_1_BIT__PRE 0x09822 9823#define SCU_RAM_QAM_RD_RSV_2__A 0x831FD59824#define SCU_RAM_QAM_RD_RSV_2__W 169825#define SCU_RAM_QAM_RD_RSV_2__M 0xFFFF9826#define SCU_RAM_QAM_RD_RSV_2__PRE 0x09827 9828#define SCU_RAM_QAM_RD_RSV_2_BIT__B 09829#define SCU_RAM_QAM_RD_RSV_2_BIT__W 169830#define SCU_RAM_QAM_RD_RSV_2_BIT__M 0xFFFF9831#define SCU_RAM_QAM_RD_RSV_2_BIT__PRE 0x09832 9833#define SCU_RAM_QAM_RD_RSV_3__A 0x831FD69834#define SCU_RAM_QAM_RD_RSV_3__W 169835#define SCU_RAM_QAM_RD_RSV_3__M 0xFFFF9836#define SCU_RAM_QAM_RD_RSV_3__PRE 0x09837 9838#define SCU_RAM_QAM_RD_RSV_3_BIT__B 09839#define SCU_RAM_QAM_RD_RSV_3_BIT__W 169840#define SCU_RAM_QAM_RD_RSV_3_BIT__M 0xFFFF9841#define SCU_RAM_QAM_RD_RSV_3_BIT__PRE 0x09842 9843#define SCU_RAM_VSB_CTL_MODE__A 0x831FD79844#define SCU_RAM_VSB_CTL_MODE__W 29845#define SCU_RAM_VSB_CTL_MODE__M 0x39846#define SCU_RAM_VSB_CTL_MODE__PRE 0x09847 9848#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__B 09849#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__W 19850#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__M 0x19851#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC__PRE 0x09852#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_OFF 0x09853#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_AGC_ON 0x19854 9855#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__B 19856#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__W 19857#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__M 0x29858#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON__PRE 0x09859#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_OFF 0x09860#define SCU_RAM_VSB_CTL_MODE_VSB_CTL_MODE_MON_ON 0x29861 9862#define SCU_RAM_VSB_NOTCH_THRESHOLD__A 0x831FD89863#define SCU_RAM_VSB_NOTCH_THRESHOLD__W 169864#define SCU_RAM_VSB_NOTCH_THRESHOLD__M 0xFFFF9865#define SCU_RAM_VSB_NOTCH_THRESHOLD__PRE 0x09866 9867#define SCU_RAM_VSB_RSV_0__A 0x831FD99868#define SCU_RAM_VSB_RSV_0__W 169869#define SCU_RAM_VSB_RSV_0__M 0xFFFF9870#define SCU_RAM_VSB_RSV_0__PRE 0x09871 9872#define SCU_RAM_VSB_RSV_1__A 0x831FDA9873#define SCU_RAM_VSB_RSV_1__W 169874#define SCU_RAM_VSB_RSV_1__M 0xFFFF9875#define SCU_RAM_VSB_RSV_1__PRE 0x09876 9877#define SCU_RAM_VSB_RSV_2__A 0x831FDB9878#define SCU_RAM_VSB_RSV_2__W 169879#define SCU_RAM_VSB_RSV_2__M 0xFFFF9880#define SCU_RAM_VSB_RSV_2__PRE 0x09881 9882#define SCU_RAM_VSB_RSV_3__A 0x831FDC9883#define SCU_RAM_VSB_RSV_3__W 169884#define SCU_RAM_VSB_RSV_3__M 0xFFFF9885#define SCU_RAM_VSB_RSV_3__PRE 0x09886 9887#define SCU_RAM_VSB_RSV_4__A 0x831FDD9888#define SCU_RAM_VSB_RSV_4__W 169889#define SCU_RAM_VSB_RSV_4__M 0xFFFF9890#define SCU_RAM_VSB_RSV_4__PRE 0x09891 9892#define SCU_RAM_VSB_RSV_5__A 0x831FDE9893#define SCU_RAM_VSB_RSV_5__W 169894#define SCU_RAM_VSB_RSV_5__M 0xFFFF9895#define SCU_RAM_VSB_RSV_5__PRE 0x09896 9897#define SCU_RAM_VSB_RSV_6__A 0x831FDF9898#define SCU_RAM_VSB_RSV_6__W 169899#define SCU_RAM_VSB_RSV_6__M 0xFFFF9900#define SCU_RAM_VSB_RSV_6__PRE 0x09901 9902#define SCU_RAM_VSB_RSV_7__A 0x831FE09903#define SCU_RAM_VSB_RSV_7__W 169904#define SCU_RAM_VSB_RSV_7__M 0xFFFF9905#define SCU_RAM_VSB_RSV_7__PRE 0x09906 9907#define SCU_RAM_VSB_RSV_8__A 0x831FE19908#define SCU_RAM_VSB_RSV_8__W 169909#define SCU_RAM_VSB_RSV_8__M 0xFFFF9910#define SCU_RAM_VSB_RSV_8__PRE 0x09911 9912#define SCU_RAM_VSB_RSV_9__A 0x831FE29913#define SCU_RAM_VSB_RSV_9__W 169914#define SCU_RAM_VSB_RSV_9__M 0xFFFF9915#define SCU_RAM_VSB_RSV_9__PRE 0x09916 9917#define SCU_RAM_VSB_RSV_10__A 0x831FE39918#define SCU_RAM_VSB_RSV_10__W 169919#define SCU_RAM_VSB_RSV_10__M 0xFFFF9920#define SCU_RAM_VSB_RSV_10__PRE 0x09921 9922#define SCU_RAM_VSB_RSV_11__A 0x831FE49923#define SCU_RAM_VSB_RSV_11__W 169924#define SCU_RAM_VSB_RSV_11__M 0xFFFF9925#define SCU_RAM_VSB_RSV_11__PRE 0x09926 9927#define SCU_RAM_VSB_RSV_12__A 0x831FE59928#define SCU_RAM_VSB_RSV_12__W 169929#define SCU_RAM_VSB_RSV_12__M 0xFFFF9930#define SCU_RAM_VSB_RSV_12__PRE 0x09931 9932#define SCU_RAM_VSB_RSV_13__A 0x831FE69933#define SCU_RAM_VSB_RSV_13__W 169934#define SCU_RAM_VSB_RSV_13__M 0xFFFF9935#define SCU_RAM_VSB_RSV_13__PRE 0x09936 9937#define SCU_RAM_VSB_AGC_POW_TGT__A 0x831FE79938#define SCU_RAM_VSB_AGC_POW_TGT__W 159939#define SCU_RAM_VSB_AGC_POW_TGT__M 0x7FFF9940#define SCU_RAM_VSB_AGC_POW_TGT__PRE 0x09941 9942#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__A 0x831FE89943#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__W 89944#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__M 0xFF9945#define SCU_RAM_VSB_OUTER_LOOP_CYCLE__PRE 0x09946 9947#define SCU_RAM_VSB_FIELD_NUMBER__A 0x831FE99948#define SCU_RAM_VSB_FIELD_NUMBER__W 99949#define SCU_RAM_VSB_FIELD_NUMBER__M 0x1FF9950#define SCU_RAM_VSB_FIELD_NUMBER__PRE 0x09951 9952#define SCU_RAM_VSB_SEGMENT_NUMBER__A 0x831FEA9953#define SCU_RAM_VSB_SEGMENT_NUMBER__W 109954#define SCU_RAM_VSB_SEGMENT_NUMBER__M 0x3FF9955#define SCU_RAM_VSB_SEGMENT_NUMBER__PRE 0x09956 9957#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB9958#define SCU_RAM_DRIVER_VER_HI__W 169959#define SCU_RAM_DRIVER_VER_HI__M 0xFFFF9960#define SCU_RAM_DRIVER_VER_HI__PRE 0x09961 9962#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC9963#define SCU_RAM_DRIVER_VER_LO__W 169964#define SCU_RAM_DRIVER_VER_LO__M 0xFFFF9965#define SCU_RAM_DRIVER_VER_LO__PRE 0x09966 9967#define SCU_RAM_PARAM_15__A 0x831FED9968#define SCU_RAM_PARAM_15__W 169969#define SCU_RAM_PARAM_15__M 0xFFFF9970#define SCU_RAM_PARAM_15__PRE 0x09971 9972#define SCU_RAM_PARAM_14__A 0x831FEE9973#define SCU_RAM_PARAM_14__W 169974#define SCU_RAM_PARAM_14__M 0xFFFF9975#define SCU_RAM_PARAM_14__PRE 0x09976 9977#define SCU_RAM_PARAM_13__A 0x831FEF9978#define SCU_RAM_PARAM_13__W 169979#define SCU_RAM_PARAM_13__M 0xFFFF9980#define SCU_RAM_PARAM_13__PRE 0x09981 9982#define SCU_RAM_PARAM_12__A 0x831FF09983#define SCU_RAM_PARAM_12__W 169984#define SCU_RAM_PARAM_12__M 0xFFFF9985#define SCU_RAM_PARAM_12__PRE 0x09986 9987#define SCU_RAM_PARAM_11__A 0x831FF19988#define SCU_RAM_PARAM_11__W 169989#define SCU_RAM_PARAM_11__M 0xFFFF9990#define SCU_RAM_PARAM_11__PRE 0x09991 9992#define SCU_RAM_PARAM_10__A 0x831FF29993#define SCU_RAM_PARAM_10__W 169994#define SCU_RAM_PARAM_10__M 0xFFFF9995#define SCU_RAM_PARAM_10__PRE 0x09996 9997#define SCU_RAM_PARAM_9__A 0x831FF39998#define SCU_RAM_PARAM_9__W 169999#define SCU_RAM_PARAM_9__M 0xFFFF10000#define SCU_RAM_PARAM_9__PRE 0x010001 10002#define SCU_RAM_PARAM_8__A 0x831FF410003#define SCU_RAM_PARAM_8__W 1610004#define SCU_RAM_PARAM_8__M 0xFFFF10005#define SCU_RAM_PARAM_8__PRE 0x010006 10007#define SCU_RAM_PARAM_7__A 0x831FF510008#define SCU_RAM_PARAM_7__W 1610009#define SCU_RAM_PARAM_7__M 0xFFFF10010#define SCU_RAM_PARAM_7__PRE 0x010011 10012#define SCU_RAM_PARAM_6__A 0x831FF610013#define SCU_RAM_PARAM_6__W 1610014#define SCU_RAM_PARAM_6__M 0xFFFF10015#define SCU_RAM_PARAM_6__PRE 0x010016 10017#define SCU_RAM_PARAM_5__A 0x831FF710018#define SCU_RAM_PARAM_5__W 1610019#define SCU_RAM_PARAM_5__M 0xFFFF10020#define SCU_RAM_PARAM_5__PRE 0x010021 10022#define SCU_RAM_PARAM_4__A 0x831FF810023#define SCU_RAM_PARAM_4__W 1610024#define SCU_RAM_PARAM_4__M 0xFFFF10025#define SCU_RAM_PARAM_4__PRE 0x010026 10027#define SCU_RAM_PARAM_3__A 0x831FF910028#define SCU_RAM_PARAM_3__W 1610029#define SCU_RAM_PARAM_3__M 0xFFFF10030#define SCU_RAM_PARAM_3__PRE 0x010031 10032#define SCU_RAM_PARAM_2__A 0x831FFA10033#define SCU_RAM_PARAM_2__W 1610034#define SCU_RAM_PARAM_2__M 0xFFFF10035#define SCU_RAM_PARAM_2__PRE 0x010036 10037#define SCU_RAM_PARAM_1__A 0x831FFB10038#define SCU_RAM_PARAM_1__W 1610039#define SCU_RAM_PARAM_1__M 0xFFFF10040#define SCU_RAM_PARAM_1__PRE 0x010041#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NOT_LOCKED 0x010042#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_DEMOD_LOCKED 0x400010043#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_LOCKED 0x800010044#define SCU_RAM_PARAM_1_RES_DEMOD_GET_LOCK_NEVER_LOCK 0xC00010045 10046#define SCU_RAM_PARAM_0__A 0x831FFC10047#define SCU_RAM_PARAM_0__W 1610048#define SCU_RAM_PARAM_0__M 0xFFFF10049#define SCU_RAM_PARAM_0__PRE 0x010050#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_MN_STANDARD 0x210051#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_B_STANDARD 0x10310052#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_G_STANDARD 0x310053#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_DK_STANDARD 0x410054#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_L_STANDARD 0x910055#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_LP_STANDARD 0x10910056#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_I_STANDARD 0xA10057#define SCU_RAM_PARAM_0_ATV_DEMOD_SETENV_FM_STANDARD 0x4010058#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_A 0x010059#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_B 0x110060#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_C 0x210061#define SCU_RAM_PARAM_0_QAM_DEMOD_SETENV_ANNEX_D 0x310062#define SCU_RAM_PARAM_0_RESULT_OK 0x010063#define SCU_RAM_PARAM_0_RESULT_UNKCMD 0xFFFF10064#define SCU_RAM_PARAM_0_RESULT_UNKSTD 0xFFFE10065#define SCU_RAM_PARAM_0_RESULT_INVPAR 0xFFFD10066#define SCU_RAM_PARAM_0_RESULT_SIZE 0xFFFC10067 10068#define SCU_RAM_COMMAND__A 0x831FFD10069#define SCU_RAM_COMMAND__W 1610070#define SCU_RAM_COMMAND__M 0xFFFF10071#define SCU_RAM_COMMAND__PRE 0x010072#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x110073#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x210074#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x310075#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x410076#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x510077#define SCU_RAM_COMMAND_CMD_DEMOD_GET_PARAM 0x610078#define SCU_RAM_COMMAND_CMD_DEMOD_HOLD 0x710079#define SCU_RAM_COMMAND_CMD_DEMOD_RESUME 0x810080#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x910081#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_ACTIVATE 0x8010082#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_INACTIVATE 0x8110083#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_SIGNAL 0x8210084#define SCU_RAM_COMMAND_CMD_STD_QAM_IRQ_MONITOR 0x8310085#define SCU_RAM_COMMAND_CMD_STD_QAM_TSK_ENABLE 0x8410086#define SCU_RAM_COMMAND_CMD_STD_QAM_FSM_SET_STATE 0x8510087#define SCU_RAM_COMMAND_CMD_DEBUG_GET_IRQ_REGS 0x8010088#define SCU_RAM_COMMAND_CMD_DEBUG_HTOL 0x8110089#define SCU_RAM_COMMAND_CMD_DEBUG_GET_STACK_POINTER 0x8210090#define SCU_RAM_COMMAND_CMD_DEBUG_START_STACK_CHECK 0x8310091#define SCU_RAM_COMMAND_CMD_DEBUG_STOP_STACK_CHECK 0x8410092#define SCU_RAM_COMMAND_CMD_ADMIN_NOP 0xFF10093#define SCU_RAM_COMMAND_CMD_ADMIN_GET_VERSION 0xFE10094#define SCU_RAM_COMMAND_CMD_ADMIN_GET_JTAG_VERSION 0xFD10095#define SCU_RAM_COMMAND_CMD_AUX_SCU_ATOMIC_ACCESS 0xC010096 10097#define SCU_RAM_COMMAND_STANDARD__B 810098#define SCU_RAM_COMMAND_STANDARD__W 810099#define SCU_RAM_COMMAND_STANDARD__M 0xFF0010100#define SCU_RAM_COMMAND_STANDARD__PRE 0x010101#define SCU_RAM_COMMAND_STANDARD_ATV 0x10010102#define SCU_RAM_COMMAND_STANDARD_QAM 0x20010103#define SCU_RAM_COMMAND_STANDARD_VSB 0x30010104#define SCU_RAM_COMMAND_STANDARD_OFDM 0x40010105#define SCU_RAM_COMMAND_STANDARD_OOB 0x800010106#define SCU_RAM_COMMAND_STANDARD_TOP 0xFF0010107 10108#define SCU_RAM_VERSION_HI__A 0x831FFE10109#define SCU_RAM_VERSION_HI__W 1610110#define SCU_RAM_VERSION_HI__M 0xFFFF10111#define SCU_RAM_VERSION_HI__PRE 0x010112 10113#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__B 1210114#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__W 410115#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__M 0xF00010116#define SCU_RAM_VERSION_HI_VER_MAJOR_N3__PRE 0x010117 10118#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__B 810119#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__W 410120#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__M 0xF0010121#define SCU_RAM_VERSION_HI_VER_MAJOR_N2__PRE 0x010122 10123#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__B 410124#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__W 410125#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__M 0xF010126#define SCU_RAM_VERSION_HI_VER_MAJOR_N1__PRE 0x010127 10128#define SCU_RAM_VERSION_HI_VER_MINOR_N1__B 010129#define SCU_RAM_VERSION_HI_VER_MINOR_N1__W 410130#define SCU_RAM_VERSION_HI_VER_MINOR_N1__M 0xF10131#define SCU_RAM_VERSION_HI_VER_MINOR_N1__PRE 0x010132 10133#define SCU_RAM_VERSION_LO__A 0x831FFF10134#define SCU_RAM_VERSION_LO__W 1610135#define SCU_RAM_VERSION_LO__M 0xFFFF10136#define SCU_RAM_VERSION_LO__PRE 0x010137 10138#define SCU_RAM_VERSION_LO_VER_PATCH_N4__B 1210139#define SCU_RAM_VERSION_LO_VER_PATCH_N4__W 410140#define SCU_RAM_VERSION_LO_VER_PATCH_N4__M 0xF00010141#define SCU_RAM_VERSION_LO_VER_PATCH_N4__PRE 0x010142 10143#define SCU_RAM_VERSION_LO_VER_PATCH_N3__B 810144#define SCU_RAM_VERSION_LO_VER_PATCH_N3__W 410145#define SCU_RAM_VERSION_LO_VER_PATCH_N3__M 0xF0010146#define SCU_RAM_VERSION_LO_VER_PATCH_N3__PRE 0x010147 10148#define SCU_RAM_VERSION_LO_VER_PATCH_N2__B 410149#define SCU_RAM_VERSION_LO_VER_PATCH_N2__W 410150#define SCU_RAM_VERSION_LO_VER_PATCH_N2__M 0xF010151#define SCU_RAM_VERSION_LO_VER_PATCH_N2__PRE 0x010152 10153#define SCU_RAM_VERSION_LO_VER_PATCH_N1__B 010154#define SCU_RAM_VERSION_LO_VER_PATCH_N1__W 410155#define SCU_RAM_VERSION_LO_VER_PATCH_N1__M 0xF10156#define SCU_RAM_VERSION_LO_VER_PATCH_N1__PRE 0x010157 10158#define SIO_COMM_EXEC__A 0x40000010159#define SIO_COMM_EXEC__W 210160#define SIO_COMM_EXEC__M 0x310161#define SIO_COMM_EXEC__PRE 0x010162#define SIO_COMM_EXEC_STOP 0x010163#define SIO_COMM_EXEC_ACTIVE 0x110164#define SIO_COMM_EXEC_HOLD 0x210165 10166#define SIO_COMM_STATE__A 0x40000110167#define SIO_COMM_STATE__W 1610168#define SIO_COMM_STATE__M 0xFFFF10169#define SIO_COMM_STATE__PRE 0x010170#define SIO_COMM_MB__A 0x40000210171#define SIO_COMM_MB__W 1610172#define SIO_COMM_MB__M 0xFFFF10173#define SIO_COMM_MB__PRE 0x010174#define SIO_COMM_INT_REQ__A 0x40000310175#define SIO_COMM_INT_REQ__W 1610176#define SIO_COMM_INT_REQ__M 0xFFFF10177#define SIO_COMM_INT_REQ__PRE 0x010178 10179#define SIO_COMM_INT_REQ_HI_REQ__B 010180#define SIO_COMM_INT_REQ_HI_REQ__W 110181#define SIO_COMM_INT_REQ_HI_REQ__M 0x110182#define SIO_COMM_INT_REQ_HI_REQ__PRE 0x010183 10184#define SIO_COMM_INT_REQ_SA_REQ__B 110185#define SIO_COMM_INT_REQ_SA_REQ__W 110186#define SIO_COMM_INT_REQ_SA_REQ__M 0x210187#define SIO_COMM_INT_REQ_SA_REQ__PRE 0x010188 10189#define SIO_COMM_INT_STA__A 0x40000510190#define SIO_COMM_INT_STA__W 1610191#define SIO_COMM_INT_STA__M 0xFFFF10192#define SIO_COMM_INT_STA__PRE 0x010193#define SIO_COMM_INT_MSK__A 0x40000610194#define SIO_COMM_INT_MSK__W 1610195#define SIO_COMM_INT_MSK__M 0xFFFF10196#define SIO_COMM_INT_MSK__PRE 0x010197#define SIO_COMM_INT_STM__A 0x40000710198#define SIO_COMM_INT_STM__W 1610199#define SIO_COMM_INT_STM__M 0xFFFF10200#define SIO_COMM_INT_STM__PRE 0x010201 10202#define SIO_TOP_COMM_EXEC__A 0x41000010203#define SIO_TOP_COMM_EXEC__W 210204#define SIO_TOP_COMM_EXEC__M 0x310205#define SIO_TOP_COMM_EXEC__PRE 0x010206#define SIO_TOP_COMM_EXEC_STOP 0x010207#define SIO_TOP_COMM_EXEC_ACTIVE 0x110208#define SIO_TOP_COMM_EXEC_HOLD 0x210209 10210#define SIO_TOP_COMM_KEY__A 0x41000F10211#define SIO_TOP_COMM_KEY__W 1610212#define SIO_TOP_COMM_KEY__M 0xFFFF10213#define SIO_TOP_COMM_KEY__PRE 0x010214#define SIO_TOP_COMM_KEY_KEY 0xFABA10215 10216#define SIO_TOP_JTAGID_LO__A 0x41001210217#define SIO_TOP_JTAGID_LO__W 1610218#define SIO_TOP_JTAGID_LO__M 0xFFFF10219#define SIO_TOP_JTAGID_LO__PRE 0x010220 10221#define SIO_TOP_JTAGID_HI__A 0x41001310222#define SIO_TOP_JTAGID_HI__W 1610223#define SIO_TOP_JTAGID_HI__M 0xFFFF10224#define SIO_TOP_JTAGID_HI__PRE 0x010225 10226#define SIO_HI_RA_RAM_S0_FLG_SMM__A 0x42001010227#define SIO_HI_RA_RAM_S0_FLG_SMM__W 110228#define SIO_HI_RA_RAM_S0_FLG_SMM__M 0x110229#define SIO_HI_RA_RAM_S0_FLG_SMM__PRE 0x010230 10231#define SIO_HI_RA_RAM_S0_DEV_ID__A 0x42001110232#define SIO_HI_RA_RAM_S0_DEV_ID__W 710233#define SIO_HI_RA_RAM_S0_DEV_ID__M 0x7F10234#define SIO_HI_RA_RAM_S0_DEV_ID__PRE 0x5210235 10236#define SIO_HI_RA_RAM_S0_FLG_CRC__A 0x42001210237#define SIO_HI_RA_RAM_S0_FLG_CRC__W 110238#define SIO_HI_RA_RAM_S0_FLG_CRC__M 0x110239#define SIO_HI_RA_RAM_S0_FLG_CRC__PRE 0x010240#define SIO_HI_RA_RAM_S0_FLG_ACC__A 0x42001310241#define SIO_HI_RA_RAM_S0_FLG_ACC__W 410242#define SIO_HI_RA_RAM_S0_FLG_ACC__M 0xF10243#define SIO_HI_RA_RAM_S0_FLG_ACC__PRE 0x010244 10245#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__B 010246#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__W 210247#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__M 0x310248#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_RWM__PRE 0x010249 10250#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__B 210251#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__W 110252#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__M 0x410253#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_BRC__PRE 0x010254 10255#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__B 310256#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__W 110257#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__M 0x810258#define SIO_HI_RA_RAM_S0_FLG_ACC_S0_SLV_SWP__PRE 0x010259 10260#define SIO_HI_RA_RAM_S0_STATE__A 0x42001410261#define SIO_HI_RA_RAM_S0_STATE__W 110262#define SIO_HI_RA_RAM_S0_STATE__M 0x110263#define SIO_HI_RA_RAM_S0_STATE__PRE 0x010264 10265#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__B 010266#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__W 110267#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__M 0x110268#define SIO_HI_RA_RAM_S0_STATE_S0_SLV_STA__PRE 0x010269 10270#define SIO_HI_RA_RAM_S0_BLK_BNK__A 0x42001510271#define SIO_HI_RA_RAM_S0_BLK_BNK__W 1210272#define SIO_HI_RA_RAM_S0_BLK_BNK__M 0xFFF10273#define SIO_HI_RA_RAM_S0_BLK_BNK__PRE 0x8210274 10275#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__B 010276#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__W 610277#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__M 0x3F10278#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BNK__PRE 0x210279 10280#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__B 610281#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__W 610282#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__M 0xFC010283#define SIO_HI_RA_RAM_S0_BLK_BNK_S0_SLV_BLK__PRE 0x8010284 10285#define SIO_HI_RA_RAM_S0_ADDR__A 0x42001610286#define SIO_HI_RA_RAM_S0_ADDR__W 1610287#define SIO_HI_RA_RAM_S0_ADDR__M 0xFFFF10288#define SIO_HI_RA_RAM_S0_ADDR__PRE 0x010289 10290#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__B 010291#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__W 1610292#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__M 0xFFFF10293#define SIO_HI_RA_RAM_S0_ADDR_S0_SLV_ADDR__PRE 0x010294 10295#define SIO_HI_RA_RAM_S0_CRC__A 0x42001710296#define SIO_HI_RA_RAM_S0_CRC__W 1610297#define SIO_HI_RA_RAM_S0_CRC__M 0xFFFF10298#define SIO_HI_RA_RAM_S0_CRC__PRE 0x010299 10300#define SIO_HI_RA_RAM_S0_BUFFER__A 0x42001810301#define SIO_HI_RA_RAM_S0_BUFFER__W 1610302#define SIO_HI_RA_RAM_S0_BUFFER__M 0xFFFF10303#define SIO_HI_RA_RAM_S0_BUFFER__PRE 0x010304 10305#define SIO_HI_RA_RAM_S0_RMWBUF__A 0x42001910306#define SIO_HI_RA_RAM_S0_RMWBUF__W 1610307#define SIO_HI_RA_RAM_S0_RMWBUF__M 0xFFFF10308#define SIO_HI_RA_RAM_S0_RMWBUF__PRE 0x010309 10310#define SIO_HI_RA_RAM_S0_FLG_VB__A 0x42001A10311#define SIO_HI_RA_RAM_S0_FLG_VB__W 110312#define SIO_HI_RA_RAM_S0_FLG_VB__M 0x110313#define SIO_HI_RA_RAM_S0_FLG_VB__PRE 0x010314 10315#define SIO_HI_RA_RAM_S0_TEMP0__A 0x42001B10316#define SIO_HI_RA_RAM_S0_TEMP0__W 1610317#define SIO_HI_RA_RAM_S0_TEMP0__M 0xFFFF10318#define SIO_HI_RA_RAM_S0_TEMP0__PRE 0x010319 10320#define SIO_HI_RA_RAM_S0_TEMP1__A 0x42001C10321#define SIO_HI_RA_RAM_S0_TEMP1__W 1610322#define SIO_HI_RA_RAM_S0_TEMP1__M 0xFFFF10323#define SIO_HI_RA_RAM_S0_TEMP1__PRE 0x010324 10325#define SIO_HI_RA_RAM_S0_OFFSET__A 0x42001D10326#define SIO_HI_RA_RAM_S0_OFFSET__W 1610327#define SIO_HI_RA_RAM_S0_OFFSET__M 0xFFFF10328#define SIO_HI_RA_RAM_S0_OFFSET__PRE 0x010329 10330#define SIO_HI_RA_RAM_S1_FLG_SMM__A 0x42002010331#define SIO_HI_RA_RAM_S1_FLG_SMM__W 110332#define SIO_HI_RA_RAM_S1_FLG_SMM__M 0x110333#define SIO_HI_RA_RAM_S1_FLG_SMM__PRE 0x010334 10335#define SIO_HI_RA_RAM_S1_DEV_ID__A 0x42002110336#define SIO_HI_RA_RAM_S1_DEV_ID__W 710337#define SIO_HI_RA_RAM_S1_DEV_ID__M 0x7F10338#define SIO_HI_RA_RAM_S1_DEV_ID__PRE 0x5210339 10340#define SIO_HI_RA_RAM_S1_FLG_CRC__A 0x42002210341#define SIO_HI_RA_RAM_S1_FLG_CRC__W 110342#define SIO_HI_RA_RAM_S1_FLG_CRC__M 0x110343#define SIO_HI_RA_RAM_S1_FLG_CRC__PRE 0x010344#define SIO_HI_RA_RAM_S1_FLG_ACC__A 0x42002310345#define SIO_HI_RA_RAM_S1_FLG_ACC__W 410346#define SIO_HI_RA_RAM_S1_FLG_ACC__M 0xF10347#define SIO_HI_RA_RAM_S1_FLG_ACC__PRE 0x010348 10349#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__B 010350#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__W 210351#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__M 0x310352#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_RWM__PRE 0x010353 10354#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__B 210355#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__W 110356#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__M 0x410357#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_BRC__PRE 0x010358 10359#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__B 310360#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__W 110361#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__M 0x810362#define SIO_HI_RA_RAM_S1_FLG_ACC_S1_SLV_SWP__PRE 0x010363 10364#define SIO_HI_RA_RAM_S1_STATE__A 0x42002410365#define SIO_HI_RA_RAM_S1_STATE__W 110366#define SIO_HI_RA_RAM_S1_STATE__M 0x110367#define SIO_HI_RA_RAM_S1_STATE__PRE 0x010368 10369#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__B 010370#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__W 110371#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__M 0x110372#define SIO_HI_RA_RAM_S1_STATE_S1_SLV_STA__PRE 0x010373 10374#define SIO_HI_RA_RAM_S1_BLK_BNK__A 0x42002510375#define SIO_HI_RA_RAM_S1_BLK_BNK__W 1210376#define SIO_HI_RA_RAM_S1_BLK_BNK__M 0xFFF10377#define SIO_HI_RA_RAM_S1_BLK_BNK__PRE 0x8210378 10379#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__B 010380#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__W 610381#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__M 0x3F10382#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BNK__PRE 0x210383 10384#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__B 610385#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__W 610386#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__M 0xFC010387#define SIO_HI_RA_RAM_S1_BLK_BNK_S1_SLV_BLK__PRE 0x8010388 10389#define SIO_HI_RA_RAM_S1_ADDR__A 0x42002610390#define SIO_HI_RA_RAM_S1_ADDR__W 1610391#define SIO_HI_RA_RAM_S1_ADDR__M 0xFFFF10392#define SIO_HI_RA_RAM_S1_ADDR__PRE 0x010393 10394#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__B 010395#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__W 1610396#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__M 0xFFFF10397#define SIO_HI_RA_RAM_S1_ADDR_S1_SLV_ADDR__PRE 0x010398 10399#define SIO_HI_RA_RAM_S1_CRC__A 0x42002710400#define SIO_HI_RA_RAM_S1_CRC__W 1610401#define SIO_HI_RA_RAM_S1_CRC__M 0xFFFF10402#define SIO_HI_RA_RAM_S1_CRC__PRE 0x010403 10404#define SIO_HI_RA_RAM_S1_BUFFER__A 0x42002810405#define SIO_HI_RA_RAM_S1_BUFFER__W 1610406#define SIO_HI_RA_RAM_S1_BUFFER__M 0xFFFF10407#define SIO_HI_RA_RAM_S1_BUFFER__PRE 0x010408 10409#define SIO_HI_RA_RAM_S1_RMWBUF__A 0x42002910410#define SIO_HI_RA_RAM_S1_RMWBUF__W 1610411#define SIO_HI_RA_RAM_S1_RMWBUF__M 0xFFFF10412#define SIO_HI_RA_RAM_S1_RMWBUF__PRE 0x010413 10414#define SIO_HI_RA_RAM_S1_FLG_VB__A 0x42002A10415#define SIO_HI_RA_RAM_S1_FLG_VB__W 110416#define SIO_HI_RA_RAM_S1_FLG_VB__M 0x110417#define SIO_HI_RA_RAM_S1_FLG_VB__PRE 0x010418 10419#define SIO_HI_RA_RAM_S1_TEMP0__A 0x42002B10420#define SIO_HI_RA_RAM_S1_TEMP0__W 1610421#define SIO_HI_RA_RAM_S1_TEMP0__M 0xFFFF10422#define SIO_HI_RA_RAM_S1_TEMP0__PRE 0x010423 10424#define SIO_HI_RA_RAM_S1_TEMP1__A 0x42002C10425#define SIO_HI_RA_RAM_S1_TEMP1__W 1610426#define SIO_HI_RA_RAM_S1_TEMP1__M 0xFFFF10427#define SIO_HI_RA_RAM_S1_TEMP1__PRE 0x010428 10429#define SIO_HI_RA_RAM_S1_OFFSET__A 0x42002D10430#define SIO_HI_RA_RAM_S1_OFFSET__W 1610431#define SIO_HI_RA_RAM_S1_OFFSET__M 0xFFFF10432#define SIO_HI_RA_RAM_S1_OFFSET__PRE 0x010433#define SIO_HI_RA_RAM_SEMA__A 0x42003010434#define SIO_HI_RA_RAM_SEMA__W 110435#define SIO_HI_RA_RAM_SEMA__M 0x110436#define SIO_HI_RA_RAM_SEMA__PRE 0x010437#define SIO_HI_RA_RAM_SEMA_FREE 0x010438#define SIO_HI_RA_RAM_SEMA_BUSY 0x110439 10440#define SIO_HI_RA_RAM_RES__A 0x42003110441#define SIO_HI_RA_RAM_RES__W 310442#define SIO_HI_RA_RAM_RES__M 0x710443#define SIO_HI_RA_RAM_RES__PRE 0x010444#define SIO_HI_RA_RAM_RES_OK 0x010445#define SIO_HI_RA_RAM_RES_ERROR 0x110446#define SIO_HI_RA_RAM_RES_I2C_START_FOUND 0x110447#define SIO_HI_RA_RAM_RES_I2C_STOP_FOUND 0x210448#define SIO_HI_RA_RAM_RES_I2C_ARB_LOST 0x310449#define SIO_HI_RA_RAM_RES_I2C_ERROR 0x410450 10451#define SIO_HI_RA_RAM_CMD__A 0x42003210452#define SIO_HI_RA_RAM_CMD__W 410453#define SIO_HI_RA_RAM_CMD__M 0xF10454#define SIO_HI_RA_RAM_CMD__PRE 0x010455#define SIO_HI_RA_RAM_CMD_NULL 0x010456#define SIO_HI_RA_RAM_CMD_UIO 0x110457#define SIO_HI_RA_RAM_CMD_RESET 0x210458#define SIO_HI_RA_RAM_CMD_CONFIG 0x310459#define SIO_HI_RA_RAM_CMD_INTERNAL_TRANSFER 0x410460#define SIO_HI_RA_RAM_CMD_I2C_TRANSMIT 0x510461#define SIO_HI_RA_RAM_CMD_EXEC 0x610462#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x710463#define SIO_HI_RA_RAM_CMD_ATOMIC_COPY 0x810464 10465#define SIO_HI_RA_RAM_PAR_1__A 0x42003310466#define SIO_HI_RA_RAM_PAR_1__W 1610467#define SIO_HI_RA_RAM_PAR_1__M 0xFFFF10468#define SIO_HI_RA_RAM_PAR_1__PRE 0x010469#define SIO_HI_RA_RAM_PAR_1_PAR1__B 010470#define SIO_HI_RA_RAM_PAR_1_PAR1__W 1610471#define SIO_HI_RA_RAM_PAR_1_PAR1__M 0xFFFF10472#define SIO_HI_RA_RAM_PAR_1_PAR1__PRE 0x010473#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x394510474 10475#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__B 010476#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__W 610477#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__M 0x3F10478#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BNK__PRE 0x010479 10480#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__B 610481#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__W 610482#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__M 0xFC010483#define SIO_HI_RA_RAM_PAR_1_ITX_SRC_BLK__PRE 0x010484 10485#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__B 010486#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__W 110487#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__M 0x110488#define SIO_HI_RA_RAM_PAR_1_I2CTX_PORT__PRE 0x010489 10490#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__B 110491#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__W 110492#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__M 0x210493#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE__PRE 0x010494#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_DISABLE 0x010495#define SIO_HI_RA_RAM_PAR_1_I2CTX_TOE_ENABLE 0x210496 10497#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__B 010498#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__W 1010499#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__M 0x3FF10500#define SIO_HI_RA_RAM_PAR_1_EXEC_FUNC__PRE 0x010501 10502#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__B 010503#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__W 610504#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__M 0x3F10505#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BNK__PRE 0x010506 10507#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__B 610508#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__W 610509#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__M 0xFC010510#define SIO_HI_RA_RAM_PAR_1_ACP_INT_BLK__PRE 0x010511 10512#define SIO_HI_RA_RAM_PAR_2__A 0x42003410513#define SIO_HI_RA_RAM_PAR_2__W 1610514#define SIO_HI_RA_RAM_PAR_2__M 0xFFFF10515#define SIO_HI_RA_RAM_PAR_2__PRE 0x010516#define SIO_HI_RA_RAM_PAR_2_PAR2__B 010517#define SIO_HI_RA_RAM_PAR_2_PAR2__W 1610518#define SIO_HI_RA_RAM_PAR_2_PAR2__M 0xFFFF10519#define SIO_HI_RA_RAM_PAR_2_PAR2__PRE 0x010520 10521#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__B 010522#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__W 710523#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F10524#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__PRE 0x2510525 10526#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__B 010527#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__W 1610528#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__M 0xFFFF10529#define SIO_HI_RA_RAM_PAR_2_ITX_SRC_OFF__PRE 0x010530 10531#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__B 010532#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__W 1610533#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__M 0xFFFF10534#define SIO_HI_RA_RAM_PAR_2_I2CTX_BUF__PRE 0x010535 10536#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__B 210537#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__W 110538#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__M 0x410539#define SIO_HI_RA_RAM_PAR_2_BRD_CFG__PRE 0x010540#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x010541#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x410542 10543#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__B 010544#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__W 1610545#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__M 0xFFFF10546#define SIO_HI_RA_RAM_PAR_2_ACP_INT_OFF__PRE 0x010547 10548#define SIO_HI_RA_RAM_PAR_3__A 0x42003510549#define SIO_HI_RA_RAM_PAR_3__W 1610550#define SIO_HI_RA_RAM_PAR_3__M 0xFFFF10551#define SIO_HI_RA_RAM_PAR_3__PRE 0x010552#define SIO_HI_RA_RAM_PAR_3_PAR3__B 010553#define SIO_HI_RA_RAM_PAR_3_PAR3__W 1610554#define SIO_HI_RA_RAM_PAR_3_PAR3__M 0xFFFF10555#define SIO_HI_RA_RAM_PAR_3_PAR3__PRE 0x010556 10557#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__B 010558#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__W 710559#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F10560#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__PRE 0x3F10561 10562#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 710563#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__W 710564#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__M 0x3F8010565#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__PRE 0x1F8010566 10567#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__B 010568#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__W 1610569#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__M 0xFFFF10570#define SIO_HI_RA_RAM_PAR_3_ITX_LEN__PRE 0x010571 10572#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__B 010573#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__W 310574#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__M 0x710575#define SIO_HI_RA_RAM_PAR_3_ACP_LEN__PRE 0x010576 10577#define SIO_HI_RA_RAM_PAR_3_ACP_RW__B 310578#define SIO_HI_RA_RAM_PAR_3_ACP_RW__W 110579#define SIO_HI_RA_RAM_PAR_3_ACP_RW__M 0x810580#define SIO_HI_RA_RAM_PAR_3_ACP_RW__PRE 0x010581#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x010582#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x810583 10584#define SIO_HI_RA_RAM_PAR_4__A 0x42003610585#define SIO_HI_RA_RAM_PAR_4__W 1610586#define SIO_HI_RA_RAM_PAR_4__M 0xFFFF10587#define SIO_HI_RA_RAM_PAR_4__PRE 0x010588#define SIO_HI_RA_RAM_PAR_4_PAR4__B 010589#define SIO_HI_RA_RAM_PAR_4_PAR4__W 1610590#define SIO_HI_RA_RAM_PAR_4_PAR4__M 0xFFFF10591#define SIO_HI_RA_RAM_PAR_4_PAR4__PRE 0x010592 10593#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__B 010594#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__W 810595#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__M 0xFF10596#define SIO_HI_RA_RAM_PAR_4_CFG_WUP__PRE 0xC110597 10598#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__B 010599#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__W 610600#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__M 0x3F10601#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BNK__PRE 0x010602 10603#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__B 610604#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__W 610605#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__M 0xFC010606#define SIO_HI_RA_RAM_PAR_4_ITX_DST_BLK__PRE 0x010607 10608#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__B 010609#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__W 610610#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__M 0x3F10611#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BNK__PRE 0x010612 10613#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__B 610614#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__W 610615#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__M 0xFC010616#define SIO_HI_RA_RAM_PAR_4_ACP_EXT_BLK__PRE 0x010617 10618#define SIO_HI_RA_RAM_PAR_5__A 0x42003710619#define SIO_HI_RA_RAM_PAR_5__W 1610620#define SIO_HI_RA_RAM_PAR_5__M 0xFFFF10621#define SIO_HI_RA_RAM_PAR_5__PRE 0x010622#define SIO_HI_RA_RAM_PAR_5_PAR5__B 010623#define SIO_HI_RA_RAM_PAR_5_PAR5__W 1610624#define SIO_HI_RA_RAM_PAR_5_PAR5__M 0xFFFF10625#define SIO_HI_RA_RAM_PAR_5_PAR5__PRE 0x010626 10627#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__B 010628#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__W 110629#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__M 0x110630#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0__PRE 0x010631#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_NO_SLAVE 0x010632#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x110633 10634#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__B 110635#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__W 110636#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__M 0x210637#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1__PRE 0x010638#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_NO_SLAVE 0x010639#define SIO_HI_RA_RAM_PAR_5_CFG_SLV1_SLAVE 0x210640 10641#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__B 310642#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__W 110643#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x810644#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__PRE 0x010645#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_AWAKE 0x010646#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x810647 10648#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__B 510649#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__W 110650#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__M 0x2010651#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST__PRE 0x010652#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_DISABLE 0x010653#define SIO_HI_RA_RAM_PAR_5_CFG_BDGST_ENABLE 0x2010654 10655#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__B 010656#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__W 1610657#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__M 0xFFFF10658#define SIO_HI_RA_RAM_PAR_5_ITX_DST_OFF__PRE 0x010659 10660#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__B 010661#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__W 1610662#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__M 0xFFFF10663#define SIO_HI_RA_RAM_PAR_5_ACP_EXT_OFF__PRE 0x010664 10665#define SIO_HI_RA_RAM_PAR_6__A 0x42003810666#define SIO_HI_RA_RAM_PAR_6__W 1610667#define SIO_HI_RA_RAM_PAR_6__M 0xFFFF10668#define SIO_HI_RA_RAM_PAR_6__PRE 0x95FF10669#define SIO_HI_RA_RAM_PAR_6_PAR6__B 010670#define SIO_HI_RA_RAM_PAR_6_PAR6__W 1610671#define SIO_HI_RA_RAM_PAR_6_PAR6__M 0xFFFF10672#define SIO_HI_RA_RAM_PAR_6_PAR6__PRE 0x010673 10674#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__B 010675#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__W 810676#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__M 0xFF10677#define SIO_HI_RA_RAM_PAR_6_CFG_TOD__PRE 0xFF10678 10679#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__B 810680#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__W 810681#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__M 0xFF0010682#define SIO_HI_RA_RAM_PAR_6_CFG_WDD__PRE 0x950010683 10684#define SIO_HI_RA_RAM_AB_TEMP__A 0x42006E10685#define SIO_HI_RA_RAM_AB_TEMP__W 1610686#define SIO_HI_RA_RAM_AB_TEMP__M 0xFFFF10687#define SIO_HI_RA_RAM_AB_TEMP__PRE 0x010688 10689#define SIO_HI_RA_RAM_I2C_CTL__A 0x42006F10690#define SIO_HI_RA_RAM_I2C_CTL__W 1610691#define SIO_HI_RA_RAM_I2C_CTL__M 0xFFFF10692#define SIO_HI_RA_RAM_I2C_CTL__PRE 0x010693 10694#define SIO_HI_RA_RAM_VB_ENTRY0__A 0x42007010695#define SIO_HI_RA_RAM_VB_ENTRY0__W 1610696#define SIO_HI_RA_RAM_VB_ENTRY0__M 0xFFFF10697#define SIO_HI_RA_RAM_VB_ENTRY0__PRE 0x010698 10699#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__B 010700#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__W 410701#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__M 0xF10702#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BNK__PRE 0x010703 10704#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__B 410705#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__W 410706#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__M 0xF010707#define SIO_HI_RA_RAM_VB_ENTRY0_HI_MAP_BLK__PRE 0x010708 10709#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__B 810710#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__W 410711#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__M 0xF0010712#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BNK__PRE 0x010713 10714#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__B 1210715#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__W 410716#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__M 0xF00010717#define SIO_HI_RA_RAM_VB_ENTRY0_HI_VIRT_BLK__PRE 0x010718 10719#define SIO_HI_RA_RAM_VB_OFFSET0__A 0x42007110720#define SIO_HI_RA_RAM_VB_OFFSET0__W 1610721#define SIO_HI_RA_RAM_VB_OFFSET0__M 0xFFFF10722#define SIO_HI_RA_RAM_VB_OFFSET0__PRE 0x010723 10724#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__B 010725#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__W 1610726#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__M 0xFFFF10727#define SIO_HI_RA_RAM_VB_OFFSET0_HI_MAP_OFF0__PRE 0x010728 10729#define SIO_HI_RA_RAM_VB_ENTRY1__A 0x42007210730#define SIO_HI_RA_RAM_VB_ENTRY1__W 1610731#define SIO_HI_RA_RAM_VB_ENTRY1__M 0xFFFF10732#define SIO_HI_RA_RAM_VB_ENTRY1__PRE 0x010733#define SIO_HI_RA_RAM_VB_OFFSET1__A 0x42007310734#define SIO_HI_RA_RAM_VB_OFFSET1__W 1610735#define SIO_HI_RA_RAM_VB_OFFSET1__M 0xFFFF10736#define SIO_HI_RA_RAM_VB_OFFSET1__PRE 0x010737 10738#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__B 010739#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__W 1610740#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__M 0xFFFF10741#define SIO_HI_RA_RAM_VB_OFFSET1_HI_MAP_OFF__PRE 0x010742 10743#define SIO_HI_RA_RAM_VB_ENTRY2__A 0x42007410744#define SIO_HI_RA_RAM_VB_ENTRY2__W 1610745#define SIO_HI_RA_RAM_VB_ENTRY2__M 0xFFFF10746#define SIO_HI_RA_RAM_VB_ENTRY2__PRE 0x010747#define SIO_HI_RA_RAM_VB_OFFSET2__A 0x42007510748#define SIO_HI_RA_RAM_VB_OFFSET2__W 1610749#define SIO_HI_RA_RAM_VB_OFFSET2__M 0xFFFF10750#define SIO_HI_RA_RAM_VB_OFFSET2__PRE 0x010751 10752#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__B 010753#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__W 1610754#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__M 0xFFFF10755#define SIO_HI_RA_RAM_VB_OFFSET2_HI_MAP_OFF__PRE 0x010756 10757#define SIO_HI_RA_RAM_VB_ENTRY3__A 0x42007610758#define SIO_HI_RA_RAM_VB_ENTRY3__W 1610759#define SIO_HI_RA_RAM_VB_ENTRY3__M 0xFFFF10760#define SIO_HI_RA_RAM_VB_ENTRY3__PRE 0x010761#define SIO_HI_RA_RAM_VB_OFFSET3__A 0x42007710762#define SIO_HI_RA_RAM_VB_OFFSET3__W 1610763#define SIO_HI_RA_RAM_VB_OFFSET3__M 0xFFFF10764#define SIO_HI_RA_RAM_VB_OFFSET3__PRE 0x010765 10766#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__B 010767#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__W 1610768#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__M 0xFFFF10769#define SIO_HI_RA_RAM_VB_OFFSET3_HI_MAP_OFF__PRE 0x010770 10771#define SIO_HI_RA_RAM_VB_ENTRY4__A 0x42007810772#define SIO_HI_RA_RAM_VB_ENTRY4__W 1610773#define SIO_HI_RA_RAM_VB_ENTRY4__M 0xFFFF10774#define SIO_HI_RA_RAM_VB_ENTRY4__PRE 0x010775#define SIO_HI_RA_RAM_VB_OFFSET4__A 0x42007910776#define SIO_HI_RA_RAM_VB_OFFSET4__W 1610777#define SIO_HI_RA_RAM_VB_OFFSET4__M 0xFFFF10778#define SIO_HI_RA_RAM_VB_OFFSET4__PRE 0x010779 10780#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__B 010781#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__W 1610782#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__M 0xFFFF10783#define SIO_HI_RA_RAM_VB_OFFSET4_HI_MAP_OFF__PRE 0x010784 10785#define SIO_HI_RA_RAM_VB_ENTRY5__A 0x42007A10786#define SIO_HI_RA_RAM_VB_ENTRY5__W 1610787#define SIO_HI_RA_RAM_VB_ENTRY5__M 0xFFFF10788#define SIO_HI_RA_RAM_VB_ENTRY5__PRE 0x010789#define SIO_HI_RA_RAM_VB_OFFSET5__A 0x42007B10790#define SIO_HI_RA_RAM_VB_OFFSET5__W 1610791#define SIO_HI_RA_RAM_VB_OFFSET5__M 0xFFFF10792#define SIO_HI_RA_RAM_VB_OFFSET5__PRE 0x010793 10794#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__B 010795#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__W 1610796#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__M 0xFFFF10797#define SIO_HI_RA_RAM_VB_OFFSET5_HI_MAP_OFF__PRE 0x010798 10799#define SIO_HI_RA_RAM_VB_ENTRY6__A 0x42007C10800#define SIO_HI_RA_RAM_VB_ENTRY6__W 1610801#define SIO_HI_RA_RAM_VB_ENTRY6__M 0xFFFF10802#define SIO_HI_RA_RAM_VB_ENTRY6__PRE 0x010803#define SIO_HI_RA_RAM_VB_OFFSET6__A 0x42007D10804#define SIO_HI_RA_RAM_VB_OFFSET6__W 1610805#define SIO_HI_RA_RAM_VB_OFFSET6__M 0xFFFF10806#define SIO_HI_RA_RAM_VB_OFFSET6__PRE 0x010807 10808#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__B 010809#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__W 1610810#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__M 0xFFFF10811#define SIO_HI_RA_RAM_VB_OFFSET6_HI_MAP_OFF__PRE 0x010812 10813#define SIO_HI_RA_RAM_VB_ENTRY7__A 0x42007E10814#define SIO_HI_RA_RAM_VB_ENTRY7__W 1610815#define SIO_HI_RA_RAM_VB_ENTRY7__M 0xFFFF10816#define SIO_HI_RA_RAM_VB_ENTRY7__PRE 0x010817#define SIO_HI_RA_RAM_VB_OFFSET7__A 0x42007F10818#define SIO_HI_RA_RAM_VB_OFFSET7__W 1610819#define SIO_HI_RA_RAM_VB_OFFSET7__M 0xFFFF10820#define SIO_HI_RA_RAM_VB_OFFSET7__PRE 0x010821 10822#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__B 010823#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__W 1610824#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__M 0xFFFF10825#define SIO_HI_RA_RAM_VB_OFFSET7_HI_MAP_OFF__PRE 0x010826 10827#define SIO_HI_IF_RAM_TRP_BPT_0__A 0x43000010828#define SIO_HI_IF_RAM_TRP_BPT_0__W 1210829#define SIO_HI_IF_RAM_TRP_BPT_0__M 0xFFF10830#define SIO_HI_IF_RAM_TRP_BPT_0__PRE 0x010831#define SIO_HI_IF_RAM_TRP_BPT_1__A 0x43000110832#define SIO_HI_IF_RAM_TRP_BPT_1__W 1210833#define SIO_HI_IF_RAM_TRP_BPT_1__M 0xFFF10834#define SIO_HI_IF_RAM_TRP_BPT_1__PRE 0x010835#define SIO_HI_IF_RAM_TRP_STK_0__A 0x43000210836#define SIO_HI_IF_RAM_TRP_STK_0__W 1210837#define SIO_HI_IF_RAM_TRP_STK_0__M 0xFFF10838#define SIO_HI_IF_RAM_TRP_STK_0__PRE 0x010839#define SIO_HI_IF_RAM_TRP_STK_1__A 0x43000310840#define SIO_HI_IF_RAM_TRP_STK_1__W 1210841#define SIO_HI_IF_RAM_TRP_STK_1__M 0xFFF10842#define SIO_HI_IF_RAM_TRP_STK_1__PRE 0x010843#define SIO_HI_IF_RAM_FUN_BASE__A 0x43030010844#define SIO_HI_IF_RAM_FUN_BASE__W 1210845#define SIO_HI_IF_RAM_FUN_BASE__M 0xFFF10846#define SIO_HI_IF_RAM_FUN_BASE__PRE 0x010847 10848#define SIO_HI_IF_COMM_EXEC__A 0x44000010849#define SIO_HI_IF_COMM_EXEC__W 210850#define SIO_HI_IF_COMM_EXEC__M 0x310851#define SIO_HI_IF_COMM_EXEC__PRE 0x010852#define SIO_HI_IF_COMM_EXEC_STOP 0x010853#define SIO_HI_IF_COMM_EXEC_ACTIVE 0x110854#define SIO_HI_IF_COMM_EXEC_HOLD 0x210855#define SIO_HI_IF_COMM_EXEC_STEP 0x310856 10857#define SIO_HI_IF_COMM_STATE__A 0x44000110858#define SIO_HI_IF_COMM_STATE__W 1010859#define SIO_HI_IF_COMM_STATE__M 0x3FF10860#define SIO_HI_IF_COMM_STATE__PRE 0x010861#define SIO_HI_IF_COMM_INT_REQ__A 0x44000310862#define SIO_HI_IF_COMM_INT_REQ__W 110863#define SIO_HI_IF_COMM_INT_REQ__M 0x110864#define SIO_HI_IF_COMM_INT_REQ__PRE 0x010865#define SIO_HI_IF_COMM_INT_STA__A 0x44000510866#define SIO_HI_IF_COMM_INT_STA__W 110867#define SIO_HI_IF_COMM_INT_STA__M 0x110868#define SIO_HI_IF_COMM_INT_STA__PRE 0x010869#define SIO_HI_IF_COMM_INT_STA_STAT__B 010870#define SIO_HI_IF_COMM_INT_STA_STAT__W 110871#define SIO_HI_IF_COMM_INT_STA_STAT__M 0x110872#define SIO_HI_IF_COMM_INT_STA_STAT__PRE 0x010873 10874#define SIO_HI_IF_COMM_INT_MSK__A 0x44000610875#define SIO_HI_IF_COMM_INT_MSK__W 110876#define SIO_HI_IF_COMM_INT_MSK__M 0x110877#define SIO_HI_IF_COMM_INT_MSK__PRE 0x010878#define SIO_HI_IF_COMM_INT_MSK_STAT__B 010879#define SIO_HI_IF_COMM_INT_MSK_STAT__W 110880#define SIO_HI_IF_COMM_INT_MSK_STAT__M 0x110881#define SIO_HI_IF_COMM_INT_MSK_STAT__PRE 0x010882 10883#define SIO_HI_IF_COMM_INT_STM__A 0x44000710884#define SIO_HI_IF_COMM_INT_STM__W 110885#define SIO_HI_IF_COMM_INT_STM__M 0x110886#define SIO_HI_IF_COMM_INT_STM__PRE 0x010887#define SIO_HI_IF_COMM_INT_STM_STAT__B 010888#define SIO_HI_IF_COMM_INT_STM_STAT__W 110889#define SIO_HI_IF_COMM_INT_STM_STAT__M 0x110890#define SIO_HI_IF_COMM_INT_STM_STAT__PRE 0x010891 10892#define SIO_HI_IF_STK_0__A 0x44001010893#define SIO_HI_IF_STK_0__W 1010894#define SIO_HI_IF_STK_0__M 0x3FF10895#define SIO_HI_IF_STK_0__PRE 0x210896 10897#define SIO_HI_IF_STK_0_ADDR__B 010898#define SIO_HI_IF_STK_0_ADDR__W 1010899#define SIO_HI_IF_STK_0_ADDR__M 0x3FF10900#define SIO_HI_IF_STK_0_ADDR__PRE 0x210901 10902#define SIO_HI_IF_STK_1__A 0x44001110903#define SIO_HI_IF_STK_1__W 1010904#define SIO_HI_IF_STK_1__M 0x3FF10905#define SIO_HI_IF_STK_1__PRE 0x210906#define SIO_HI_IF_STK_1_ADDR__B 010907#define SIO_HI_IF_STK_1_ADDR__W 1010908#define SIO_HI_IF_STK_1_ADDR__M 0x3FF10909#define SIO_HI_IF_STK_1_ADDR__PRE 0x210910 10911#define SIO_HI_IF_STK_2__A 0x44001210912#define SIO_HI_IF_STK_2__W 1010913#define SIO_HI_IF_STK_2__M 0x3FF10914#define SIO_HI_IF_STK_2__PRE 0x210915#define SIO_HI_IF_STK_2_ADDR__B 010916#define SIO_HI_IF_STK_2_ADDR__W 1010917#define SIO_HI_IF_STK_2_ADDR__M 0x3FF10918#define SIO_HI_IF_STK_2_ADDR__PRE 0x210919 10920#define SIO_HI_IF_STK_3__A 0x44001310921#define SIO_HI_IF_STK_3__W 1010922#define SIO_HI_IF_STK_3__M 0x3FF10923#define SIO_HI_IF_STK_3__PRE 0x210924 10925#define SIO_HI_IF_STK_3_ADDR__B 010926#define SIO_HI_IF_STK_3_ADDR__W 1010927#define SIO_HI_IF_STK_3_ADDR__M 0x3FF10928#define SIO_HI_IF_STK_3_ADDR__PRE 0x210929 10930#define SIO_HI_IF_BPT_IDX__A 0x44001F10931#define SIO_HI_IF_BPT_IDX__W 110932#define SIO_HI_IF_BPT_IDX__M 0x110933#define SIO_HI_IF_BPT_IDX__PRE 0x010934 10935#define SIO_HI_IF_BPT_IDX_ADDR__B 010936#define SIO_HI_IF_BPT_IDX_ADDR__W 110937#define SIO_HI_IF_BPT_IDX_ADDR__M 0x110938#define SIO_HI_IF_BPT_IDX_ADDR__PRE 0x010939 10940#define SIO_HI_IF_BPT__A 0x44002010941#define SIO_HI_IF_BPT__W 1010942#define SIO_HI_IF_BPT__M 0x3FF10943#define SIO_HI_IF_BPT__PRE 0x210944 10945#define SIO_HI_IF_BPT_ADDR__B 010946#define SIO_HI_IF_BPT_ADDR__W 1010947#define SIO_HI_IF_BPT_ADDR__M 0x3FF10948#define SIO_HI_IF_BPT_ADDR__PRE 0x210949 10950#define SIO_CC_COMM_EXEC__A 0x45000010951#define SIO_CC_COMM_EXEC__W 210952#define SIO_CC_COMM_EXEC__M 0x310953#define SIO_CC_COMM_EXEC__PRE 0x010954#define SIO_CC_COMM_EXEC_STOP 0x010955#define SIO_CC_COMM_EXEC_ACTIVE 0x110956#define SIO_CC_COMM_EXEC_HOLD 0x210957 10958#define SIO_CC_PLL_MODE__A 0x45001010959#define SIO_CC_PLL_MODE__W 610960#define SIO_CC_PLL_MODE__M 0x3F10961#define SIO_CC_PLL_MODE__PRE 0x010962 10963#define SIO_CC_PLL_MODE_FREF_SEL__B 010964#define SIO_CC_PLL_MODE_FREF_SEL__W 210965#define SIO_CC_PLL_MODE_FREF_SEL__M 0x310966#define SIO_CC_PLL_MODE_FREF_SEL__PRE 0x010967#define SIO_CC_PLL_MODE_FREF_SEL_OHW 0x010968#define SIO_CC_PLL_MODE_FREF_SEL_27_00 0x110969#define SIO_CC_PLL_MODE_FREF_SEL_20_25 0x210970#define SIO_CC_PLL_MODE_FREF_SEL_4_00 0x310971 10972#define SIO_CC_PLL_MODE_LOCKSEL__B 210973#define SIO_CC_PLL_MODE_LOCKSEL__W 210974#define SIO_CC_PLL_MODE_LOCKSEL__M 0xC10975#define SIO_CC_PLL_MODE_LOCKSEL__PRE 0x010976 10977#define SIO_CC_PLL_MODE_BYPASS__B 410978#define SIO_CC_PLL_MODE_BYPASS__W 210979#define SIO_CC_PLL_MODE_BYPASS__M 0x3010980#define SIO_CC_PLL_MODE_BYPASS__PRE 0x010981#define SIO_CC_PLL_MODE_BYPASS_OHW 0x010982#define SIO_CC_PLL_MODE_BYPASS_OFF 0x1010983#define SIO_CC_PLL_MODE_BYPASS_ON 0x2010984 10985#define SIO_CC_PLL_TEST__A 0x45001110986#define SIO_CC_PLL_TEST__W 810987#define SIO_CC_PLL_TEST__M 0xFF10988#define SIO_CC_PLL_TEST__PRE 0x010989 10990#define SIO_CC_PLL_LOCK__A 0x45001210991#define SIO_CC_PLL_LOCK__W 110992#define SIO_CC_PLL_LOCK__M 0x110993#define SIO_CC_PLL_LOCK__PRE 0x010994#define SIO_CC_CLK_MODE__A 0x45001410995#define SIO_CC_CLK_MODE__W 510996#define SIO_CC_CLK_MODE__M 0x1F10997#define SIO_CC_CLK_MODE__PRE 0x010998 10999#define SIO_CC_CLK_MODE_DELAY__B 011000#define SIO_CC_CLK_MODE_DELAY__W 411001#define SIO_CC_CLK_MODE_DELAY__M 0xF11002#define SIO_CC_CLK_MODE_DELAY__PRE 0x011003 11004#define SIO_CC_CLK_MODE_INVERT__B 411005#define SIO_CC_CLK_MODE_INVERT__W 111006#define SIO_CC_CLK_MODE_INVERT__M 0x1011007#define SIO_CC_CLK_MODE_INVERT__PRE 0x011008 11009#define SIO_CC_PWD_MODE__A 0x45001511010#define SIO_CC_PWD_MODE__W 311011#define SIO_CC_PWD_MODE__M 0x711012#define SIO_CC_PWD_MODE__PRE 0x011013 11014#define SIO_CC_PWD_MODE_LEVEL__B 011015#define SIO_CC_PWD_MODE_LEVEL__W 211016#define SIO_CC_PWD_MODE_LEVEL__M 0x311017#define SIO_CC_PWD_MODE_LEVEL__PRE 0x011018#define SIO_CC_PWD_MODE_LEVEL_NONE 0x011019#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x111020#define SIO_CC_PWD_MODE_LEVEL_PLL 0x211021#define SIO_CC_PWD_MODE_LEVEL_OSC 0x311022 11023#define SIO_CC_PWD_MODE_USE_LOCK__B 211024#define SIO_CC_PWD_MODE_USE_LOCK__W 111025#define SIO_CC_PWD_MODE_USE_LOCK__M 0x411026#define SIO_CC_PWD_MODE_USE_LOCK__PRE 0x011027 11028#define SIO_CC_SOFT_RST__A 0x45001611029#define SIO_CC_SOFT_RST__W 211030#define SIO_CC_SOFT_RST__M 0x311031#define SIO_CC_SOFT_RST__PRE 0x011032 11033#define SIO_CC_SOFT_RST_SYS__B 011034#define SIO_CC_SOFT_RST_SYS__W 111035#define SIO_CC_SOFT_RST_SYS__M 0x111036#define SIO_CC_SOFT_RST_SYS__PRE 0x011037 11038#define SIO_CC_SOFT_RST_OSC__B 111039#define SIO_CC_SOFT_RST_OSC__W 111040#define SIO_CC_SOFT_RST_OSC__M 0x211041#define SIO_CC_SOFT_RST_OSC__PRE 0x011042 11043#define SIO_CC_UPDATE__A 0x45001711044#define SIO_CC_UPDATE__W 1611045#define SIO_CC_UPDATE__M 0xFFFF11046#define SIO_CC_UPDATE__PRE 0x011047#define SIO_CC_UPDATE_KEY 0xFABA11048 11049#define SIO_SA_COMM_EXEC__A 0x46000011050#define SIO_SA_COMM_EXEC__W 211051#define SIO_SA_COMM_EXEC__M 0x311052#define SIO_SA_COMM_EXEC__PRE 0x011053#define SIO_SA_COMM_EXEC_STOP 0x011054#define SIO_SA_COMM_EXEC_ACTIVE 0x111055#define SIO_SA_COMM_EXEC_HOLD 0x211056 11057#define SIO_SA_COMM_INT_REQ__A 0x46000311058#define SIO_SA_COMM_INT_REQ__W 111059#define SIO_SA_COMM_INT_REQ__M 0x111060#define SIO_SA_COMM_INT_REQ__PRE 0x011061#define SIO_SA_COMM_INT_STA__A 0x46000511062#define SIO_SA_COMM_INT_STA__W 411063#define SIO_SA_COMM_INT_STA__M 0xF11064#define SIO_SA_COMM_INT_STA__PRE 0x011065 11066#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__B 011067#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__W 111068#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__M 0x111069#define SIO_SA_COMM_INT_STA_TR_END_INT_STA__PRE 0x011070 11071#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__B 111072#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__W 111073#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__M 0x211074#define SIO_SA_COMM_INT_STA_TR_BUFF_EMPTY_INT__PRE 0x011075 11076#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__B 211077#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__W 111078#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__M 0x411079#define SIO_SA_COMM_INT_STA_RX_END_INT_STA__PRE 0x011080 11081#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__B 311082#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__W 111083#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__M 0x811084#define SIO_SA_COMM_INT_STA_RX_BUFF_FULL_INT__PRE 0x011085 11086#define SIO_SA_COMM_INT_MSK__A 0x46000611087#define SIO_SA_COMM_INT_MSK__W 411088#define SIO_SA_COMM_INT_MSK__M 0xF11089#define SIO_SA_COMM_INT_MSK__PRE 0x011090 11091#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__B 011092#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__W 111093#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__M 0x111094#define SIO_SA_COMM_INT_MSK_TR_END_INT_MASK__PRE 0x011095 11096#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__B 111097#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__W 111098#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__M 0x211099#define SIO_SA_COMM_INT_MSK_TR_BUFF_EMPTY_MASK__PRE 0x011100 11101#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__B 211102#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__W 111103#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__M 0x411104#define SIO_SA_COMM_INT_MSK_RX_END_INT_MASK__PRE 0x011105 11106#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__B 311107#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__W 111108#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__M 0x811109#define SIO_SA_COMM_INT_MSK_RX_BUFF_FULL_MASK__PRE 0x011110 11111#define SIO_SA_COMM_INT_STM__A 0x46000711112#define SIO_SA_COMM_INT_STM__W 411113#define SIO_SA_COMM_INT_STM__M 0xF11114#define SIO_SA_COMM_INT_STM__PRE 0x011115 11116#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__B 011117#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__W 111118#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__M 0x111119#define SIO_SA_COMM_INT_STM_TR_END_INT_MASK__PRE 0x011120 11121#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__B 111122#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__W 111123#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__M 0x211124#define SIO_SA_COMM_INT_STM_TR_BUFF_EMPTY_MASK__PRE 0x011125 11126#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__B 211127#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__W 111128#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__M 0x411129#define SIO_SA_COMM_INT_STM_RX_END_INT_MASK__PRE 0x011130 11131#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__B 311132#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__W 111133#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__M 0x811134#define SIO_SA_COMM_INT_STM_RX_BUFF_FULL_MASK__PRE 0x011135 11136#define SIO_SA_PRESCALER__A 0x46001011137#define SIO_SA_PRESCALER__W 1311138#define SIO_SA_PRESCALER__M 0x1FFF11139#define SIO_SA_PRESCALER__PRE 0x18B711140#define SIO_SA_TX_DATA0__A 0x46001111141#define SIO_SA_TX_DATA0__W 1611142#define SIO_SA_TX_DATA0__M 0xFFFF11143#define SIO_SA_TX_DATA0__PRE 0x011144#define SIO_SA_TX_DATA1__A 0x46001211145#define SIO_SA_TX_DATA1__W 1611146#define SIO_SA_TX_DATA1__M 0xFFFF11147#define SIO_SA_TX_DATA1__PRE 0x011148#define SIO_SA_TX_DATA2__A 0x46001311149#define SIO_SA_TX_DATA2__W 1611150#define SIO_SA_TX_DATA2__M 0xFFFF11151#define SIO_SA_TX_DATA2__PRE 0x011152#define SIO_SA_TX_DATA3__A 0x46001411153#define SIO_SA_TX_DATA3__W 1611154#define SIO_SA_TX_DATA3__M 0xFFFF11155#define SIO_SA_TX_DATA3__PRE 0x011156#define SIO_SA_TX_LENGTH__A 0x46001511157#define SIO_SA_TX_LENGTH__W 611158#define SIO_SA_TX_LENGTH__M 0x3F11159#define SIO_SA_TX_LENGTH__PRE 0x011160#define SIO_SA_TX_COMMAND__A 0x46001611161#define SIO_SA_TX_COMMAND__W 211162#define SIO_SA_TX_COMMAND__M 0x311163#define SIO_SA_TX_COMMAND__PRE 0x311164 11165#define SIO_SA_TX_COMMAND_TX_INVERT__B 011166#define SIO_SA_TX_COMMAND_TX_INVERT__W 111167#define SIO_SA_TX_COMMAND_TX_INVERT__M 0x111168#define SIO_SA_TX_COMMAND_TX_INVERT__PRE 0x111169 11170#define SIO_SA_TX_COMMAND_TX_ENABLE__B 111171#define SIO_SA_TX_COMMAND_TX_ENABLE__W 111172#define SIO_SA_TX_COMMAND_TX_ENABLE__M 0x211173#define SIO_SA_TX_COMMAND_TX_ENABLE__PRE 0x211174 11175#define SIO_SA_TX_STATUS__A 0x46001711176#define SIO_SA_TX_STATUS__W 211177#define SIO_SA_TX_STATUS__M 0x311178#define SIO_SA_TX_STATUS__PRE 0x011179 11180#define SIO_SA_TX_STATUS_BUSY__B 011181#define SIO_SA_TX_STATUS_BUSY__W 111182#define SIO_SA_TX_STATUS_BUSY__M 0x111183#define SIO_SA_TX_STATUS_BUSY__PRE 0x011184 11185#define SIO_SA_TX_STATUS_BUFF_FULL__B 111186#define SIO_SA_TX_STATUS_BUFF_FULL__W 111187#define SIO_SA_TX_STATUS_BUFF_FULL__M 0x211188#define SIO_SA_TX_STATUS_BUFF_FULL__PRE 0x011189 11190#define SIO_SA_RX_DATA0__A 0x46001811191#define SIO_SA_RX_DATA0__W 1611192#define SIO_SA_RX_DATA0__M 0xFFFF11193#define SIO_SA_RX_DATA0__PRE 0x011194#define SIO_SA_RX_DATA1__A 0x46001911195#define SIO_SA_RX_DATA1__W 1611196#define SIO_SA_RX_DATA1__M 0xFFFF11197#define SIO_SA_RX_DATA1__PRE 0x011198#define SIO_SA_RX_LENGTH__A 0x46001A11199#define SIO_SA_RX_LENGTH__W 611200#define SIO_SA_RX_LENGTH__M 0x3F11201#define SIO_SA_RX_LENGTH__PRE 0x011202#define SIO_SA_RX_COMMAND__A 0x46001B11203#define SIO_SA_RX_COMMAND__W 111204#define SIO_SA_RX_COMMAND__M 0x111205#define SIO_SA_RX_COMMAND__PRE 0x111206 11207#define SIO_SA_RX_COMMAND_RX_INVERT__B 011208#define SIO_SA_RX_COMMAND_RX_INVERT__W 111209#define SIO_SA_RX_COMMAND_RX_INVERT__M 0x111210#define SIO_SA_RX_COMMAND_RX_INVERT__PRE 0x111211 11212#define SIO_SA_RX_STATUS__A 0x46001C11213#define SIO_SA_RX_STATUS__W 211214#define SIO_SA_RX_STATUS__M 0x311215#define SIO_SA_RX_STATUS__PRE 0x011216 11217#define SIO_SA_RX_STATUS_BUSY__B 011218#define SIO_SA_RX_STATUS_BUSY__W 111219#define SIO_SA_RX_STATUS_BUSY__M 0x111220#define SIO_SA_RX_STATUS_BUSY__PRE 0x011221 11222#define SIO_SA_RX_STATUS_BUFF_FULL__B 111223#define SIO_SA_RX_STATUS_BUFF_FULL__W 111224#define SIO_SA_RX_STATUS_BUFF_FULL__M 0x211225#define SIO_SA_RX_STATUS_BUFF_FULL__PRE 0x011226 11227#define SIO_PDR_COMM_EXEC__A 0x7F000011228#define SIO_PDR_COMM_EXEC__W 211229#define SIO_PDR_COMM_EXEC__M 0x311230#define SIO_PDR_COMM_EXEC__PRE 0x011231#define SIO_PDR_COMM_EXEC_STOP 0x011232#define SIO_PDR_COMM_EXEC_ACTIVE 0x111233#define SIO_PDR_COMM_EXEC_HOLD 0x211234 11235#define SIO_PDR_MON_CFG__A 0x7F001011236#define SIO_PDR_MON_CFG__W 211237#define SIO_PDR_MON_CFG__M 0x311238#define SIO_PDR_MON_CFG__PRE 0x011239 11240#define SIO_PDR_MON_CFG_OSEL__B 011241#define SIO_PDR_MON_CFG_OSEL__W 111242#define SIO_PDR_MON_CFG_OSEL__M 0x111243#define SIO_PDR_MON_CFG_OSEL__PRE 0x011244 11245#define SIO_PDR_MON_CFG_IACT__B 111246#define SIO_PDR_MON_CFG_IACT__W 111247#define SIO_PDR_MON_CFG_IACT__M 0x211248#define SIO_PDR_MON_CFG_IACT__PRE 0x011249 11250#define SIO_PDR_FDB_CFG__A 0x7F001111251#define SIO_PDR_FDB_CFG__W 211252#define SIO_PDR_FDB_CFG__M 0x311253#define SIO_PDR_FDB_CFG__PRE 0x011254#define SIO_PDR_FDB_CFG_SEL__B 011255#define SIO_PDR_FDB_CFG_SEL__W 211256#define SIO_PDR_FDB_CFG_SEL__M 0x311257#define SIO_PDR_FDB_CFG_SEL__PRE 0x011258 11259#define SIO_PDR_SMA_RX_SEL__A 0x7F001211260#define SIO_PDR_SMA_RX_SEL__W 411261#define SIO_PDR_SMA_RX_SEL__M 0xF11262#define SIO_PDR_SMA_RX_SEL__PRE 0x011263#define SIO_PDR_SMA_RX_SEL_SEL__B 011264#define SIO_PDR_SMA_RX_SEL_SEL__W 411265#define SIO_PDR_SMA_RX_SEL_SEL__M 0xF11266#define SIO_PDR_SMA_RX_SEL_SEL__PRE 0x011267 11268#define SIO_PDR_SMA_TX_SILENT__A 0x7F001311269#define SIO_PDR_SMA_TX_SILENT__W 111270#define SIO_PDR_SMA_TX_SILENT__M 0x111271#define SIO_PDR_SMA_TX_SILENT__PRE 0x011272#define SIO_PDR_UIO_IN_LO__A 0x7F001411273#define SIO_PDR_UIO_IN_LO__W 1611274#define SIO_PDR_UIO_IN_LO__M 0xFFFF11275#define SIO_PDR_UIO_IN_LO__PRE 0x011276#define SIO_PDR_UIO_IN_LO_DATA__B 011277#define SIO_PDR_UIO_IN_LO_DATA__W 1611278#define SIO_PDR_UIO_IN_LO_DATA__M 0xFFFF11279#define SIO_PDR_UIO_IN_LO_DATA__PRE 0x011280 11281#define SIO_PDR_UIO_IN_HI__A 0x7F001511282#define SIO_PDR_UIO_IN_HI__W 1411283#define SIO_PDR_UIO_IN_HI__M 0x3FFF11284#define SIO_PDR_UIO_IN_HI__PRE 0x011285#define SIO_PDR_UIO_IN_HI_DATA__B 011286#define SIO_PDR_UIO_IN_HI_DATA__W 1411287#define SIO_PDR_UIO_IN_HI_DATA__M 0x3FFF11288#define SIO_PDR_UIO_IN_HI_DATA__PRE 0x011289 11290#define SIO_PDR_UIO_OUT_LO__A 0x7F001611291#define SIO_PDR_UIO_OUT_LO__W 1611292#define SIO_PDR_UIO_OUT_LO__M 0xFFFF11293#define SIO_PDR_UIO_OUT_LO__PRE 0x011294#define SIO_PDR_UIO_OUT_LO_DATA__B 011295#define SIO_PDR_UIO_OUT_LO_DATA__W 1611296#define SIO_PDR_UIO_OUT_LO_DATA__M 0xFFFF11297#define SIO_PDR_UIO_OUT_LO_DATA__PRE 0x011298 11299#define SIO_PDR_UIO_OUT_HI__A 0x7F001711300#define SIO_PDR_UIO_OUT_HI__W 1411301#define SIO_PDR_UIO_OUT_HI__M 0x3FFF11302#define SIO_PDR_UIO_OUT_HI__PRE 0x011303#define SIO_PDR_UIO_OUT_HI_DATA__B 011304#define SIO_PDR_UIO_OUT_HI_DATA__W 1411305#define SIO_PDR_UIO_OUT_HI_DATA__M 0x3FFF11306#define SIO_PDR_UIO_OUT_HI_DATA__PRE 0x011307 11308#define SIO_PDR_PWM1_MODE__A 0x7F001811309#define SIO_PDR_PWM1_MODE__W 211310#define SIO_PDR_PWM1_MODE__M 0x311311#define SIO_PDR_PWM1_MODE__PRE 0x011312#define SIO_PDR_PWM1_PRESCALE__A 0x7F001911313#define SIO_PDR_PWM1_PRESCALE__W 611314#define SIO_PDR_PWM1_PRESCALE__M 0x3F11315#define SIO_PDR_PWM1_PRESCALE__PRE 0x011316#define SIO_PDR_PWM1_VALUE__A 0x7F001A11317#define SIO_PDR_PWM1_VALUE__W 1111318#define SIO_PDR_PWM1_VALUE__M 0x7FF11319#define SIO_PDR_PWM1_VALUE__PRE 0x011320#define SIO_PDR_PWM2_MODE__A 0x7F001C11321#define SIO_PDR_PWM2_MODE__W 211322#define SIO_PDR_PWM2_MODE__M 0x311323#define SIO_PDR_PWM2_MODE__PRE 0x011324#define SIO_PDR_PWM2_PRESCALE__A 0x7F001D11325#define SIO_PDR_PWM2_PRESCALE__W 611326#define SIO_PDR_PWM2_PRESCALE__M 0x3F11327#define SIO_PDR_PWM2_PRESCALE__PRE 0x011328#define SIO_PDR_PWM2_VALUE__A 0x7F001E11329#define SIO_PDR_PWM2_VALUE__W 1111330#define SIO_PDR_PWM2_VALUE__M 0x7FF11331#define SIO_PDR_PWM2_VALUE__PRE 0x011332#define SIO_PDR_OHW_CFG__A 0x7F001F11333#define SIO_PDR_OHW_CFG__W 711334#define SIO_PDR_OHW_CFG__M 0x7F11335#define SIO_PDR_OHW_CFG__PRE 0x011336 11337#define SIO_PDR_OHW_CFG_FREF_SEL__B 011338#define SIO_PDR_OHW_CFG_FREF_SEL__W 211339#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x311340#define SIO_PDR_OHW_CFG_FREF_SEL__PRE 0x011341 11342#define SIO_PDR_OHW_CFG_BYPASS__B 211343#define SIO_PDR_OHW_CFG_BYPASS__W 111344#define SIO_PDR_OHW_CFG_BYPASS__M 0x411345#define SIO_PDR_OHW_CFG_BYPASS__PRE 0x011346 11347#define SIO_PDR_OHW_CFG_ASEL__B 311348#define SIO_PDR_OHW_CFG_ASEL__W 311349#define SIO_PDR_OHW_CFG_ASEL__M 0x3811350#define SIO_PDR_OHW_CFG_ASEL__PRE 0x011351 11352#define SIO_PDR_OHW_CFG_SPEED__B 611353#define SIO_PDR_OHW_CFG_SPEED__W 111354#define SIO_PDR_OHW_CFG_SPEED__M 0x4011355#define SIO_PDR_OHW_CFG_SPEED__PRE 0x011356 11357#define SIO_PDR_I2S_WS_CFG__A 0x7F002011358#define SIO_PDR_I2S_WS_CFG__W 911359#define SIO_PDR_I2S_WS_CFG__M 0x1FF11360#define SIO_PDR_I2S_WS_CFG__PRE 0x1011361#define SIO_PDR_I2S_WS_CFG_MODE__B 011362#define SIO_PDR_I2S_WS_CFG_MODE__W 311363#define SIO_PDR_I2S_WS_CFG_MODE__M 0x711364#define SIO_PDR_I2S_WS_CFG_MODE__PRE 0x011365#define SIO_PDR_I2S_WS_CFG_DRIVE__B 311366#define SIO_PDR_I2S_WS_CFG_DRIVE__W 311367#define SIO_PDR_I2S_WS_CFG_DRIVE__M 0x3811368#define SIO_PDR_I2S_WS_CFG_DRIVE__PRE 0x1011369#define SIO_PDR_I2S_WS_CFG_KEEP__B 611370#define SIO_PDR_I2S_WS_CFG_KEEP__W 211371#define SIO_PDR_I2S_WS_CFG_KEEP__M 0xC011372#define SIO_PDR_I2S_WS_CFG_KEEP__PRE 0x011373#define SIO_PDR_I2S_WS_CFG_UIO__B 811374#define SIO_PDR_I2S_WS_CFG_UIO__W 111375#define SIO_PDR_I2S_WS_CFG_UIO__M 0x10011376#define SIO_PDR_I2S_WS_CFG_UIO__PRE 0x011377 11378#define SIO_PDR_GPIO_CFG__A 0x7F002111379#define SIO_PDR_GPIO_CFG__W 911380#define SIO_PDR_GPIO_CFG__M 0x1FF11381#define SIO_PDR_GPIO_CFG__PRE 0x1011382#define SIO_PDR_GPIO_CFG_MODE__B 011383#define SIO_PDR_GPIO_CFG_MODE__W 311384#define SIO_PDR_GPIO_CFG_MODE__M 0x711385#define SIO_PDR_GPIO_CFG_MODE__PRE 0x011386#define SIO_PDR_GPIO_CFG_DRIVE__B 311387#define SIO_PDR_GPIO_CFG_DRIVE__W 311388#define SIO_PDR_GPIO_CFG_DRIVE__M 0x3811389#define SIO_PDR_GPIO_CFG_DRIVE__PRE 0x1011390#define SIO_PDR_GPIO_CFG_KEEP__B 611391#define SIO_PDR_GPIO_CFG_KEEP__W 211392#define SIO_PDR_GPIO_CFG_KEEP__M 0xC011393#define SIO_PDR_GPIO_CFG_KEEP__PRE 0x011394#define SIO_PDR_GPIO_CFG_UIO__B 811395#define SIO_PDR_GPIO_CFG_UIO__W 111396#define SIO_PDR_GPIO_CFG_UIO__M 0x10011397#define SIO_PDR_GPIO_CFG_UIO__PRE 0x011398 11399#define SIO_PDR_IRQN_CFG__A 0x7F002211400#define SIO_PDR_IRQN_CFG__W 911401#define SIO_PDR_IRQN_CFG__M 0x1FF11402#define SIO_PDR_IRQN_CFG__PRE 0x1011403#define SIO_PDR_IRQN_CFG_MODE__B 011404#define SIO_PDR_IRQN_CFG_MODE__W 311405#define SIO_PDR_IRQN_CFG_MODE__M 0x711406#define SIO_PDR_IRQN_CFG_MODE__PRE 0x011407#define SIO_PDR_IRQN_CFG_DRIVE__B 311408#define SIO_PDR_IRQN_CFG_DRIVE__W 311409#define SIO_PDR_IRQN_CFG_DRIVE__M 0x3811410#define SIO_PDR_IRQN_CFG_DRIVE__PRE 0x1011411#define SIO_PDR_IRQN_CFG_KEEP__B 611412#define SIO_PDR_IRQN_CFG_KEEP__W 211413#define SIO_PDR_IRQN_CFG_KEEP__M 0xC011414#define SIO_PDR_IRQN_CFG_KEEP__PRE 0x011415#define SIO_PDR_IRQN_CFG_UIO__B 811416#define SIO_PDR_IRQN_CFG_UIO__W 111417#define SIO_PDR_IRQN_CFG_UIO__M 0x10011418#define SIO_PDR_IRQN_CFG_UIO__PRE 0x011419 11420#define SIO_PDR_OOB_CRX_CFG__A 0x7F002311421#define SIO_PDR_OOB_CRX_CFG__W 911422#define SIO_PDR_OOB_CRX_CFG__M 0x1FF11423#define SIO_PDR_OOB_CRX_CFG__PRE 0x1011424#define SIO_PDR_OOB_CRX_CFG_MODE__B 011425#define SIO_PDR_OOB_CRX_CFG_MODE__W 311426#define SIO_PDR_OOB_CRX_CFG_MODE__M 0x711427#define SIO_PDR_OOB_CRX_CFG_MODE__PRE 0x011428#define SIO_PDR_OOB_CRX_CFG_DRIVE__B 311429#define SIO_PDR_OOB_CRX_CFG_DRIVE__W 311430#define SIO_PDR_OOB_CRX_CFG_DRIVE__M 0x3811431#define SIO_PDR_OOB_CRX_CFG_DRIVE__PRE 0x1011432#define SIO_PDR_OOB_CRX_CFG_KEEP__B 611433#define SIO_PDR_OOB_CRX_CFG_KEEP__W 211434#define SIO_PDR_OOB_CRX_CFG_KEEP__M 0xC011435#define SIO_PDR_OOB_CRX_CFG_KEEP__PRE 0x011436#define SIO_PDR_OOB_CRX_CFG_UIO__B 811437#define SIO_PDR_OOB_CRX_CFG_UIO__W 111438#define SIO_PDR_OOB_CRX_CFG_UIO__M 0x10011439#define SIO_PDR_OOB_CRX_CFG_UIO__PRE 0x011440 11441#define SIO_PDR_OOB_DRX_CFG__A 0x7F002411442#define SIO_PDR_OOB_DRX_CFG__W 911443#define SIO_PDR_OOB_DRX_CFG__M 0x1FF11444#define SIO_PDR_OOB_DRX_CFG__PRE 0x1011445#define SIO_PDR_OOB_DRX_CFG_MODE__B 011446#define SIO_PDR_OOB_DRX_CFG_MODE__W 311447#define SIO_PDR_OOB_DRX_CFG_MODE__M 0x711448#define SIO_PDR_OOB_DRX_CFG_MODE__PRE 0x011449#define SIO_PDR_OOB_DRX_CFG_DRIVE__B 311450#define SIO_PDR_OOB_DRX_CFG_DRIVE__W 311451#define SIO_PDR_OOB_DRX_CFG_DRIVE__M 0x3811452#define SIO_PDR_OOB_DRX_CFG_DRIVE__PRE 0x1011453#define SIO_PDR_OOB_DRX_CFG_KEEP__B 611454#define SIO_PDR_OOB_DRX_CFG_KEEP__W 211455#define SIO_PDR_OOB_DRX_CFG_KEEP__M 0xC011456#define SIO_PDR_OOB_DRX_CFG_KEEP__PRE 0x011457#define SIO_PDR_OOB_DRX_CFG_UIO__B 811458#define SIO_PDR_OOB_DRX_CFG_UIO__W 111459#define SIO_PDR_OOB_DRX_CFG_UIO__M 0x10011460#define SIO_PDR_OOB_DRX_CFG_UIO__PRE 0x011461 11462#define SIO_PDR_MSTRT_CFG__A 0x7F002511463#define SIO_PDR_MSTRT_CFG__W 911464#define SIO_PDR_MSTRT_CFG__M 0x1FF11465#define SIO_PDR_MSTRT_CFG__PRE 0x5011466#define SIO_PDR_MSTRT_CFG_MODE__B 011467#define SIO_PDR_MSTRT_CFG_MODE__W 311468#define SIO_PDR_MSTRT_CFG_MODE__M 0x711469#define SIO_PDR_MSTRT_CFG_MODE__PRE 0x011470#define SIO_PDR_MSTRT_CFG_DRIVE__B 311471#define SIO_PDR_MSTRT_CFG_DRIVE__W 311472#define SIO_PDR_MSTRT_CFG_DRIVE__M 0x3811473#define SIO_PDR_MSTRT_CFG_DRIVE__PRE 0x1011474#define SIO_PDR_MSTRT_CFG_KEEP__B 611475#define SIO_PDR_MSTRT_CFG_KEEP__W 211476#define SIO_PDR_MSTRT_CFG_KEEP__M 0xC011477#define SIO_PDR_MSTRT_CFG_KEEP__PRE 0x4011478#define SIO_PDR_MSTRT_CFG_UIO__B 811479#define SIO_PDR_MSTRT_CFG_UIO__W 111480#define SIO_PDR_MSTRT_CFG_UIO__M 0x10011481#define SIO_PDR_MSTRT_CFG_UIO__PRE 0x011482 11483#define SIO_PDR_MERR_CFG__A 0x7F002611484#define SIO_PDR_MERR_CFG__W 911485#define SIO_PDR_MERR_CFG__M 0x1FF11486#define SIO_PDR_MERR_CFG__PRE 0x5011487#define SIO_PDR_MERR_CFG_MODE__B 011488#define SIO_PDR_MERR_CFG_MODE__W 311489#define SIO_PDR_MERR_CFG_MODE__M 0x711490#define SIO_PDR_MERR_CFG_MODE__PRE 0x011491#define SIO_PDR_MERR_CFG_DRIVE__B 311492#define SIO_PDR_MERR_CFG_DRIVE__W 311493#define SIO_PDR_MERR_CFG_DRIVE__M 0x3811494#define SIO_PDR_MERR_CFG_DRIVE__PRE 0x1011495#define SIO_PDR_MERR_CFG_KEEP__B 611496#define SIO_PDR_MERR_CFG_KEEP__W 211497#define SIO_PDR_MERR_CFG_KEEP__M 0xC011498#define SIO_PDR_MERR_CFG_KEEP__PRE 0x4011499#define SIO_PDR_MERR_CFG_UIO__B 811500#define SIO_PDR_MERR_CFG_UIO__W 111501#define SIO_PDR_MERR_CFG_UIO__M 0x10011502#define SIO_PDR_MERR_CFG_UIO__PRE 0x011503 11504#define SIO_PDR_MCLK_CFG__A 0x7F002811505#define SIO_PDR_MCLK_CFG__W 911506#define SIO_PDR_MCLK_CFG__M 0x1FF11507#define SIO_PDR_MCLK_CFG__PRE 0x5011508#define SIO_PDR_MCLK_CFG_MODE__B 011509#define SIO_PDR_MCLK_CFG_MODE__W 311510#define SIO_PDR_MCLK_CFG_MODE__M 0x711511#define SIO_PDR_MCLK_CFG_MODE__PRE 0x011512#define SIO_PDR_MCLK_CFG_DRIVE__B 311513#define SIO_PDR_MCLK_CFG_DRIVE__W 311514#define SIO_PDR_MCLK_CFG_DRIVE__M 0x3811515#define SIO_PDR_MCLK_CFG_DRIVE__PRE 0x1011516#define SIO_PDR_MCLK_CFG_KEEP__B 611517#define SIO_PDR_MCLK_CFG_KEEP__W 211518#define SIO_PDR_MCLK_CFG_KEEP__M 0xC011519#define SIO_PDR_MCLK_CFG_KEEP__PRE 0x4011520#define SIO_PDR_MCLK_CFG_UIO__B 811521#define SIO_PDR_MCLK_CFG_UIO__W 111522#define SIO_PDR_MCLK_CFG_UIO__M 0x10011523#define SIO_PDR_MCLK_CFG_UIO__PRE 0x011524 11525#define SIO_PDR_MVAL_CFG__A 0x7F002911526#define SIO_PDR_MVAL_CFG__W 911527#define SIO_PDR_MVAL_CFG__M 0x1FF11528#define SIO_PDR_MVAL_CFG__PRE 0x5011529#define SIO_PDR_MVAL_CFG_MODE__B 011530#define SIO_PDR_MVAL_CFG_MODE__W 311531#define SIO_PDR_MVAL_CFG_MODE__M 0x711532#define SIO_PDR_MVAL_CFG_MODE__PRE 0x011533#define SIO_PDR_MVAL_CFG_DRIVE__B 311534#define SIO_PDR_MVAL_CFG_DRIVE__W 311535#define SIO_PDR_MVAL_CFG_DRIVE__M 0x3811536#define SIO_PDR_MVAL_CFG_DRIVE__PRE 0x1011537#define SIO_PDR_MVAL_CFG_KEEP__B 611538#define SIO_PDR_MVAL_CFG_KEEP__W 211539#define SIO_PDR_MVAL_CFG_KEEP__M 0xC011540#define SIO_PDR_MVAL_CFG_KEEP__PRE 0x4011541#define SIO_PDR_MVAL_CFG_UIO__B 811542#define SIO_PDR_MVAL_CFG_UIO__W 111543#define SIO_PDR_MVAL_CFG_UIO__M 0x10011544#define SIO_PDR_MVAL_CFG_UIO__PRE 0x011545 11546#define SIO_PDR_MD0_CFG__A 0x7F002A11547#define SIO_PDR_MD0_CFG__W 911548#define SIO_PDR_MD0_CFG__M 0x1FF11549#define SIO_PDR_MD0_CFG__PRE 0x5011550#define SIO_PDR_MD0_CFG_MODE__B 011551#define SIO_PDR_MD0_CFG_MODE__W 311552#define SIO_PDR_MD0_CFG_MODE__M 0x711553#define SIO_PDR_MD0_CFG_MODE__PRE 0x011554#define SIO_PDR_MD0_CFG_DRIVE__B 311555#define SIO_PDR_MD0_CFG_DRIVE__W 311556#define SIO_PDR_MD0_CFG_DRIVE__M 0x3811557#define SIO_PDR_MD0_CFG_DRIVE__PRE 0x1011558#define SIO_PDR_MD0_CFG_KEEP__B 611559#define SIO_PDR_MD0_CFG_KEEP__W 211560#define SIO_PDR_MD0_CFG_KEEP__M 0xC011561#define SIO_PDR_MD0_CFG_KEEP__PRE 0x4011562#define SIO_PDR_MD0_CFG_UIO__B 811563#define SIO_PDR_MD0_CFG_UIO__W 111564#define SIO_PDR_MD0_CFG_UIO__M 0x10011565#define SIO_PDR_MD0_CFG_UIO__PRE 0x011566 11567#define SIO_PDR_MD1_CFG__A 0x7F002B11568#define SIO_PDR_MD1_CFG__W 911569#define SIO_PDR_MD1_CFG__M 0x1FF11570#define SIO_PDR_MD1_CFG__PRE 0x5011571#define SIO_PDR_MD1_CFG_MODE__B 011572#define SIO_PDR_MD1_CFG_MODE__W 311573#define SIO_PDR_MD1_CFG_MODE__M 0x711574#define SIO_PDR_MD1_CFG_MODE__PRE 0x011575#define SIO_PDR_MD1_CFG_DRIVE__B 311576#define SIO_PDR_MD1_CFG_DRIVE__W 311577#define SIO_PDR_MD1_CFG_DRIVE__M 0x3811578#define SIO_PDR_MD1_CFG_DRIVE__PRE 0x1011579#define SIO_PDR_MD1_CFG_KEEP__B 611580#define SIO_PDR_MD1_CFG_KEEP__W 211581#define SIO_PDR_MD1_CFG_KEEP__M 0xC011582#define SIO_PDR_MD1_CFG_KEEP__PRE 0x4011583#define SIO_PDR_MD1_CFG_UIO__B 811584#define SIO_PDR_MD1_CFG_UIO__W 111585#define SIO_PDR_MD1_CFG_UIO__M 0x10011586#define SIO_PDR_MD1_CFG_UIO__PRE 0x011587 11588#define SIO_PDR_MD2_CFG__A 0x7F002C11589#define SIO_PDR_MD2_CFG__W 911590#define SIO_PDR_MD2_CFG__M 0x1FF11591#define SIO_PDR_MD2_CFG__PRE 0x5011592#define SIO_PDR_MD2_CFG_MODE__B 011593#define SIO_PDR_MD2_CFG_MODE__W 311594#define SIO_PDR_MD2_CFG_MODE__M 0x711595#define SIO_PDR_MD2_CFG_MODE__PRE 0x011596#define SIO_PDR_MD2_CFG_DRIVE__B 311597#define SIO_PDR_MD2_CFG_DRIVE__W 311598#define SIO_PDR_MD2_CFG_DRIVE__M 0x3811599#define SIO_PDR_MD2_CFG_DRIVE__PRE 0x1011600#define SIO_PDR_MD2_CFG_KEEP__B 611601#define SIO_PDR_MD2_CFG_KEEP__W 211602#define SIO_PDR_MD2_CFG_KEEP__M 0xC011603#define SIO_PDR_MD2_CFG_KEEP__PRE 0x4011604#define SIO_PDR_MD2_CFG_UIO__B 811605#define SIO_PDR_MD2_CFG_UIO__W 111606#define SIO_PDR_MD2_CFG_UIO__M 0x10011607#define SIO_PDR_MD2_CFG_UIO__PRE 0x011608 11609#define SIO_PDR_MD3_CFG__A 0x7F002D11610#define SIO_PDR_MD3_CFG__W 911611#define SIO_PDR_MD3_CFG__M 0x1FF11612#define SIO_PDR_MD3_CFG__PRE 0x5011613#define SIO_PDR_MD3_CFG_MODE__B 011614#define SIO_PDR_MD3_CFG_MODE__W 311615#define SIO_PDR_MD3_CFG_MODE__M 0x711616#define SIO_PDR_MD3_CFG_MODE__PRE 0x011617#define SIO_PDR_MD3_CFG_DRIVE__B 311618#define SIO_PDR_MD3_CFG_DRIVE__W 311619#define SIO_PDR_MD3_CFG_DRIVE__M 0x3811620#define SIO_PDR_MD3_CFG_DRIVE__PRE 0x1011621#define SIO_PDR_MD3_CFG_KEEP__B 611622#define SIO_PDR_MD3_CFG_KEEP__W 211623#define SIO_PDR_MD3_CFG_KEEP__M 0xC011624#define SIO_PDR_MD3_CFG_KEEP__PRE 0x4011625#define SIO_PDR_MD3_CFG_UIO__B 811626#define SIO_PDR_MD3_CFG_UIO__W 111627#define SIO_PDR_MD3_CFG_UIO__M 0x10011628#define SIO_PDR_MD3_CFG_UIO__PRE 0x011629 11630#define SIO_PDR_MD4_CFG__A 0x7F002F11631#define SIO_PDR_MD4_CFG__W 911632#define SIO_PDR_MD4_CFG__M 0x1FF11633#define SIO_PDR_MD4_CFG__PRE 0x5011634#define SIO_PDR_MD4_CFG_MODE__B 011635#define SIO_PDR_MD4_CFG_MODE__W 311636#define SIO_PDR_MD4_CFG_MODE__M 0x711637#define SIO_PDR_MD4_CFG_MODE__PRE 0x011638#define SIO_PDR_MD4_CFG_DRIVE__B 311639#define SIO_PDR_MD4_CFG_DRIVE__W 311640#define SIO_PDR_MD4_CFG_DRIVE__M 0x3811641#define SIO_PDR_MD4_CFG_DRIVE__PRE 0x1011642#define SIO_PDR_MD4_CFG_KEEP__B 611643#define SIO_PDR_MD4_CFG_KEEP__W 211644#define SIO_PDR_MD4_CFG_KEEP__M 0xC011645#define SIO_PDR_MD4_CFG_KEEP__PRE 0x4011646#define SIO_PDR_MD4_CFG_UIO__B 811647#define SIO_PDR_MD4_CFG_UIO__W 111648#define SIO_PDR_MD4_CFG_UIO__M 0x10011649#define SIO_PDR_MD4_CFG_UIO__PRE 0x011650 11651#define SIO_PDR_MD5_CFG__A 0x7F003011652#define SIO_PDR_MD5_CFG__W 911653#define SIO_PDR_MD5_CFG__M 0x1FF11654#define SIO_PDR_MD5_CFG__PRE 0x5011655#define SIO_PDR_MD5_CFG_MODE__B 011656#define SIO_PDR_MD5_CFG_MODE__W 311657#define SIO_PDR_MD5_CFG_MODE__M 0x711658#define SIO_PDR_MD5_CFG_MODE__PRE 0x011659#define SIO_PDR_MD5_CFG_DRIVE__B 311660#define SIO_PDR_MD5_CFG_DRIVE__W 311661#define SIO_PDR_MD5_CFG_DRIVE__M 0x3811662#define SIO_PDR_MD5_CFG_DRIVE__PRE 0x1011663#define SIO_PDR_MD5_CFG_KEEP__B 611664#define SIO_PDR_MD5_CFG_KEEP__W 211665#define SIO_PDR_MD5_CFG_KEEP__M 0xC011666#define SIO_PDR_MD5_CFG_KEEP__PRE 0x4011667#define SIO_PDR_MD5_CFG_UIO__B 811668#define SIO_PDR_MD5_CFG_UIO__W 111669#define SIO_PDR_MD5_CFG_UIO__M 0x10011670#define SIO_PDR_MD5_CFG_UIO__PRE 0x011671 11672#define SIO_PDR_MD6_CFG__A 0x7F003111673#define SIO_PDR_MD6_CFG__W 911674#define SIO_PDR_MD6_CFG__M 0x1FF11675#define SIO_PDR_MD6_CFG__PRE 0x5011676#define SIO_PDR_MD6_CFG_MODE__B 011677#define SIO_PDR_MD6_CFG_MODE__W 311678#define SIO_PDR_MD6_CFG_MODE__M 0x711679#define SIO_PDR_MD6_CFG_MODE__PRE 0x011680#define SIO_PDR_MD6_CFG_DRIVE__B 311681#define SIO_PDR_MD6_CFG_DRIVE__W 311682#define SIO_PDR_MD6_CFG_DRIVE__M 0x3811683#define SIO_PDR_MD6_CFG_DRIVE__PRE 0x1011684#define SIO_PDR_MD6_CFG_KEEP__B 611685#define SIO_PDR_MD6_CFG_KEEP__W 211686#define SIO_PDR_MD6_CFG_KEEP__M 0xC011687#define SIO_PDR_MD6_CFG_KEEP__PRE 0x4011688#define SIO_PDR_MD6_CFG_UIO__B 811689#define SIO_PDR_MD6_CFG_UIO__W 111690#define SIO_PDR_MD6_CFG_UIO__M 0x10011691#define SIO_PDR_MD6_CFG_UIO__PRE 0x011692 11693#define SIO_PDR_MD7_CFG__A 0x7F003211694#define SIO_PDR_MD7_CFG__W 911695#define SIO_PDR_MD7_CFG__M 0x1FF11696#define SIO_PDR_MD7_CFG__PRE 0x5011697#define SIO_PDR_MD7_CFG_MODE__B 011698#define SIO_PDR_MD7_CFG_MODE__W 311699#define SIO_PDR_MD7_CFG_MODE__M 0x711700#define SIO_PDR_MD7_CFG_MODE__PRE 0x011701#define SIO_PDR_MD7_CFG_DRIVE__B 311702#define SIO_PDR_MD7_CFG_DRIVE__W 311703#define SIO_PDR_MD7_CFG_DRIVE__M 0x3811704#define SIO_PDR_MD7_CFG_DRIVE__PRE 0x1011705#define SIO_PDR_MD7_CFG_KEEP__B 611706#define SIO_PDR_MD7_CFG_KEEP__W 211707#define SIO_PDR_MD7_CFG_KEEP__M 0xC011708#define SIO_PDR_MD7_CFG_KEEP__PRE 0x4011709#define SIO_PDR_MD7_CFG_UIO__B 811710#define SIO_PDR_MD7_CFG_UIO__W 111711#define SIO_PDR_MD7_CFG_UIO__M 0x10011712#define SIO_PDR_MD7_CFG_UIO__PRE 0x011713 11714#define SIO_PDR_I2C_SCL1_CFG__A 0x7F003311715#define SIO_PDR_I2C_SCL1_CFG__W 911716#define SIO_PDR_I2C_SCL1_CFG__M 0x1FF11717#define SIO_PDR_I2C_SCL1_CFG__PRE 0x1111718#define SIO_PDR_I2C_SCL1_CFG_MODE__B 011719#define SIO_PDR_I2C_SCL1_CFG_MODE__W 311720#define SIO_PDR_I2C_SCL1_CFG_MODE__M 0x711721#define SIO_PDR_I2C_SCL1_CFG_MODE__PRE 0x111722#define SIO_PDR_I2C_SCL1_CFG_DRIVE__B 311723#define SIO_PDR_I2C_SCL1_CFG_DRIVE__W 311724#define SIO_PDR_I2C_SCL1_CFG_DRIVE__M 0x3811725#define SIO_PDR_I2C_SCL1_CFG_DRIVE__PRE 0x1011726#define SIO_PDR_I2C_SCL1_CFG_KEEP__B 611727#define SIO_PDR_I2C_SCL1_CFG_KEEP__W 211728#define SIO_PDR_I2C_SCL1_CFG_KEEP__M 0xC011729#define SIO_PDR_I2C_SCL1_CFG_KEEP__PRE 0x011730#define SIO_PDR_I2C_SCL1_CFG_UIO__B 811731#define SIO_PDR_I2C_SCL1_CFG_UIO__W 111732#define SIO_PDR_I2C_SCL1_CFG_UIO__M 0x10011733#define SIO_PDR_I2C_SCL1_CFG_UIO__PRE 0x011734 11735#define SIO_PDR_I2C_SDA1_CFG__A 0x7F003411736#define SIO_PDR_I2C_SDA1_CFG__W 911737#define SIO_PDR_I2C_SDA1_CFG__M 0x1FF11738#define SIO_PDR_I2C_SDA1_CFG__PRE 0x1111739#define SIO_PDR_I2C_SDA1_CFG_MODE__B 011740#define SIO_PDR_I2C_SDA1_CFG_MODE__W 311741#define SIO_PDR_I2C_SDA1_CFG_MODE__M 0x711742#define SIO_PDR_I2C_SDA1_CFG_MODE__PRE 0x111743#define SIO_PDR_I2C_SDA1_CFG_DRIVE__B 311744#define SIO_PDR_I2C_SDA1_CFG_DRIVE__W 311745#define SIO_PDR_I2C_SDA1_CFG_DRIVE__M 0x3811746#define SIO_PDR_I2C_SDA1_CFG_DRIVE__PRE 0x1011747#define SIO_PDR_I2C_SDA1_CFG_KEEP__B 611748#define SIO_PDR_I2C_SDA1_CFG_KEEP__W 211749#define SIO_PDR_I2C_SDA1_CFG_KEEP__M 0xC011750#define SIO_PDR_I2C_SDA1_CFG_KEEP__PRE 0x011751#define SIO_PDR_I2C_SDA1_CFG_UIO__B 811752#define SIO_PDR_I2C_SDA1_CFG_UIO__W 111753#define SIO_PDR_I2C_SDA1_CFG_UIO__M 0x10011754#define SIO_PDR_I2C_SDA1_CFG_UIO__PRE 0x011755 11756#define SIO_PDR_VSYNC_CFG__A 0x7F003611757#define SIO_PDR_VSYNC_CFG__W 911758#define SIO_PDR_VSYNC_CFG__M 0x1FF11759#define SIO_PDR_VSYNC_CFG__PRE 0x1011760#define SIO_PDR_VSYNC_CFG_MODE__B 011761#define SIO_PDR_VSYNC_CFG_MODE__W 311762#define SIO_PDR_VSYNC_CFG_MODE__M 0x711763#define SIO_PDR_VSYNC_CFG_MODE__PRE 0x011764#define SIO_PDR_VSYNC_CFG_DRIVE__B 311765#define SIO_PDR_VSYNC_CFG_DRIVE__W 311766#define SIO_PDR_VSYNC_CFG_DRIVE__M 0x3811767#define SIO_PDR_VSYNC_CFG_DRIVE__PRE 0x1011768#define SIO_PDR_VSYNC_CFG_KEEP__B 611769#define SIO_PDR_VSYNC_CFG_KEEP__W 211770#define SIO_PDR_VSYNC_CFG_KEEP__M 0xC011771#define SIO_PDR_VSYNC_CFG_KEEP__PRE 0x011772#define SIO_PDR_VSYNC_CFG_UIO__B 811773#define SIO_PDR_VSYNC_CFG_UIO__W 111774#define SIO_PDR_VSYNC_CFG_UIO__M 0x10011775#define SIO_PDR_VSYNC_CFG_UIO__PRE 0x011776 11777#define SIO_PDR_SMA_RX_CFG__A 0x7F003711778#define SIO_PDR_SMA_RX_CFG__W 911779#define SIO_PDR_SMA_RX_CFG__M 0x1FF11780#define SIO_PDR_SMA_RX_CFG__PRE 0x1011781#define SIO_PDR_SMA_RX_CFG_MODE__B 011782#define SIO_PDR_SMA_RX_CFG_MODE__W 311783#define SIO_PDR_SMA_RX_CFG_MODE__M 0x711784#define SIO_PDR_SMA_RX_CFG_MODE__PRE 0x011785#define SIO_PDR_SMA_RX_CFG_DRIVE__B 311786#define SIO_PDR_SMA_RX_CFG_DRIVE__W 311787#define SIO_PDR_SMA_RX_CFG_DRIVE__M 0x3811788#define SIO_PDR_SMA_RX_CFG_DRIVE__PRE 0x1011789#define SIO_PDR_SMA_RX_CFG_KEEP__B 611790#define SIO_PDR_SMA_RX_CFG_KEEP__W 211791#define SIO_PDR_SMA_RX_CFG_KEEP__M 0xC011792#define SIO_PDR_SMA_RX_CFG_KEEP__PRE 0x011793#define SIO_PDR_SMA_RX_CFG_UIO__B 811794#define SIO_PDR_SMA_RX_CFG_UIO__W 111795#define SIO_PDR_SMA_RX_CFG_UIO__M 0x10011796#define SIO_PDR_SMA_RX_CFG_UIO__PRE 0x011797 11798#define SIO_PDR_SMA_TX_CFG__A 0x7F003811799#define SIO_PDR_SMA_TX_CFG__W 911800#define SIO_PDR_SMA_TX_CFG__M 0x1FF11801#define SIO_PDR_SMA_TX_CFG__PRE 0x9011802#define SIO_PDR_SMA_TX_CFG_MODE__B 011803#define SIO_PDR_SMA_TX_CFG_MODE__W 311804#define SIO_PDR_SMA_TX_CFG_MODE__M 0x711805#define SIO_PDR_SMA_TX_CFG_MODE__PRE 0x011806#define SIO_PDR_SMA_TX_CFG_DRIVE__B 311807#define SIO_PDR_SMA_TX_CFG_DRIVE__W 311808#define SIO_PDR_SMA_TX_CFG_DRIVE__M 0x3811809#define SIO_PDR_SMA_TX_CFG_DRIVE__PRE 0x1011810#define SIO_PDR_SMA_TX_CFG_KEEP__B 611811#define SIO_PDR_SMA_TX_CFG_KEEP__W 211812#define SIO_PDR_SMA_TX_CFG_KEEP__M 0xC011813#define SIO_PDR_SMA_TX_CFG_KEEP__PRE 0x8011814#define SIO_PDR_SMA_TX_CFG_UIO__B 811815#define SIO_PDR_SMA_TX_CFG_UIO__W 111816#define SIO_PDR_SMA_TX_CFG_UIO__M 0x10011817#define SIO_PDR_SMA_TX_CFG_UIO__PRE 0x011818 11819#define SIO_PDR_I2C_SDA2_CFG__A 0x7F003F11820#define SIO_PDR_I2C_SDA2_CFG__W 911821#define SIO_PDR_I2C_SDA2_CFG__M 0x1FF11822#define SIO_PDR_I2C_SDA2_CFG__PRE 0x1111823#define SIO_PDR_I2C_SDA2_CFG_MODE__B 011824#define SIO_PDR_I2C_SDA2_CFG_MODE__W 311825#define SIO_PDR_I2C_SDA2_CFG_MODE__M 0x711826#define SIO_PDR_I2C_SDA2_CFG_MODE__PRE 0x111827#define SIO_PDR_I2C_SDA2_CFG_DRIVE__B 311828#define SIO_PDR_I2C_SDA2_CFG_DRIVE__W 311829#define SIO_PDR_I2C_SDA2_CFG_DRIVE__M 0x3811830#define SIO_PDR_I2C_SDA2_CFG_DRIVE__PRE 0x1011831#define SIO_PDR_I2C_SDA2_CFG_KEEP__B 611832#define SIO_PDR_I2C_SDA2_CFG_KEEP__W 211833#define SIO_PDR_I2C_SDA2_CFG_KEEP__M 0xC011834#define SIO_PDR_I2C_SDA2_CFG_KEEP__PRE 0x011835#define SIO_PDR_I2C_SDA2_CFG_UIO__B 811836#define SIO_PDR_I2C_SDA2_CFG_UIO__W 111837#define SIO_PDR_I2C_SDA2_CFG_UIO__M 0x10011838#define SIO_PDR_I2C_SDA2_CFG_UIO__PRE 0x011839 11840#define SIO_PDR_I2C_SCL2_CFG__A 0x7F004011841#define SIO_PDR_I2C_SCL2_CFG__W 911842#define SIO_PDR_I2C_SCL2_CFG__M 0x1FF11843#define SIO_PDR_I2C_SCL2_CFG__PRE 0x1111844#define SIO_PDR_I2C_SCL2_CFG_MODE__B 011845#define SIO_PDR_I2C_SCL2_CFG_MODE__W 311846#define SIO_PDR_I2C_SCL2_CFG_MODE__M 0x711847#define SIO_PDR_I2C_SCL2_CFG_MODE__PRE 0x111848#define SIO_PDR_I2C_SCL2_CFG_DRIVE__B 311849#define SIO_PDR_I2C_SCL2_CFG_DRIVE__W 311850#define SIO_PDR_I2C_SCL2_CFG_DRIVE__M 0x3811851#define SIO_PDR_I2C_SCL2_CFG_DRIVE__PRE 0x1011852#define SIO_PDR_I2C_SCL2_CFG_KEEP__B 611853#define SIO_PDR_I2C_SCL2_CFG_KEEP__W 211854#define SIO_PDR_I2C_SCL2_CFG_KEEP__M 0xC011855#define SIO_PDR_I2C_SCL2_CFG_KEEP__PRE 0x011856#define SIO_PDR_I2C_SCL2_CFG_UIO__B 811857#define SIO_PDR_I2C_SCL2_CFG_UIO__W 111858#define SIO_PDR_I2C_SCL2_CFG_UIO__M 0x10011859#define SIO_PDR_I2C_SCL2_CFG_UIO__PRE 0x011860 11861#define SIO_PDR_I2S_CL_CFG__A 0x7F004111862#define SIO_PDR_I2S_CL_CFG__W 911863#define SIO_PDR_I2S_CL_CFG__M 0x1FF11864#define SIO_PDR_I2S_CL_CFG__PRE 0x1011865#define SIO_PDR_I2S_CL_CFG_MODE__B 011866#define SIO_PDR_I2S_CL_CFG_MODE__W 311867#define SIO_PDR_I2S_CL_CFG_MODE__M 0x711868#define SIO_PDR_I2S_CL_CFG_MODE__PRE 0x011869#define SIO_PDR_I2S_CL_CFG_DRIVE__B 311870#define SIO_PDR_I2S_CL_CFG_DRIVE__W 311871#define SIO_PDR_I2S_CL_CFG_DRIVE__M 0x3811872#define SIO_PDR_I2S_CL_CFG_DRIVE__PRE 0x1011873#define SIO_PDR_I2S_CL_CFG_KEEP__B 611874#define SIO_PDR_I2S_CL_CFG_KEEP__W 211875#define SIO_PDR_I2S_CL_CFG_KEEP__M 0xC011876#define SIO_PDR_I2S_CL_CFG_KEEP__PRE 0x011877#define SIO_PDR_I2S_CL_CFG_UIO__B 811878#define SIO_PDR_I2S_CL_CFG_UIO__W 111879#define SIO_PDR_I2S_CL_CFG_UIO__M 0x10011880#define SIO_PDR_I2S_CL_CFG_UIO__PRE 0x011881 11882#define SIO_PDR_I2S_DA_CFG__A 0x7F004211883#define SIO_PDR_I2S_DA_CFG__W 911884#define SIO_PDR_I2S_DA_CFG__M 0x1FF11885#define SIO_PDR_I2S_DA_CFG__PRE 0x1011886#define SIO_PDR_I2S_DA_CFG_MODE__B 011887#define SIO_PDR_I2S_DA_CFG_MODE__W 311888#define SIO_PDR_I2S_DA_CFG_MODE__M 0x711889#define SIO_PDR_I2S_DA_CFG_MODE__PRE 0x011890#define SIO_PDR_I2S_DA_CFG_DRIVE__B 311891#define SIO_PDR_I2S_DA_CFG_DRIVE__W 311892#define SIO_PDR_I2S_DA_CFG_DRIVE__M 0x3811893#define SIO_PDR_I2S_DA_CFG_DRIVE__PRE 0x1011894#define SIO_PDR_I2S_DA_CFG_KEEP__B 611895#define SIO_PDR_I2S_DA_CFG_KEEP__W 211896#define SIO_PDR_I2S_DA_CFG_KEEP__M 0xC011897#define SIO_PDR_I2S_DA_CFG_KEEP__PRE 0x011898#define SIO_PDR_I2S_DA_CFG_UIO__B 811899#define SIO_PDR_I2S_DA_CFG_UIO__W 111900#define SIO_PDR_I2S_DA_CFG_UIO__M 0x10011901#define SIO_PDR_I2S_DA_CFG_UIO__PRE 0x011902 11903#define SIO_PDR_GPIO_GPIO_FNC__A 0x7F005011904#define SIO_PDR_GPIO_GPIO_FNC__W 211905#define SIO_PDR_GPIO_GPIO_FNC__M 0x311906#define SIO_PDR_GPIO_GPIO_FNC__PRE 0x011907#define SIO_PDR_GPIO_GPIO_FNC_SEL__B 011908#define SIO_PDR_GPIO_GPIO_FNC_SEL__W 211909#define SIO_PDR_GPIO_GPIO_FNC_SEL__M 0x311910#define SIO_PDR_GPIO_GPIO_FNC_SEL__PRE 0x011911 11912#define SIO_PDR_IRQN_GPIO_FNC__A 0x7F005111913#define SIO_PDR_IRQN_GPIO_FNC__W 211914#define SIO_PDR_IRQN_GPIO_FNC__M 0x311915#define SIO_PDR_IRQN_GPIO_FNC__PRE 0x011916#define SIO_PDR_IRQN_GPIO_FNC_SEL__B 011917#define SIO_PDR_IRQN_GPIO_FNC_SEL__W 211918#define SIO_PDR_IRQN_GPIO_FNC_SEL__M 0x311919#define SIO_PDR_IRQN_GPIO_FNC_SEL__PRE 0x011920 11921#define SIO_PDR_MSTRT_GPIO_FNC__A 0x7F005211922#define SIO_PDR_MSTRT_GPIO_FNC__W 211923#define SIO_PDR_MSTRT_GPIO_FNC__M 0x311924#define SIO_PDR_MSTRT_GPIO_FNC__PRE 0x011925#define SIO_PDR_MSTRT_GPIO_FNC_SEL__B 011926#define SIO_PDR_MSTRT_GPIO_FNC_SEL__W 211927#define SIO_PDR_MSTRT_GPIO_FNC_SEL__M 0x311928#define SIO_PDR_MSTRT_GPIO_FNC_SEL__PRE 0x011929 11930#define SIO_PDR_MERR_GPIO_FNC__A 0x7F005311931#define SIO_PDR_MERR_GPIO_FNC__W 211932#define SIO_PDR_MERR_GPIO_FNC__M 0x311933#define SIO_PDR_MERR_GPIO_FNC__PRE 0x011934#define SIO_PDR_MERR_GPIO_FNC_SEL__B 011935#define SIO_PDR_MERR_GPIO_FNC_SEL__W 211936#define SIO_PDR_MERR_GPIO_FNC_SEL__M 0x311937#define SIO_PDR_MERR_GPIO_FNC_SEL__PRE 0x011938 11939#define SIO_PDR_MCLK_GPIO_FNC__A 0x7F005411940#define SIO_PDR_MCLK_GPIO_FNC__W 211941#define SIO_PDR_MCLK_GPIO_FNC__M 0x311942#define SIO_PDR_MCLK_GPIO_FNC__PRE 0x011943#define SIO_PDR_MCLK_GPIO_FNC_SEL__B 011944#define SIO_PDR_MCLK_GPIO_FNC_SEL__W 211945#define SIO_PDR_MCLK_GPIO_FNC_SEL__M 0x311946#define SIO_PDR_MCLK_GPIO_FNC_SEL__PRE 0x011947 11948#define SIO_PDR_MVAL_GPIO_FNC__A 0x7F005511949#define SIO_PDR_MVAL_GPIO_FNC__W 211950#define SIO_PDR_MVAL_GPIO_FNC__M 0x311951#define SIO_PDR_MVAL_GPIO_FNC__PRE 0x011952#define SIO_PDR_MVAL_GPIO_FNC_SEL__B 011953#define SIO_PDR_MVAL_GPIO_FNC_SEL__W 211954#define SIO_PDR_MVAL_GPIO_FNC_SEL__M 0x311955#define SIO_PDR_MVAL_GPIO_FNC_SEL__PRE 0x011956 11957#define SIO_PDR_MD0_GPIO_FNC__A 0x7F005611958#define SIO_PDR_MD0_GPIO_FNC__W 211959#define SIO_PDR_MD0_GPIO_FNC__M 0x311960#define SIO_PDR_MD0_GPIO_FNC__PRE 0x011961#define SIO_PDR_MD0_GPIO_FNC_SEL__B 011962#define SIO_PDR_MD0_GPIO_FNC_SEL__W 211963#define SIO_PDR_MD0_GPIO_FNC_SEL__M 0x311964#define SIO_PDR_MD0_GPIO_FNC_SEL__PRE 0x011965 11966#define SIO_PDR_MD1_GPIO_FNC__A 0x7F005711967#define SIO_PDR_MD1_GPIO_FNC__W 211968#define SIO_PDR_MD1_GPIO_FNC__M 0x311969#define SIO_PDR_MD1_GPIO_FNC__PRE 0x011970#define SIO_PDR_MD1_GPIO_FNC_SEL__B 011971#define SIO_PDR_MD1_GPIO_FNC_SEL__W 211972#define SIO_PDR_MD1_GPIO_FNC_SEL__M 0x311973#define SIO_PDR_MD1_GPIO_FNC_SEL__PRE 0x011974 11975#define SIO_PDR_MD2_GPIO_FNC__A 0x7F005811976#define SIO_PDR_MD2_GPIO_FNC__W 211977#define SIO_PDR_MD2_GPIO_FNC__M 0x311978#define SIO_PDR_MD2_GPIO_FNC__PRE 0x011979#define SIO_PDR_MD2_GPIO_FNC_SEL__B 011980#define SIO_PDR_MD2_GPIO_FNC_SEL__W 211981#define SIO_PDR_MD2_GPIO_FNC_SEL__M 0x311982#define SIO_PDR_MD2_GPIO_FNC_SEL__PRE 0x011983 11984#define SIO_PDR_MD3_GPIO_FNC__A 0x7F005911985#define SIO_PDR_MD3_GPIO_FNC__W 211986#define SIO_PDR_MD3_GPIO_FNC__M 0x311987#define SIO_PDR_MD3_GPIO_FNC__PRE 0x011988#define SIO_PDR_MD3_GPIO_FNC_SEL__B 011989#define SIO_PDR_MD3_GPIO_FNC_SEL__W 211990#define SIO_PDR_MD3_GPIO_FNC_SEL__M 0x311991#define SIO_PDR_MD3_GPIO_FNC_SEL__PRE 0x011992 11993#define SIO_PDR_MD4_GPIO_FNC__A 0x7F005A11994#define SIO_PDR_MD4_GPIO_FNC__W 211995#define SIO_PDR_MD4_GPIO_FNC__M 0x311996#define SIO_PDR_MD4_GPIO_FNC__PRE 0x011997#define SIO_PDR_MD4_GPIO_FNC_SEL__B 011998#define SIO_PDR_MD4_GPIO_FNC_SEL__W 211999#define SIO_PDR_MD4_GPIO_FNC_SEL__M 0x312000#define SIO_PDR_MD4_GPIO_FNC_SEL__PRE 0x012001 12002#define SIO_PDR_MD5_GPIO_FNC__A 0x7F005B12003#define SIO_PDR_MD5_GPIO_FNC__W 212004#define SIO_PDR_MD5_GPIO_FNC__M 0x312005#define SIO_PDR_MD5_GPIO_FNC__PRE 0x012006#define SIO_PDR_MD5_GPIO_FNC_SEL__B 012007#define SIO_PDR_MD5_GPIO_FNC_SEL__W 212008#define SIO_PDR_MD5_GPIO_FNC_SEL__M 0x312009#define SIO_PDR_MD5_GPIO_FNC_SEL__PRE 0x012010 12011#define SIO_PDR_MD6_GPIO_FNC__A 0x7F005C12012#define SIO_PDR_MD6_GPIO_FNC__W 212013#define SIO_PDR_MD6_GPIO_FNC__M 0x312014#define SIO_PDR_MD6_GPIO_FNC__PRE 0x012015#define SIO_PDR_MD6_GPIO_FNC_SEL__B 012016#define SIO_PDR_MD6_GPIO_FNC_SEL__W 212017#define SIO_PDR_MD6_GPIO_FNC_SEL__M 0x312018#define SIO_PDR_MD6_GPIO_FNC_SEL__PRE 0x012019 12020#define SIO_PDR_MD7_GPIO_FNC__A 0x7F005D12021#define SIO_PDR_MD7_GPIO_FNC__W 212022#define SIO_PDR_MD7_GPIO_FNC__M 0x312023#define SIO_PDR_MD7_GPIO_FNC__PRE 0x012024#define SIO_PDR_MD7_GPIO_FNC_SEL__B 012025#define SIO_PDR_MD7_GPIO_FNC_SEL__W 212026#define SIO_PDR_MD7_GPIO_FNC_SEL__M 0x312027#define SIO_PDR_MD7_GPIO_FNC_SEL__PRE 0x012028 12029#define SIO_PDR_SMA_RX_GPIO_FNC__A 0x7F005E12030#define SIO_PDR_SMA_RX_GPIO_FNC__W 212031#define SIO_PDR_SMA_RX_GPIO_FNC__M 0x312032#define SIO_PDR_SMA_RX_GPIO_FNC__PRE 0x012033#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__B 012034#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__W 212035#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__M 0x312036#define SIO_PDR_SMA_RX_GPIO_FNC_SEL__PRE 0x012037 12038#define SIO_PDR_SMA_TX_GPIO_FNC__A 0x7F005F12039#define SIO_PDR_SMA_TX_GPIO_FNC__W 212040#define SIO_PDR_SMA_TX_GPIO_FNC__M 0x312041#define SIO_PDR_SMA_TX_GPIO_FNC__PRE 0x012042#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__B 012043#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__W 212044#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__M 0x312045#define SIO_PDR_SMA_TX_GPIO_FNC_SEL__PRE 0x012046 12047#define VSB_COMM_EXEC__A 0x1C0000012048#define VSB_COMM_EXEC__W 212049#define VSB_COMM_EXEC__M 0x312050#define VSB_COMM_EXEC__PRE 0x012051#define VSB_COMM_EXEC_STOP 0x012052#define VSB_COMM_EXEC_ACTIVE 0x112053#define VSB_COMM_EXEC_HOLD 0x212054 12055#define VSB_COMM_MB__A 0x1C0000212056#define VSB_COMM_MB__W 1612057#define VSB_COMM_MB__M 0xFFFF12058#define VSB_COMM_MB__PRE 0x012059#define VSB_COMM_INT_REQ__A 0x1C0000312060#define VSB_COMM_INT_REQ__W 112061#define VSB_COMM_INT_REQ__M 0x112062#define VSB_COMM_INT_REQ__PRE 0x012063 12064#define VSB_COMM_INT_REQ_TOP_INT_REQ__B 012065#define VSB_COMM_INT_REQ_TOP_INT_REQ__W 112066#define VSB_COMM_INT_REQ_TOP_INT_REQ__M 0x112067#define VSB_COMM_INT_REQ_TOP_INT_REQ__PRE 0x012068 12069#define VSB_COMM_INT_STA__A 0x1C0000512070#define VSB_COMM_INT_STA__W 1612071#define VSB_COMM_INT_STA__M 0xFFFF12072#define VSB_COMM_INT_STA__PRE 0x012073 12074#define VSB_COMM_INT_MSK__A 0x1C0000612075#define VSB_COMM_INT_MSK__W 1612076#define VSB_COMM_INT_MSK__M 0xFFFF12077#define VSB_COMM_INT_MSK__PRE 0x012078 12079#define VSB_COMM_INT_STM__A 0x1C0000712080#define VSB_COMM_INT_STM__W 1612081#define VSB_COMM_INT_STM__M 0xFFFF12082#define VSB_COMM_INT_STM__PRE 0x012083 12084#define VSB_TOP_COMM_EXEC__A 0x1C1000012085#define VSB_TOP_COMM_EXEC__W 212086#define VSB_TOP_COMM_EXEC__M 0x312087#define VSB_TOP_COMM_EXEC__PRE 0x012088#define VSB_TOP_COMM_EXEC_STOP 0x012089#define VSB_TOP_COMM_EXEC_ACTIVE 0x112090#define VSB_TOP_COMM_EXEC_HOLD 0x212091 12092#define VSB_TOP_COMM_MB__A 0x1C1000212093#define VSB_TOP_COMM_MB__W 1012094#define VSB_TOP_COMM_MB__M 0x3FF12095#define VSB_TOP_COMM_MB__PRE 0x012096 12097#define VSB_TOP_COMM_MB_CTL__B 012098#define VSB_TOP_COMM_MB_CTL__W 112099#define VSB_TOP_COMM_MB_CTL__M 0x112100#define VSB_TOP_COMM_MB_CTL__PRE 0x012101#define VSB_TOP_COMM_MB_CTL_CTL_OFF 0x012102#define VSB_TOP_COMM_MB_CTL_CTL_ON 0x112103 12104#define VSB_TOP_COMM_MB_OBS__B 112105#define VSB_TOP_COMM_MB_OBS__W 112106#define VSB_TOP_COMM_MB_OBS__M 0x212107#define VSB_TOP_COMM_MB_OBS__PRE 0x012108#define VSB_TOP_COMM_MB_OBS_OBS_OFF 0x012109#define VSB_TOP_COMM_MB_OBS_OBS_ON 0x212110 12111#define VSB_TOP_COMM_MB_MUX_CTL__B 212112#define VSB_TOP_COMM_MB_MUX_CTL__W 412113#define VSB_TOP_COMM_MB_MUX_CTL__M 0x3C12114#define VSB_TOP_COMM_MB_MUX_CTL__PRE 0x012115 12116#define VSB_TOP_COMM_MB_MUX_OBS__B 612117#define VSB_TOP_COMM_MB_MUX_OBS__W 412118#define VSB_TOP_COMM_MB_MUX_OBS__M 0x3C012119#define VSB_TOP_COMM_MB_MUX_OBS__PRE 0x012120#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FEC 0x012121#define VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM 0x4012122#define VSB_TOP_COMM_MB_MUX_OBS_VSB_IQM_AMPLITUDE 0x8012123#define VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_1 0xC012124#define VSB_TOP_COMM_MB_MUX_OBS_VSB_TCMEQ_2 0x10012125#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_1 0x14012126#define VSB_TOP_COMM_MB_MUX_OBS_VSB_FFE_2 0x18012127#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_1 0x1C012128#define VSB_TOP_COMM_MB_MUX_OBS_VSB_DFE_2 0x20012129 12130#define VSB_TOP_COMM_INT_REQ__A 0x1C1000312131#define VSB_TOP_COMM_INT_REQ__W 112132#define VSB_TOP_COMM_INT_REQ__M 0x112133#define VSB_TOP_COMM_INT_REQ__PRE 0x012134#define VSB_TOP_COMM_INT_STA__A 0x1C1000512135#define VSB_TOP_COMM_INT_STA__W 612136#define VSB_TOP_COMM_INT_STA__M 0x3F12137#define VSB_TOP_COMM_INT_STA__PRE 0x012138 12139#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__B 012140#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__W 112141#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__M 0x112142#define VSB_TOP_COMM_INT_STA_FIELD_INT_STA__PRE 0x012143 12144#define VSB_TOP_COMM_INT_STA_LOCK_STA__B 112145#define VSB_TOP_COMM_INT_STA_LOCK_STA__W 112146#define VSB_TOP_COMM_INT_STA_LOCK_STA__M 0x212147#define VSB_TOP_COMM_INT_STA_LOCK_STA__PRE 0x012148 12149#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__B 212150#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__W 112151#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__M 0x412152#define VSB_TOP_COMM_INT_STA_UNLOCK_STA__PRE 0x012153 12154#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__B 312155#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__W 112156#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__M 0x812157#define VSB_TOP_COMM_INT_STA_TAPREADER_STA__PRE 0x012158 12159#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__B 412160#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__W 112161#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__M 0x1012162#define VSB_TOP_COMM_INT_STA_SEGSYNCINTR_STA__PRE 0x012163 12164#define VSB_TOP_COMM_INT_STA_MERSER_STA__B 512165#define VSB_TOP_COMM_INT_STA_MERSER_STA__W 112166#define VSB_TOP_COMM_INT_STA_MERSER_STA__M 0x2012167#define VSB_TOP_COMM_INT_STA_MERSER_STA__PRE 0x012168 12169#define VSB_TOP_COMM_INT_MSK__A 0x1C1000612170#define VSB_TOP_COMM_INT_MSK__W 612171#define VSB_TOP_COMM_INT_MSK__M 0x3F12172#define VSB_TOP_COMM_INT_MSK__PRE 0x012173 12174#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__B 012175#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__W 112176#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__M 0x112177#define VSB_TOP_COMM_INT_MSK_FIELD_INT_MSK__PRE 0x012178 12179#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__B 112180#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__W 112181#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__M 0x212182#define VSB_TOP_COMM_INT_MSK_LOCK_MSK__PRE 0x012183 12184#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__B 212185#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__W 112186#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__M 0x412187#define VSB_TOP_COMM_INT_MSK_UNLOCK_MSK__PRE 0x012188 12189#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__B 312190#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__W 112191#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__M 0x812192#define VSB_TOP_COMM_INT_MSK_TAPREADER_MSK__PRE 0x012193 12194#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__B 412195#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__W 112196#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__M 0x1012197#define VSB_TOP_COMM_INT_MSK_SEGSYNCINTR_MSK__PRE 0x012198 12199#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__B 512200#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__W 112201#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__M 0x2012202#define VSB_TOP_COMM_INT_MSK_MERSER_MSK__PRE 0x012203 12204#define VSB_TOP_COMM_INT_STM__A 0x1C1000712205#define VSB_TOP_COMM_INT_STM__W 612206#define VSB_TOP_COMM_INT_STM__M 0x3F12207#define VSB_TOP_COMM_INT_STM__PRE 0x012208 12209#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__B 012210#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__W 112211#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__M 0x112212#define VSB_TOP_COMM_INT_STM_FIELD_INT_STM__PRE 0x012213 12214#define VSB_TOP_COMM_INT_STM_LOCK_STM__B 112215#define VSB_TOP_COMM_INT_STM_LOCK_STM__W 112216#define VSB_TOP_COMM_INT_STM_LOCK_STM__M 0x212217#define VSB_TOP_COMM_INT_STM_LOCK_STM__PRE 0x012218 12219#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__B 212220#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__W 112221#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__M 0x412222#define VSB_TOP_COMM_INT_STM_UNLOCK_STM__PRE 0x012223 12224#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__B 312225#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__W 112226#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__M 0x812227#define VSB_TOP_COMM_INT_STM_TAPREADER_STM__PRE 0x012228 12229#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__B 412230#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__W 112231#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__M 0x1012232#define VSB_TOP_COMM_INT_STM_SEGSYNCINTR_STM__PRE 0x012233 12234#define VSB_TOP_COMM_INT_STM_MERSER_STM__B 512235#define VSB_TOP_COMM_INT_STM_MERSER_STM__W 112236#define VSB_TOP_COMM_INT_STM_MERSER_STM__M 0x2012237#define VSB_TOP_COMM_INT_STM_MERSER_STM__PRE 0x012238 12239#define VSB_TOP_CKGN1ACQ__A 0x1C1001012240#define VSB_TOP_CKGN1ACQ__W 812241#define VSB_TOP_CKGN1ACQ__M 0xFF12242#define VSB_TOP_CKGN1ACQ__PRE 0x412243 12244#define VSB_TOP_CKGN1TRK__A 0x1C1001112245#define VSB_TOP_CKGN1TRK__W 812246#define VSB_TOP_CKGN1TRK__M 0xFF12247#define VSB_TOP_CKGN1TRK__PRE 0x012248 12249#define VSB_TOP_CKGN2ACQ__A 0x1C1001212250#define VSB_TOP_CKGN2ACQ__W 812251#define VSB_TOP_CKGN2ACQ__M 0xFF12252#define VSB_TOP_CKGN2ACQ__PRE 0x212253 12254#define VSB_TOP_CKGN2TRK__A 0x1C1001312255#define VSB_TOP_CKGN2TRK__W 812256#define VSB_TOP_CKGN2TRK__M 0xFF12257#define VSB_TOP_CKGN2TRK__PRE 0x112258 12259#define VSB_TOP_CKGN3__A 0x1C1001412260#define VSB_TOP_CKGN3__W 812261#define VSB_TOP_CKGN3__M 0xFF12262#define VSB_TOP_CKGN3__PRE 0x512263 12264#define VSB_TOP_CYGN1ACQ__A 0x1C1001512265#define VSB_TOP_CYGN1ACQ__W 812266#define VSB_TOP_CYGN1ACQ__M 0xFF12267#define VSB_TOP_CYGN1ACQ__PRE 0x312268 12269#define VSB_TOP_CYGN1TRK__A 0x1C1001612270#define VSB_TOP_CYGN1TRK__W 812271#define VSB_TOP_CYGN1TRK__M 0xFF12272#define VSB_TOP_CYGN1TRK__PRE 0x012273 12274#define VSB_TOP_CYGN2ACQ__A 0x1C1001712275#define VSB_TOP_CYGN2ACQ__W 812276#define VSB_TOP_CYGN2ACQ__M 0xFF12277#define VSB_TOP_CYGN2ACQ__PRE 0x312278 12279#define VSB_TOP_CYGN2TRK__A 0x1C1001812280#define VSB_TOP_CYGN2TRK__W 812281#define VSB_TOP_CYGN2TRK__M 0xFF12282#define VSB_TOP_CYGN2TRK__PRE 0x212283 12284#define VSB_TOP_CYGN3__A 0x1C1001912285#define VSB_TOP_CYGN3__W 812286#define VSB_TOP_CYGN3__M 0xFF12287#define VSB_TOP_CYGN3__PRE 0x612288#define VSB_TOP_SYNCCTRLWORD__A 0x1C1001A12289#define VSB_TOP_SYNCCTRLWORD__W 512290#define VSB_TOP_SYNCCTRLWORD__M 0x1F12291#define VSB_TOP_SYNCCTRLWORD__PRE 0x012292 12293#define VSB_TOP_SYNCCTRLWORD_PRST__B 012294#define VSB_TOP_SYNCCTRLWORD_PRST__W 112295#define VSB_TOP_SYNCCTRLWORD_PRST__M 0x112296#define VSB_TOP_SYNCCTRLWORD_PRST__PRE 0x012297 12298#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__B 112299#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__W 112300#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__M 0x212301#define VSB_TOP_SYNCCTRLWORD_DCFREEZ__PRE 0x012302 12303#define VSB_TOP_SYNCCTRLWORD_INVCNST__B 212304#define VSB_TOP_SYNCCTRLWORD_INVCNST__W 112305#define VSB_TOP_SYNCCTRLWORD_INVCNST__M 0x412306#define VSB_TOP_SYNCCTRLWORD_INVCNST__PRE 0x012307 12308#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__B 312309#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__W 112310#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__M 0x812311#define VSB_TOP_SYNCCTRLWORD_CPUAGCRST__PRE 0x012312 12313#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__B 412314#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__W 112315#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__M 0x1012316#define VSB_TOP_SYNCCTRLWORD_AGCIGNOREFS__PRE 0x012317 12318#define VSB_TOP_MAINSMUP__A 0x1C1001B12319#define VSB_TOP_MAINSMUP__W 812320#define VSB_TOP_MAINSMUP__M 0xFF12321#define VSB_TOP_MAINSMUP__PRE 0xFF12322 12323#define VSB_TOP_EQSMUP__A 0x1C1001C12324#define VSB_TOP_EQSMUP__W 812325#define VSB_TOP_EQSMUP__M 0xFF12326#define VSB_TOP_EQSMUP__PRE 0xFF12327#define VSB_TOP_SYSMUXCTRL__A 0x1C1001D12328#define VSB_TOP_SYSMUXCTRL__W 1312329#define VSB_TOP_SYSMUXCTRL__M 0x1FFF12330#define VSB_TOP_SYSMUXCTRL__PRE 0x012331 12332#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__B 012333#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__W 112334#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__M 0x112335#define VSB_TOP_SYSMUXCTRL_CYLK_STATIC__PRE 0x012336 12337#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__B 112338#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__W 112339#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__M 0x212340#define VSB_TOP_SYSMUXCTRL_CYLK_SEL_STATIC__PRE 0x012341 12342#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__B 212343#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__W 112344#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__M 0x412345#define VSB_TOP_SYSMUXCTRL_CTCALDONE_STATIC__PRE 0x012346 12347#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__B 312348#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__W 112349#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__M 0x812350#define VSB_TOP_SYSMUXCTRL_CTCALDONE_SEL_STATIC__PRE 0x012351 12352#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__B 412353#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__W 112354#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__M 0x1012355#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_STATIC__PRE 0x012356 12357#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__B 512358#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__W 112359#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__M 0x2012360#define VSB_TOP_SYSMUXCTRL_FRAMELOCK_SEL_STATIC__PRE 0x012361 12362#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__B 612363#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__W 112364#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__M 0x4012365#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_STATIC__PRE 0x012366 12367#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__B 712368#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__W 112369#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__M 0x8012370#define VSB_TOP_SYSMUXCTRL_FRAMESYNC_SEL_STATIC__PRE 0x012371 12372#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__B 812373#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__W 412374#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__M 0xF0012375#define VSB_TOP_SYSMUXCTRL_SNROVTH_STATIC__PRE 0x012376 12377#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__B 1212378#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__W 112379#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__M 0x100012380#define VSB_TOP_SYSMUXCTRL_SNROVTH_SEL_STATIC__PRE 0x012381 12382#define VSB_TOP_SNRTH_RCA1__A 0x1C1001E12383#define VSB_TOP_SNRTH_RCA1__W 812384#define VSB_TOP_SNRTH_RCA1__M 0xFF12385#define VSB_TOP_SNRTH_RCA1__PRE 0x5312386 12387#define VSB_TOP_SNRTH_RCA1_DN__B 012388#define VSB_TOP_SNRTH_RCA1_DN__W 412389#define VSB_TOP_SNRTH_RCA1_DN__M 0xF12390#define VSB_TOP_SNRTH_RCA1_DN__PRE 0x312391 12392#define VSB_TOP_SNRTH_RCA1_UP__B 412393#define VSB_TOP_SNRTH_RCA1_UP__W 412394#define VSB_TOP_SNRTH_RCA1_UP__M 0xF012395#define VSB_TOP_SNRTH_RCA1_UP__PRE 0x5012396 12397#define VSB_TOP_SNRTH_RCA2__A 0x1C1001F12398#define VSB_TOP_SNRTH_RCA2__W 812399#define VSB_TOP_SNRTH_RCA2__M 0xFF12400#define VSB_TOP_SNRTH_RCA2__PRE 0x7512401 12402#define VSB_TOP_SNRTH_RCA2_DN__B 012403#define VSB_TOP_SNRTH_RCA2_DN__W 412404#define VSB_TOP_SNRTH_RCA2_DN__M 0xF12405#define VSB_TOP_SNRTH_RCA2_DN__PRE 0x512406 12407#define VSB_TOP_SNRTH_RCA2_UP__B 412408#define VSB_TOP_SNRTH_RCA2_UP__W 412409#define VSB_TOP_SNRTH_RCA2_UP__M 0xF012410#define VSB_TOP_SNRTH_RCA2_UP__PRE 0x7012411 12412#define VSB_TOP_SNRTH_DDM1__A 0x1C1002012413#define VSB_TOP_SNRTH_DDM1__W 812414#define VSB_TOP_SNRTH_DDM1__M 0xFF12415#define VSB_TOP_SNRTH_DDM1__PRE 0xCA12416 12417#define VSB_TOP_SNRTH_DDM1_DN__B 012418#define VSB_TOP_SNRTH_DDM1_DN__W 412419#define VSB_TOP_SNRTH_DDM1_DN__M 0xF12420#define VSB_TOP_SNRTH_DDM1_DN__PRE 0xA12421 12422#define VSB_TOP_SNRTH_DDM1_UP__B 412423#define VSB_TOP_SNRTH_DDM1_UP__W 412424#define VSB_TOP_SNRTH_DDM1_UP__M 0xF012425#define VSB_TOP_SNRTH_DDM1_UP__PRE 0xC012426 12427#define VSB_TOP_SNRTH_DDM2__A 0x1C1002112428#define VSB_TOP_SNRTH_DDM2__W 812429#define VSB_TOP_SNRTH_DDM2__M 0xFF12430#define VSB_TOP_SNRTH_DDM2__PRE 0xCA12431 12432#define VSB_TOP_SNRTH_DDM2_DN__B 012433#define VSB_TOP_SNRTH_DDM2_DN__W 412434#define VSB_TOP_SNRTH_DDM2_DN__M 0xF12435#define VSB_TOP_SNRTH_DDM2_DN__PRE 0xA12436 12437#define VSB_TOP_SNRTH_DDM2_UP__B 412438#define VSB_TOP_SNRTH_DDM2_UP__W 412439#define VSB_TOP_SNRTH_DDM2_UP__M 0xF012440#define VSB_TOP_SNRTH_DDM2_UP__PRE 0xC012441 12442#define VSB_TOP_SNRTH_PT__A 0x1C1002212443#define VSB_TOP_SNRTH_PT__W 812444#define VSB_TOP_SNRTH_PT__M 0xFF12445#define VSB_TOP_SNRTH_PT__PRE 0xD812446 12447#define VSB_TOP_SNRTH_PT_DN__B 012448#define VSB_TOP_SNRTH_PT_DN__W 412449#define VSB_TOP_SNRTH_PT_DN__M 0xF12450#define VSB_TOP_SNRTH_PT_DN__PRE 0x812451 12452#define VSB_TOP_SNRTH_PT_UP__B 412453#define VSB_TOP_SNRTH_PT_UP__W 412454#define VSB_TOP_SNRTH_PT_UP__M 0xF012455#define VSB_TOP_SNRTH_PT_UP__PRE 0xD012456 12457#define VSB_TOP_CYSMSTATES__A 0x1C1002312458#define VSB_TOP_CYSMSTATES__W 812459#define VSB_TOP_CYSMSTATES__M 0xFF12460#define VSB_TOP_CYSMSTATES__PRE 0x012461 12462#define VSB_TOP_CYSMSTATES_SYSST__B 012463#define VSB_TOP_CYSMSTATES_SYSST__W 412464#define VSB_TOP_CYSMSTATES_SYSST__M 0xF12465#define VSB_TOP_CYSMSTATES_SYSST__PRE 0x012466 12467#define VSB_TOP_CYSMSTATES_EQST__B 412468#define VSB_TOP_CYSMSTATES_EQST__W 412469#define VSB_TOP_CYSMSTATES_EQST__M 0xF012470#define VSB_TOP_CYSMSTATES_EQST__PRE 0x012471 12472#define VSB_TOP_SMALL_NOTCH_CONTROL__A 0x1C1002412473#define VSB_TOP_SMALL_NOTCH_CONTROL__W 812474#define VSB_TOP_SMALL_NOTCH_CONTROL__M 0xFF12475#define VSB_TOP_SMALL_NOTCH_CONTROL__PRE 0x012476 12477#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__B 012478#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__W 112479#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__M 0x112480#define VSB_TOP_SMALL_NOTCH_CONTROL_GO__PRE 0x012481 12482#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__B 112483#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__W 112484#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__M 0x212485#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS1__PRE 0x012486 12487#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__B 212488#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__W 112489#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__M 0x412490#define VSB_TOP_SMALL_NOTCH_CONTROL_BYPASS2__PRE 0x012491 12492#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__B 312493#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__W 412494#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__M 0x7812495#define VSB_TOP_SMALL_NOTCH_CONTROL_SPARE__PRE 0x012496 12497#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__B 712498#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__W 112499#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__M 0x8012500#define VSB_TOP_SMALL_NOTCH_CONTROL_SOFT_RESET__PRE 0x012501 12502#define VSB_TOP_TAPREADCYC__A 0x1C1002512503#define VSB_TOP_TAPREADCYC__W 912504#define VSB_TOP_TAPREADCYC__M 0x1FF12505#define VSB_TOP_TAPREADCYC__PRE 0x112506 12507#define VSB_TOP_VALIDPKLVL__A 0x1C1002612508#define VSB_TOP_VALIDPKLVL__W 1312509#define VSB_TOP_VALIDPKLVL__M 0x1FFF12510#define VSB_TOP_VALIDPKLVL__PRE 0x10012511 12512#define VSB_TOP_CENTROID_FINE_DELAY__A 0x1C1002712513#define VSB_TOP_CENTROID_FINE_DELAY__W 1012514#define VSB_TOP_CENTROID_FINE_DELAY__M 0x3FF12515#define VSB_TOP_CENTROID_FINE_DELAY__PRE 0xFF12516 12517#define VSB_TOP_CENTROID_SMACH_DELAY__A 0x1C1002812518#define VSB_TOP_CENTROID_SMACH_DELAY__W 1012519#define VSB_TOP_CENTROID_SMACH_DELAY__M 0x3FF12520#define VSB_TOP_CENTROID_SMACH_DELAY__PRE 0x1FF12521 12522#define VSB_TOP_SNR__A 0x1C1002912523#define VSB_TOP_SNR__W 1412524#define VSB_TOP_SNR__M 0x3FFF12525#define VSB_TOP_SNR__PRE 0x012526#define VSB_TOP_LOCKSTATUS__A 0x1C1002A12527#define VSB_TOP_LOCKSTATUS__W 712528#define VSB_TOP_LOCKSTATUS__M 0x7F12529#define VSB_TOP_LOCKSTATUS__PRE 0x012530 12531#define VSB_TOP_LOCKSTATUS_VSBMODE__B 012532#define VSB_TOP_LOCKSTATUS_VSBMODE__W 412533#define VSB_TOP_LOCKSTATUS_VSBMODE__M 0xF12534#define VSB_TOP_LOCKSTATUS_VSBMODE__PRE 0x012535 12536#define VSB_TOP_LOCKSTATUS_FRMLOCK__B 412537#define VSB_TOP_LOCKSTATUS_FRMLOCK__W 112538#define VSB_TOP_LOCKSTATUS_FRMLOCK__M 0x1012539#define VSB_TOP_LOCKSTATUS_FRMLOCK__PRE 0x012540 12541#define VSB_TOP_LOCKSTATUS_CYLOCK__B 512542#define VSB_TOP_LOCKSTATUS_CYLOCK__W 112543#define VSB_TOP_LOCKSTATUS_CYLOCK__M 0x2012544#define VSB_TOP_LOCKSTATUS_CYLOCK__PRE 0x012545 12546#define VSB_TOP_LOCKSTATUS_DDMON__B 612547#define VSB_TOP_LOCKSTATUS_DDMON__W 112548#define VSB_TOP_LOCKSTATUS_DDMON__M 0x4012549#define VSB_TOP_LOCKSTATUS_DDMON__PRE 0x012550 12551#define VSB_TOP_CTST__A 0x1C1002B12552#define VSB_TOP_CTST__W 412553#define VSB_TOP_CTST__M 0xF12554#define VSB_TOP_CTST__PRE 0x012555#define VSB_TOP_EQSMRSTCTRL__A 0x1C1002C12556#define VSB_TOP_EQSMRSTCTRL__W 712557#define VSB_TOP_EQSMRSTCTRL__M 0x7F12558#define VSB_TOP_EQSMRSTCTRL__PRE 0x012559 12560#define VSB_TOP_EQSMRSTCTRL_RCAON__B 012561#define VSB_TOP_EQSMRSTCTRL_RCAON__W 112562#define VSB_TOP_EQSMRSTCTRL_RCAON__M 0x112563#define VSB_TOP_EQSMRSTCTRL_RCAON__PRE 0x012564 12565#define VSB_TOP_EQSMRSTCTRL_DFEON__B 112566#define VSB_TOP_EQSMRSTCTRL_DFEON__W 112567#define VSB_TOP_EQSMRSTCTRL_DFEON__M 0x212568#define VSB_TOP_EQSMRSTCTRL_DFEON__PRE 0x012569 12570#define VSB_TOP_EQSMRSTCTRL_DDMEN1__B 212571#define VSB_TOP_EQSMRSTCTRL_DDMEN1__W 112572#define VSB_TOP_EQSMRSTCTRL_DDMEN1__M 0x412573#define VSB_TOP_EQSMRSTCTRL_DDMEN1__PRE 0x012574 12575#define VSB_TOP_EQSMRSTCTRL_DDMEN2__B 312576#define VSB_TOP_EQSMRSTCTRL_DDMEN2__W 112577#define VSB_TOP_EQSMRSTCTRL_DDMEN2__M 0x812578#define VSB_TOP_EQSMRSTCTRL_DDMEN2__PRE 0x012579 12580#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__B 412581#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__W 112582#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__M 0x1012583#define VSB_TOP_EQSMRSTCTRL_DIGIAGCON__PRE 0x012584 12585#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__B 512586#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__W 112587#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__M 0x2012588#define VSB_TOP_EQSMRSTCTRL_PARAINITEN__PRE 0x012589 12590#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__B 612591#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__W 112592#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__M 0x4012593#define VSB_TOP_EQSMRSTCTRL_TIMEOUTFRMCNTEN__PRE 0x012594 12595#define VSB_TOP_EQSMTRNCTRL__A 0x1C1002D12596#define VSB_TOP_EQSMTRNCTRL__W 712597#define VSB_TOP_EQSMTRNCTRL__M 0x7F12598#define VSB_TOP_EQSMTRNCTRL__PRE 0x4012599 12600#define VSB_TOP_EQSMTRNCTRL_RCAON__B 012601#define VSB_TOP_EQSMTRNCTRL_RCAON__W 112602#define VSB_TOP_EQSMTRNCTRL_RCAON__M 0x112603#define VSB_TOP_EQSMTRNCTRL_RCAON__PRE 0x012604 12605#define VSB_TOP_EQSMTRNCTRL_DFEON__B 112606#define VSB_TOP_EQSMTRNCTRL_DFEON__W 112607#define VSB_TOP_EQSMTRNCTRL_DFEON__M 0x212608#define VSB_TOP_EQSMTRNCTRL_DFEON__PRE 0x012609 12610#define VSB_TOP_EQSMTRNCTRL_DDMEN1__B 212611#define VSB_TOP_EQSMTRNCTRL_DDMEN1__W 112612#define VSB_TOP_EQSMTRNCTRL_DDMEN1__M 0x412613#define VSB_TOP_EQSMTRNCTRL_DDMEN1__PRE 0x012614 12615#define VSB_TOP_EQSMTRNCTRL_DDMEN2__B 312616#define VSB_TOP_EQSMTRNCTRL_DDMEN2__W 112617#define VSB_TOP_EQSMTRNCTRL_DDMEN2__M 0x812618#define VSB_TOP_EQSMTRNCTRL_DDMEN2__PRE 0x012619 12620#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__B 412621#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__W 112622#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__M 0x1012623#define VSB_TOP_EQSMTRNCTRL_DIGIAGCON__PRE 0x012624 12625#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__B 512626#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__W 112627#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__M 0x2012628#define VSB_TOP_EQSMTRNCTRL_PARAINITEN__PRE 0x012629 12630#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__B 612631#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__W 112632#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__M 0x4012633#define VSB_TOP_EQSMTRNCTRL_TIMEOUTFRMCNTEN__PRE 0x4012634 12635#define VSB_TOP_EQSMRCA1CTRL__A 0x1C1002E12636#define VSB_TOP_EQSMRCA1CTRL__W 712637#define VSB_TOP_EQSMRCA1CTRL__M 0x7F12638#define VSB_TOP_EQSMRCA1CTRL__PRE 0x112639 12640#define VSB_TOP_EQSMRCA1CTRL_RCAON__B 012641#define VSB_TOP_EQSMRCA1CTRL_RCAON__W 112642#define VSB_TOP_EQSMRCA1CTRL_RCAON__M 0x112643#define VSB_TOP_EQSMRCA1CTRL_RCAON__PRE 0x112644 12645#define VSB_TOP_EQSMRCA1CTRL_DFEON__B 112646#define VSB_TOP_EQSMRCA1CTRL_DFEON__W 112647#define VSB_TOP_EQSMRCA1CTRL_DFEON__M 0x212648#define VSB_TOP_EQSMRCA1CTRL_DFEON__PRE 0x012649 12650#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__B 212651#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__W 112652#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__M 0x412653#define VSB_TOP_EQSMRCA1CTRL_DDMEN1__PRE 0x012654 12655#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__B 312656#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__W 112657#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__M 0x812658#define VSB_TOP_EQSMRCA1CTRL_DDMEN2__PRE 0x012659 12660#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__B 412661#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__W 112662#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__M 0x1012663#define VSB_TOP_EQSMRCA1CTRL_DIGIAGCON__PRE 0x012664 12665#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__B 512666#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__W 112667#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__M 0x2012668#define VSB_TOP_EQSMRCA1CTRL_PARAINITEN__PRE 0x012669 12670#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__B 612671#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__W 112672#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__M 0x4012673#define VSB_TOP_EQSMRCA1CTRL_TIMEOUTFRMCNTEN__PRE 0x012674 12675#define VSB_TOP_EQSMRCA2CTRL__A 0x1C1002F12676#define VSB_TOP_EQSMRCA2CTRL__W 712677#define VSB_TOP_EQSMRCA2CTRL__M 0x7F12678#define VSB_TOP_EQSMRCA2CTRL__PRE 0x312679 12680#define VSB_TOP_EQSMRCA2CTRL_RCAON__B 012681#define VSB_TOP_EQSMRCA2CTRL_RCAON__W 112682#define VSB_TOP_EQSMRCA2CTRL_RCAON__M 0x112683#define VSB_TOP_EQSMRCA2CTRL_RCAON__PRE 0x112684 12685#define VSB_TOP_EQSMRCA2CTRL_DFEON__B 112686#define VSB_TOP_EQSMRCA2CTRL_DFEON__W 112687#define VSB_TOP_EQSMRCA2CTRL_DFEON__M 0x212688#define VSB_TOP_EQSMRCA2CTRL_DFEON__PRE 0x212689 12690#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__B 212691#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__W 112692#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__M 0x412693#define VSB_TOP_EQSMRCA2CTRL_DDMEN1__PRE 0x012694 12695#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__B 312696#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__W 112697#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__M 0x812698#define VSB_TOP_EQSMRCA2CTRL_DDMEN2__PRE 0x012699 12700#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__B 412701#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__W 112702#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__M 0x1012703#define VSB_TOP_EQSMRCA2CTRL_DIGIAGCON__PRE 0x012704 12705#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__B 512706#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__W 112707#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__M 0x2012708#define VSB_TOP_EQSMRCA2CTRL_PARAINITEN__PRE 0x012709 12710#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__B 612711#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__W 112712#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__M 0x4012713#define VSB_TOP_EQSMRCA2CTRL_TIMEOUTFRMCNTEN__PRE 0x012714 12715#define VSB_TOP_EQSMDDM1CTRL__A 0x1C1003012716#define VSB_TOP_EQSMDDM1CTRL__W 712717#define VSB_TOP_EQSMDDM1CTRL__M 0x7F12718#define VSB_TOP_EQSMDDM1CTRL__PRE 0x612719 12720#define VSB_TOP_EQSMDDM1CTRL_RCAON__B 012721#define VSB_TOP_EQSMDDM1CTRL_RCAON__W 112722#define VSB_TOP_EQSMDDM1CTRL_RCAON__M 0x112723#define VSB_TOP_EQSMDDM1CTRL_RCAON__PRE 0x012724 12725#define VSB_TOP_EQSMDDM1CTRL_DFEON__B 112726#define VSB_TOP_EQSMDDM1CTRL_DFEON__W 112727#define VSB_TOP_EQSMDDM1CTRL_DFEON__M 0x212728#define VSB_TOP_EQSMDDM1CTRL_DFEON__PRE 0x212729 12730#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__B 212731#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__W 112732#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__M 0x412733#define VSB_TOP_EQSMDDM1CTRL_DDMEN1__PRE 0x412734 12735#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__B 312736#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__W 112737#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__M 0x812738#define VSB_TOP_EQSMDDM1CTRL_DDMEN2__PRE 0x012739 12740#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__B 412741#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__W 112742#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__M 0x1012743#define VSB_TOP_EQSMDDM1CTRL_DIGIAGCON__PRE 0x012744 12745#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__B 512746#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__W 112747#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__M 0x2012748#define VSB_TOP_EQSMDDM1CTRL_PARAINITEN__PRE 0x012749 12750#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__B 612751#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__W 112752#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__M 0x4012753#define VSB_TOP_EQSMDDM1CTRL_TIMEOUTFRMCNTEN__PRE 0x012754 12755#define VSB_TOP_EQSMDDM2CTRL__A 0x1C1003112756#define VSB_TOP_EQSMDDM2CTRL__W 712757#define VSB_TOP_EQSMDDM2CTRL__M 0x7F12758#define VSB_TOP_EQSMDDM2CTRL__PRE 0x1E12759 12760#define VSB_TOP_EQSMDDM2CTRL_RCAON__B 012761#define VSB_TOP_EQSMDDM2CTRL_RCAON__W 112762#define VSB_TOP_EQSMDDM2CTRL_RCAON__M 0x112763#define VSB_TOP_EQSMDDM2CTRL_RCAON__PRE 0x012764 12765#define VSB_TOP_EQSMDDM2CTRL_DFEON__B 112766#define VSB_TOP_EQSMDDM2CTRL_DFEON__W 112767#define VSB_TOP_EQSMDDM2CTRL_DFEON__M 0x212768#define VSB_TOP_EQSMDDM2CTRL_DFEON__PRE 0x212769 12770#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__B 212771#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__W 112772#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__M 0x412773#define VSB_TOP_EQSMDDM2CTRL_DDMEN1__PRE 0x412774 12775#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__B 312776#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__W 112777#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__M 0x812778#define VSB_TOP_EQSMDDM2CTRL_DDMEN2__PRE 0x812779 12780#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__B 412781#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__W 112782#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__M 0x1012783#define VSB_TOP_EQSMDDM2CTRL_DIGIAGCON__PRE 0x1012784 12785#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__B 512786#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__W 112787#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__M 0x2012788#define VSB_TOP_EQSMDDM2CTRL_PARAINITEN__PRE 0x012789 12790#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__B 612791#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__W 112792#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__M 0x4012793#define VSB_TOP_EQSMDDM2CTRL_TIMEOUTFRMCNTEN__PRE 0x012794 12795#define VSB_TOP_SYSSMRSTCTRL__A 0x1C1003212796#define VSB_TOP_SYSSMRSTCTRL__W 1112797#define VSB_TOP_SYSSMRSTCTRL__M 0x7FF12798#define VSB_TOP_SYSSMRSTCTRL__PRE 0x7F912799 12800#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__B 012801#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__W 112802#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__M 0x112803#define VSB_TOP_SYSSMRSTCTRL_RSTCTCAL__PRE 0x112804 12805#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__B 112806#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__W 112807#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__M 0x212808#define VSB_TOP_SYSSMRSTCTRL_CTCALEN__PRE 0x012809 12810#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__B 212811#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__W 112812#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__M 0x412813#define VSB_TOP_SYSSMRSTCTRL_STARTTRN__PRE 0x012814 12815#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__B 312816#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__W 112817#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__M 0x812818#define VSB_TOP_SYSSMRSTCTRL_RSTFRMSYNCDET__PRE 0x812819 12820#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__B 412821#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__W 112822#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__M 0x1012823#define VSB_TOP_SYSSMRSTCTRL_RSTCYDET__PRE 0x1012824 12825#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__B 512826#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__W 112827#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__M 0x2012828#define VSB_TOP_SYSSMRSTCTRL_RSTDCRMV__PRE 0x2012829 12830#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__B 612831#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__W 112832#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__M 0x4012833#define VSB_TOP_SYSSMRSTCTRL_RSTEQSIG__PRE 0x4012834 12835#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__B 712836#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__W 112837#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__M 0x8012838#define VSB_TOP_SYSSMRSTCTRL_CKFRZ__PRE 0x8012839 12840#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__B 812841#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__W 112842#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__M 0x10012843#define VSB_TOP_SYSSMRSTCTRL_CKBWSW__PRE 0x10012844 12845#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__B 912846#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__W 112847#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__M 0x20012848#define VSB_TOP_SYSSMRSTCTRL_NCOBWSW__PRE 0x20012849 12850#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__B 1012851#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__W 112852#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__M 0x40012853#define VSB_TOP_SYSSMRSTCTRL_NCOTIMEOUTCNTEN__PRE 0x40012854 12855#define VSB_TOP_SYSSMCYCTRL__A 0x1C1003312856#define VSB_TOP_SYSSMCYCTRL__W 1112857#define VSB_TOP_SYSSMCYCTRL__M 0x7FF12858#define VSB_TOP_SYSSMCYCTRL__PRE 0x4E912859 12860#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__B 012861#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__W 112862#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__M 0x112863#define VSB_TOP_SYSSMCYCTRL_RSTCTCAL__PRE 0x112864 12865#define VSB_TOP_SYSSMCYCTRL_CTCALEN__B 112866#define VSB_TOP_SYSSMCYCTRL_CTCALEN__W 112867#define VSB_TOP_SYSSMCYCTRL_CTCALEN__M 0x212868#define VSB_TOP_SYSSMCYCTRL_CTCALEN__PRE 0x012869 12870#define VSB_TOP_SYSSMCYCTRL_STARTTRN__B 212871#define VSB_TOP_SYSSMCYCTRL_STARTTRN__W 112872#define VSB_TOP_SYSSMCYCTRL_STARTTRN__M 0x412873#define VSB_TOP_SYSSMCYCTRL_STARTTRN__PRE 0x012874 12875#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__B 312876#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__W 112877#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__M 0x812878#define VSB_TOP_SYSSMCYCTRL_RSTFRMSYNCDET__PRE 0x812879 12880#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__B 412881#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__W 112882#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__M 0x1012883#define VSB_TOP_SYSSMCYCTRL_RSTCYDET__PRE 0x012884 12885#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__B 512886#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__W 112887#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__M 0x2012888#define VSB_TOP_SYSSMCYCTRL_RSTDCRMV__PRE 0x2012889 12890#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__B 612891#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__W 112892#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__M 0x4012893#define VSB_TOP_SYSSMCYCTRL_RSTEQSIG__PRE 0x4012894 12895#define VSB_TOP_SYSSMCYCTRL_CKFRZ__B 712896#define VSB_TOP_SYSSMCYCTRL_CKFRZ__W 112897#define VSB_TOP_SYSSMCYCTRL_CKFRZ__M 0x8012898#define VSB_TOP_SYSSMCYCTRL_CKFRZ__PRE 0x8012899 12900#define VSB_TOP_SYSSMCYCTRL_CKBWSW__B 812901#define VSB_TOP_SYSSMCYCTRL_CKBWSW__W 112902#define VSB_TOP_SYSSMCYCTRL_CKBWSW__M 0x10012903#define VSB_TOP_SYSSMCYCTRL_CKBWSW__PRE 0x012904 12905#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__B 912906#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__W 112907#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__M 0x20012908#define VSB_TOP_SYSSMCYCTRL_NCOBWSW__PRE 0x012909 12910#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__B 1012911#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__W 112912#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__M 0x40012913#define VSB_TOP_SYSSMCYCTRL_NCOTIMEOUTCNTEN__PRE 0x40012914 12915#define VSB_TOP_SYSSMTRNCTRL__A 0x1C1003412916#define VSB_TOP_SYSSMTRNCTRL__W 1112917#define VSB_TOP_SYSSMTRNCTRL__M 0x7FF12918#define VSB_TOP_SYSSMTRNCTRL__PRE 0x20412919 12920#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__B 012921#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__W 112922#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__M 0x112923#define VSB_TOP_SYSSMTRNCTRL_RSTCTCAL__PRE 0x012924 12925#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__B 112926#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__W 112927#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__M 0x212928#define VSB_TOP_SYSSMTRNCTRL_CTCALEN__PRE 0x012929 12930#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__B 212931#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__W 112932#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__M 0x412933#define VSB_TOP_SYSSMTRNCTRL_STARTTRN__PRE 0x412934 12935#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__B 312936#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__W 112937#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__M 0x812938#define VSB_TOP_SYSSMTRNCTRL_RSTFRMSYNCDET__PRE 0x012939 12940#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__B 412941#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__W 112942#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__M 0x1012943#define VSB_TOP_SYSSMTRNCTRL_RSTCYDET__PRE 0x012944 12945#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__B 512946#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__W 112947#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__M 0x2012948#define VSB_TOP_SYSSMTRNCTRL_RSTDCRMV__PRE 0x012949 12950#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__B 612951#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__W 112952#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__M 0x4012953#define VSB_TOP_SYSSMTRNCTRL_RSTEQSIG__PRE 0x012954 12955#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__B 712956#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__W 112957#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__M 0x8012958#define VSB_TOP_SYSSMTRNCTRL_CKFRZ__PRE 0x012959 12960#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__B 812961#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__W 112962#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__M 0x10012963#define VSB_TOP_SYSSMTRNCTRL_CKBWSW__PRE 0x012964 12965#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__B 912966#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__W 112967#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__M 0x20012968#define VSB_TOP_SYSSMTRNCTRL_NCOBWSW__PRE 0x20012969 12970#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__B 1012971#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__W 112972#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__M 0x40012973#define VSB_TOP_SYSSMTRNCTRL_NCOTIMEOUTCNTEN__PRE 0x012974 12975#define VSB_TOP_SYSSMEQCTRL__A 0x1C1003512976#define VSB_TOP_SYSSMEQCTRL__W 1112977#define VSB_TOP_SYSSMEQCTRL__M 0x7FF12978#define VSB_TOP_SYSSMEQCTRL__PRE 0x30412979 12980#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__B 012981#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__W 112982#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__M 0x112983#define VSB_TOP_SYSSMEQCTRL_RSTCTCAL__PRE 0x012984 12985#define VSB_TOP_SYSSMEQCTRL_CTCALEN__B 112986#define VSB_TOP_SYSSMEQCTRL_CTCALEN__W 112987#define VSB_TOP_SYSSMEQCTRL_CTCALEN__M 0x212988#define VSB_TOP_SYSSMEQCTRL_CTCALEN__PRE 0x012989 12990#define VSB_TOP_SYSSMEQCTRL_STARTTRN__B 212991#define VSB_TOP_SYSSMEQCTRL_STARTTRN__W 112992#define VSB_TOP_SYSSMEQCTRL_STARTTRN__M 0x412993#define VSB_TOP_SYSSMEQCTRL_STARTTRN__PRE 0x412994 12995#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__B 312996#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__W 112997#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__M 0x812998#define VSB_TOP_SYSSMEQCTRL_RSTFRMSYNCDET__PRE 0x012999 13000#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__B 413001#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__W 113002#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__M 0x1013003#define VSB_TOP_SYSSMEQCTRL_RSTCYDET__PRE 0x013004 13005#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__B 513006#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__W 113007#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__M 0x2013008#define VSB_TOP_SYSSMEQCTRL_RSTDCRMV__PRE 0x013009 13010#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__B 613011#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__W 113012#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__M 0x4013013#define VSB_TOP_SYSSMEQCTRL_RSTEQSIG__PRE 0x013014 13015#define VSB_TOP_SYSSMEQCTRL_CKFRZ__B 713016#define VSB_TOP_SYSSMEQCTRL_CKFRZ__W 113017#define VSB_TOP_SYSSMEQCTRL_CKFRZ__M 0x8013018#define VSB_TOP_SYSSMEQCTRL_CKFRZ__PRE 0x013019 13020#define VSB_TOP_SYSSMEQCTRL_CKBWSW__B 813021#define VSB_TOP_SYSSMEQCTRL_CKBWSW__W 113022#define VSB_TOP_SYSSMEQCTRL_CKBWSW__M 0x10013023#define VSB_TOP_SYSSMEQCTRL_CKBWSW__PRE 0x10013024 13025#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__B 913026#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__W 113027#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__M 0x20013028#define VSB_TOP_SYSSMEQCTRL_NCOBWSW__PRE 0x20013029 13030#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__B 1013031#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__W 113032#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__M 0x40013033#define VSB_TOP_SYSSMEQCTRL_NCOTIMEOUTCNTEN__PRE 0x013034 13035#define VSB_TOP_SYSSMAGCCTRL__A 0x1C1003613036#define VSB_TOP_SYSSMAGCCTRL__W 1113037#define VSB_TOP_SYSSMAGCCTRL__M 0x7FF13038#define VSB_TOP_SYSSMAGCCTRL__PRE 0xF913039 13040#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__B 013041#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__W 113042#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__M 0x113043#define VSB_TOP_SYSSMAGCCTRL_RSTCTCAL__PRE 0x113044 13045#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__B 113046#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__W 113047#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__M 0x213048#define VSB_TOP_SYSSMAGCCTRL_CTCALEN__PRE 0x013049 13050#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__B 213051#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__W 113052#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__M 0x413053#define VSB_TOP_SYSSMAGCCTRL_STARTTRN__PRE 0x013054 13055#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__B 313056#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__W 113057#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__M 0x813058#define VSB_TOP_SYSSMAGCCTRL_RSTFRMSYNCDET__PRE 0x813059 13060#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__B 413061#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__W 113062#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__M 0x1013063#define VSB_TOP_SYSSMAGCCTRL_RSTCYDET__PRE 0x1013064 13065#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__B 513066#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__W 113067#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__M 0x2013068#define VSB_TOP_SYSSMAGCCTRL_RSTDCRMV__PRE 0x2013069 13070#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__B 613071#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__W 113072#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__M 0x4013073#define VSB_TOP_SYSSMAGCCTRL_RSTEQSIG__PRE 0x4013074 13075#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__B 713076#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__W 113077#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__M 0x8013078#define VSB_TOP_SYSSMAGCCTRL_CKFRZ__PRE 0x8013079 13080#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__B 813081#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__W 113082#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__M 0x10013083#define VSB_TOP_SYSSMAGCCTRL_CKBWSW__PRE 0x013084 13085#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__B 913086#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__W 113087#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__M 0x20013088#define VSB_TOP_SYSSMAGCCTRL_NCOBWSW__PRE 0x013089 13090#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__B 1013091#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__W 113092#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__M 0x40013093#define VSB_TOP_SYSSMAGCCTRL_NCOTIMEOUTCNTEN__PRE 0x013094 13095#define VSB_TOP_SYSSMCTCTRL__A 0x1C1003713096#define VSB_TOP_SYSSMCTCTRL__W 1113097#define VSB_TOP_SYSSMCTCTRL__M 0x7FF13098#define VSB_TOP_SYSSMCTCTRL__PRE 0x4A13099 13100#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__B 013101#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__W 113102#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__M 0x113103#define VSB_TOP_SYSSMCTCTRL_RSTCTCAL__PRE 0x013104 13105#define VSB_TOP_SYSSMCTCTRL_CTCALEN__B 113106#define VSB_TOP_SYSSMCTCTRL_CTCALEN__W 113107#define VSB_TOP_SYSSMCTCTRL_CTCALEN__M 0x213108#define VSB_TOP_SYSSMCTCTRL_CTCALEN__PRE 0x213109 13110#define VSB_TOP_SYSSMCTCTRL_STARTTRN__B 213111#define VSB_TOP_SYSSMCTCTRL_STARTTRN__W 113112#define VSB_TOP_SYSSMCTCTRL_STARTTRN__M 0x413113#define VSB_TOP_SYSSMCTCTRL_STARTTRN__PRE 0x013114 13115#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__B 313116#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__W 113117#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__M 0x813118#define VSB_TOP_SYSSMCTCTRL_RSTFRMSYNCDET__PRE 0x813119 13120#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__B 413121#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__W 113122#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__M 0x1013123#define VSB_TOP_SYSSMCTCTRL_RSTCYDET__PRE 0x013124 13125#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__B 513126#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__W 113127#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__M 0x2013128#define VSB_TOP_SYSSMCTCTRL_RSTDCRMV__PRE 0x013129 13130#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__B 613131#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__W 113132#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__M 0x4013133#define VSB_TOP_SYSSMCTCTRL_RSTEQSIG__PRE 0x4013134 13135#define VSB_TOP_SYSSMCTCTRL_CKFRZ__B 713136#define VSB_TOP_SYSSMCTCTRL_CKFRZ__W 113137#define VSB_TOP_SYSSMCTCTRL_CKFRZ__M 0x8013138#define VSB_TOP_SYSSMCTCTRL_CKFRZ__PRE 0x013139 13140#define VSB_TOP_SYSSMCTCTRL_CKBWSW__B 813141#define VSB_TOP_SYSSMCTCTRL_CKBWSW__W 113142#define VSB_TOP_SYSSMCTCTRL_CKBWSW__M 0x10013143#define VSB_TOP_SYSSMCTCTRL_CKBWSW__PRE 0x013144 13145#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__B 913146#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__W 113147#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__M 0x20013148#define VSB_TOP_SYSSMCTCTRL_NCOBWSW__PRE 0x013149 13150#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__B 1013151#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__W 113152#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__M 0x40013153#define VSB_TOP_SYSSMCTCTRL_NCOTIMEOUTCNTEN__PRE 0x013154 13155#define VSB_TOP_EQCTRL__A 0x1C1003813156#define VSB_TOP_EQCTRL__W 1013157#define VSB_TOP_EQCTRL__M 0x3FF13158#define VSB_TOP_EQCTRL__PRE 0x613159 13160#define VSB_TOP_EQCTRL_STASSIGNEN__B 013161#define VSB_TOP_EQCTRL_STASSIGNEN__W 113162#define VSB_TOP_EQCTRL_STASSIGNEN__M 0x113163#define VSB_TOP_EQCTRL_STASSIGNEN__PRE 0x013164 13165#define VSB_TOP_EQCTRL_ORCANCMAEN__B 113166#define VSB_TOP_EQCTRL_ORCANCMAEN__W 113167#define VSB_TOP_EQCTRL_ORCANCMAEN__M 0x213168#define VSB_TOP_EQCTRL_ORCANCMAEN__PRE 0x213169 13170#define VSB_TOP_EQCTRL_ODAGCGO__B 213171#define VSB_TOP_EQCTRL_ODAGCGO__W 113172#define VSB_TOP_EQCTRL_ODAGCGO__M 0x413173#define VSB_TOP_EQCTRL_ODAGCGO__PRE 0x413174 13175#define VSB_TOP_EQCTRL_OPTGAIN__B 313176#define VSB_TOP_EQCTRL_OPTGAIN__W 313177#define VSB_TOP_EQCTRL_OPTGAIN__M 0x3813178#define VSB_TOP_EQCTRL_OPTGAIN__PRE 0x013179 13180#define VSB_TOP_EQCTRL_TAPRAMWRTEN__B 613181#define VSB_TOP_EQCTRL_TAPRAMWRTEN__W 113182#define VSB_TOP_EQCTRL_TAPRAMWRTEN__M 0x4013183#define VSB_TOP_EQCTRL_TAPRAMWRTEN__PRE 0x013184 13185#define VSB_TOP_EQCTRL_CMAGAIN__B 713186#define VSB_TOP_EQCTRL_CMAGAIN__W 313187#define VSB_TOP_EQCTRL_CMAGAIN__M 0x38013188#define VSB_TOP_EQCTRL_CMAGAIN__PRE 0x013189 13190#define VSB_TOP_PREEQAGCCTRL__A 0x1C1003913191#define VSB_TOP_PREEQAGCCTRL__W 513192#define VSB_TOP_PREEQAGCCTRL__M 0x1F13193#define VSB_TOP_PREEQAGCCTRL__PRE 0x1013194 13195#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__B 013196#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__W 413197#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__M 0xF13198#define VSB_TOP_PREEQAGCCTRL_PREEQAGCBWSEL__PRE 0x013199 13200#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__B 413201#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__W 113202#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__M 0x1013203#define VSB_TOP_PREEQAGCCTRL_PREEQAGCFRZ__PRE 0x1013204 13205#define VSB_TOP_PREEQAGCPWRREFLVLHI__A 0x1C1003A13206#define VSB_TOP_PREEQAGCPWRREFLVLHI__W 813207#define VSB_TOP_PREEQAGCPWRREFLVLHI__M 0xFF13208#define VSB_TOP_PREEQAGCPWRREFLVLHI__PRE 0x013209 13210#define VSB_TOP_PREEQAGCPWRREFLVLLO__A 0x1C1003B13211#define VSB_TOP_PREEQAGCPWRREFLVLLO__W 1613212#define VSB_TOP_PREEQAGCPWRREFLVLLO__M 0xFFFF13213#define VSB_TOP_PREEQAGCPWRREFLVLLO__PRE 0x1D6613214 13215#define VSB_TOP_CORINGSEL__A 0x1C1003C13216#define VSB_TOP_CORINGSEL__W 813217#define VSB_TOP_CORINGSEL__M 0xFF13218#define VSB_TOP_CORINGSEL__PRE 0x313219#define VSB_TOP_BEDETCTRL__A 0x1C1003D13220#define VSB_TOP_BEDETCTRL__W 913221#define VSB_TOP_BEDETCTRL__M 0x1FF13222#define VSB_TOP_BEDETCTRL__PRE 0x14513223 13224#define VSB_TOP_BEDETCTRL_MIXRATIO__B 013225#define VSB_TOP_BEDETCTRL_MIXRATIO__W 313226#define VSB_TOP_BEDETCTRL_MIXRATIO__M 0x713227#define VSB_TOP_BEDETCTRL_MIXRATIO__PRE 0x513228 13229#define VSB_TOP_BEDETCTRL_CYOFFSEL__B 313230#define VSB_TOP_BEDETCTRL_CYOFFSEL__W 113231#define VSB_TOP_BEDETCTRL_CYOFFSEL__M 0x813232#define VSB_TOP_BEDETCTRL_CYOFFSEL__PRE 0x013233 13234#define VSB_TOP_BEDETCTRL_DATAOFFSEL__B 413235#define VSB_TOP_BEDETCTRL_DATAOFFSEL__W 113236#define VSB_TOP_BEDETCTRL_DATAOFFSEL__M 0x1013237#define VSB_TOP_BEDETCTRL_DATAOFFSEL__PRE 0x013238 13239#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__B 513240#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__W 113241#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__M 0x2013242#define VSB_TOP_BEDETCTRL_BYPASS_DSQ__PRE 0x013243 13244#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__B 613245#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__W 113246#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__M 0x4013247#define VSB_TOP_BEDETCTRL_BYPASS_PSQ__PRE 0x4013248 13249#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__B 713250#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__W 113251#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__M 0x8013252#define VSB_TOP_BEDETCTRL_BYPASS_CSQ__PRE 0x013253 13254#define VSB_TOP_BEDETCTRL_BYPASS_DMP__B 813255#define VSB_TOP_BEDETCTRL_BYPASS_DMP__W 113256#define VSB_TOP_BEDETCTRL_BYPASS_DMP__M 0x10013257#define VSB_TOP_BEDETCTRL_BYPASS_DMP__PRE 0x10013258 13259#define VSB_TOP_LBAGCREFLVL__A 0x1C1003E13260#define VSB_TOP_LBAGCREFLVL__W 1213261#define VSB_TOP_LBAGCREFLVL__M 0xFFF13262#define VSB_TOP_LBAGCREFLVL__PRE 0x20013263 13264#define VSB_TOP_UBAGCREFLVL__A 0x1C1003F13265#define VSB_TOP_UBAGCREFLVL__W 1213266#define VSB_TOP_UBAGCREFLVL__M 0xFFF13267#define VSB_TOP_UBAGCREFLVL__PRE 0x40013268 13269#define VSB_TOP_NOTCH1_BIN_NUM__A 0x1C1004013270#define VSB_TOP_NOTCH1_BIN_NUM__W 1113271#define VSB_TOP_NOTCH1_BIN_NUM__M 0x7FF13272#define VSB_TOP_NOTCH1_BIN_NUM__PRE 0xB213273 13274#define VSB_TOP_NOTCH2_BIN_NUM__A 0x1C1004113275#define VSB_TOP_NOTCH2_BIN_NUM__W 1113276#define VSB_TOP_NOTCH2_BIN_NUM__M 0x7FF13277#define VSB_TOP_NOTCH2_BIN_NUM__PRE 0x40B13278 13279#define VSB_TOP_NOTCH_START_BIN_NUM__A 0x1C1004213280#define VSB_TOP_NOTCH_START_BIN_NUM__W 1113281#define VSB_TOP_NOTCH_START_BIN_NUM__M 0x7FF13282#define VSB_TOP_NOTCH_START_BIN_NUM__PRE 0x7C013283 13284#define VSB_TOP_NOTCH_STOP_BIN_NUM__A 0x1C1004313285#define VSB_TOP_NOTCH_STOP_BIN_NUM__W 1113286#define VSB_TOP_NOTCH_STOP_BIN_NUM__M 0x7FF13287#define VSB_TOP_NOTCH_STOP_BIN_NUM__PRE 0x43F13288 13289#define VSB_TOP_NOTCH_TEST_DURATION__A 0x1C1004413290#define VSB_TOP_NOTCH_TEST_DURATION__W 1113291#define VSB_TOP_NOTCH_TEST_DURATION__M 0x7FF13292#define VSB_TOP_NOTCH_TEST_DURATION__PRE 0x7FF13293 13294#define VSB_TOP_RESULT_LARGE_PEAK_BIN__A 0x1C1004513295#define VSB_TOP_RESULT_LARGE_PEAK_BIN__W 1113296#define VSB_TOP_RESULT_LARGE_PEAK_BIN__M 0x7FF13297#define VSB_TOP_RESULT_LARGE_PEAK_BIN__PRE 0x013298 13299#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__A 0x1C1004613300#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__W 1613301#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__M 0xFFFF13302#define VSB_TOP_RESULT_LARGE_PEAK_VALUE__PRE 0x013303 13304#define VSB_TOP_RESULT_SMALL_PEAK_BIN__A 0x1C1004713305#define VSB_TOP_RESULT_SMALL_PEAK_BIN__W 1113306#define VSB_TOP_RESULT_SMALL_PEAK_BIN__M 0x7FF13307#define VSB_TOP_RESULT_SMALL_PEAK_BIN__PRE 0x013308 13309#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__A 0x1C1004813310#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__W 1613311#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__M 0xFFFF13312#define VSB_TOP_RESULT_SMALL_PEAK_VALUE__PRE 0x013313 13314#define VSB_TOP_NOTCH_SWEEP_RUNNING__A 0x1C1004913315#define VSB_TOP_NOTCH_SWEEP_RUNNING__W 113316#define VSB_TOP_NOTCH_SWEEP_RUNNING__M 0x113317#define VSB_TOP_NOTCH_SWEEP_RUNNING__PRE 0x013318 13319#define VSB_TOP_PREEQDAGCRATIO__A 0x1C1004A13320#define VSB_TOP_PREEQDAGCRATIO__W 1313321#define VSB_TOP_PREEQDAGCRATIO__M 0x1FFF13322#define VSB_TOP_PREEQDAGCRATIO__PRE 0x013323#define VSB_TOP_AGC_TRUNCCTRL__A 0x1C1004B13324#define VSB_TOP_AGC_TRUNCCTRL__W 413325#define VSB_TOP_AGC_TRUNCCTRL__M 0xF13326#define VSB_TOP_AGC_TRUNCCTRL__PRE 0xF13327 13328#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__B 013329#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__W 213330#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__M 0x313331#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_LSB__PRE 0x313332 13333#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__B 213334#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__W 113335#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__M 0x413336#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_12N__PRE 0x413337 13338#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__B 313339#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__W 113340#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__M 0x813341#define VSB_TOP_AGC_TRUNCCTRL_TRUNC_EN__PRE 0x813342 13343#define VSB_TOP_BEAGC_DEADZONEINIT__A 0x1C1004C13344#define VSB_TOP_BEAGC_DEADZONEINIT__W 813345#define VSB_TOP_BEAGC_DEADZONEINIT__M 0xFF13346#define VSB_TOP_BEAGC_DEADZONEINIT__PRE 0x5013347 13348#define VSB_TOP_BEAGC_REFLEVEL__A 0x1C1004D13349#define VSB_TOP_BEAGC_REFLEVEL__W 913350#define VSB_TOP_BEAGC_REFLEVEL__M 0x1FF13351#define VSB_TOP_BEAGC_REFLEVEL__PRE 0xAE13352 13353#define VSB_TOP_BEAGC_GAINSHIFT__A 0x1C1004E13354#define VSB_TOP_BEAGC_GAINSHIFT__W 313355#define VSB_TOP_BEAGC_GAINSHIFT__M 0x713356#define VSB_TOP_BEAGC_GAINSHIFT__PRE 0x313357 13358#define VSB_TOP_BEAGC_REGINIT__A 0x1C1004F13359#define VSB_TOP_BEAGC_REGINIT__W 1513360#define VSB_TOP_BEAGC_REGINIT__M 0x7FFF13361#define VSB_TOP_BEAGC_REGINIT__PRE 0x4013362 13363#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__B 1413364#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__W 113365#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__M 0x400013366#define VSB_TOP_BEAGC_REGINIT_BEAGC_RST__PRE 0x013367 13368#define VSB_TOP_BEAGC_SCALE__A 0x1C1005013369#define VSB_TOP_BEAGC_SCALE__W 1413370#define VSB_TOP_BEAGC_SCALE__M 0x3FFF13371#define VSB_TOP_BEAGC_SCALE__PRE 0x013372 13373#define VSB_TOP_CFAGC_DEADZONEINIT__A 0x1C1005113374#define VSB_TOP_CFAGC_DEADZONEINIT__W 813375#define VSB_TOP_CFAGC_DEADZONEINIT__M 0xFF13376#define VSB_TOP_CFAGC_DEADZONEINIT__PRE 0x5013377 13378#define VSB_TOP_CFAGC_REFLEVEL__A 0x1C1005213379#define VSB_TOP_CFAGC_REFLEVEL__W 913380#define VSB_TOP_CFAGC_REFLEVEL__M 0x1FF13381#define VSB_TOP_CFAGC_REFLEVEL__PRE 0xAE13382 13383#define VSB_TOP_CFAGC_GAINSHIFT__A 0x1C1005313384#define VSB_TOP_CFAGC_GAINSHIFT__W 313385#define VSB_TOP_CFAGC_GAINSHIFT__M 0x713386#define VSB_TOP_CFAGC_GAINSHIFT__PRE 0x313387 13388#define VSB_TOP_CFAGC_REGINIT__A 0x1C1005413389#define VSB_TOP_CFAGC_REGINIT__W 1513390#define VSB_TOP_CFAGC_REGINIT__M 0x7FFF13391#define VSB_TOP_CFAGC_REGINIT__PRE 0x8013392 13393#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__B 1413394#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__W 113395#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__M 0x400013396#define VSB_TOP_CFAGC_REGINIT_CFAGC_RST__PRE 0x013397 13398#define VSB_TOP_CFAGC_SCALE__A 0x1C1005513399#define VSB_TOP_CFAGC_SCALE__W 1413400#define VSB_TOP_CFAGC_SCALE__M 0x3FFF13401#define VSB_TOP_CFAGC_SCALE__PRE 0x013402 13403#define VSB_TOP_CKTRKONCTL__A 0x1C1005613404#define VSB_TOP_CKTRKONCTL__W 213405#define VSB_TOP_CKTRKONCTL__M 0x313406#define VSB_TOP_CKTRKONCTL__PRE 0x013407 13408#define VSB_TOP_CYTRKONCTL__A 0x1C1005713409#define VSB_TOP_CYTRKONCTL__W 213410#define VSB_TOP_CYTRKONCTL__M 0x313411#define VSB_TOP_CYTRKONCTL__PRE 0x013412 13413#define VSB_TOP_PTONCTL__A 0x1C1005813414#define VSB_TOP_PTONCTL__W 213415#define VSB_TOP_PTONCTL__M 0x313416#define VSB_TOP_PTONCTL__PRE 0x013417 13418#define VSB_TOP_NOTCH_SCALE_1__A 0x1C1005913419#define VSB_TOP_NOTCH_SCALE_1__W 813420#define VSB_TOP_NOTCH_SCALE_1__M 0xFF13421#define VSB_TOP_NOTCH_SCALE_1__PRE 0xA13422 13423#define VSB_TOP_NOTCH_SCALE_2__A 0x1C1005A13424#define VSB_TOP_NOTCH_SCALE_2__W 813425#define VSB_TOP_NOTCH_SCALE_2__M 0xFF13426#define VSB_TOP_NOTCH_SCALE_2__PRE 0xA13427 13428#define VSB_TOP_FIRSTLARGFFETAP__A 0x1C1005B13429#define VSB_TOP_FIRSTLARGFFETAP__W 1213430#define VSB_TOP_FIRSTLARGFFETAP__M 0xFFF13431#define VSB_TOP_FIRSTLARGFFETAP__PRE 0x013432 13433#define VSB_TOP_FIRSTLARGFFETAPADDR__A 0x1C1005C13434#define VSB_TOP_FIRSTLARGFFETAPADDR__W 1113435#define VSB_TOP_FIRSTLARGFFETAPADDR__M 0x7FF13436#define VSB_TOP_FIRSTLARGFFETAPADDR__PRE 0x013437 13438#define VSB_TOP_SECONDLARGFFETAP__A 0x1C1005D13439#define VSB_TOP_SECONDLARGFFETAP__W 1213440#define VSB_TOP_SECONDLARGFFETAP__M 0xFFF13441#define VSB_TOP_SECONDLARGFFETAP__PRE 0x013442 13443#define VSB_TOP_SECONDLARGFFETAPADDR__A 0x1C1005E13444#define VSB_TOP_SECONDLARGFFETAPADDR__W 1113445#define VSB_TOP_SECONDLARGFFETAPADDR__M 0x7FF13446#define VSB_TOP_SECONDLARGFFETAPADDR__PRE 0x013447 13448#define VSB_TOP_FIRSTLARGDFETAP__A 0x1C1005F13449#define VSB_TOP_FIRSTLARGDFETAP__W 1213450#define VSB_TOP_FIRSTLARGDFETAP__M 0xFFF13451#define VSB_TOP_FIRSTLARGDFETAP__PRE 0x013452 13453#define VSB_TOP_FIRSTLARGDFETAPADDR__A 0x1C1006013454#define VSB_TOP_FIRSTLARGDFETAPADDR__W 1113455#define VSB_TOP_FIRSTLARGDFETAPADDR__M 0x7FF13456#define VSB_TOP_FIRSTLARGDFETAPADDR__PRE 0x013457 13458#define VSB_TOP_SECONDLARGDFETAP__A 0x1C1006113459#define VSB_TOP_SECONDLARGDFETAP__W 1213460#define VSB_TOP_SECONDLARGDFETAP__M 0xFFF13461#define VSB_TOP_SECONDLARGDFETAP__PRE 0x013462 13463#define VSB_TOP_SECONDLARGDFETAPADDR__A 0x1C1006213464#define VSB_TOP_SECONDLARGDFETAPADDR__W 1113465#define VSB_TOP_SECONDLARGDFETAPADDR__M 0x7FF13466#define VSB_TOP_SECONDLARGDFETAPADDR__PRE 0x013467 13468#define VSB_TOP_PARAOWDBUS__A 0x1C1006313469#define VSB_TOP_PARAOWDBUS__W 1213470#define VSB_TOP_PARAOWDBUS__M 0xFFF13471#define VSB_TOP_PARAOWDBUS__PRE 0x013472#define VSB_TOP_PARAOWCTRL__A 0x1C1006413473#define VSB_TOP_PARAOWCTRL__W 713474#define VSB_TOP_PARAOWCTRL__M 0x7F13475#define VSB_TOP_PARAOWCTRL__PRE 0x013476 13477#define VSB_TOP_PARAOWCTRL_PARAOWABUS__B 013478#define VSB_TOP_PARAOWCTRL_PARAOWABUS__W 613479#define VSB_TOP_PARAOWCTRL_PARAOWABUS__M 0x3F13480#define VSB_TOP_PARAOWCTRL_PARAOWABUS__PRE 0x013481 13482#define VSB_TOP_PARAOWCTRL_PARAOWEN__B 613483#define VSB_TOP_PARAOWCTRL_PARAOWEN__W 113484#define VSB_TOP_PARAOWCTRL_PARAOWEN__M 0x4013485#define VSB_TOP_PARAOWCTRL_PARAOWEN__PRE 0x013486 13487#define VSB_TOP_CURRENTSEGLOCAT__A 0x1C1006513488#define VSB_TOP_CURRENTSEGLOCAT__W 1013489#define VSB_TOP_CURRENTSEGLOCAT__M 0x3FF13490#define VSB_TOP_CURRENTSEGLOCAT__PRE 0x013491 13492#define VSB_TOP_MEASUREMENT_PERIOD__A 0x1C1006613493#define VSB_TOP_MEASUREMENT_PERIOD__W 1613494#define VSB_TOP_MEASUREMENT_PERIOD__M 0xFFFF13495#define VSB_TOP_MEASUREMENT_PERIOD__PRE 0x013496 13497#define VSB_TOP_NR_SYM_ERRS__A 0x1C1006713498#define VSB_TOP_NR_SYM_ERRS__W 1613499#define VSB_TOP_NR_SYM_ERRS__M 0xFFFF13500#define VSB_TOP_NR_SYM_ERRS__PRE 0xFFFF13501 13502#define VSB_TOP_ERR_ENERGY_L__A 0x1C1006813503#define VSB_TOP_ERR_ENERGY_L__W 1613504#define VSB_TOP_ERR_ENERGY_L__M 0xFFFF13505#define VSB_TOP_ERR_ENERGY_L__PRE 0xFFFF13506 13507#define VSB_TOP_ERR_ENERGY_H__A 0x1C1006913508#define VSB_TOP_ERR_ENERGY_H__W 1613509#define VSB_TOP_ERR_ENERGY_H__M 0xFFFF13510#define VSB_TOP_ERR_ENERGY_H__PRE 0xFFFF13511 13512#define VSB_TOP_SLICER_SEL_8LEV__A 0x1C1006A13513#define VSB_TOP_SLICER_SEL_8LEV__W 113514#define VSB_TOP_SLICER_SEL_8LEV__M 0x113515#define VSB_TOP_SLICER_SEL_8LEV__PRE 0x113516 13517#define VSB_TOP_BNFIELD__A 0x1C1006B13518#define VSB_TOP_BNFIELD__W 313519#define VSB_TOP_BNFIELD__M 0x713520#define VSB_TOP_BNFIELD__PRE 0x313521 13522#define VSB_TOP_CLPLASTNUM__A 0x1C1006C13523#define VSB_TOP_CLPLASTNUM__W 813524#define VSB_TOP_CLPLASTNUM__M 0xFF13525#define VSB_TOP_CLPLASTNUM__PRE 0x013526 13527#define VSB_TOP_BNSQERR__A 0x1C1006D13528#define VSB_TOP_BNSQERR__W 1613529#define VSB_TOP_BNSQERR__M 0xFFFF13530#define VSB_TOP_BNSQERR__PRE 0x1AD13531 13532#define VSB_TOP_BNTHRESH__A 0x1C1006E13533#define VSB_TOP_BNTHRESH__W 913534#define VSB_TOP_BNTHRESH__M 0x1FF13535#define VSB_TOP_BNTHRESH__PRE 0x12013536 13537#define VSB_TOP_BNCLPNUM__A 0x1C1006F13538#define VSB_TOP_BNCLPNUM__W 1613539#define VSB_TOP_BNCLPNUM__M 0xFFFF13540#define VSB_TOP_BNCLPNUM__PRE 0x013541#define VSB_TOP_PHASELOCKCTRL__A 0x1C1007013542#define VSB_TOP_PHASELOCKCTRL__W 713543#define VSB_TOP_PHASELOCKCTRL__M 0x7F13544#define VSB_TOP_PHASELOCKCTRL__PRE 0x013545 13546#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__B 013547#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__W 113548#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__M 0x113549#define VSB_TOP_PHASELOCKCTRL_DFORCEPOLARITY__PRE 0x013550 13551#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__B 113552#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__W 113553#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__M 0x213554#define VSB_TOP_PHASELOCKCTRL_DFORCEPLL__PRE 0x013555 13556#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__B 213557#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__W 113558#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__M 0x413559#define VSB_TOP_PHASELOCKCTRL_PFORCEPOLARITY__PRE 0x013560 13561#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__B 313562#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__W 113563#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__M 0x813564#define VSB_TOP_PHASELOCKCTRL_PFORCEPLL__PRE 0x013565 13566#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__B 413567#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__W 113568#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__M 0x1013569#define VSB_TOP_PHASELOCKCTRL_CFORCEPOLARITY__PRE 0x013570 13571#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__B 513572#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__W 113573#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__M 0x2013574#define VSB_TOP_PHASELOCKCTRL_CFORCEPLL__PRE 0x013575 13576#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__B 613577#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__W 113578#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__M 0x4013579#define VSB_TOP_PHASELOCKCTRL_IQSWITCH__PRE 0x013580 13581#define VSB_TOP_DLOCKACCUM__A 0x1C1007113582#define VSB_TOP_DLOCKACCUM__W 1613583#define VSB_TOP_DLOCKACCUM__M 0xFFFF13584#define VSB_TOP_DLOCKACCUM__PRE 0x013585 13586#define VSB_TOP_PLOCKACCUM__A 0x1C1007213587#define VSB_TOP_PLOCKACCUM__W 1613588#define VSB_TOP_PLOCKACCUM__M 0xFFFF13589#define VSB_TOP_PLOCKACCUM__PRE 0x013590 13591#define VSB_TOP_CLOCKACCUM__A 0x1C1007313592#define VSB_TOP_CLOCKACCUM__W 1613593#define VSB_TOP_CLOCKACCUM__M 0xFFFF13594#define VSB_TOP_CLOCKACCUM__PRE 0x013595 13596#define VSB_TOP_DCRMVACUMI__A 0x1C1007413597#define VSB_TOP_DCRMVACUMI__W 1013598#define VSB_TOP_DCRMVACUMI__M 0x3FF13599#define VSB_TOP_DCRMVACUMI__PRE 0x013600 13601#define VSB_TOP_DCRMVACUMQ__A 0x1C1007513602#define VSB_TOP_DCRMVACUMQ__W 1013603#define VSB_TOP_DCRMVACUMQ__M 0x3FF13604#define VSB_TOP_DCRMVACUMQ__PRE 0x013605 13606#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A 0x1C2000013607#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__W 1213608#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__M 0xFFF13609#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__PRE 0x013610 13611#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__A 0x1C2000113612#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__W 1213613#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__M 0xFFF13614#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO2__PRE 0x013615 13616#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__A 0x1C2000213617#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__W 1213618#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__M 0xFFF13619#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO3__PRE 0x013620 13621#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__A 0x1C2000313622#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__W 1213623#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__M 0xFFF13624#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO4__PRE 0x013625 13626#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__A 0x1C2000413627#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__W 1213628#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__M 0xFFF13629#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO5__PRE 0x013630 13631#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__A 0x1C2000513632#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__W 1213633#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__M 0xFFF13634#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO6__PRE 0x013635 13636#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__A 0x1C2000613637#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__W 1213638#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__M 0xFFF13639#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO7__PRE 0x013640 13641#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__A 0x1C2000713642#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__W 1213643#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__M 0xFFF13644#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO8__PRE 0x013645 13646#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__A 0x1C2000813647#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__W 1213648#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__M 0xFFF13649#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO9__PRE 0x013650 13651#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__A 0x1C2000913652#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__W 1213653#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__M 0xFFF13654#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO10__PRE 0x013655 13656#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__A 0x1C2000A13657#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__W 1213658#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__M 0xFFF13659#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO11__PRE 0x013660 13661#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__A 0x1C2000B13662#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__W 1213663#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__M 0xFFF13664#define VSB_SYSCTRL_RAM0_FFETRAINLKRATIO12__PRE 0x013665 13666#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__A 0x1C2000C13667#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__W 1213668#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__M 0xFFF13669#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO1__PRE 0x013670 13671#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__A 0x1C2000D13672#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__W 1213673#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__M 0xFFF13674#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO2__PRE 0x013675 13676#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__A 0x1C2000E13677#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__W 1213678#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__M 0xFFF13679#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO3__PRE 0x013680 13681#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__A 0x1C2000F13682#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__W 1213683#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__M 0xFFF13684#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO4__PRE 0x013685 13686#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__A 0x1C2001013687#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__W 1213688#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__M 0xFFF13689#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO5__PRE 0x013690 13691#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__A 0x1C2001113692#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__W 1213693#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__M 0xFFF13694#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO6__PRE 0x013695 13696#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__A 0x1C2001213697#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__W 1213698#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__M 0xFFF13699#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO7__PRE 0x013700 13701#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__A 0x1C2001313702#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__W 1213703#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__M 0xFFF13704#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO8__PRE 0x013705 13706#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__A 0x1C2001413707#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__W 1213708#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__M 0xFFF13709#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO9__PRE 0x013710 13711#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__A 0x1C2001513712#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__W 1213713#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__M 0xFFF13714#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO10__PRE 0x013715 13716#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__A 0x1C2001613717#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__W 1213718#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__M 0xFFF13719#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO11__PRE 0x013720 13721#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__A 0x1C2001713722#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__W 1213723#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__M 0xFFF13724#define VSB_SYSCTRL_RAM0_FFERCA1TRAINLKRATIO12__PRE 0x013725 13726#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__A 0x1C2001813727#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__W 1213728#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__M 0xFFF13729#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO1__PRE 0x013730 13731#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__A 0x1C2001913732#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__W 1213733#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__M 0xFFF13734#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO2__PRE 0x013735 13736#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__A 0x1C2001A13737#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__W 1213738#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__M 0xFFF13739#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO3__PRE 0x013740 13741#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__A 0x1C2001B13742#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__W 1213743#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__M 0xFFF13744#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO4__PRE 0x013745 13746#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__A 0x1C2001C13747#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__W 1213748#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__M 0xFFF13749#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO5__PRE 0x013750 13751#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__A 0x1C2001D13752#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__W 1213753#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__M 0xFFF13754#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO6__PRE 0x013755 13756#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__A 0x1C2001E13757#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__W 1213758#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__M 0xFFF13759#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO7__PRE 0x013760 13761#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__A 0x1C2001F13762#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__W 1213763#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__M 0xFFF13764#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO8__PRE 0x013765 13766#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__A 0x1C2002013767#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__W 1213768#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__M 0xFFF13769#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO9__PRE 0x013770 13771#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__A 0x1C2002113772#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__W 1213773#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__M 0xFFF13774#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO10__PRE 0x013775 13776#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__A 0x1C2002213777#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__W 1213778#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__M 0xFFF13779#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO11__PRE 0x013780 13781#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__A 0x1C2002313782#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__W 1213783#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__M 0xFFF13784#define VSB_SYSCTRL_RAM0_FFERCA1DATALKRATIO12__PRE 0x013785 13786#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__A 0x1C2002413787#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__W 1213788#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__M 0xFFF13789#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO1__PRE 0x013790 13791#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__A 0x1C2002513792#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__W 1213793#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__M 0xFFF13794#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO2__PRE 0x013795 13796#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__A 0x1C2002613797#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__W 1213798#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__M 0xFFF13799#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO3__PRE 0x013800 13801#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__A 0x1C2002713802#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__W 1213803#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__M 0xFFF13804#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO4__PRE 0x013805 13806#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__A 0x1C2002813807#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__W 1213808#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__M 0xFFF13809#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO5__PRE 0x013810 13811#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__A 0x1C2002913812#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__W 1213813#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__M 0xFFF13814#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO6__PRE 0x013815 13816#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__A 0x1C2002A13817#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__W 1213818#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__M 0xFFF13819#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO7__PRE 0x013820 13821#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__A 0x1C2002B13822#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__W 1213823#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__M 0xFFF13824#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO8__PRE 0x013825 13826#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__A 0x1C2002C13827#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__W 1213828#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__M 0xFFF13829#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO9__PRE 0x013830 13831#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__A 0x1C2002D13832#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__W 1213833#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__M 0xFFF13834#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO10__PRE 0x013835 13836#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__A 0x1C2002E13837#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__W 1213838#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__M 0xFFF13839#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO11__PRE 0x013840 13841#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__A 0x1C2002F13842#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__W 1213843#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__M 0xFFF13844#define VSB_SYSCTRL_RAM0_FFERCA2TRAINLKRATIO12__PRE 0x013845 13846#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__A 0x1C2003013847#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__W 1213848#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__M 0xFFF13849#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO1__PRE 0x013850 13851#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__A 0x1C2003113852#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__W 1213853#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__M 0xFFF13854#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO2__PRE 0x013855 13856#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__A 0x1C2003213857#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__W 1213858#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__M 0xFFF13859#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO3__PRE 0x013860 13861#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__A 0x1C2003313862#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__W 1213863#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__M 0xFFF13864#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO4__PRE 0x013865 13866#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__A 0x1C2003413867#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__W 1213868#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__M 0xFFF13869#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO5__PRE 0x013870 13871#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__A 0x1C2003513872#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__W 1213873#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__M 0xFFF13874#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO6__PRE 0x013875 13876#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__A 0x1C2003613877#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__W 1213878#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__M 0xFFF13879#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO7__PRE 0x013880 13881#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__A 0x1C2003713882#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__W 1213883#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__M 0xFFF13884#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO8__PRE 0x013885 13886#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__A 0x1C2003813887#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__W 1213888#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__M 0xFFF13889#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO9__PRE 0x013890 13891#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__A 0x1C2003913892#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__W 1213893#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__M 0xFFF13894#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO10__PRE 0x013895 13896#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__A 0x1C2003A13897#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__W 1213898#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__M 0xFFF13899#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO11__PRE 0x013900 13901#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__A 0x1C2003B13902#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__W 1213903#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__M 0xFFF13904#define VSB_SYSCTRL_RAM0_FFERCA2DATALKRATIO12__PRE 0x013905 13906#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__A 0x1C2003C13907#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__W 1213908#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__M 0xFFF13909#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO1__PRE 0x013910 13911#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__A 0x1C2003D13912#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__W 1213913#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__M 0xFFF13914#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO2__PRE 0x013915 13916#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__A 0x1C2003E13917#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__W 1213918#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__M 0xFFF13919#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO3__PRE 0x013920 13921#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__A 0x1C2003F13922#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__W 1213923#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__M 0xFFF13924#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO4__PRE 0x013925 13926#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__A 0x1C2004013927#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__W 1213928#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__M 0xFFF13929#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO5__PRE 0x013930 13931#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__A 0x1C2004113932#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__W 1213933#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__M 0xFFF13934#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO6__PRE 0x013935 13936#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__A 0x1C2004213937#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__W 1213938#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__M 0xFFF13939#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO7__PRE 0x013940 13941#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__A 0x1C2004313942#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__W 1213943#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__M 0xFFF13944#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO8__PRE 0x013945 13946#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__A 0x1C2004413947#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__W 1213948#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__M 0xFFF13949#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO9__PRE 0x013950 13951#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__A 0x1C2004513952#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__W 1213953#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__M 0xFFF13954#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO10__PRE 0x013955 13956#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__A 0x1C2004613957#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__W 1213958#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__M 0xFFF13959#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO11__PRE 0x013960 13961#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__A 0x1C2004713962#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__W 1213963#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__M 0xFFF13964#define VSB_SYSCTRL_RAM0_FFEDDM1TRAINLKRATIO12__PRE 0x013965 13966#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__A 0x1C2004813967#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__W 1213968#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__M 0xFFF13969#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO1__PRE 0x013970 13971#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__A 0x1C2004913972#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__W 1213973#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__M 0xFFF13974#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO2__PRE 0x013975 13976#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__A 0x1C2004A13977#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__W 1213978#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__M 0xFFF13979#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO3__PRE 0x013980 13981#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__A 0x1C2004B13982#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__W 1213983#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__M 0xFFF13984#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO4__PRE 0x013985 13986#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__A 0x1C2004C13987#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__W 1213988#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__M 0xFFF13989#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO5__PRE 0x013990 13991#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__A 0x1C2004D13992#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__W 1213993#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__M 0xFFF13994#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO6__PRE 0x013995 13996#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__A 0x1C2004E13997#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__W 1213998#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__M 0xFFF13999#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO7__PRE 0x014000 14001#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__A 0x1C2004F14002#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__W 1214003#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__M 0xFFF14004#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO8__PRE 0x014005 14006#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__A 0x1C2005014007#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__W 1214008#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__M 0xFFF14009#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO9__PRE 0x014010 14011#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__A 0x1C2005114012#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__W 1214013#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__M 0xFFF14014#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO10__PRE 0x014015 14016#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__A 0x1C2005214017#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__W 1214018#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__M 0xFFF14019#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO11__PRE 0x014020 14021#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__A 0x1C2005314022#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__W 1214023#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__M 0xFFF14024#define VSB_SYSCTRL_RAM0_FFEDDM1DATALKRATIO12__PRE 0x014025 14026#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__A 0x1C2005414027#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__W 1214028#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__M 0xFFF14029#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO1__PRE 0x014030 14031#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__A 0x1C2005514032#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__W 1214033#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__M 0xFFF14034#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO2__PRE 0x014035 14036#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__A 0x1C2005614037#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__W 1214038#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__M 0xFFF14039#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO3__PRE 0x014040 14041#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__A 0x1C2005714042#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__W 1214043#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__M 0xFFF14044#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO4__PRE 0x014045 14046#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__A 0x1C2005814047#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__W 1214048#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__M 0xFFF14049#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO5__PRE 0x014050 14051#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__A 0x1C2005914052#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__W 1214053#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__M 0xFFF14054#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO6__PRE 0x014055 14056#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__A 0x1C2005A14057#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__W 1214058#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__M 0xFFF14059#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO7__PRE 0x014060 14061#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__A 0x1C2005B14062#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__W 1214063#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__M 0xFFF14064#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO8__PRE 0x014065 14066#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__A 0x1C2005C14067#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__W 1214068#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__M 0xFFF14069#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO9__PRE 0x014070 14071#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__A 0x1C2005D14072#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__W 1214073#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__M 0xFFF14074#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO10__PRE 0x014075 14076#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__A 0x1C2005E14077#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__W 1214078#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__M 0xFFF14079#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO11__PRE 0x014080 14081#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__A 0x1C2005F14082#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__W 1214083#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__M 0xFFF14084#define VSB_SYSCTRL_RAM0_FFEDDM2TRAINLKRATIO12__PRE 0x014085 14086#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__A 0x1C2006014087#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__W 1214088#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__M 0xFFF14089#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO1__PRE 0x014090 14091#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__A 0x1C2006114092#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__W 1214093#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__M 0xFFF14094#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO2__PRE 0x014095 14096#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__A 0x1C2006214097#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__W 1214098#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__M 0xFFF14099#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO3__PRE 0x014100 14101#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__A 0x1C2006314102#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__W 1214103#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__M 0xFFF14104#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO4__PRE 0x014105 14106#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__A 0x1C2006414107#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__W 1214108#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__M 0xFFF14109#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO5__PRE 0x014110 14111#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__A 0x1C2006514112#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__W 1214113#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__M 0xFFF14114#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO6__PRE 0x014115 14116#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__A 0x1C2006614117#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__W 1214118#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__M 0xFFF14119#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO7__PRE 0x014120 14121#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__A 0x1C2006714122#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__W 1214123#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__M 0xFFF14124#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO8__PRE 0x014125 14126#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__A 0x1C2006814127#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__W 1214128#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__M 0xFFF14129#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO9__PRE 0x014130 14131#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__A 0x1C2006914132#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__W 1214133#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__M 0xFFF14134#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO10__PRE 0x014135 14136#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__A 0x1C2006A14137#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__W 1214138#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__M 0xFFF14139#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO11__PRE 0x014140 14141#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__A 0x1C2006B14142#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__W 1214143#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__M 0xFFF14144#define VSB_SYSCTRL_RAM0_FFEDDM2DATALKRATIO12__PRE 0x014145 14146#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__A 0x1C2006C14147#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__W 714148#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__M 0x7F14149#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN1__PRE 0x014150 14151#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__A 0x1C2006D14152#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__W 714153#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__M 0x7F14154#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN2__PRE 0x014155 14156#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__A 0x1C2006E14157#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__W 714158#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__M 0x7F14159#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN3__PRE 0x014160 14161#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__A 0x1C2006F14162#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__W 714163#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__M 0x7F14164#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN4__PRE 0x014165 14166#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__A 0x1C2007014167#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__W 714168#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__M 0x7F14169#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN5__PRE 0x014170 14171#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__A 0x1C2007114172#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__W 714173#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__M 0x7F14174#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN6__PRE 0x014175 14176#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__A 0x1C2007214177#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__W 714178#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__M 0x7F14179#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN7__PRE 0x014180 14181#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__A 0x1C2007314182#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__W 714183#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__M 0x7F14184#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN8__PRE 0x014185 14186#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__A 0x1C2007414187#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__W 714188#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__M 0x7F14189#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN9__PRE 0x014190 14191#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__A 0x1C2007514192#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__W 714193#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__M 0x7F14194#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN10__PRE 0x014195 14196#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__A 0x1C2007614197#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__W 714198#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__M 0x7F14199#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN11__PRE 0x014200 14201#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__A 0x1C2007714202#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__W 714203#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__M 0x7F14204#define VSB_SYSCTRL_RAM0_FIRTRAINGAIN12__PRE 0x014205#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__A 0x1C2007814206#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__W 1514207#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__M 0x7FFF14208#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1__PRE 0x014209 14210#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__B 014211#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__W 714212#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__M 0x7F14213#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1TRAINGAIN1__PRE 0x014214 14215#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__B 814216#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__W 714217#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__M 0x7F0014218#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN1_FIRRCA1DATAGAIN1__PRE 0x014219 14220#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__A 0x1C2007914221#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__W 1514222#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__M 0x7FFF14223#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2__PRE 0x014224 14225#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__B 014226#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__W 714227#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__M 0x7F14228#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1TRAINGAIN2__PRE 0x014229 14230#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__B 814231#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__W 714232#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__M 0x7F0014233#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN2_FIRRCA1DATAGAIN2__PRE 0x014234 14235#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__A 0x1C2007A14236#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__W 1514237#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__M 0x7FFF14238#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3__PRE 0x014239 14240#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__B 014241#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__W 714242#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__M 0x7F14243#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1TRAINGAIN3__PRE 0x014244 14245#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__B 814246#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__W 714247#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__M 0x7F0014248#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN3_FIRRCA1DATAGAIN3__PRE 0x014249 14250#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__A 0x1C2007B14251#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__W 1514252#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__M 0x7FFF14253#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4__PRE 0x014254 14255#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__B 014256#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__W 714257#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__M 0x7F14258#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1TRAINGAIN4__PRE 0x014259 14260#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__B 814261#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__W 714262#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__M 0x7F0014263#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN4_FIRRCA1DATAGAIN4__PRE 0x014264 14265#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__A 0x1C2007C14266#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__W 1514267#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__M 0x7FFF14268#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5__PRE 0x014269 14270#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__B 014271#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__W 714272#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__M 0x7F14273#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1TRAINGAIN5__PRE 0x014274 14275#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__B 814276#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__W 714277#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__M 0x7F0014278#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN5_FIRRCA1DATAGAIN5__PRE 0x014279 14280#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__A 0x1C2007D14281#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__W 1514282#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__M 0x7FFF14283#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6__PRE 0x014284 14285#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__B 014286#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__W 714287#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__M 0x7F14288#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1TRAINGAIN6__PRE 0x014289 14290#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__B 814291#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__W 714292#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__M 0x7F0014293#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN6_FIRRCA1DATAGAIN6__PRE 0x014294 14295#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__A 0x1C2007E14296#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__W 1514297#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__M 0x7FFF14298#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7__PRE 0x014299 14300#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__B 014301#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__W 714302#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__M 0x7F14303#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1TRAINGAIN7__PRE 0x014304 14305#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__B 814306#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__W 714307#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__M 0x7F0014308#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN7_FIRRCA1DATAGAIN7__PRE 0x014309 14310#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__A 0x1C2007F14311#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__W 1514312#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__M 0x7FFF14313#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8__PRE 0x014314 14315#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__B 014316#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__W 714317#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__M 0x7F14318#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1TRAINGAIN8__PRE 0x014319 14320#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__B 814321#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__W 714322#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__M 0x7F0014323#define VSB_SYSCTRL_RAM0_FIRRCA1GAIN8_FIRRCA1DATAGAIN8__PRE 0x014324 14325#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A 0x1C3000014326#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__W 1514327#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__M 0x7FFF14328#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__PRE 0x014329 14330#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__B 014331#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__W 714332#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__M 0x7F14333#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1TRAINGAIN9__PRE 0x014334 14335#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__B 814336#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__W 714337#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__M 0x7F0014338#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN9_FIRRCA1DATAGAIN9__PRE 0x014339 14340#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__A 0x1C3000114341#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__W 1514342#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__M 0x7FFF14343#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10__PRE 0x014344 14345#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__B 014346#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__W 714347#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__M 0x7F14348#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1TRAINGAIN10__PRE 0x014349 14350#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__B 814351#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__W 714352#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__M 0x7F0014353#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN10_FIRRCA1DATAGAIN10__PRE 0x014354 14355#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__A 0x1C3000214356#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__W 1514357#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__M 0x7FFF14358#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11__PRE 0x014359 14360#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__B 014361#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__W 714362#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__M 0x7F14363#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1TRAINGAIN11__PRE 0x014364 14365#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__B 814366#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__W 714367#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__M 0x7F0014368#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN11_FIRRCA1DATAGAIN11__PRE 0x014369 14370#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__A 0x1C3000314371#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__W 1514372#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__M 0x7FFF14373#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12__PRE 0x014374 14375#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__B 014376#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__W 714377#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__M 0x7F14378#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1TRAINGAIN12__PRE 0x014379 14380#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__B 814381#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__W 714382#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__M 0x7F0014383#define VSB_SYSCTRL_RAM1_FIRRCA1GAIN12_FIRRCA1DATAGAIN12__PRE 0x014384 14385#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__A 0x1C3000414386#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__W 1514387#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__M 0x7FFF14388#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1__PRE 0x014389 14390#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__B 014391#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__W 714392#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__M 0x7F14393#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2TRAINGAIN1__PRE 0x014394 14395#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__B 814396#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__W 714397#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__M 0x7F0014398#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN1_FIRRCA2DATAGAIN1__PRE 0x014399 14400#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__A 0x1C3000514401#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__W 1514402#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__M 0x7FFF14403#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2__PRE 0x014404 14405#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__B 014406#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__W 714407#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__M 0x7F14408#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2TRAINGAIN2__PRE 0x014409 14410#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__B 814411#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__W 714412#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__M 0x7F0014413#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN2_FIRRCA2DATAGAIN2__PRE 0x014414 14415#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__A 0x1C3000614416#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__W 1514417#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__M 0x7FFF14418#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3__PRE 0x014419 14420#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__B 014421#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__W 714422#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__M 0x7F14423#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2TRAINGAIN3__PRE 0x014424 14425#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__B 814426#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__W 714427#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__M 0x7F0014428#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN3_FIRRCA2DATAGAIN3__PRE 0x014429 14430#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__A 0x1C3000714431#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__W 1514432#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__M 0x7FFF14433#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4__PRE 0x014434 14435#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__B 014436#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__W 714437#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__M 0x7F14438#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2TRAINGAIN4__PRE 0x014439 14440#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__B 814441#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__W 714442#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__M 0x7F0014443#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN4_FIRRCA2DATAGAIN4__PRE 0x014444 14445#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__A 0x1C3000814446#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__W 1514447#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__M 0x7FFF14448#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5__PRE 0x014449 14450#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__B 014451#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__W 714452#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__M 0x7F14453#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2TRAINGAIN5__PRE 0x014454 14455#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__B 814456#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__W 714457#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__M 0x7F0014458#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN5_FIRRCA2DATAGAIN5__PRE 0x014459 14460#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__A 0x1C3000914461#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__W 1514462#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__M 0x7FFF14463#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6__PRE 0x014464 14465#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__B 014466#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__W 714467#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__M 0x7F14468#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2TRAINGAIN6__PRE 0x014469 14470#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__B 814471#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__W 714472#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__M 0x7F0014473#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN6_FIRRCA2DATAGAIN6__PRE 0x014474 14475#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__A 0x1C3000A14476#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__W 1514477#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__M 0x7FFF14478#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7__PRE 0x014479 14480#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__B 014481#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__W 714482#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__M 0x7F14483#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2TRAINGAIN7__PRE 0x014484 14485#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__B 814486#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__W 714487#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__M 0x7F0014488#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN7_FIRRCA2DATAGAIN7__PRE 0x014489 14490#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__A 0x1C3000B14491#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__W 1514492#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__M 0x7FFF14493#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8__PRE 0x014494 14495#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__B 014496#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__W 714497#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__M 0x7F14498#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2TRAINGAIN8__PRE 0x014499 14500#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__B 814501#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__W 714502#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__M 0x7F0014503#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN8_FIRRCA2DATAGAIN8__PRE 0x014504 14505#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__A 0x1C3000C14506#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__W 1514507#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__M 0x7FFF14508#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9__PRE 0x014509 14510#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__B 014511#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__W 714512#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__M 0x7F14513#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2TRAINGAIN9__PRE 0x014514 14515#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__B 814516#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__W 714517#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__M 0x7F0014518#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN9_FIRRCA2DATAGAIN9__PRE 0x014519 14520#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__A 0x1C3000D14521#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__W 1514522#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__M 0x7FFF14523#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10__PRE 0x014524 14525#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__B 014526#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__W 714527#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__M 0x7F14528#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2TRAINGAIN10__PRE 0x014529 14530#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__B 814531#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__W 714532#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__M 0x7F0014533#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN10_FIRRCA2DATAGAIN10__PRE 0x014534 14535#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__A 0x1C3000E14536#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__W 1514537#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__M 0x7FFF14538#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11__PRE 0x014539 14540#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__B 014541#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__W 714542#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__M 0x7F14543#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2TRAINGAIN11__PRE 0x014544 14545#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__B 814546#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__W 714547#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__M 0x7F0014548#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN11_FIRRCA2DATAGAIN11__PRE 0x014549 14550#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__A 0x1C3000F14551#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__W 1514552#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__M 0x7FFF14553#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12__PRE 0x014554 14555#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__B 014556#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__W 714557#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__M 0x7F14558#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2TRAINGAIN12__PRE 0x014559 14560#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__B 814561#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__W 714562#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__M 0x7F0014563#define VSB_SYSCTRL_RAM1_FIRRCA2GAIN12_FIRRCA2DATAGAIN12__PRE 0x014564 14565#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__A 0x1C3001014566#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__W 1514567#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__M 0x7FFF14568#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1__PRE 0x014569 14570#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__B 014571#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__W 714572#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__M 0x7F14573#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1TRAINGAIN1__PRE 0x014574 14575#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__B 814576#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__W 714577#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__M 0x7F0014578#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN1_FIRDDM1DATAGAIN1__PRE 0x014579 14580#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__A 0x1C3001114581#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__W 1514582#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__M 0x7FFF14583#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2__PRE 0x014584 14585#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__B 014586#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__W 714587#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__M 0x7F14588#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1TRAINGAIN2__PRE 0x014589 14590#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__B 814591#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__W 714592#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__M 0x7F0014593#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN2_FIRDDM1DATAGAIN2__PRE 0x014594 14595#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__A 0x1C3001214596#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__W 1514597#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__M 0x7FFF14598#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3__PRE 0x014599 14600#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__B 014601#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__W 714602#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__M 0x7F14603#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1TRAINGAIN3__PRE 0x014604 14605#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__B 814606#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__W 714607#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__M 0x7F0014608#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN3_FIRDDM1DATAGAIN3__PRE 0x014609 14610#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__A 0x1C3001314611#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__W 1514612#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__M 0x7FFF14613#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4__PRE 0x014614 14615#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__B 014616#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__W 714617#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__M 0x7F14618#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1TRAINGAIN4__PRE 0x014619 14620#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__B 814621#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__W 714622#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__M 0x7F0014623#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN4_FIRDDM1DATAGAIN4__PRE 0x014624 14625#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__A 0x1C3001414626#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__W 1514627#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__M 0x7FFF14628#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5__PRE 0x014629 14630#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__B 014631#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__W 714632#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__M 0x7F14633#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1TRAINGAIN5__PRE 0x014634 14635#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__B 814636#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__W 714637#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__M 0x7F0014638#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN5_FIRDDM1DATAGAIN5__PRE 0x014639 14640#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__A 0x1C3001514641#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__W 1514642#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__M 0x7FFF14643#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6__PRE 0x014644 14645#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__B 014646#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__W 714647#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__M 0x7F14648#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1TRAINGAIN6__PRE 0x014649 14650#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__B 814651#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__W 714652#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__M 0x7F0014653#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN6_FIRDDM1DATAGAIN6__PRE 0x014654 14655#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__A 0x1C3001614656#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__W 1514657#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__M 0x7FFF14658#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7__PRE 0x014659 14660#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__B 014661#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__W 714662#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__M 0x7F14663#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1TRAINGAIN7__PRE 0x014664 14665#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__B 814666#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__W 714667#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__M 0x7F0014668#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN7_FIRDDM1DATAGAIN7__PRE 0x014669 14670#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__A 0x1C3001714671#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__W 1514672#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__M 0x7FFF14673#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8__PRE 0x014674 14675#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__B 014676#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__W 714677#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__M 0x7F14678#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1TRAINGAIN8__PRE 0x014679 14680#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__B 814681#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__W 714682#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__M 0x7F0014683#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN8_FIRDDM1DATAGAIN8__PRE 0x014684 14685#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__A 0x1C3001814686#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__W 1514687#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__M 0x7FFF14688#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9__PRE 0x014689 14690#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__B 014691#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__W 714692#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__M 0x7F14693#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1TRAINGAIN9__PRE 0x014694 14695#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__B 814696#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__W 714697#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__M 0x7F0014698#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN9_FIRDDM1DATAGAIN9__PRE 0x014699 14700#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__A 0x1C3001914701#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__W 1514702#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__M 0x7FFF14703#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10__PRE 0x014704 14705#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__B 014706#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__W 714707#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__M 0x7F14708#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1TRAINGAIN10__PRE 0x014709 14710#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__B 814711#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__W 714712#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__M 0x7F0014713#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN10_FIRDDM1DATAGAIN10__PRE 0x014714 14715#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__A 0x1C3001A14716#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__W 1514717#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__M 0x7FFF14718#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11__PRE 0x014719 14720#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__B 014721#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__W 714722#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__M 0x7F14723#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1TRAINGAIN11__PRE 0x014724 14725#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__B 814726#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__W 714727#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__M 0x7F0014728#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN11_FIRDDM1DATAGAIN11__PRE 0x014729 14730#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__A 0x1C3001B14731#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__W 1514732#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__M 0x7FFF14733#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12__PRE 0x014734 14735#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__B 014736#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__W 714737#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__M 0x7F14738#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1TRAINGAIN12__PRE 0x014739 14740#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__B 814741#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__W 714742#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__M 0x7F0014743#define VSB_SYSCTRL_RAM1_FIRDDM1GAIN12_FIRDDM1DATAGAIN12__PRE 0x014744 14745#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__A 0x1C3001C14746#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__W 1514747#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__M 0x7FFF14748#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1__PRE 0x014749 14750#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__B 014751#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__W 714752#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__M 0x7F14753#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2TRAINGAIN1__PRE 0x014754 14755#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__B 814756#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__W 714757#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__M 0x7F0014758#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN1_FIRDDM2DATAGAIN1__PRE 0x014759 14760#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__A 0x1C3001D14761#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__W 1514762#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__M 0x7FFF14763#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2__PRE 0x014764 14765#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__B 014766#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__W 714767#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__M 0x7F14768#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2TRAINGAIN2__PRE 0x014769 14770#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__B 814771#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__W 714772#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__M 0x7F0014773#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN2_FIRDDM2DATAGAIN2__PRE 0x014774 14775#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__A 0x1C3001E14776#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__W 1514777#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__M 0x7FFF14778#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3__PRE 0x014779 14780#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__B 014781#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__W 714782#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__M 0x7F14783#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2TRAINGAIN3__PRE 0x014784 14785#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__B 814786#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__W 714787#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__M 0x7F0014788#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN3_FIRDDM2DATAGAIN3__PRE 0x014789 14790#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__A 0x1C3001F14791#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__W 1514792#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__M 0x7FFF14793#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4__PRE 0x014794 14795#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__B 014796#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__W 714797#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__M 0x7F14798#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2TRAINGAIN4__PRE 0x014799 14800#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__B 814801#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__W 714802#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__M 0x7F0014803#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN4_FIRDDM2DATAGAIN4__PRE 0x014804 14805#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__A 0x1C3002014806#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__W 1514807#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__M 0x7FFF14808#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5__PRE 0x014809 14810#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__B 014811#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__W 714812#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__M 0x7F14813#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2TRAINGAIN5__PRE 0x014814 14815#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__B 814816#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__W 714817#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__M 0x7F0014818#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN5_FIRDDM2DATAGAIN5__PRE 0x014819 14820#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__A 0x1C3002114821#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__W 1514822#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__M 0x7FFF14823#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6__PRE 0x014824 14825#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__B 014826#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__W 714827#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__M 0x7F14828#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2TRAINGAIN6__PRE 0x014829 14830#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__B 814831#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__W 714832#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__M 0x7F0014833#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN6_FIRDDM2DATAGAIN6__PRE 0x014834 14835#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__A 0x1C3002214836#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__W 1514837#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__M 0x7FFF14838#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7__PRE 0x014839 14840#define VSB_SYSCTRL_RAM1_FIRDDM2GAIN7_FIRDDM2TRAINGAIN7__B 014841#define VSB_SYSCTRL_RAM1_FIRDDM2GAINFile truncated to the first 1 MiB.