998 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * drx3973d_map_firm.h4 *5 * Copyright (C) 2006-2007 Micronas6 */7 8#ifndef __DRX3973D_MAP__H__9#define __DRX3973D_MAP__H__10 11/*12 * Note: originally, this file contained 12000+ lines of data13 * Probably a few lines for every firwmare assembler instruction. However,14 * only a few defines were actually used. So, removed all uneeded lines.15 * If ever needed, the other lines can be easily obtained via git history.16 */17 18#define HI_COMM_EXEC__A 0x40000019#define HI_COMM_MB__A 0x40000220#define HI_CT_REG_COMM_STATE__A 0x41000121#define HI_RA_RAM_SRV_RES__A 0x42003122#define HI_RA_RAM_SRV_CMD__A 0x42003223#define HI_RA_RAM_SRV_CMD_RESET 0x224#define HI_RA_RAM_SRV_CMD_CONFIG 0x325#define HI_RA_RAM_SRV_CMD_EXECUTE 0x626#define HI_RA_RAM_SRV_RST_KEY__A 0x42003327#define HI_RA_RAM_SRV_RST_KEY_ACT 0x397328#define HI_RA_RAM_SRV_CFG_KEY__A 0x42003329#define HI_RA_RAM_SRV_CFG_DIV__A 0x42003430#define HI_RA_RAM_SRV_CFG_BDL__A 0x42003531#define HI_RA_RAM_SRV_CFG_WUP__A 0x42003632#define HI_RA_RAM_SRV_CFG_ACT__A 0x42003733#define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x134#define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x435#define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x036#define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x437#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x838#define HI_RA_RAM_USR_BEGIN__A 0x42004039#define HI_IF_RAM_TRP_BPT0__AX 0x43000040#define HI_IF_RAM_USR_BEGIN__A 0x43020041#define SC_COMM_EXEC__A 0x80000042#define SC_COMM_EXEC_CTL_STOP 0x043#define SC_COMM_STATE__A 0x80000144#define SC_RA_RAM_PARAM0__A 0x82004045#define SC_RA_RAM_PARAM1__A 0x82004146#define SC_RA_RAM_CMD_ADDR__A 0x82004247#define SC_RA_RAM_CMD__A 0x82004348#define SC_RA_RAM_CMD_PROC_START 0x149#define SC_RA_RAM_CMD_SET_PREF_PARAM 0x350#define SC_RA_RAM_CMD_GET_OP_PARAM 0x551#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x152#define SC_RA_RAM_LOCKTRACK_MIN 0x153#define SC_RA_RAM_OP_PARAM_MODE_2K 0x054#define SC_RA_RAM_OP_PARAM_MODE_8K 0x155#define SC_RA_RAM_OP_PARAM_GUARD_32 0x056#define SC_RA_RAM_OP_PARAM_GUARD_16 0x457#define SC_RA_RAM_OP_PARAM_GUARD_8 0x858#define SC_RA_RAM_OP_PARAM_GUARD_4 0xC59#define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x060#define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x1061#define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x2062#define SC_RA_RAM_OP_PARAM_HIER_NO 0x063#define SC_RA_RAM_OP_PARAM_HIER_A1 0x4064#define SC_RA_RAM_OP_PARAM_HIER_A2 0x8065#define SC_RA_RAM_OP_PARAM_HIER_A4 0xC066#define SC_RA_RAM_OP_PARAM_RATE_1_2 0x067#define SC_RA_RAM_OP_PARAM_RATE_2_3 0x20068#define SC_RA_RAM_OP_PARAM_RATE_3_4 0x40069#define SC_RA_RAM_OP_PARAM_RATE_5_6 0x60070#define SC_RA_RAM_OP_PARAM_RATE_7_8 0x80071#define SC_RA_RAM_OP_PARAM_PRIO_HI 0x072#define SC_RA_RAM_OP_PARAM_PRIO_LO 0x100073#define SC_RA_RAM_OP_AUTO_MODE__M 0x174#define SC_RA_RAM_OP_AUTO_GUARD__M 0x275#define SC_RA_RAM_OP_AUTO_CONST__M 0x476#define SC_RA_RAM_OP_AUTO_HIER__M 0x877#define SC_RA_RAM_OP_AUTO_RATE__M 0x1078#define SC_RA_RAM_LOCK__A 0x82004B79#define SC_RA_RAM_LOCK_DEMOD__M 0x180#define SC_RA_RAM_LOCK_FEC__M 0x281#define SC_RA_RAM_LOCK_MPEG__M 0x482#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C83#define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x184#define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D85#define SC_RA_RAM_CONFIG__A 0x82005086#define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x487#define SC_RA_RAM_CONFIG_FREQSCAN__M 0x1088#define SC_RA_RAM_CONFIG_SLAVE__M 0x2089#define SC_RA_RAM_IF_SAVE__AX 0x82008E90#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D191#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x992#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D293#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x494#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D395#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x10096#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D497#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x898#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D599#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8100#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6101#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200102#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7103#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9104#define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8105#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4106#define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9107#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100108#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA109#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB110#define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB111#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1112#define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC113#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40114#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD115#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8116#define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9117#define SC_RA_RAM_BAND__A 0x8200EC118#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4119#define SC_RA_RAM_LC_ABS_2K__PRE 0x1F120#define SC_RA_RAM_LC_ABS_8K__A 0x8200F5121#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F122#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6123#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4124#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB125#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5126#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF127#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5128#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E129#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5130#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A131#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6132#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB133#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5134#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F135#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5136#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197137#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5138#define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE139#define SC_RA_RAM_PROC_LOCKTRACK 0x0140#define FE_COMM_EXEC__A 0xC00000141#define FE_AD_REG_COMM_EXEC__A 0xC10000142#define FE_AD_REG_FDB_IN__A 0xC10012143#define FE_AD_REG_PD__A 0xC10013144#define FE_AD_REG_INVEXT__A 0xC10014145#define FE_AD_REG_CLKNEG__A 0xC10015146#define FE_AG_REG_COMM_EXEC__A 0xC20000147#define FE_AG_REG_AG_MODE_LOP__A 0xC20010148#define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10149#define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0150#define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10151#define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20152#define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0153#define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000154#define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0155#define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000156#define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000157#define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0158#define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000159#define FE_AG_REG_AG_MODE_HIP__A 0xC20011160#define FE_AG_REG_AG_PGA_MODE__A 0xC20012161#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0162#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1163#define FE_AG_REG_AG_AGC_SIO__A 0xC20013164#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2165#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0166#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2167#define FE_AG_REG_AG_PWD__A 0xC20015168#define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2169#define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0170#define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2171#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016172#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017173#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A174#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B175#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020176#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024177#define FE_AG_REG_EGC_SET_LVL__A 0xC20025178#define FE_AG_REG_EGC_SET_LVL__M 0x1FF179#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026180#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027181#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028182#define FE_AG_REG_EGC_FLA_INC__A 0xC20029183#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A184#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B185#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C186#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D187#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E188#define FE_AG_REG_PM1_AGC_WRI__A 0xC20030189#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF190#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031191#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032192#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033193#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034194#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035195#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF196#define FE_AG_REG_PM2_AGC_WRI__A 0xC20036197#define FE_AG_REG_IND_WIN__A 0xC2003C198#define FE_AG_REG_IND_THD_LOL__A 0xC2003D199#define FE_AG_REG_IND_THD_HIL__A 0xC2003E200#define FE_AG_REG_IND_DEL__A 0xC2003F201#define FE_AG_REG_IND_PD1_WRI__A 0xC20040202#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041203#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042204#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043205#define FE_AG_REG_PDC_RUR_CNT__A 0xC20044206#define FE_AG_REG_PDC_SET_LVL__A 0xC20045207#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046208#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047209#define FE_AG_REG_PDC_FLA_STP__A 0xC20048210#define FE_AG_REG_PDC_SLO_STP__A 0xC20049211#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A212#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B213#define FE_AG_REG_PDC_MAX__A 0xC2004C214#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D215#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E216#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F217#define FE_AG_REG_TGC_RUR_CNT__A 0xC20050218#define FE_AG_REG_TGC_SET_LVL__A 0xC20051219#define FE_AG_REG_TGC_SET_LVL__M 0x3F220#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052221#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053222#define FE_AG_REG_TGC_FLA_STP__A 0xC20054223#define FE_AG_REG_TGC_SLO_STP__A 0xC20055224#define FE_AG_REG_TGC_MAP_DAT__A 0xC20056225#define FE_AG_REG_FGA_AUR_CNT__A 0xC20057226#define FE_AG_REG_FGA_RUR_CNT__A 0xC20058227#define FE_AG_REG_FGM_WRI__A 0xC20061228#define FE_AG_REG_BGC_FGC_WRI__A 0xC20068229#define FE_AG_REG_BGC_CGC_WRI__A 0xC20069230#define FE_FS_REG_COMM_EXEC__A 0xC30000231#define FE_FS_REG_ADD_INC_LOP__A 0xC30010232#define FE_FD_REG_COMM_EXEC__A 0xC40000233#define FE_FD_REG_SCL__A 0xC40010234#define FE_FD_REG_MAX_LEV__A 0xC40011235#define FE_FD_REG_NR__A 0xC40012236#define FE_FD_REG_MEAS_VAL__A 0xC40014237#define FE_IF_REG_COMM_EXEC__A 0xC50000238#define FE_IF_REG_INCR0__A 0xC50010239#define FE_IF_REG_INCR0__W 16240#define FE_IF_REG_INCR0__M 0xFFFF241#define FE_IF_REG_INCR1__A 0xC50011242#define FE_IF_REG_INCR1__M 0xFF243#define FE_CF_REG_COMM_EXEC__A 0xC60000244#define FE_CF_REG_SCL__A 0xC60010245#define FE_CF_REG_MAX_LEV__A 0xC60011246#define FE_CF_REG_NR__A 0xC60012247#define FE_CF_REG_IMP_VAL__A 0xC60013248#define FE_CF_REG_MEAS_VAL__A 0xC60014249#define FE_CU_REG_COMM_EXEC__A 0xC70000250#define FE_CU_REG_FRM_CNT_RST__A 0xC70011251#define FE_CU_REG_FRM_CNT_STR__A 0xC70012252#define FT_COMM_EXEC__A 0x1000000253#define FT_REG_COMM_EXEC__A 0x1010000254#define CP_COMM_EXEC__A 0x1400000255#define CP_REG_COMM_EXEC__A 0x1410000256#define CP_REG_INTERVAL__A 0x1410011257#define CP_REG_BR_SPL_OFFSET__A 0x1410023258#define CP_REG_BR_STR_DEL__A 0x1410024259#define CP_REG_RT_ANG_INC0__A 0x1410030260#define CP_REG_RT_ANG_INC1__A 0x1410031261#define CP_REG_RT_DETECT_ENA__A 0x1410032262#define CP_REG_RT_DETECT_TRH__A 0x1410033263#define CP_REG_RT_EXP_MARG__A 0x141003E264#define CP_REG_AC_NEXP_OFFS__A 0x1410040265#define CP_REG_AC_AVER_POW__A 0x1410041266#define CP_REG_AC_MAX_POW__A 0x1410042267#define CP_REG_AC_WEIGHT_MAN__A 0x1410043268#define CP_REG_AC_WEIGHT_EXP__A 0x1410044269#define CP_REG_AC_AMP_MODE__A 0x1410047270#define CP_REG_AC_AMP_FIX__A 0x1410048271#define CP_REG_AC_ANG_MODE__A 0x141004A272#define CE_COMM_EXEC__A 0x1800000273#define CE_REG_COMM_EXEC__A 0x1810000274#define CE_REG_TAPSET__A 0x1810011275#define CE_REG_AVG_POW__A 0x1810012276#define CE_REG_MAX_POW__A 0x1810013277#define CE_REG_ATT__A 0x1810014278#define CE_REG_NRED__A 0x1810015279#define CE_REG_NE_ERR_SELECT__A 0x1810043280#define CE_REG_NE_TD_CAL__A 0x1810044281#define CE_REG_NE_MIXAVG__A 0x1810046282#define CE_REG_NE_NUPD_OFS__A 0x1810047283#define CE_REG_PE_NEXP_OFFS__A 0x1810050284#define CE_REG_PE_TIMESHIFT__A 0x1810051285#define CE_REG_TP_A0_TAP_NEW__A 0x1810064286#define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065287#define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066288#define CE_REG_TP_A1_TAP_NEW__A 0x1810068289#define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069290#define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A291#define CE_REG_TI_NEXP_OFFS__A 0x1810070292#define CE_REG_FI_SHT_INCR__A 0x1810090293#define CE_REG_FI_EXP_NORM__A 0x1810091294#define CE_REG_IR_INPUTSEL__A 0x18100A0295#define CE_REG_IR_STARTPOS__A 0x18100A1296#define CE_REG_IR_NEXP_THRES__A 0x18100A2297#define CE_REG_FR_TREAL00__A 0x1820010298#define CE_REG_FR_TIMAG00__A 0x1820011299#define CE_REG_FR_TREAL01__A 0x1820012300#define CE_REG_FR_TIMAG01__A 0x1820013301#define CE_REG_FR_TREAL02__A 0x1820014302#define CE_REG_FR_TIMAG02__A 0x1820015303#define CE_REG_FR_TREAL03__A 0x1820016304#define CE_REG_FR_TIMAG03__A 0x1820017305#define CE_REG_FR_TREAL04__A 0x1820018306#define CE_REG_FR_TIMAG04__A 0x1820019307#define CE_REG_FR_TREAL05__A 0x182001A308#define CE_REG_FR_TIMAG05__A 0x182001B309#define CE_REG_FR_TREAL06__A 0x182001C310#define CE_REG_FR_TIMAG06__A 0x182001D311#define CE_REG_FR_TREAL07__A 0x182001E312#define CE_REG_FR_TIMAG07__A 0x182001F313#define CE_REG_FR_TREAL08__A 0x1820020314#define CE_REG_FR_TIMAG08__A 0x1820021315#define CE_REG_FR_TREAL09__A 0x1820022316#define CE_REG_FR_TIMAG09__A 0x1820023317#define CE_REG_FR_TREAL10__A 0x1820024318#define CE_REG_FR_TIMAG10__A 0x1820025319#define CE_REG_FR_TREAL11__A 0x1820026320#define CE_REG_FR_TIMAG11__A 0x1820027321#define CE_REG_FR_MID_TAP__A 0x1820028322#define CE_REG_FR_SQS_G00__A 0x1820029323#define CE_REG_FR_SQS_G01__A 0x182002A324#define CE_REG_FR_SQS_G02__A 0x182002B325#define CE_REG_FR_SQS_G03__A 0x182002C326#define CE_REG_FR_SQS_G04__A 0x182002D327#define CE_REG_FR_SQS_G05__A 0x182002E328#define CE_REG_FR_SQS_G06__A 0x182002F329#define CE_REG_FR_SQS_G07__A 0x1820030330#define CE_REG_FR_SQS_G08__A 0x1820031331#define CE_REG_FR_SQS_G09__A 0x1820032332#define CE_REG_FR_SQS_G10__A 0x1820033333#define CE_REG_FR_SQS_G11__A 0x1820034334#define CE_REG_FR_SQS_G12__A 0x1820035335#define CE_REG_FR_RIO_G00__A 0x1820036336#define CE_REG_FR_RIO_G01__A 0x1820037337#define CE_REG_FR_RIO_G02__A 0x1820038338#define CE_REG_FR_RIO_G03__A 0x1820039339#define CE_REG_FR_RIO_G04__A 0x182003A340#define CE_REG_FR_RIO_G05__A 0x182003B341#define CE_REG_FR_RIO_G06__A 0x182003C342#define CE_REG_FR_RIO_G07__A 0x182003D343#define CE_REG_FR_RIO_G08__A 0x182003E344#define CE_REG_FR_RIO_G09__A 0x182003F345#define CE_REG_FR_RIO_G10__A 0x1820040346#define CE_REG_FR_MODE__A 0x1820041347#define CE_REG_FR_SQS_TRH__A 0x1820042348#define CE_REG_FR_RIO_GAIN__A 0x1820043349#define CE_REG_FR_BYPASS__A 0x1820044350#define CE_REG_FR_PM_SET__A 0x1820045351#define CE_REG_FR_ERR_SH__A 0x1820046352#define CE_REG_FR_MAN_SH__A 0x1820047353#define CE_REG_FR_TAP_SH__A 0x1820048354#define EQ_COMM_EXEC__A 0x1C00000355#define EQ_REG_COMM_EXEC__A 0x1C10000356#define EQ_REG_COMM_MB__A 0x1C10002357#define EQ_REG_IS_GAIN_MAN__A 0x1C10015358#define EQ_REG_IS_GAIN_EXP__A 0x1C10016359#define EQ_REG_IS_CLIP_EXP__A 0x1C10017360#define EQ_REG_SN_CEGAIN__A 0x1C1002A361#define EQ_REG_SN_OFFSET__A 0x1C1002B362#define EQ_REG_RC_SEL_CAR__A 0x1C10032363#define EQ_REG_RC_SEL_CAR_INIT 0x0364#define EQ_REG_RC_SEL_CAR_DIV_ON 0x1365#define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0366#define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2367#define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0368#define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8369#define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0370#define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20371#define EQ_REG_OT_CONST__A 0x1C10046372#define EQ_REG_OT_ALPHA__A 0x1C10047373#define EQ_REG_OT_QNT_THRES0__A 0x1C10048374#define EQ_REG_OT_QNT_THRES1__A 0x1C10049375#define EQ_REG_OT_CSI_STEP__A 0x1C1004A376#define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B377#define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061378#define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062379#define EC_SB_REG_COMM_EXEC__A 0x2010000380#define EC_SB_REG_TR_MODE__A 0x2010010381#define EC_SB_REG_TR_MODE_8K 0x0382#define EC_SB_REG_TR_MODE_2K 0x1383#define EC_SB_REG_CONST__A 0x2010011384#define EC_SB_REG_CONST_QPSK 0x0385#define EC_SB_REG_CONST_16QAM 0x1386#define EC_SB_REG_CONST_64QAM 0x2387#define EC_SB_REG_ALPHA__A 0x2010012388#define EC_SB_REG_PRIOR__A 0x2010013389#define EC_SB_REG_PRIOR_HI 0x0390#define EC_SB_REG_PRIOR_LO 0x1391#define EC_SB_REG_CSI_HI__A 0x2010014392#define EC_SB_REG_CSI_LO__A 0x2010015393#define EC_SB_REG_SMB_TGL__A 0x2010016394#define EC_SB_REG_SNR_HI__A 0x2010017395#define EC_SB_REG_SNR_MID__A 0x2010018396#define EC_SB_REG_SNR_LO__A 0x2010019397#define EC_SB_REG_SCALE_MSB__A 0x201001A398#define EC_SB_REG_SCALE_BIT2__A 0x201001B399#define EC_SB_REG_SCALE_LSB__A 0x201001C400#define EC_SB_REG_CSI_OFS__A 0x201001D401#define EC_VD_REG_COMM_EXEC__A 0x2090000402#define EC_VD_REG_FORCE__A 0x2090010403#define EC_VD_REG_SET_CODERATE__A 0x2090011404#define EC_VD_REG_SET_CODERATE_C1_2 0x0405#define EC_VD_REG_SET_CODERATE_C2_3 0x1406#define EC_VD_REG_SET_CODERATE_C3_4 0x2407#define EC_VD_REG_SET_CODERATE_C5_6 0x3408#define EC_VD_REG_SET_CODERATE_C7_8 0x4409#define EC_VD_REG_REQ_SMB_CNT__A 0x2090012410#define EC_VD_REG_RLK_ENA__A 0x2090014411#define EC_OD_REG_COMM_EXEC__A 0x2110000412#define EC_OD_REG_SYNC__A 0x2110010413#define EC_OD_DEINT_RAM__A 0x2120000414#define EC_RS_REG_COMM_EXEC__A 0x2130000415#define EC_RS_REG_REQ_PCK_CNT__A 0x2130010416#define EC_RS_REG_VAL__A 0x2130011417#define EC_RS_REG_VAL_PCK 0x1418#define EC_RS_EC_RAM__A 0x2140000419#define EC_OC_REG_COMM_EXEC__A 0x2150000420#define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1421#define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2422#define EC_OC_REG_COMM_INT_STA__A 0x2150007423#define EC_OC_REG_OC_MODE_LOP__A 0x2150010424#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1425#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0426#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1427#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4428#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0429#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80430#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80431#define EC_OC_REG_OC_MODE_HIP__A 0x2150011432#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10433#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200434#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0435#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200436#define EC_OC_REG_OC_MPG_SIO__A 0x2150012437#define EC_OC_REG_OC_MPG_SIO__M 0xFFF438#define EC_OC_REG_OC_MON_SIO__A 0x2150013439#define EC_OC_REG_DTO_INC_LOP__A 0x2150014440#define EC_OC_REG_DTO_INC_HIP__A 0x2150015441#define EC_OC_REG_SNC_ISC_LVL__A 0x2150016442#define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0443#define EC_OC_REG_TMD_TOP_MODE__A 0x215001D444#define EC_OC_REG_TMD_TOP_CNT__A 0x215001E445#define EC_OC_REG_TMD_HIL_MAR__A 0x215001F446#define EC_OC_REG_TMD_LOL_MAR__A 0x2150020447#define EC_OC_REG_TMD_CUR_CNT__A 0x2150021448#define EC_OC_REG_AVR_ASH_CNT__A 0x2150023449#define EC_OC_REG_AVR_BSH_CNT__A 0x2150024450#define EC_OC_REG_RCN_MODE__A 0x2150027451#define EC_OC_REG_RCN_CRA_LOP__A 0x2150028452#define EC_OC_REG_RCN_CRA_HIP__A 0x2150029453#define EC_OC_REG_RCN_CST_LOP__A 0x215002A454#define EC_OC_REG_RCN_CST_HIP__A 0x215002B455#define EC_OC_REG_RCN_SET_LVL__A 0x215002C456#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D457#define EC_OC_REG_RCN_CLP_LOP__A 0x2150032458#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033459#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034460#define EC_OC_REG_RCN_MAP_HIP__A 0x2150035461#define EC_OC_REG_OCR_MPG_UOS__A 0x2150036462#define EC_OC_REG_OCR_MPG_UOS__M 0xFFF463#define EC_OC_REG_OCR_MPG_UOS_INIT 0x0464#define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038465#define EC_OC_REG_OCR_MON_UOS__A 0x2150039466#define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1467#define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2468#define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4469#define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8470#define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10471#define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20472#define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40473#define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80474#define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100475#define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200476#define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400477#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800478#define EC_OC_REG_OCR_MON_WRI__A 0x215003A479#define EC_OC_REG_OCR_MON_WRI_INIT 0x0480#define EC_OC_REG_IPR_INV_MPG__A 0x2150045481#define CC_REG_OSC_MODE__A 0x2410010482#define CC_REG_OSC_MODE_M20 0x1483#define CC_REG_PLL_MODE__A 0x2410011484#define CC_REG_PLL_MODE_BYPASS_PLL 0x1485#define CC_REG_PLL_MODE_PUMP_CUR_12 0x14486#define CC_REG_REF_DIVIDE__A 0x2410012487#define CC_REG_PWD_MODE__A 0x2410015488#define CC_REG_PWD_MODE_DOWN_PLL 0x2489#define CC_REG_UPDATE__A 0x2410017490#define CC_REG_UPDATE_KEY 0x3973491#define CC_REG_JTAGID_L__A 0x2410019492#define LC_COMM_EXEC__A 0x2800000493#define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C494#define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A495#define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8496#define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060497#define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4498#define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061499#define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1500#define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068501#define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4502#define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069503#define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1504#define B_HI_COMM_EXEC__A 0x400000505#define B_HI_COMM_MB__A 0x400002506#define B_HI_CT_REG_COMM_STATE__A 0x410001507#define B_HI_RA_RAM_SRV_RES__A 0x420031508#define B_HI_RA_RAM_SRV_CMD__A 0x420032509#define B_HI_RA_RAM_SRV_CMD_RESET 0x2510#define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3511#define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6512#define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033513#define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973514#define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033515#define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034516#define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035517#define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036518#define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037519#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1520#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4521#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0522#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4523#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8524#define B_HI_RA_RAM_USR_BEGIN__A 0x420040525#define B_HI_IF_RAM_TRP_BPT0__AX 0x430000526#define B_HI_IF_RAM_USR_BEGIN__A 0x430200527#define B_SC_COMM_EXEC__A 0x800000528#define B_SC_COMM_EXEC_CTL_STOP 0x0529#define B_SC_COMM_STATE__A 0x800001530#define B_SC_RA_RAM_PARAM0__A 0x820040531#define B_SC_RA_RAM_PARAM1__A 0x820041532#define B_SC_RA_RAM_CMD_ADDR__A 0x820042533#define B_SC_RA_RAM_CMD__A 0x820043534#define B_SC_RA_RAM_CMD_PROC_START 0x1535#define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3536#define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5537#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1538#define B_SC_RA_RAM_LOCKTRACK_MIN 0x1539#define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0540#define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1541#define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0542#define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4543#define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8544#define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC545#define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0546#define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10547#define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20548#define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0549#define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40550#define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80551#define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0552#define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0553#define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200554#define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400555#define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600556#define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800557#define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0558#define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000559#define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1560#define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2561#define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4562#define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8563#define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10564#define B_SC_RA_RAM_LOCK__A 0x82004B565#define B_SC_RA_RAM_LOCK_DEMOD__M 0x1566#define B_SC_RA_RAM_LOCK_FEC__M 0x2567#define B_SC_RA_RAM_LOCK_MPEG__M 0x4568#define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C569#define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1570#define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D571#define B_SC_RA_RAM_CONFIG__A 0x820050572#define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4573#define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10574#define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20575#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200576#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400577#define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D578#define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E579#define B_SC_RA_RAM_IF_SAVE__AX 0x82008E580#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098581#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099582#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A583#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B584#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C585#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D586#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E587#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F588#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1589#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9590#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2591#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4592#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3593#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100594#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4595#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8596#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5597#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8598#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6599#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200600#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7601#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9602#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8603#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4604#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9605#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100606#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA607#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB608#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB609#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1610#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC611#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40612#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD613#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8614#define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9615#define B_SC_RA_RAM_BAND__A 0x8200EC616#define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4617#define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F618#define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5619#define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F620#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100621#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4622#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2623#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4624#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D625#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5626#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D627#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4628#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133629#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5630#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114631#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5632#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A633#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4634#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB635#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4636#define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE637#define B_SC_RA_RAM_PROC_LOCKTRACK 0x0638#define B_FE_COMM_EXEC__A 0xC00000639#define B_FE_AD_REG_COMM_EXEC__A 0xC10000640#define B_FE_AD_REG_FDB_IN__A 0xC10012641#define B_FE_AD_REG_PD__A 0xC10013642#define B_FE_AD_REG_INVEXT__A 0xC10014643#define B_FE_AD_REG_CLKNEG__A 0xC10015644#define B_FE_AG_REG_COMM_EXEC__A 0xC20000645#define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010646#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10647#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0648#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10649#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20650#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0651#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000652#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0653#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000654#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000655#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0656#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000657#define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011658#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8659#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0660#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8661#define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012662#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0663#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1664#define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013665#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2666#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0667#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2668#define B_FE_AG_REG_AG_PWD__A 0xC20015669#define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2670#define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0671#define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2672#define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016673#define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017674#define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A675#define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B676#define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020677#define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024678#define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025679#define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF680#define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026681#define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027682#define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028683#define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029684#define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A685#define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B686#define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C687#define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D688#define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E689#define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030690#define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF691#define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031692#define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032693#define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033694#define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034695#define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035696#define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF697#define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036698#define B_FE_AG_REG_IND_WIN__A 0xC2003C699#define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D700#define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E701#define B_FE_AG_REG_IND_DEL__A 0xC2003F702#define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040703#define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041704#define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042705#define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043706#define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044707#define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045708#define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046709#define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047710#define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048711#define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049712#define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A713#define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B714#define B_FE_AG_REG_PDC_MAX__A 0xC2004C715#define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D716#define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E717#define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F718#define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050719#define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051720#define B_FE_AG_REG_TGC_SET_LVL__M 0x3F721#define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052722#define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053723#define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054724#define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055725#define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056726#define B_FE_AG_REG_FGM_WRI__A 0xC20061727#define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068728#define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069729#define B_FE_FS_REG_COMM_EXEC__A 0xC30000730#define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010731#define B_FE_FD_REG_COMM_EXEC__A 0xC40000732#define B_FE_FD_REG_SCL__A 0xC40010733#define B_FE_FD_REG_MAX_LEV__A 0xC40011734#define B_FE_FD_REG_NR__A 0xC40012735#define B_FE_FD_REG_MEAS_VAL__A 0xC40014736#define B_FE_IF_REG_COMM_EXEC__A 0xC50000737#define B_FE_IF_REG_INCR0__A 0xC50010738#define B_FE_IF_REG_INCR0__W 16739#define B_FE_IF_REG_INCR0__M 0xFFFF740#define B_FE_IF_REG_INCR1__A 0xC50011741#define B_FE_IF_REG_INCR1__M 0xFF742#define B_FE_CF_REG_COMM_EXEC__A 0xC60000743#define B_FE_CF_REG_SCL__A 0xC60010744#define B_FE_CF_REG_MAX_LEV__A 0xC60011745#define B_FE_CF_REG_NR__A 0xC60012746#define B_FE_CF_REG_IMP_VAL__A 0xC60013747#define B_FE_CF_REG_MEAS_VAL__A 0xC60014748#define B_FE_CU_REG_COMM_EXEC__A 0xC70000749#define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011750#define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012751#define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020752#define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021753#define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027754#define B_FT_COMM_EXEC__A 0x1000000755#define B_FT_REG_COMM_EXEC__A 0x1010000756#define B_CP_COMM_EXEC__A 0x1400000757#define B_CP_REG_COMM_EXEC__A 0x1410000758#define B_CP_REG_INTERVAL__A 0x1410011759#define B_CP_REG_BR_SPL_OFFSET__A 0x1410023760#define B_CP_REG_BR_STR_DEL__A 0x1410024761#define B_CP_REG_RT_ANG_INC0__A 0x1410030762#define B_CP_REG_RT_ANG_INC1__A 0x1410031763#define B_CP_REG_RT_DETECT_TRH__A 0x1410033764#define B_CP_REG_AC_NEXP_OFFS__A 0x1410040765#define B_CP_REG_AC_AVER_POW__A 0x1410041766#define B_CP_REG_AC_MAX_POW__A 0x1410042767#define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043768#define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044769#define B_CP_REG_AC_AMP_MODE__A 0x1410047770#define B_CP_REG_AC_AMP_FIX__A 0x1410048771#define B_CP_REG_AC_ANG_MODE__A 0x141004A772#define B_CE_COMM_EXEC__A 0x1800000773#define B_CE_REG_COMM_EXEC__A 0x1810000774#define B_CE_REG_TAPSET__A 0x1810011775#define B_CE_REG_AVG_POW__A 0x1810012776#define B_CE_REG_MAX_POW__A 0x1810013777#define B_CE_REG_ATT__A 0x1810014778#define B_CE_REG_NRED__A 0x1810015779#define B_CE_REG_NE_ERR_SELECT__A 0x1810043780#define B_CE_REG_NE_TD_CAL__A 0x1810044781#define B_CE_REG_NE_MIXAVG__A 0x1810046782#define B_CE_REG_NE_NUPD_OFS__A 0x1810047783#define B_CE_REG_PE_NEXP_OFFS__A 0x1810050784#define B_CE_REG_PE_TIMESHIFT__A 0x1810051785#define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064786#define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065787#define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066788#define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068789#define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069790#define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A791#define B_CE_REG_TI_PHN_ENABLE__A 0x1810073792#define B_CE_REG_FI_SHT_INCR__A 0x1810090793#define B_CE_REG_FI_EXP_NORM__A 0x1810091794#define B_CE_REG_IR_INPUTSEL__A 0x18100A0795#define B_CE_REG_IR_STARTPOS__A 0x18100A1796#define B_CE_REG_IR_NEXP_THRES__A 0x18100A2797#define B_CE_REG_FR_TREAL00__A 0x1820010798#define B_CE_REG_FR_TIMAG00__A 0x1820011799#define B_CE_REG_FR_TREAL01__A 0x1820012800#define B_CE_REG_FR_TIMAG01__A 0x1820013801#define B_CE_REG_FR_TREAL02__A 0x1820014802#define B_CE_REG_FR_TIMAG02__A 0x1820015803#define B_CE_REG_FR_TREAL03__A 0x1820016804#define B_CE_REG_FR_TIMAG03__A 0x1820017805#define B_CE_REG_FR_TREAL04__A 0x1820018806#define B_CE_REG_FR_TIMAG04__A 0x1820019807#define B_CE_REG_FR_TREAL05__A 0x182001A808#define B_CE_REG_FR_TIMAG05__A 0x182001B809#define B_CE_REG_FR_TREAL06__A 0x182001C810#define B_CE_REG_FR_TIMAG06__A 0x182001D811#define B_CE_REG_FR_TREAL07__A 0x182001E812#define B_CE_REG_FR_TIMAG07__A 0x182001F813#define B_CE_REG_FR_TREAL08__A 0x1820020814#define B_CE_REG_FR_TIMAG08__A 0x1820021815#define B_CE_REG_FR_TREAL09__A 0x1820022816#define B_CE_REG_FR_TIMAG09__A 0x1820023817#define B_CE_REG_FR_TREAL10__A 0x1820024818#define B_CE_REG_FR_TIMAG10__A 0x1820025819#define B_CE_REG_FR_TREAL11__A 0x1820026820#define B_CE_REG_FR_TIMAG11__A 0x1820027821#define B_CE_REG_FR_MID_TAP__A 0x1820028822#define B_CE_REG_FR_SQS_G00__A 0x1820029823#define B_CE_REG_FR_SQS_G01__A 0x182002A824#define B_CE_REG_FR_SQS_G02__A 0x182002B825#define B_CE_REG_FR_SQS_G03__A 0x182002C826#define B_CE_REG_FR_SQS_G04__A 0x182002D827#define B_CE_REG_FR_SQS_G05__A 0x182002E828#define B_CE_REG_FR_SQS_G06__A 0x182002F829#define B_CE_REG_FR_SQS_G07__A 0x1820030830#define B_CE_REG_FR_SQS_G08__A 0x1820031831#define B_CE_REG_FR_SQS_G09__A 0x1820032832#define B_CE_REG_FR_SQS_G10__A 0x1820033833#define B_CE_REG_FR_SQS_G11__A 0x1820034834#define B_CE_REG_FR_SQS_G12__A 0x1820035835#define B_CE_REG_FR_RIO_G00__A 0x1820036836#define B_CE_REG_FR_RIO_G01__A 0x1820037837#define B_CE_REG_FR_RIO_G02__A 0x1820038838#define B_CE_REG_FR_RIO_G03__A 0x1820039839#define B_CE_REG_FR_RIO_G04__A 0x182003A840#define B_CE_REG_FR_RIO_G05__A 0x182003B841#define B_CE_REG_FR_RIO_G06__A 0x182003C842#define B_CE_REG_FR_RIO_G07__A 0x182003D843#define B_CE_REG_FR_RIO_G08__A 0x182003E844#define B_CE_REG_FR_RIO_G09__A 0x182003F845#define B_CE_REG_FR_RIO_G10__A 0x1820040846#define B_CE_REG_FR_MODE__A 0x1820041847#define B_CE_REG_FR_SQS_TRH__A 0x1820042848#define B_CE_REG_FR_RIO_GAIN__A 0x1820043849#define B_CE_REG_FR_BYPASS__A 0x1820044850#define B_CE_REG_FR_PM_SET__A 0x1820045851#define B_CE_REG_FR_ERR_SH__A 0x1820046852#define B_CE_REG_FR_MAN_SH__A 0x1820047853#define B_CE_REG_FR_TAP_SH__A 0x1820048854#define B_EQ_COMM_EXEC__A 0x1C00000855#define B_EQ_REG_COMM_EXEC__A 0x1C10000856#define B_EQ_REG_COMM_MB__A 0x1C10002857#define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015858#define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016859#define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017860#define B_EQ_REG_SN_CEGAIN__A 0x1C1002A861#define B_EQ_REG_SN_OFFSET__A 0x1C1002B862#define B_EQ_REG_RC_SEL_CAR__A 0x1C10032863#define B_EQ_REG_RC_SEL_CAR_INIT 0x2864#define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1865#define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0866#define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2867#define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0868#define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8869#define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0870#define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20871#define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80872#define B_EQ_REG_OT_CONST__A 0x1C10046873#define B_EQ_REG_OT_ALPHA__A 0x1C10047874#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048875#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049876#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A877#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B878#define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061879#define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062880#define B_EC_SB_REG_COMM_EXEC__A 0x2010000881#define B_EC_SB_REG_TR_MODE__A 0x2010010882#define B_EC_SB_REG_TR_MODE_8K 0x0883#define B_EC_SB_REG_TR_MODE_2K 0x1884#define B_EC_SB_REG_CONST__A 0x2010011885#define B_EC_SB_REG_CONST_QPSK 0x0886#define B_EC_SB_REG_CONST_16QAM 0x1887#define B_EC_SB_REG_CONST_64QAM 0x2888#define B_EC_SB_REG_ALPHA__A 0x2010012889#define B_EC_SB_REG_PRIOR__A 0x2010013890#define B_EC_SB_REG_PRIOR_HI 0x0891#define B_EC_SB_REG_PRIOR_LO 0x1892#define B_EC_SB_REG_CSI_HI__A 0x2010014893#define B_EC_SB_REG_CSI_LO__A 0x2010015894#define B_EC_SB_REG_SMB_TGL__A 0x2010016895#define B_EC_SB_REG_SNR_HI__A 0x2010017896#define B_EC_SB_REG_SNR_MID__A 0x2010018897#define B_EC_SB_REG_SNR_LO__A 0x2010019898#define B_EC_SB_REG_SCALE_MSB__A 0x201001A899#define B_EC_SB_REG_SCALE_BIT2__A 0x201001B900#define B_EC_SB_REG_SCALE_LSB__A 0x201001C901#define B_EC_SB_REG_CSI_OFS0__A 0x201001D902#define B_EC_SB_REG_CSI_OFS1__A 0x201001E903#define B_EC_SB_REG_CSI_OFS2__A 0x201001F904#define B_EC_VD_REG_COMM_EXEC__A 0x2090000905#define B_EC_VD_REG_FORCE__A 0x2090010906#define B_EC_VD_REG_SET_CODERATE__A 0x2090011907#define B_EC_VD_REG_SET_CODERATE_C1_2 0x0908#define B_EC_VD_REG_SET_CODERATE_C2_3 0x1909#define B_EC_VD_REG_SET_CODERATE_C3_4 0x2910#define B_EC_VD_REG_SET_CODERATE_C5_6 0x3911#define B_EC_VD_REG_SET_CODERATE_C7_8 0x4912#define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012913#define B_EC_VD_REG_RLK_ENA__A 0x2090014914#define B_EC_OD_REG_COMM_EXEC__A 0x2110000915#define B_EC_OD_REG_SYNC__A 0x2110664916#define B_EC_OD_DEINT_RAM__A 0x2120000917#define B_EC_RS_REG_COMM_EXEC__A 0x2130000918#define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010919#define B_EC_RS_REG_VAL__A 0x2130011920#define B_EC_RS_REG_VAL_PCK 0x1921#define B_EC_RS_EC_RAM__A 0x2140000922#define B_EC_OC_REG_COMM_EXEC__A 0x2150000923#define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1924#define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2925#define B_EC_OC_REG_COMM_INT_STA__A 0x2150007926#define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010927#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1928#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0929#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1930#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4931#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0932#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80933#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80934#define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011935#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10936#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200937#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0938#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200939#define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012940#define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF941#define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014942#define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015943#define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016944#define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0945#define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D946#define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E947#define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F948#define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020949#define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021950#define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023951#define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024952#define B_EC_OC_REG_RCN_MODE__A 0x2150027953#define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028954#define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029955#define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A956#define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B957#define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C958#define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D959#define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032960#define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033961#define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034962#define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035963#define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036964#define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF965#define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0966#define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038967#define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045968#define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047969#define B_EC_OC_REG_DTO_PER__A 0x2150048970#define B_EC_OC_REG_DTO_BUR__A 0x2150049971#define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A972#define B_CC_REG_OSC_MODE__A 0x2410010973#define B_CC_REG_OSC_MODE_M20 0x1974#define B_CC_REG_PLL_MODE__A 0x2410011975#define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1976#define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14977#define B_CC_REG_REF_DIVIDE__A 0x2410012978#define B_CC_REG_PWD_MODE__A 0x2410015979#define B_CC_REG_PWD_MODE_DOWN_PLL 0x2980#define B_CC_REG_UPDATE__A 0x2410017981#define B_CC_REG_UPDATE_KEY 0x3973982#define B_CC_REG_JTAGID_L__A 0x2410019983#define B_CC_REG_DIVERSITY__A 0x241001B984#define B_LC_COMM_EXEC__A 0x2800000985#define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C986#define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A987#define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8988#define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060989#define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4990#define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061991#define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1992#define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068993#define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4994#define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069995#define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1996 997#endif998