456 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2#define AUD_COMM_EXEC__A 0x10000003#define AUD_COMM_EXEC_STOP 0x04#define FEC_COMM_EXEC__A 0x1C000005#define FEC_COMM_EXEC_STOP 0x06#define FEC_COMM_EXEC_ACTIVE 0x17#define FEC_DI_COMM_EXEC__A 0x1C200008#define FEC_DI_COMM_EXEC_STOP 0x09#define FEC_DI_INPUT_CTL__A 0x1C2001610#define FEC_RS_COMM_EXEC__A 0x1C3000011#define FEC_RS_COMM_EXEC_STOP 0x012#define FEC_RS_MEASUREMENT_PERIOD__A 0x1C3001213#define FEC_RS_MEASUREMENT_PRESCALE__A 0x1C3001314#define FEC_RS_NR_BIT_ERRORS__A 0x1C3001415#define FEC_OC_MODE__A 0x1C4001116#define FEC_OC_MODE_PARITY__M 0x117#define FEC_OC_DTO_MODE__A 0x1C4001418#define FEC_OC_DTO_MODE_DYNAMIC__M 0x119#define FEC_OC_DTO_MODE_OFFSET_ENABLE__M 0x420#define FEC_OC_DTO_PERIOD__A 0x1C4001521#define FEC_OC_DTO_BURST_LEN__A 0x1C4001822#define FEC_OC_FCT_MODE__A 0x1C4001A23#define FEC_OC_FCT_MODE__PRE 0x024#define FEC_OC_FCT_MODE_RAT_ENA__M 0x125#define FEC_OC_FCT_MODE_VIRT_ENA__M 0x226#define FEC_OC_TMD_MODE__A 0x1C4001E27#define FEC_OC_TMD_COUNT__A 0x1C4001F28#define FEC_OC_TMD_HI_MARGIN__A 0x1C4002029#define FEC_OC_TMD_LO_MARGIN__A 0x1C4002130#define FEC_OC_TMD_INT_UPD_RATE__A 0x1C4002331#define FEC_OC_AVR_PARM_A__A 0x1C4002632#define FEC_OC_AVR_PARM_B__A 0x1C4002733#define FEC_OC_RCN_GAIN__A 0x1C4002E34#define FEC_OC_RCN_CTL_RATE_LO__A 0x1C4003035#define FEC_OC_RCN_CTL_STEP_LO__A 0x1C4003236#define FEC_OC_RCN_CTL_STEP_HI__A 0x1C4003337#define FEC_OC_SNC_MODE__A 0x1C4004038#define FEC_OC_SNC_MODE_SHUTDOWN__M 0x1039#define FEC_OC_SNC_LWM__A 0x1C4004140#define FEC_OC_SNC_HWM__A 0x1C4004241#define FEC_OC_SNC_UNLOCK__A 0x1C4004342#define FEC_OC_SNC_FAIL_PERIOD__A 0x1C4004643#define FEC_OC_IPR_MODE__A 0x1C4004844#define FEC_OC_IPR_MODE_SERIAL__M 0x145#define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M 0x446#define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M 0x1047#define FEC_OC_IPR_INVERT__A 0x1C4004948#define FEC_OC_IPR_INVERT_MD0__M 0x149#define FEC_OC_IPR_INVERT_MD1__M 0x250#define FEC_OC_IPR_INVERT_MD2__M 0x451#define FEC_OC_IPR_INVERT_MD3__M 0x852#define FEC_OC_IPR_INVERT_MD4__M 0x1053#define FEC_OC_IPR_INVERT_MD5__M 0x2054#define FEC_OC_IPR_INVERT_MD6__M 0x4055#define FEC_OC_IPR_INVERT_MD7__M 0x8056#define FEC_OC_IPR_INVERT_MERR__M 0x10057#define FEC_OC_IPR_INVERT_MSTRT__M 0x20058#define FEC_OC_IPR_INVERT_MVAL__M 0x40059#define FEC_OC_IPR_INVERT_MCLK__M 0x80060#define FEC_OC_OCR_INVERT__A 0x1C4005261#define IQM_COMM_EXEC__A 0x180000062#define IQM_COMM_EXEC_B_STOP 0x063#define IQM_COMM_EXEC_B_ACTIVE 0x164#define IQM_FS_RATE_OFS_LO__A 0x182001065#define IQM_FS_ADJ_SEL__A 0x182001466#define IQM_FS_ADJ_SEL_B_OFF 0x067#define IQM_FS_ADJ_SEL_B_QAM 0x168#define IQM_FS_ADJ_SEL_B_VSB 0x269#define IQM_FD_RATESEL__A 0x183001070#define IQM_RC_RATE_OFS_LO__A 0x184001071#define IQM_RC_RATE_OFS_LO__W 1672#define IQM_RC_RATE_OFS_LO__M 0xFFFF73#define IQM_RC_RATE_OFS_HI__M 0xFF74#define IQM_RC_ADJ_SEL__A 0x184001475#define IQM_RC_ADJ_SEL_B_OFF 0x076#define IQM_RC_ADJ_SEL_B_QAM 0x177#define IQM_RC_ADJ_SEL_B_VSB 0x278#define IQM_RC_STRETCH__A 0x184001679#define IQM_CF_COMM_INT_MSK__A 0x186000680#define IQM_CF_SYMMETRIC__A 0x186001081#define IQM_CF_MIDTAP__A 0x186001182#define IQM_CF_MIDTAP_RE__B 083#define IQM_CF_MIDTAP_IM__B 184#define IQM_CF_OUT_ENA__A 0x186001285#define IQM_CF_OUT_ENA_QAM__B 186#define IQM_CF_OUT_ENA_OFDM__M 0x487#define IQM_CF_ADJ_SEL__A 0x186001388#define IQM_CF_SCALE__A 0x186001489#define IQM_CF_SCALE_SH__A 0x186001590#define IQM_CF_SCALE_SH__PRE 0x091#define IQM_CF_POW_MEAS_LEN__A 0x186001792#define IQM_CF_DS_ENA__A 0x186001993#define IQM_CF_TAP_RE0__A 0x186002094#define IQM_CF_TAP_IM0__A 0x186004095#define IQM_CF_CLP_VAL__A 0x186006096#define IQM_CF_DATATH__A 0x186006197#define IQM_CF_PKDTH__A 0x186006298#define IQM_CF_WND_LEN__A 0x186006399#define IQM_CF_DET_LCT__A 0x1860064100#define IQM_CF_BYPASSDET__A 0x1860067101#define IQM_AF_COMM_EXEC__A 0x1870000102#define IQM_AF_COMM_EXEC_ACTIVE 0x1103#define IQM_AF_CLKNEG__A 0x1870012104#define IQM_AF_CLKNEG_CLKNEGDATA__M 0x2105#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS 0x0106#define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG 0x2107#define IQM_AF_START_LOCK__A 0x187001B108#define IQM_AF_PHASE0__A 0x187001C109#define IQM_AF_PHASE1__A 0x187001D110#define IQM_AF_PHASE2__A 0x187001E111#define IQM_AF_CLP_LEN__A 0x1870023112#define IQM_AF_CLP_TH__A 0x1870024113#define IQM_AF_SNS_LEN__A 0x1870026114#define IQM_AF_AGC_IF__A 0x1870028115#define IQM_AF_AGC_RF__A 0x1870029116#define IQM_AF_PDREF__A 0x187002B117#define IQM_AF_PDREF__M 0x1F118#define IQM_AF_STDBY__A 0x187002C119#define IQM_AF_STDBY_STDBY_ADC_STANDBY 0x2120#define IQM_AF_STDBY_STDBY_AMP_STANDBY 0x4121#define IQM_AF_STDBY_STDBY_PD_STANDBY 0x8122#define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY 0x10123#define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY 0x20124#define IQM_AF_AMUX__A 0x187002D125#define IQM_AF_AMUX_SIGNAL2ADC 0x1126#define IQM_AF_UPD_SEL__A 0x187002F127#define IQM_AF_INC_LCT__A 0x1870034128#define IQM_AF_INC_BYPASS__A 0x1870036129#define OFDM_CP_COMM_EXEC__A 0x2800000130#define OFDM_CP_COMM_EXEC_STOP 0x0131#define OFDM_EC_SB_PRIOR__A 0x3410013132#define OFDM_EC_SB_PRIOR_HI 0x0133#define OFDM_EC_SB_PRIOR_LO 0x1134#define OFDM_EC_VD_ERR_BIT_CNT__A 0x3420017135#define OFDM_EC_VD_IN_BIT_CNT__A 0x3420018136#define OFDM_EQ_TOP_TD_TPS_CONST__A 0x3010054137#define OFDM_EQ_TOP_TD_TPS_CONST__M 0x3138#define OFDM_EQ_TOP_TD_TPS_CONST_64QAM 0x2139#define OFDM_EQ_TOP_TD_TPS_CODE_HP__A 0x3010056140#define OFDM_EQ_TOP_TD_TPS_CODE_HP__M 0x7141#define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 0x4142#define OFDM_EQ_TOP_TD_SQR_ERR_I__A 0x301005E143#define OFDM_EQ_TOP_TD_SQR_ERR_Q__A 0x301005F144#define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A 0x3010060145#define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A 0x3010061146#define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A 0x3010062147#define OFDM_LC_COMM_EXEC__A 0x3800000148#define OFDM_LC_COMM_EXEC_STOP 0x0149#define OFDM_SC_COMM_EXEC__A 0x3C00000150#define OFDM_SC_COMM_EXEC_STOP 0x0151#define OFDM_SC_COMM_STATE__A 0x3C00001152#define OFDM_SC_RA_RAM_PARAM0__A 0x3C20040153#define OFDM_SC_RA_RAM_PARAM1__A 0x3C20041154#define OFDM_SC_RA_RAM_CMD_ADDR__A 0x3C20042155#define OFDM_SC_RA_RAM_CMD__A 0x3C20043156#define OFDM_SC_RA_RAM_CMD_NULL 0x0157#define OFDM_SC_RA_RAM_CMD_PROC_START 0x1158#define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3159#define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4160#define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM 0x5161#define OFDM_SC_RA_RAM_CMD_USER_IO 0x6162#define OFDM_SC_RA_RAM_CMD_SET_TIMER 0x7163#define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8164#define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1165#define OFDM_SC_RA_RAM_LOCKTRACK_MIN 0x1166#define OFDM_SC_RA_RAM_OP_PARAM__A 0x3C20048167#define OFDM_SC_RA_RAM_OP_PARAM_MODE__M 0x3168#define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K 0x0169#define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K 0x1170#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 0x0171#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 0x4172#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 0x8173#define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 0xC174#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0175#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10176#define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20177#define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO 0x0178#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 0x40179#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 0x80180#define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0181#define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0182#define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200183#define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400184#define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600185#define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800186#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0187#define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000188#define OFDM_SC_RA_RAM_OP_AUTO_MODE__M 0x1189#define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M 0x2190#define OFDM_SC_RA_RAM_OP_AUTO_CONST__M 0x4191#define OFDM_SC_RA_RAM_OP_AUTO_HIER__M 0x8192#define OFDM_SC_RA_RAM_OP_AUTO_RATE__M 0x10193#define OFDM_SC_RA_RAM_LOCK__A 0x3C2004B194#define OFDM_SC_RA_RAM_LOCK_DEMOD__M 0x1195#define OFDM_SC_RA_RAM_LOCK_FEC__M 0x2196#define OFDM_SC_RA_RAM_LOCK_MPEG__M 0x4197#define OFDM_SC_RA_RAM_LOCK_NODVBT__M 0x8198#define OFDM_SC_RA_RAM_BE_OPT_DELAY__A 0x3C2004D199#define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x3C2004E200#define OFDM_SC_RA_RAM_ECHO_THRES__A 0x3C2004F201#define OFDM_SC_RA_RAM_ECHO_THRES_8K__B 0202#define OFDM_SC_RA_RAM_ECHO_THRES_8K__M 0xFF203#define OFDM_SC_RA_RAM_ECHO_THRES_2K__B 8204#define OFDM_SC_RA_RAM_ECHO_THRES_2K__M 0xFF00205#define OFDM_SC_RA_RAM_CONFIG__A 0x3C20050206#define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M 0x800207#define OFDM_SC_RA_RAM_FR_THRES_8K__A 0x3C2007D208#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x3C200E0209#define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x3C200E1210#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x3C200E3211#define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x3C200E4212#define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A 0x3C200F8213#define QAM_COMM_EXEC__A 0x1400000214#define QAM_COMM_EXEC_STOP 0x0215#define QAM_COMM_EXEC_ACTIVE 0x1216#define QAM_TOP_ANNEX_A 0x0217#define QAM_TOP_ANNEX_C 0x2218#define QAM_SL_ERR_POWER__A 0x1430017219#define QAM_DQ_QUAL_FUN0__A 0x1440018220#define QAM_DQ_QUAL_FUN1__A 0x1440019221#define QAM_DQ_QUAL_FUN2__A 0x144001A222#define QAM_DQ_QUAL_FUN3__A 0x144001B223#define QAM_DQ_QUAL_FUN4__A 0x144001C224#define QAM_DQ_QUAL_FUN5__A 0x144001D225#define QAM_LC_MODE__A 0x1450010226#define QAM_LC_QUAL_TAB0__A 0x1450018227#define QAM_LC_QUAL_TAB1__A 0x1450019228#define QAM_LC_QUAL_TAB2__A 0x145001A229#define QAM_LC_QUAL_TAB3__A 0x145001B230#define QAM_LC_QUAL_TAB4__A 0x145001C231#define QAM_LC_QUAL_TAB5__A 0x145001D232#define QAM_LC_QUAL_TAB6__A 0x145001E233#define QAM_LC_QUAL_TAB8__A 0x145001F234#define QAM_LC_QUAL_TAB9__A 0x1450020235#define QAM_LC_QUAL_TAB10__A 0x1450021236#define QAM_LC_QUAL_TAB12__A 0x1450022237#define QAM_LC_QUAL_TAB15__A 0x1450023238#define QAM_LC_QUAL_TAB16__A 0x1450024239#define QAM_LC_QUAL_TAB20__A 0x1450025240#define QAM_LC_QUAL_TAB25__A 0x1450026241#define QAM_LC_LPF_FACTORP__A 0x1450028242#define QAM_LC_LPF_FACTORI__A 0x1450029243#define QAM_LC_RATE_LIMIT__A 0x145002A244#define QAM_LC_SYMBOL_FREQ__A 0x145002B245#define QAM_SY_TIMEOUT__A 0x1470011246#define QAM_SY_TIMEOUT__PRE 0x3A98247#define QAM_SY_SYNC_LWM__A 0x1470012248#define QAM_SY_SYNC_AWM__A 0x1470013249#define QAM_SY_SYNC_HWM__A 0x1470014250#define QAM_SY_SP_INV__A 0x1470017251#define QAM_SY_SP_INV_SPECTRUM_INV_DIS 0x0252#define SCU_COMM_EXEC__A 0x800000253#define SCU_COMM_EXEC_STOP 0x0254#define SCU_COMM_EXEC_ACTIVE 0x1255#define SCU_COMM_EXEC_HOLD 0x2256#define SCU_RAM_DRIVER_DEBUG__A 0x831EBF257#define SCU_RAM_QAM_FSM_STEP_PERIOD__A 0x831EC4258#define SCU_RAM_GPIO__A 0x831EC7259#define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE 0x0260#define SCU_RAM_AGC_CLP_CTRL_MODE__A 0x831EC8261#define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A 0x831ECB262#define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A 0x831F05263#define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A 0x831F15264#define SCU_RAM_AGC_KI_CYCLEN__A 0x831F17265#define SCU_RAM_AGC_SNS_CYCLEN__A 0x831F18266#define SCU_RAM_AGC_RF_SNS_DEV_MAX__A 0x831F19267#define SCU_RAM_AGC_RF_SNS_DEV_MIN__A 0x831F1A268#define SCU_RAM_AGC_RF_MAX__A 0x831F1B269#define SCU_RAM_AGC_CONFIG__A 0x831F24270#define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M 0x1271#define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M 0x2272#define SCU_RAM_AGC_CONFIG_INV_IF_POL__M 0x100273#define SCU_RAM_AGC_CONFIG_INV_RF_POL__M 0x200274#define SCU_RAM_AGC_KI__A 0x831F25275#define SCU_RAM_AGC_KI_RF__B 4276#define SCU_RAM_AGC_KI_RF__M 0xF0277#define SCU_RAM_AGC_KI_IF__B 8278#define SCU_RAM_AGC_KI_IF__M 0xF00279#define SCU_RAM_AGC_KI_RED__A 0x831F26280#define SCU_RAM_AGC_KI_RED_RAGC_RED__B 2281#define SCU_RAM_AGC_KI_RED_RAGC_RED__M 0xC282#define SCU_RAM_AGC_KI_RED_IAGC_RED__B 4283#define SCU_RAM_AGC_KI_RED_IAGC_RED__M 0x30284#define SCU_RAM_AGC_KI_INNERGAIN_MIN__A 0x831F27285#define SCU_RAM_AGC_KI_MINGAIN__A 0x831F28286#define SCU_RAM_AGC_KI_MAXGAIN__A 0x831F29287#define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A 0x831F2A288#define SCU_RAM_AGC_KI_MIN__A 0x831F2B289#define SCU_RAM_AGC_KI_MAX__A 0x831F2C290#define SCU_RAM_AGC_CLP_SUM__A 0x831F2D291#define SCU_RAM_AGC_CLP_SUM_MIN__A 0x831F2E292#define SCU_RAM_AGC_CLP_SUM_MAX__A 0x831F2F293#define SCU_RAM_AGC_CLP_CYCLEN__A 0x831F30294#define SCU_RAM_AGC_CLP_CYCCNT__A 0x831F31295#define SCU_RAM_AGC_CLP_DIR_TO__A 0x831F32296#define SCU_RAM_AGC_CLP_DIR_WD__A 0x831F33297#define SCU_RAM_AGC_CLP_DIR_STP__A 0x831F34298#define SCU_RAM_AGC_SNS_SUM__A 0x831F35299#define SCU_RAM_AGC_SNS_SUM_MIN__A 0x831F36300#define SCU_RAM_AGC_SNS_SUM_MAX__A 0x831F37301#define SCU_RAM_AGC_SNS_CYCCNT__A 0x831F38302#define SCU_RAM_AGC_SNS_DIR_TO__A 0x831F39303#define SCU_RAM_AGC_SNS_DIR_WD__A 0x831F3A304#define SCU_RAM_AGC_SNS_DIR_STP__A 0x831F3B305#define SCU_RAM_AGC_INGAIN_TGT__A 0x831F3D306#define SCU_RAM_AGC_INGAIN_TGT_MIN__A 0x831F3E307#define SCU_RAM_AGC_INGAIN_TGT_MAX__A 0x831F3F308#define SCU_RAM_AGC_IF_IACCU_HI__A 0x831F40309#define SCU_RAM_AGC_IF_IACCU_LO__A 0x831F41310#define SCU_RAM_AGC_IF_IACCU_HI_TGT__A 0x831F42311#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A 0x831F43312#define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A 0x831F44313#define SCU_RAM_AGC_RF_IACCU_HI__A 0x831F45314#define SCU_RAM_AGC_RF_IACCU_LO__A 0x831F46315#define SCU_RAM_AGC_RF_IACCU_HI_CO__A 0x831F47316#define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A 0x831F84317#define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A 0x831F85318#define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A 0x831F86319#define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A 0x831F87320#define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A 0x831F88321#define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A 0x831F89322#define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A 0x831F8A323#define SCU_RAM_QAM_FSM_RTH__A 0x831F8E324#define SCU_RAM_QAM_FSM_FTH__A 0x831F8F325#define SCU_RAM_QAM_FSM_PTH__A 0x831F90326#define SCU_RAM_QAM_FSM_MTH__A 0x831F91327#define SCU_RAM_QAM_FSM_CTH__A 0x831F92328#define SCU_RAM_QAM_FSM_QTH__A 0x831F93329#define SCU_RAM_QAM_FSM_RATE_LIM__A 0x831F94330#define SCU_RAM_QAM_FSM_FREQ_LIM__A 0x831F95331#define SCU_RAM_QAM_FSM_COUNT_LIM__A 0x831F96332#define SCU_RAM_QAM_LC_CA_COARSE__A 0x831F97333#define SCU_RAM_QAM_LC_CA_FINE__A 0x831F99334#define SCU_RAM_QAM_LC_CP_COARSE__A 0x831F9A335#define SCU_RAM_QAM_LC_CP_MEDIUM__A 0x831F9B336#define SCU_RAM_QAM_LC_CP_FINE__A 0x831F9C337#define SCU_RAM_QAM_LC_CI_COARSE__A 0x831F9D338#define SCU_RAM_QAM_LC_CI_MEDIUM__A 0x831F9E339#define SCU_RAM_QAM_LC_CI_FINE__A 0x831F9F340#define SCU_RAM_QAM_LC_EP_COARSE__A 0x831FA0341#define SCU_RAM_QAM_LC_EP_MEDIUM__A 0x831FA1342#define SCU_RAM_QAM_LC_EP_FINE__A 0x831FA2343#define SCU_RAM_QAM_LC_EI_COARSE__A 0x831FA3344#define SCU_RAM_QAM_LC_EI_MEDIUM__A 0x831FA4345#define SCU_RAM_QAM_LC_EI_FINE__A 0x831FA5346#define SCU_RAM_QAM_LC_CF_COARSE__A 0x831FA6347#define SCU_RAM_QAM_LC_CF_MEDIUM__A 0x831FA7348#define SCU_RAM_QAM_LC_CF_FINE__A 0x831FA8349#define SCU_RAM_QAM_LC_CF1_COARSE__A 0x831FA9350#define SCU_RAM_QAM_LC_CF1_MEDIUM__A 0x831FAA351#define SCU_RAM_QAM_LC_CF1_FINE__A 0x831FAB352#define SCU_RAM_QAM_SL_SIG_POWER__A 0x831FAC353#define SCU_RAM_QAM_EQ_CMA_RAD0__A 0x831FAD354#define SCU_RAM_QAM_EQ_CMA_RAD1__A 0x831FAE355#define SCU_RAM_QAM_EQ_CMA_RAD2__A 0x831FAF356#define SCU_RAM_QAM_EQ_CMA_RAD3__A 0x831FB0357#define SCU_RAM_QAM_EQ_CMA_RAD4__A 0x831FB1358#define SCU_RAM_QAM_EQ_CMA_RAD5__A 0x831FB2359#define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED 0x4000360#define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED 0x8000361#define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK 0xC000362#define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A 0x831FEA363#define SCU_RAM_DRIVER_VER_HI__A 0x831FEB364#define SCU_RAM_DRIVER_VER_LO__A 0x831FEC365#define SCU_RAM_PARAM_15__A 0x831FED366#define SCU_RAM_PARAM_0__A 0x831FFC367#define SCU_RAM_COMMAND__A 0x831FFD368#define SCU_RAM_COMMAND_CMD_DEMOD_RESET 0x1369#define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV 0x2370#define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM 0x3371#define SCU_RAM_COMMAND_CMD_DEMOD_START 0x4372#define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK 0x5373#define SCU_RAM_COMMAND_CMD_DEMOD_STOP 0x9374#define SCU_RAM_COMMAND_STANDARD_QAM 0x200375#define SCU_RAM_COMMAND_STANDARD_OFDM 0x400376#define SIO_TOP_COMM_KEY__A 0x41000F377#define SIO_TOP_COMM_KEY_KEY 0xFABA378#define SIO_TOP_JTAGID_LO__A 0x410012379#define SIO_HI_RA_RAM_RES__A 0x420031380#define SIO_HI_RA_RAM_CMD__A 0x420032381#define SIO_HI_RA_RAM_CMD_RESET 0x2382#define SIO_HI_RA_RAM_CMD_CONFIG 0x3383#define SIO_HI_RA_RAM_CMD_BRDCTRL 0x7384#define SIO_HI_RA_RAM_PAR_1__A 0x420033385#define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY 0x3945386#define SIO_HI_RA_RAM_PAR_2__A 0x420034387#define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M 0x7F388#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN 0x0389#define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED 0x4390#define SIO_HI_RA_RAM_PAR_3__A 0x420035391#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M 0x7F392#define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B 7393#define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ 0x0394#define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE 0x8395#define SIO_HI_RA_RAM_PAR_4__A 0x420036396#define SIO_HI_RA_RAM_PAR_5__A 0x420037397#define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE 0x1398#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M 0x8399#define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ 0x8400#define SIO_HI_RA_RAM_PAR_6__A 0x420038401#define SIO_CC_PLL_LOCK__A 0x450012402#define SIO_CC_PWD_MODE__A 0x450015403#define SIO_CC_PWD_MODE_LEVEL_NONE 0x0404#define SIO_CC_PWD_MODE_LEVEL_OFDM 0x1405#define SIO_CC_PWD_MODE_LEVEL_CLOCK 0x2406#define SIO_CC_PWD_MODE_LEVEL_PLL 0x3407#define SIO_CC_PWD_MODE_LEVEL_OSC 0x4408#define SIO_CC_SOFT_RST__A 0x450016409#define SIO_CC_SOFT_RST_OFDM__M 0x1410#define SIO_CC_SOFT_RST_SYS__M 0x2411#define SIO_CC_SOFT_RST_OSC__M 0x4412#define SIO_CC_UPDATE__A 0x450017413#define SIO_CC_UPDATE_KEY 0xFABA414#define SIO_OFDM_SH_OFDM_RING_ENABLE__A 0x470010415#define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF 0x0416#define SIO_OFDM_SH_OFDM_RING_ENABLE_ON 0x1417#define SIO_OFDM_SH_OFDM_RING_STATUS__A 0x470012418#define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN 0x0419#define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED 0x1420#define SIO_BL_COMM_EXEC__A 0x480000421#define SIO_BL_COMM_EXEC_ACTIVE 0x1422#define SIO_BL_STATUS__A 0x480010423#define SIO_BL_MODE__A 0x480011424#define SIO_BL_MODE_DIRECT 0x0425#define SIO_BL_MODE_CHAIN 0x1426#define SIO_BL_ENABLE__A 0x480012427#define SIO_BL_ENABLE_ON 0x1428#define SIO_BL_TGT_HDR__A 0x480014429#define SIO_BL_TGT_ADDR__A 0x480015430#define SIO_BL_SRC_ADDR__A 0x480016431#define SIO_BL_SRC_LEN__A 0x480017432#define SIO_BL_CHAIN_ADDR__A 0x480018433#define SIO_BL_CHAIN_LEN__A 0x480019434#define SIO_PDR_MON_CFG__A 0x7F0010435#define SIO_PDR_UIO_IN_HI__A 0x7F0015436#define SIO_PDR_UIO_OUT_LO__A 0x7F0016437#define SIO_PDR_OHW_CFG__A 0x7F001F438#define SIO_PDR_OHW_CFG_FREF_SEL__M 0x3439#define SIO_PDR_GPIO_CFG__A 0x7F0021440#define SIO_PDR_MSTRT_CFG__A 0x7F0025441#define SIO_PDR_MERR_CFG__A 0x7F0026442#define SIO_PDR_MCLK_CFG__A 0x7F0028443#define SIO_PDR_MCLK_CFG_DRIVE__B 3444#define SIO_PDR_MVAL_CFG__A 0x7F0029445#define SIO_PDR_MD0_CFG__A 0x7F002A446#define SIO_PDR_MD0_CFG_DRIVE__B 3447#define SIO_PDR_MD1_CFG__A 0x7F002B448#define SIO_PDR_MD2_CFG__A 0x7F002C449#define SIO_PDR_MD3_CFG__A 0x7F002D450#define SIO_PDR_MD4_CFG__A 0x7F002F451#define SIO_PDR_MD5_CFG__A 0x7F0030452#define SIO_PDR_MD6_CFG__A 0x7F0031453#define SIO_PDR_MD7_CFG__A 0x7F0032454#define SIO_PDR_SMA_RX_CFG__A 0x7F0037455#define SIO_PDR_SMA_TX_CFG__A 0x7F0038456