359 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved4 *5 * This program may alternatively be licensed under a proprietary license from6 * MaxLinear, Inc.7 *8 */9 10#ifndef __MXL58X_REGISTERS_H__11#define __MXL58X_REGISTERS_H__12 13#define HYDRA_INTR_STATUS_REG 0x8003000814#define HYDRA_INTR_MASK_REG 0x8003000C15 16#define HYDRA_CRYSTAL_SETTING 0x3FFFC5F0 /* 0 - 24 MHz & 1 - 27 MHz */17#define HYDRA_CRYSTAL_CAP 0x3FFFEDA4 /* 0 - 24 MHz & 1 - 27 MHz */18 19#define HYDRA_CPU_RESET_REG 0x8003003C20#define HYDRA_CPU_RESET_DATA 0x0000040021 22#define HYDRA_RESET_TRANSPORT_FIFO_REG 0x8003002823#define HYDRA_RESET_TRANSPORT_FIFO_DATA 0x0000000024 25#define HYDRA_RESET_BBAND_REG 0x8003002426#define HYDRA_RESET_BBAND_DATA 0x0000000027 28#define HYDRA_RESET_XBAR_REG 0x8003002029#define HYDRA_RESET_XBAR_DATA 0x0000000030 31#define HYDRA_MODULES_CLK_1_REG 0x8003001432#define HYDRA_DISABLE_CLK_1 0x0000000033 34#define HYDRA_MODULES_CLK_2_REG 0x8003001C35#define HYDRA_DISABLE_CLK_2 0x0000000B36 37#define HYDRA_PRCM_ROOT_CLK_REG 0x8003001838#define HYDRA_PRCM_ROOT_CLK_DISABLE 0x0000000039 40#define HYDRA_CPU_RESET_CHECK_REG 0x8003000841#define HYDRA_CPU_RESET_CHECK_OFFSET 0x40000000 /* <bit 30> */42 43#define HYDRA_SKU_ID_REG 0x9000019044 45#define FW_DL_SIGN_ADDR 0x3FFFEAE046 47/* Register to check if FW is running or not */48#define HYDRA_HEAR_BEAT 0x3FFFEDDC49 50/* Firmware version */51#define HYDRA_FIRMWARE_VERSION 0x3FFFEDB852#define HYDRA_FW_RC_VERSION 0x3FFFCFAC53 54/* Firmware patch version */55#define HYDRA_FIRMWARE_PATCH_VERSION 0x3FFFEDC256 57/* SOC operating temperature in C */58#define HYDRA_TEMPARATURE 0x3FFFEDB459 60/* Demod & Tuner status registers */61/* Demod 0 status base address */62#define HYDRA_DEMOD_0_BASE_ADDR 0x3FFFC64C63 64/* Tuner 0 status base address */65#define HYDRA_TUNER_0_BASE_ADDR 0x3FFFCE4C66 67#define POWER_FROM_ADCRSSI_READBACK 0x3FFFEB6C68 69/* Macros to determine base address of respective demod or tuner */70#define HYDRA_DMD_STATUS_OFFSET(demodID) ((demodID) * 0x100)71#define HYDRA_TUNER_STATUS_OFFSET(tunerID) ((tunerID) * 0x40)72 73/* Demod status address offset from respective demod's base address */74#define HYDRA_DMD_AGC_DIG_LEVEL_ADDR_OFFSET 0x3FFFC64C75#define HYDRA_DMD_LOCK_STATUS_ADDR_OFFSET 0x3FFFC65076#define HYDRA_DMD_ACQ_STATUS_ADDR_OFFSET 0x3FFFC65477 78#define HYDRA_DMD_STANDARD_ADDR_OFFSET 0x3FFFC65879#define HYDRA_DMD_SPECTRUM_INVERSION_ADDR_OFFSET 0x3FFFC65C80#define HYDRA_DMD_SPECTRUM_ROLL_OFF_ADDR_OFFSET 0x3FFFC66081#define HYDRA_DMD_SYMBOL_RATE_ADDR_OFFSET 0x3FFFC66482#define HYDRA_DMD_MODULATION_SCHEME_ADDR_OFFSET 0x3FFFC66883#define HYDRA_DMD_FEC_CODE_RATE_ADDR_OFFSET 0x3FFFC66C84 85#define HYDRA_DMD_SNR_ADDR_OFFSET 0x3FFFC67086#define HYDRA_DMD_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67487#define HYDRA_DMD_CTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67888#define HYDRA_DMD_STR_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC67C89#define HYDRA_DMD_FTL_FREQ_OFFSET_ADDR_OFFSET 0x3FFFC68090#define HYDRA_DMD_STR_NBC_SYNC_LOCK_ADDR_OFFSET 0x3FFFC68491#define HYDRA_DMD_CYCLE_SLIP_COUNT_ADDR_OFFSET 0x3FFFC68892 93#define HYDRA_DMD_DISPLAY_I_ADDR_OFFSET 0x3FFFC68C94#define HYDRA_DMD_DISPLAY_Q_ADDR_OFFSET 0x3FFFC68E95 96#define HYDRA_DMD_DVBS2_CRC_ERRORS_ADDR_OFFSET 0x3FFFC69097#define HYDRA_DMD_DVBS2_PER_COUNT_ADDR_OFFSET 0x3FFFC69498#define HYDRA_DMD_DVBS2_PER_WINDOW_ADDR_OFFSET 0x3FFFC69899 100#define HYDRA_DMD_DVBS_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC69C101#define HYDRA_DMD_DVBS_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6A0102#define HYDRA_DMD_DVBS_BER_COUNT_ADDR_OFFSET 0x3FFFC6A4103#define HYDRA_DMD_DVBS_BER_WINDOW_ADDR_OFFSET 0x3FFFC6A8104 105/* Debug-purpose DVB-S DMD 0 */106#define HYDRA_DMD_DVBS_1ST_CORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6C8 /* corrected RS Errors: 1st iteration */107#define HYDRA_DMD_DVBS_1ST_UNCORR_RS_ERRORS_ADDR_OFFSET 0x3FFFC6CC /* uncorrected RS Errors: 1st iteration */108#define HYDRA_DMD_DVBS_BER_COUNT_1ST_ADDR_OFFSET 0x3FFFC6D0109#define HYDRA_DMD_DVBS_BER_WINDOW_1ST_ADDR_OFFSET 0x3FFFC6D4110 111#define HYDRA_DMD_TUNER_ID_ADDR_OFFSET 0x3FFFC6AC112#define HYDRA_DMD_DVBS2_PILOT_ON_OFF_ADDR_OFFSET 0x3FFFC6B0113#define HYDRA_DMD_FREQ_SEARCH_RANGE_KHZ_ADDR_OFFSET 0x3FFFC6B4114#define HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET 0x3FFFC6B8115#define HYDRA_DMD_STATUS_CENTER_FREQ_IN_KHZ_ADDR 0x3FFFC704116#define HYDRA_DMD_STATUS_INPUT_POWER_ADDR 0x3FFFC708117 118/* DVB-S new scaled_BER_count for a new BER API, see HYDRA-1343 "DVB-S post viterbi information" */119#define DMD0_STATUS_DVBS_1ST_SCALED_BER_COUNT_ADDR 0x3FFFC710 /* DMD 0: 1st iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */120#define DMD0_STATUS_DVBS_SCALED_BER_COUNT_ADDR 0x3FFFC714 /* DMD 0: 2nd iteration BER count scaled by HYDRA_BER_COUNT_SCALING_FACTOR */121 122#define DMD0_SPECTRUM_MIN_GAIN_STATUS 0x3FFFC73C123#define DMD0_SPECTRUM_MIN_GAIN_WB_SAGC_VALUE 0x3FFFC740124#define DMD0_SPECTRUM_MIN_GAIN_NB_SAGC_VALUE 0x3FFFC744125 126#define HYDRA_DMD_STATUS_END_ADDR_OFFSET 0x3FFFC748127 128/* Tuner status address offset from respective tuners's base address */129#define HYDRA_TUNER_DEMOD_ID_ADDR_OFFSET 0x3FFFCE4C130#define HYDRA_TUNER_AGC_LOCK_OFFSET 0x3FFFCE50131#define HYDRA_TUNER_SPECTRUM_STATUS_OFFSET 0x3FFFCE54132#define HYDRA_TUNER_SPECTRUM_BIN_SIZE_OFFSET 0x3FFFCE58133#define HYDRA_TUNER_SPECTRUM_ADDRESS_OFFSET 0x3FFFCE5C134#define HYDRA_TUNER_ENABLE_COMPLETE 0x3FFFEB78135 136#define HYDRA_DEMOD_STATUS_LOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_YES)137#define HYDRA_DEMOD_STATUS_UNLOCK(devId, demodId) write_register(devId, (HYDRA_DMD_STATUS_LOCK_ADDR_OFFSET + HYDRA_DMD_STATUS_OFFSET(demodId)), MXL_NO)138 139#define HYDRA_VERSION 0x3FFFEDB8140#define HYDRA_DEMOD0_VERSION 0x3FFFEDBC141#define HYDRA_DEMOD1_VERSION 0x3FFFEDC0142#define HYDRA_DEMOD2_VERSION 0x3FFFEDC4143#define HYDRA_DEMOD3_VERSION 0x3FFFEDC8144#define HYDRA_DEMOD4_VERSION 0x3FFFEDCC145#define HYDRA_DEMOD5_VERSION 0x3FFFEDD0146#define HYDRA_DEMOD6_VERSION 0x3FFFEDD4147#define HYDRA_DEMOD7_VERSION 0x3FFFEDD8148#define HYDRA_HEAR_BEAT 0x3FFFEDDC149#define HYDRA_SKU_MGMT 0x3FFFEBC0150 151#define MXL_HYDRA_FPGA_A_ADDRESS 0x91C00000152#define MXL_HYDRA_FPGA_B_ADDRESS 0x91D00000153 154/* TS control base address */155#define HYDRA_TS_CTRL_BASE_ADDR 0x90700000156 157#define MPEG_MUX_MODE_SLICE0_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x08)158 159#define MPEG_MUX_MODE_SLICE1_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x08)160 161#define PID_BANK_SEL_SLICE0_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190)162#define PID_BANK_SEL_SLICE1_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)163 164#define MPEG_CLK_GATED_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x20)165 166#define MPEG_CLK_ALWAYS_ON_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1D4)167 168#define HYDRA_REGULAR_PID_BANK_A_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190)169 170#define HYDRA_FIXED_PID_BANK_A_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x190)171 172#define HYDRA_REGULAR_PID_BANK_B_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)173 174#define HYDRA_FIXED_PID_BANK_B_REG (HYDRA_TS_CTRL_BASE_ADDR + 0x1B0)175 176#define FIXED_PID_TBL_REG_ADDRESS_0 (HYDRA_TS_CTRL_BASE_ADDR + 0x9000)177#define FIXED_PID_TBL_REG_ADDRESS_1 (HYDRA_TS_CTRL_BASE_ADDR + 0x9100)178#define FIXED_PID_TBL_REG_ADDRESS_2 (HYDRA_TS_CTRL_BASE_ADDR + 0x9200)179#define FIXED_PID_TBL_REG_ADDRESS_3 (HYDRA_TS_CTRL_BASE_ADDR + 0x9300)180 181#define FIXED_PID_TBL_REG_ADDRESS_4 (HYDRA_TS_CTRL_BASE_ADDR + 0xB000)182#define FIXED_PID_TBL_REG_ADDRESS_5 (HYDRA_TS_CTRL_BASE_ADDR + 0xB100)183#define FIXED_PID_TBL_REG_ADDRESS_6 (HYDRA_TS_CTRL_BASE_ADDR + 0xB200)184#define FIXED_PID_TBL_REG_ADDRESS_7 (HYDRA_TS_CTRL_BASE_ADDR + 0xB300)185 186#define REGULAR_PID_TBL_REG_ADDRESS_0 (HYDRA_TS_CTRL_BASE_ADDR + 0x8000)187#define REGULAR_PID_TBL_REG_ADDRESS_1 (HYDRA_TS_CTRL_BASE_ADDR + 0x8200)188#define REGULAR_PID_TBL_REG_ADDRESS_2 (HYDRA_TS_CTRL_BASE_ADDR + 0x8400)189#define REGULAR_PID_TBL_REG_ADDRESS_3 (HYDRA_TS_CTRL_BASE_ADDR + 0x8600)190 191#define REGULAR_PID_TBL_REG_ADDRESS_4 (HYDRA_TS_CTRL_BASE_ADDR + 0xA000)192#define REGULAR_PID_TBL_REG_ADDRESS_5 (HYDRA_TS_CTRL_BASE_ADDR + 0xA200)193#define REGULAR_PID_TBL_REG_ADDRESS_6 (HYDRA_TS_CTRL_BASE_ADDR + 0xA400)194#define REGULAR_PID_TBL_REG_ADDRESS_7 (HYDRA_TS_CTRL_BASE_ADDR + 0xA600)195 196/***************************************************************************/197 198#define PAD_MUX_GPIO_00_SYNC_BASEADDR 0x90000188199 200 201#define PAD_MUX_UART_RX_C_PINMUX_BASEADDR 0x9000001C202 203#define XPT_PACKET_GAP_MIN_BASEADDR 0x90700044204#define XPT_NCO_COUNT_BASEADDR 0x90700238205 206#define XPT_NCO_COUNT_BASEADDR1 0x9070023C207 208/* V2 DigRF status register */209 210#define XPT_PID_BASEADDR 0x90708000211 212#define XPT_PID_REMAP_BASEADDR 0x90708004213 214#define XPT_KNOWN_PID_BASEADDR 0x90709000215 216#define XPT_PID_BASEADDR1 0x9070A000217 218#define XPT_PID_REMAP_BASEADDR1 0x9070A004219 220#define XPT_KNOWN_PID_BASEADDR1 0x9070B000221 222#define XPT_BERT_LOCK_BASEADDR 0x907000B8223 224#define XPT_BERT_BASEADDR 0x907000BC225 226#define XPT_BERT_INVERT_BASEADDR 0x907000C0227 228#define XPT_BERT_HEADER_BASEADDR 0x907000C4229 230#define XPT_BERT_BASEADDR1 0x907000C8231 232#define XPT_BERT_BIT_COUNT0_BASEADDR 0x907000CC233 234#define XPT_BERT_BIT_COUNT0_BASEADDR1 0x907000D0235 236#define XPT_BERT_BIT_COUNT1_BASEADDR 0x907000D4237 238#define XPT_BERT_BIT_COUNT1_BASEADDR1 0x907000D8239 240#define XPT_BERT_BIT_COUNT2_BASEADDR 0x907000DC241 242#define XPT_BERT_BIT_COUNT2_BASEADDR1 0x907000E0243 244#define XPT_BERT_BIT_COUNT3_BASEADDR 0x907000E4245 246#define XPT_BERT_BIT_COUNT3_BASEADDR1 0x907000E8247 248#define XPT_BERT_BIT_COUNT4_BASEADDR 0x907000EC249 250#define XPT_BERT_BIT_COUNT4_BASEADDR1 0x907000F0251 252#define XPT_BERT_BIT_COUNT5_BASEADDR 0x907000F4253 254#define XPT_BERT_BIT_COUNT5_BASEADDR1 0x907000F8255 256#define XPT_BERT_BIT_COUNT6_BASEADDR 0x907000FC257 258#define XPT_BERT_BIT_COUNT6_BASEADDR1 0x90700100259 260#define XPT_BERT_BIT_COUNT7_BASEADDR 0x90700104261 262#define XPT_BERT_BIT_COUNT7_BASEADDR1 0x90700108263 264#define XPT_BERT_ERR_COUNT0_BASEADDR 0x9070010C265 266#define XPT_BERT_ERR_COUNT0_BASEADDR1 0x90700110267 268#define XPT_BERT_ERR_COUNT1_BASEADDR 0x90700114269 270#define XPT_BERT_ERR_COUNT1_BASEADDR1 0x90700118271 272#define XPT_BERT_ERR_COUNT2_BASEADDR 0x9070011C273 274#define XPT_BERT_ERR_COUNT2_BASEADDR1 0x90700120275 276#define XPT_BERT_ERR_COUNT3_BASEADDR 0x90700124277 278#define XPT_BERT_ERR_COUNT3_BASEADDR1 0x90700128279 280#define XPT_BERT_ERR_COUNT4_BASEADDR 0x9070012C281 282#define XPT_BERT_ERR_COUNT4_BASEADDR1 0x90700130283 284#define XPT_BERT_ERR_COUNT5_BASEADDR 0x90700134285 286#define XPT_BERT_ERR_COUNT5_BASEADDR1 0x90700138287 288#define XPT_BERT_ERR_COUNT6_BASEADDR 0x9070013C289 290#define XPT_BERT_ERR_COUNT6_BASEADDR1 0x90700140291 292#define XPT_BERT_ERR_COUNT7_BASEADDR 0x90700144293 294#define XPT_BERT_ERR_COUNT7_BASEADDR1 0x90700148295 296#define XPT_BERT_ERROR_BASEADDR 0x9070014C297 298#define XPT_BERT_ANALYZER_BASEADDR 0x90700150299 300#define XPT_BERT_ANALYZER_BASEADDR1 0x90700154301 302#define XPT_BERT_ANALYZER_BASEADDR2 0x90700158303 304#define XPT_BERT_ANALYZER_BASEADDR3 0x9070015C305 306#define XPT_BERT_ANALYZER_BASEADDR4 0x90700160307 308#define XPT_BERT_ANALYZER_BASEADDR5 0x90700164309 310#define XPT_BERT_ANALYZER_BASEADDR6 0x90700168311 312#define XPT_BERT_ANALYZER_BASEADDR7 0x9070016C313 314#define XPT_BERT_ANALYZER_BASEADDR8 0x90700170315 316#define XPT_BERT_ANALYZER_BASEADDR9 0x90700174317 318#define XPT_DMD0_BASEADDR 0x9070024C319 320/* V2 AGC Gain Freeze & step */321#define DBG_ENABLE_DISABLE_AGC (0x3FFFCF60) /* 1: DISABLE, 0:ENABLE */322#define WB_DFE0_DFE_FB_RF1_BASEADDR 0x903004A4323 324#define WB_DFE1_DFE_FB_RF1_BASEADDR 0x904004A4325 326#define WB_DFE2_DFE_FB_RF1_BASEADDR 0x905004A4327 328#define WB_DFE3_DFE_FB_RF1_BASEADDR 0x906004A4329 330#define AFE_REG_D2A_TA_RFFE_LNA_BO_1P8_BASEADDR 0x90200104331 332#define AFE_REG_AFE_REG_SPARE_BASEADDR 0x902000A0333 334#define AFE_REG_AFE_REG_SPARE_BASEADDR1 0x902000B4335 336#define AFE_REG_AFE_REG_SPARE_BASEADDR2 0x902000C4337 338#define AFE_REG_AFE_REG_SPARE_BASEADDR3 0x902000D4339 340#define WB_DFE0_DFE_FB_AGC_BASEADDR 0x90300498341 342#define WB_DFE1_DFE_FB_AGC_BASEADDR 0x90400498343 344#define WB_DFE2_DFE_FB_AGC_BASEADDR 0x90500498345 346#define WB_DFE3_DFE_FB_AGC_BASEADDR 0x90600498347 348#define WDT_WD_INT_BASEADDR 0x8002000C349 350#define FSK_TX_FTM_BASEADDR 0x80090000351 352#define FSK_TX_FTM_TX_CNT_BASEADDR 0x80090018353 354#define AFE_REG_D2A_FSK_BIAS_BASEADDR 0x90200040355 356#define DMD_TEI_BASEADDR 0x3FFFEBE0357 358#endif /* __MXL58X_REGISTERS_H__ */359