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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Driver for Silicon Labs Si2161 DVB-T and Si2165 DVB-C/-T Demodulator4 *5 * Copyright (C) 2013-2017 Matthias Schwarzott <zzam@gentoo.org>6 *7 * References:8 * https://www.silabs.com/Support%20Documents/TechnicalDocs/Si2165-short.pdf9 */10 11#include <linux/delay.h>12#include <linux/errno.h>13#include <linux/init.h>14#include <linux/kernel.h>15#include <linux/module.h>16#include <linux/string.h>17#include <linux/slab.h>18#include <linux/firmware.h>19#include <linux/regmap.h>20 21#include <media/dvb_frontend.h>22#include <linux/int_log.h>23#include "si2165_priv.h"24#include "si2165.h"25 26/*27 * Hauppauge WinTV-HVR-930C-HD B130 / PCTV QuatroStick 521e 1113xx28 * uses 16 MHz xtal29 *30 * Hauppauge WinTV-HVR-930C-HD B131 / PCTV QuatroStick 522e 1114xx31 * uses 24 MHz clock provided by tuner32 */33 34struct si2165_state {35 struct i2c_client *client;36 37 struct regmap *regmap;38 39 struct dvb_frontend fe;40 41 struct si2165_config config;42 43 u8 chip_revcode;44 u8 chip_type;45 46 /* calculated by xtal and div settings */47 u32 fvco_hz;48 u32 sys_clk;49 u32 adc_clk;50 51 /* DVBv3 stats */52 u64 ber_prev;53 54 bool has_dvbc;55 bool has_dvbt;56 bool firmware_loaded;57};58 59static int si2165_write(struct si2165_state *state, const u16 reg,60 const u8 *src, const int count)61{62 int ret;63 64 dev_dbg(&state->client->dev, "i2c write: reg: 0x%04x, data: %*ph\n",65 reg, count, src);66 67 ret = regmap_bulk_write(state->regmap, reg, src, count);68 69 if (ret)70 dev_err(&state->client->dev, "%s: ret == %d\n", __func__, ret);71 72 return ret;73}74 75static int si2165_read(struct si2165_state *state,76 const u16 reg, u8 *val, const int count)77{78 int ret = regmap_bulk_read(state->regmap, reg, val, count);79 80 if (ret) {81 dev_err(&state->client->dev, "%s: error (addr %02x reg %04x error (ret == %i)\n",82 __func__, state->config.i2c_addr, reg, ret);83 return ret;84 }85 86 dev_dbg(&state->client->dev, "i2c read: reg: 0x%04x, data: %*ph\n",87 reg, count, val);88 89 return 0;90}91 92static int si2165_readreg8(struct si2165_state *state,93 const u16 reg, u8 *val)94{95 unsigned int val_tmp;96 int ret = regmap_read(state->regmap, reg, &val_tmp);97 *val = (u8)val_tmp;98 dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%02x\n", reg, *val);99 return ret;100}101 102static int si2165_readreg16(struct si2165_state *state,103 const u16 reg, u16 *val)104{105 u8 buf[2];106 107 int ret = si2165_read(state, reg, buf, 2);108 *val = buf[0] | buf[1] << 8;109 dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%04x\n", reg, *val);110 return ret;111}112 113static int si2165_readreg24(struct si2165_state *state,114 const u16 reg, u32 *val)115{116 u8 buf[3];117 118 int ret = si2165_read(state, reg, buf, 3);119 *val = buf[0] | buf[1] << 8 | buf[2] << 16;120 dev_dbg(&state->client->dev, "reg read: R(0x%04x)=0x%06x\n", reg, *val);121 return ret;122}123 124static int si2165_writereg8(struct si2165_state *state, const u16 reg, u8 val)125{126 return regmap_write(state->regmap, reg, val);127}128 129static int si2165_writereg16(struct si2165_state *state, const u16 reg, u16 val)130{131 u8 buf[2] = { val & 0xff, (val >> 8) & 0xff };132 133 return si2165_write(state, reg, buf, 2);134}135 136static int si2165_writereg24(struct si2165_state *state, const u16 reg, u32 val)137{138 u8 buf[3] = { val & 0xff, (val >> 8) & 0xff, (val >> 16) & 0xff };139 140 return si2165_write(state, reg, buf, 3);141}142 143static int si2165_writereg32(struct si2165_state *state, const u16 reg, u32 val)144{145 u8 buf[4] = {146 val & 0xff,147 (val >> 8) & 0xff,148 (val >> 16) & 0xff,149 (val >> 24) & 0xff150 };151 return si2165_write(state, reg, buf, 4);152}153 154static int si2165_writereg_mask8(struct si2165_state *state, const u16 reg,155 u8 val, u8 mask)156{157 if (mask != 0xff) {158 u8 tmp;159 int ret = si2165_readreg8(state, reg, &tmp);160 161 if (ret < 0)162 return ret;163 164 val &= mask;165 tmp &= ~mask;166 val |= tmp;167 }168 return si2165_writereg8(state, reg, val);169}170 171#define REG16(reg, val) \172 { (reg), (val) & 0xff }, \173 { (reg) + 1, (val) >> 8 & 0xff }174struct si2165_reg_value_pair {175 u16 reg;176 u8 val;177};178 179static int si2165_write_reg_list(struct si2165_state *state,180 const struct si2165_reg_value_pair *regs,181 int count)182{183 int i;184 int ret;185 186 for (i = 0; i < count; i++) {187 ret = si2165_writereg8(state, regs[i].reg, regs[i].val);188 if (ret < 0)189 return ret;190 }191 return 0;192}193 194static int si2165_get_tune_settings(struct dvb_frontend *fe,195 struct dvb_frontend_tune_settings *s)196{197 s->min_delay_ms = 1000;198 return 0;199}200 201static int si2165_init_pll(struct si2165_state *state)202{203 u32 ref_freq_hz = state->config.ref_freq_hz;204 u8 divr = 1; /* 1..7 */205 u8 divp = 1; /* only 1 or 4 */206 u8 divn = 56; /* 1..63 */207 u8 divm = 8;208 u8 divl = 12;209 u8 buf[4];210 211 /*212 * hardcoded values can be deleted if calculation is verified213 * or it yields the same values as the windows driver214 */215 switch (ref_freq_hz) {216 case 16000000u:217 divn = 56;218 break;219 case 24000000u:220 divr = 2;221 divp = 4;222 divn = 19;223 break;224 default:225 /* ref_freq / divr must be between 4 and 16 MHz */226 if (ref_freq_hz > 16000000u)227 divr = 2;228 229 /*230 * now select divn and divp such that231 * fvco is in 1624..1824 MHz232 */233 if (1624000000u * divr > ref_freq_hz * 2u * 63u)234 divp = 4;235 236 /* is this already correct regarding rounding? */237 divn = 1624000000u * divr / (ref_freq_hz * 2u * divp);238 break;239 }240 241 /* adc_clk and sys_clk depend on xtal and pll settings */242 state->fvco_hz = ref_freq_hz / divr243 * 2u * divn * divp;244 state->adc_clk = state->fvco_hz / (divm * 4u);245 state->sys_clk = state->fvco_hz / (divl * 2u);246 247 /* write all 4 pll registers 0x00a0..0x00a3 at once */248 buf[0] = divl;249 buf[1] = divm;250 buf[2] = (divn & 0x3f) | ((divp == 1) ? 0x40 : 0x00) | 0x80;251 buf[3] = divr;252 return si2165_write(state, REG_PLL_DIVL, buf, 4);253}254 255static int si2165_adjust_pll_divl(struct si2165_state *state, u8 divl)256{257 state->sys_clk = state->fvco_hz / (divl * 2u);258 return si2165_writereg8(state, REG_PLL_DIVL, divl);259}260 261static u32 si2165_get_fe_clk(struct si2165_state *state)262{263 /* assume Oversampling mode Ovr4 is used */264 return state->adc_clk;265}266 267static int si2165_wait_init_done(struct si2165_state *state)268{269 int ret;270 u8 val = 0;271 int i;272 273 for (i = 0; i < 3; ++i) {274 ret = si2165_readreg8(state, REG_INIT_DONE, &val);275 if (ret < 0)276 return ret;277 if (val == 0x01)278 return 0;279 usleep_range(1000, 50000);280 }281 dev_err(&state->client->dev, "init_done was not set\n");282 return -EINVAL;283}284 285static int si2165_upload_firmware_block(struct si2165_state *state,286 const u8 *data, u32 len, u32 *poffset,287 u32 block_count)288{289 int ret;290 u8 buf_ctrl[4] = { 0x00, 0x00, 0x00, 0xc0 };291 u8 wordcount;292 u32 cur_block = 0;293 u32 offset = poffset ? *poffset : 0;294 295 if (len < 4)296 return -EINVAL;297 if (len % 4 != 0)298 return -EINVAL;299 300 dev_dbg(&state->client->dev,301 "fw load: %s: called with len=0x%x offset=0x%x blockcount=0x%x\n",302 __func__, len, offset, block_count);303 while (offset + 12 <= len && cur_block < block_count) {304 dev_dbg(&state->client->dev,305 "fw load: %s: in while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n",306 __func__, len, offset, cur_block, block_count);307 wordcount = data[offset];308 if (wordcount < 1 || data[offset + 1] ||309 data[offset + 2] || data[offset + 3]) {310 dev_warn(&state->client->dev,311 "bad fw data[0..3] = %*ph\n",312 4, data);313 return -EINVAL;314 }315 316 if (offset + 8 + wordcount * 4 > len) {317 dev_warn(&state->client->dev,318 "len is too small for block len=%d, wordcount=%d\n",319 len, wordcount);320 return -EINVAL;321 }322 323 buf_ctrl[0] = wordcount - 1;324 325 ret = si2165_write(state, REG_DCOM_CONTROL_BYTE, buf_ctrl, 4);326 if (ret < 0)327 goto error;328 ret = si2165_write(state, REG_DCOM_ADDR, data + offset + 4, 4);329 if (ret < 0)330 goto error;331 332 offset += 8;333 334 while (wordcount > 0) {335 ret = si2165_write(state, REG_DCOM_DATA,336 data + offset, 4);337 if (ret < 0)338 goto error;339 wordcount--;340 offset += 4;341 }342 cur_block++;343 }344 345 dev_dbg(&state->client->dev,346 "fw load: %s: after while len=0x%x offset=0x%x cur_block=0x%x blockcount=0x%x\n",347 __func__, len, offset, cur_block, block_count);348 349 if (poffset)350 *poffset = offset;351 352 dev_dbg(&state->client->dev,353 "fw load: %s: returned offset=0x%x\n",354 __func__, offset);355 356 return 0;357error:358 return ret;359}360 361static int si2165_upload_firmware(struct si2165_state *state)362{363 /* int ret; */364 u8 val[3];365 u16 val16;366 int ret;367 368 const struct firmware *fw = NULL;369 u8 *fw_file;370 const u8 *data;371 u32 len;372 u32 offset;373 u8 patch_version;374 u8 block_count;375 u16 crc_expected;376 377 switch (state->chip_revcode) {378 case 0x03: /* revision D */379 fw_file = SI2165_FIRMWARE_REV_D;380 break;381 default:382 dev_info(&state->client->dev, "no firmware file for revision=%d\n",383 state->chip_revcode);384 return 0;385 }386 387 /* request the firmware, this will block and timeout */388 ret = request_firmware(&fw, fw_file, &state->client->dev);389 if (ret) {390 dev_warn(&state->client->dev, "firmware file '%s' not found\n",391 fw_file);392 goto error;393 }394 395 data = fw->data;396 len = fw->size;397 398 dev_info(&state->client->dev, "downloading firmware from file '%s' size=%d\n",399 fw_file, len);400 401 if (len % 4 != 0) {402 dev_warn(&state->client->dev, "firmware size is not multiple of 4\n");403 ret = -EINVAL;404 goto error;405 }406 407 /* check header (8 bytes) */408 if (len < 8) {409 dev_warn(&state->client->dev, "firmware header is missing\n");410 ret = -EINVAL;411 goto error;412 }413 414 if (data[0] != 1 || data[1] != 0) {415 dev_warn(&state->client->dev, "firmware file version is wrong\n");416 ret = -EINVAL;417 goto error;418 }419 420 patch_version = data[2];421 block_count = data[4];422 crc_expected = data[7] << 8 | data[6];423 424 /* start uploading fw */425 /* boot/wdog status */426 ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);427 if (ret < 0)428 goto error;429 /* reset */430 ret = si2165_writereg8(state, REG_RST_ALL, 0x00);431 if (ret < 0)432 goto error;433 /* boot/wdog status */434 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);435 if (ret < 0)436 goto error;437 438 /* enable reset on error */439 ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);440 if (ret < 0)441 goto error;442 ret = si2165_readreg8(state, REG_EN_RST_ERROR, val);443 if (ret < 0)444 goto error;445 ret = si2165_writereg8(state, REG_EN_RST_ERROR, 0x02);446 if (ret < 0)447 goto error;448 449 /* start right after the header */450 offset = 8;451 452 dev_info(&state->client->dev, "%s: extracted patch_version=0x%02x, block_count=0x%02x, crc_expected=0x%04x\n",453 __func__, patch_version, block_count, crc_expected);454 455 ret = si2165_upload_firmware_block(state, data, len, &offset, 1);456 if (ret < 0)457 goto error;458 459 ret = si2165_writereg8(state, REG_PATCH_VERSION, patch_version);460 if (ret < 0)461 goto error;462 463 /* reset crc */464 ret = si2165_writereg8(state, REG_RST_CRC, 0x01);465 if (ret)466 goto error;467 468 ret = si2165_upload_firmware_block(state, data, len,469 &offset, block_count);470 if (ret < 0) {471 dev_err(&state->client->dev,472 "firmware could not be uploaded\n");473 goto error;474 }475 476 /* read crc */477 ret = si2165_readreg16(state, REG_CRC, &val16);478 if (ret)479 goto error;480 481 if (val16 != crc_expected) {482 dev_err(&state->client->dev,483 "firmware crc mismatch %04x != %04x\n",484 val16, crc_expected);485 ret = -EINVAL;486 goto error;487 }488 489 ret = si2165_upload_firmware_block(state, data, len, &offset, 5);490 if (ret)491 goto error;492 493 if (len != offset) {494 dev_err(&state->client->dev,495 "firmware len mismatch %04x != %04x\n",496 len, offset);497 ret = -EINVAL;498 goto error;499 }500 501 /* reset watchdog error register */502 ret = si2165_writereg_mask8(state, REG_WDOG_AND_BOOT, 0x02, 0x02);503 if (ret < 0)504 goto error;505 506 /* enable reset on error */507 ret = si2165_writereg_mask8(state, REG_EN_RST_ERROR, 0x01, 0x01);508 if (ret < 0)509 goto error;510 511 dev_info(&state->client->dev, "fw load finished\n");512 513 ret = 0;514 state->firmware_loaded = true;515error:516 release_firmware(fw);517 fw = NULL;518 519 return ret;520}521 522static int si2165_init(struct dvb_frontend *fe)523{524 int ret = 0;525 struct si2165_state *state = fe->demodulator_priv;526 struct dtv_frontend_properties *c = &fe->dtv_property_cache;527 u8 val;528 u8 patch_version = 0x00;529 530 dev_dbg(&state->client->dev, "%s: called\n", __func__);531 532 /* powerup */533 ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);534 if (ret < 0)535 goto error;536 /* dsp_clock_enable */537 ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x01);538 if (ret < 0)539 goto error;540 /* verify chip_mode */541 ret = si2165_readreg8(state, REG_CHIP_MODE, &val);542 if (ret < 0)543 goto error;544 if (val != state->config.chip_mode) {545 dev_err(&state->client->dev, "could not set chip_mode\n");546 return -EINVAL;547 }548 549 /* agc */550 ret = si2165_writereg8(state, REG_AGC_IF_TRI, 0x00);551 if (ret < 0)552 goto error;553 ret = si2165_writereg8(state, REG_AGC_IF_SLR, 0x01);554 if (ret < 0)555 goto error;556 ret = si2165_writereg8(state, REG_AGC2_OUTPUT, 0x00);557 if (ret < 0)558 goto error;559 ret = si2165_writereg8(state, REG_AGC2_CLKDIV, 0x07);560 if (ret < 0)561 goto error;562 /* rssi pad */563 ret = si2165_writereg8(state, REG_RSSI_PAD_CTRL, 0x00);564 if (ret < 0)565 goto error;566 ret = si2165_writereg8(state, REG_RSSI_ENABLE, 0x00);567 if (ret < 0)568 goto error;569 570 ret = si2165_init_pll(state);571 if (ret < 0)572 goto error;573 574 /* enable chip_init */575 ret = si2165_writereg8(state, REG_CHIP_INIT, 0x01);576 if (ret < 0)577 goto error;578 /* set start_init */579 ret = si2165_writereg8(state, REG_START_INIT, 0x01);580 if (ret < 0)581 goto error;582 ret = si2165_wait_init_done(state);583 if (ret < 0)584 goto error;585 586 /* disable chip_init */587 ret = si2165_writereg8(state, REG_CHIP_INIT, 0x00);588 if (ret < 0)589 goto error;590 591 /* ber_pkt - default 65535 */592 ret = si2165_writereg16(state, REG_BER_PKT,593 STATISTICS_PERIOD_PKT_COUNT);594 if (ret < 0)595 goto error;596 597 ret = si2165_readreg8(state, REG_PATCH_VERSION, &patch_version);598 if (ret < 0)599 goto error;600 601 ret = si2165_writereg8(state, REG_AUTO_RESET, 0x00);602 if (ret < 0)603 goto error;604 605 /* dsp_addr_jump */606 ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);607 if (ret < 0)608 goto error;609 /* boot/wdog status */610 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, &val);611 if (ret < 0)612 goto error;613 614 if (patch_version == 0x00) {615 ret = si2165_upload_firmware(state);616 if (ret < 0)617 goto error;618 }619 620 /* ts output config */621 ret = si2165_writereg8(state, REG_TS_DATA_MODE, 0x20);622 if (ret < 0)623 return ret;624 ret = si2165_writereg16(state, REG_TS_TRI, 0x00fe);625 if (ret < 0)626 return ret;627 ret = si2165_writereg24(state, REG_TS_SLR, 0x555555);628 if (ret < 0)629 return ret;630 ret = si2165_writereg8(state, REG_TS_CLK_MODE, 0x01);631 if (ret < 0)632 return ret;633 ret = si2165_writereg8(state, REG_TS_PARALLEL_MODE, 0x00);634 if (ret < 0)635 return ret;636 637 c = &state->fe.dtv_property_cache;638 c->cnr.len = 1;639 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;640 c->post_bit_error.len = 1;641 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;642 c->post_bit_count.len = 1;643 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;644 645 return 0;646error:647 return ret;648}649 650static int si2165_sleep(struct dvb_frontend *fe)651{652 int ret;653 struct si2165_state *state = fe->demodulator_priv;654 655 /* dsp clock disable */656 ret = si2165_writereg8(state, REG_DSP_CLOCK, 0x00);657 if (ret < 0)658 return ret;659 /* chip mode */660 ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);661 if (ret < 0)662 return ret;663 return 0;664}665 666static int si2165_read_status(struct dvb_frontend *fe, enum fe_status *status)667{668 int ret;669 u8 u8tmp;670 u32 u32tmp;671 struct si2165_state *state = fe->demodulator_priv;672 struct dtv_frontend_properties *c = &fe->dtv_property_cache;673 u32 delsys = c->delivery_system;674 675 *status = 0;676 677 switch (delsys) {678 case SYS_DVBT:679 /* check fast signal type */680 ret = si2165_readreg8(state, REG_CHECK_SIGNAL, &u8tmp);681 if (ret < 0)682 return ret;683 switch (u8tmp & 0x3) {684 case 0: /* searching */685 case 1: /* nothing */686 break;687 case 2: /* digital signal */688 *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER;689 break;690 }691 break;692 case SYS_DVBC_ANNEX_A:693 /* check packet sync lock */694 ret = si2165_readreg8(state, REG_PS_LOCK, &u8tmp);695 if (ret < 0)696 return ret;697 if (u8tmp & 0x01) {698 *status |= FE_HAS_SIGNAL;699 *status |= FE_HAS_CARRIER;700 *status |= FE_HAS_VITERBI;701 *status |= FE_HAS_SYNC;702 }703 break;704 }705 706 /* check fec_lock */707 ret = si2165_readreg8(state, REG_FEC_LOCK, &u8tmp);708 if (ret < 0)709 return ret;710 if (u8tmp & 0x01) {711 *status |= FE_HAS_SIGNAL;712 *status |= FE_HAS_CARRIER;713 *status |= FE_HAS_VITERBI;714 *status |= FE_HAS_SYNC;715 *status |= FE_HAS_LOCK;716 }717 718 /* CNR */719 if (delsys == SYS_DVBC_ANNEX_A && *status & FE_HAS_VITERBI) {720 ret = si2165_readreg24(state, REG_C_N, &u32tmp);721 if (ret < 0)722 return ret;723 /*724 * svalue =725 * 1000 * c_n/dB =726 * 1000 * 10 * log10(2^24 / regval) =727 * 1000 * 10 * (log10(2^24) - log10(regval)) =728 * 1000 * 10 * (intlog10(2^24) - intlog10(regval)) / 2^24729 *730 * intlog10(x) = log10(x) * 2^24731 * intlog10(2^24) = log10(2^24) * 2^24 = 121210686732 */733 u32tmp = (1000 * 10 * (121210686 - (u64)intlog10(u32tmp)))734 >> 24;735 c->cnr.stat[0].scale = FE_SCALE_DECIBEL;736 c->cnr.stat[0].svalue = u32tmp;737 } else738 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;739 740 /* BER */741 if (*status & FE_HAS_VITERBI) {742 if (c->post_bit_error.stat[0].scale == FE_SCALE_NOT_AVAILABLE) {743 /* start new sampling period to get rid of old data*/744 ret = si2165_writereg8(state, REG_BER_RST, 0x01);745 if (ret < 0)746 return ret;747 748 /* set scale to enter read code on next call */749 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER;750 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER;751 c->post_bit_error.stat[0].uvalue = 0;752 c->post_bit_count.stat[0].uvalue = 0;753 754 /*755 * reset DVBv3 value to deliver a good result756 * for the first call757 */758 state->ber_prev = 0;759 760 } else {761 ret = si2165_readreg8(state, REG_BER_AVAIL, &u8tmp);762 if (ret < 0)763 return ret;764 765 if (u8tmp & 1) {766 u32 biterrcnt;767 768 ret = si2165_readreg24(state, REG_BER_BIT,769 &biterrcnt);770 if (ret < 0)771 return ret;772 773 c->post_bit_error.stat[0].uvalue +=774 biterrcnt;775 c->post_bit_count.stat[0].uvalue +=776 STATISTICS_PERIOD_BIT_COUNT;777 778 /* start new sampling period */779 ret = si2165_writereg8(state,780 REG_BER_RST, 0x01);781 if (ret < 0)782 return ret;783 784 dev_dbg(&state->client->dev,785 "post_bit_error=%u post_bit_count=%u\n",786 biterrcnt, STATISTICS_PERIOD_BIT_COUNT);787 }788 }789 } else {790 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;791 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;792 }793 794 return 0;795}796 797static int si2165_read_snr(struct dvb_frontend *fe, u16 *snr)798{799 struct dtv_frontend_properties *c = &fe->dtv_property_cache;800 801 if (c->cnr.stat[0].scale == FE_SCALE_DECIBEL)802 *snr = div_s64(c->cnr.stat[0].svalue, 100);803 else804 *snr = 0;805 return 0;806}807 808static int si2165_read_ber(struct dvb_frontend *fe, u32 *ber)809{810 struct si2165_state *state = fe->demodulator_priv;811 struct dtv_frontend_properties *c = &fe->dtv_property_cache;812 813 if (c->post_bit_error.stat[0].scale != FE_SCALE_COUNTER) {814 *ber = 0;815 return 0;816 }817 818 *ber = c->post_bit_error.stat[0].uvalue - state->ber_prev;819 state->ber_prev = c->post_bit_error.stat[0].uvalue;820 821 return 0;822}823 824static int si2165_set_oversamp(struct si2165_state *state, u32 dvb_rate)825{826 u64 oversamp;827 u32 reg_value;828 829 if (!dvb_rate)830 return -EINVAL;831 832 oversamp = si2165_get_fe_clk(state);833 oversamp <<= 23;834 do_div(oversamp, dvb_rate);835 reg_value = oversamp & 0x3fffffff;836 837 dev_dbg(&state->client->dev, "Write oversamp=%#x\n", reg_value);838 return si2165_writereg32(state, REG_OVERSAMP, reg_value);839}840 841static int si2165_set_if_freq_shift(struct si2165_state *state)842{843 struct dvb_frontend *fe = &state->fe;844 u64 if_freq_shift;845 s32 reg_value = 0;846 u32 fe_clk = si2165_get_fe_clk(state);847 u32 IF = 0;848 849 if (!fe->ops.tuner_ops.get_if_frequency) {850 dev_err(&state->client->dev,851 "Error: get_if_frequency() not defined at tuner. Can't work without it!\n");852 return -EINVAL;853 }854 855 if (!fe_clk)856 return -EINVAL;857 858 fe->ops.tuner_ops.get_if_frequency(fe, &IF);859 if_freq_shift = IF;860 if_freq_shift <<= 29;861 862 do_div(if_freq_shift, fe_clk);863 reg_value = (s32)if_freq_shift;864 865 if (state->config.inversion)866 reg_value = -reg_value;867 868 reg_value = reg_value & 0x1fffffff;869 870 /* if_freq_shift, usbdump contained 0x023ee08f; */871 return si2165_writereg32(state, REG_IF_FREQ_SHIFT, reg_value);872}873 874static const struct si2165_reg_value_pair dvbt_regs[] = {875 /* standard = DVB-T */876 { REG_DVB_STANDARD, 0x01 },877 /* impulsive_noise_remover */878 { REG_IMPULSIVE_NOISE_REM, 0x01 },879 { REG_AUTO_RESET, 0x00 },880 /* agc2 */881 { REG_AGC2_MIN, 0x41 },882 { REG_AGC2_KACQ, 0x0e },883 { REG_AGC2_KLOC, 0x10 },884 /* agc */885 { REG_AGC_UNFREEZE_THR, 0x03 },886 { REG_AGC_CRESTF_DBX8, 0x78 },887 /* agc */888 { REG_AAF_CRESTF_DBX8, 0x78 },889 { REG_ACI_CRESTF_DBX8, 0x68 },890 /* freq_sync_range */891 REG16(REG_FREQ_SYNC_RANGE, 0x0064),892 /* gp_reg0 */893 { REG_GP_REG0_MSB, 0x00 }894};895 896static int si2165_set_frontend_dvbt(struct dvb_frontend *fe)897{898 int ret;899 struct dtv_frontend_properties *p = &fe->dtv_property_cache;900 struct si2165_state *state = fe->demodulator_priv;901 u32 dvb_rate = 0;902 u16 bw10k;903 u32 bw_hz = p->bandwidth_hz;904 905 dev_dbg(&state->client->dev, "%s: called\n", __func__);906 907 if (!state->has_dvbt)908 return -EINVAL;909 910 /* no bandwidth auto-detection */911 if (bw_hz == 0)912 return -EINVAL;913 914 dvb_rate = bw_hz * 8 / 7;915 bw10k = bw_hz / 10000;916 917 ret = si2165_adjust_pll_divl(state, 12);918 if (ret < 0)919 return ret;920 921 /* bandwidth in 10KHz steps */922 ret = si2165_writereg16(state, REG_T_BANDWIDTH, bw10k);923 if (ret < 0)924 return ret;925 ret = si2165_set_oversamp(state, dvb_rate);926 if (ret < 0)927 return ret;928 929 ret = si2165_write_reg_list(state, dvbt_regs, ARRAY_SIZE(dvbt_regs));930 if (ret < 0)931 return ret;932 933 return 0;934}935 936static const struct si2165_reg_value_pair dvbc_regs[] = {937 /* standard = DVB-C */938 { REG_DVB_STANDARD, 0x05 },939 940 /* agc2 */941 { REG_AGC2_MIN, 0x50 },942 { REG_AGC2_KACQ, 0x0e },943 { REG_AGC2_KLOC, 0x10 },944 /* agc */945 { REG_AGC_UNFREEZE_THR, 0x03 },946 { REG_AGC_CRESTF_DBX8, 0x68 },947 /* agc */948 { REG_AAF_CRESTF_DBX8, 0x68 },949 { REG_ACI_CRESTF_DBX8, 0x50 },950 951 { REG_EQ_AUTO_CONTROL, 0x0d },952 953 { REG_KP_LOCK, 0x05 },954 { REG_CENTRAL_TAP, 0x09 },955 REG16(REG_UNKNOWN_350, 0x3e80),956 957 { REG_AUTO_RESET, 0x01 },958 REG16(REG_UNKNOWN_24C, 0x0000),959 REG16(REG_UNKNOWN_27C, 0x0000),960 { REG_SWEEP_STEP, 0x03 },961 { REG_AGC_IF_TRI, 0x00 },962};963 964static int si2165_set_frontend_dvbc(struct dvb_frontend *fe)965{966 struct si2165_state *state = fe->demodulator_priv;967 int ret;968 struct dtv_frontend_properties *p = &fe->dtv_property_cache;969 const u32 dvb_rate = p->symbol_rate;970 u8 u8tmp;971 972 if (!state->has_dvbc)973 return -EINVAL;974 975 if (dvb_rate == 0)976 return -EINVAL;977 978 ret = si2165_adjust_pll_divl(state, 14);979 if (ret < 0)980 return ret;981 982 /* Oversampling */983 ret = si2165_set_oversamp(state, dvb_rate);984 if (ret < 0)985 return ret;986 987 switch (p->modulation) {988 case QPSK:989 u8tmp = 0x3;990 break;991 case QAM_16:992 u8tmp = 0x7;993 break;994 case QAM_32:995 u8tmp = 0x8;996 break;997 case QAM_64:998 u8tmp = 0x9;999 break;1000 case QAM_128:1001 u8tmp = 0xa;1002 break;1003 case QAM_256:1004 default:1005 u8tmp = 0xb;1006 break;1007 }1008 ret = si2165_writereg8(state, REG_REQ_CONSTELLATION, u8tmp);1009 if (ret < 0)1010 return ret;1011 1012 ret = si2165_writereg32(state, REG_LOCK_TIMEOUT, 0x007a1200);1013 if (ret < 0)1014 return ret;1015 1016 ret = si2165_write_reg_list(state, dvbc_regs, ARRAY_SIZE(dvbc_regs));1017 if (ret < 0)1018 return ret;1019 1020 return 0;1021}1022 1023static const struct si2165_reg_value_pair adc_rewrite[] = {1024 { REG_ADC_RI1, 0x46 },1025 { REG_ADC_RI3, 0x00 },1026 { REG_ADC_RI5, 0x0a },1027 { REG_ADC_RI6, 0xff },1028 { REG_ADC_RI8, 0x70 }1029};1030 1031static int si2165_set_frontend(struct dvb_frontend *fe)1032{1033 struct si2165_state *state = fe->demodulator_priv;1034 struct dtv_frontend_properties *p = &fe->dtv_property_cache;1035 u32 delsys = p->delivery_system;1036 int ret;1037 u8 val[3];1038 1039 /* initial setting of if freq shift */1040 ret = si2165_set_if_freq_shift(state);1041 if (ret < 0)1042 return ret;1043 1044 switch (delsys) {1045 case SYS_DVBT:1046 ret = si2165_set_frontend_dvbt(fe);1047 if (ret < 0)1048 return ret;1049 break;1050 case SYS_DVBC_ANNEX_A:1051 ret = si2165_set_frontend_dvbc(fe);1052 if (ret < 0)1053 return ret;1054 break;1055 default:1056 return -EINVAL;1057 }1058 1059 /* dsp_addr_jump */1060 ret = si2165_writereg32(state, REG_ADDR_JUMP, 0xf4000000);1061 if (ret < 0)1062 return ret;1063 1064 if (fe->ops.tuner_ops.set_params)1065 fe->ops.tuner_ops.set_params(fe);1066 1067 /* recalc if_freq_shift if IF might has changed */1068 ret = si2165_set_if_freq_shift(state);1069 if (ret < 0)1070 return ret;1071 1072 /* boot/wdog status */1073 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);1074 if (ret < 0)1075 return ret;1076 ret = si2165_writereg8(state, REG_WDOG_AND_BOOT, 0x00);1077 if (ret < 0)1078 return ret;1079 1080 /* reset all */1081 ret = si2165_writereg8(state, REG_RST_ALL, 0x00);1082 if (ret < 0)1083 return ret;1084 /* gp_reg0 */1085 ret = si2165_writereg32(state, REG_GP_REG0_LSB, 0x00000000);1086 if (ret < 0)1087 return ret;1088 1089 /* write adc values after each reset*/1090 ret = si2165_write_reg_list(state, adc_rewrite,1091 ARRAY_SIZE(adc_rewrite));1092 if (ret < 0)1093 return ret;1094 1095 /* start_synchro */1096 ret = si2165_writereg8(state, REG_START_SYNCHRO, 0x01);1097 if (ret < 0)1098 return ret;1099 /* boot/wdog status */1100 ret = si2165_readreg8(state, REG_WDOG_AND_BOOT, val);1101 if (ret < 0)1102 return ret;1103 1104 return 0;1105}1106 1107static const struct dvb_frontend_ops si2165_ops = {1108 .info = {1109 .name = "Silicon Labs ",1110 /* For DVB-C */1111 .symbol_rate_min = 1000000,1112 .symbol_rate_max = 7200000,1113 /* For DVB-T */1114 .frequency_stepsize_hz = 166667,1115 .caps = FE_CAN_FEC_1_2 |1116 FE_CAN_FEC_2_3 |1117 FE_CAN_FEC_3_4 |1118 FE_CAN_FEC_5_6 |1119 FE_CAN_FEC_7_8 |1120 FE_CAN_FEC_AUTO |1121 FE_CAN_QPSK |1122 FE_CAN_QAM_16 |1123 FE_CAN_QAM_32 |1124 FE_CAN_QAM_64 |1125 FE_CAN_QAM_128 |1126 FE_CAN_QAM_256 |1127 FE_CAN_GUARD_INTERVAL_AUTO |1128 FE_CAN_HIERARCHY_AUTO |1129 FE_CAN_MUTE_TS |1130 FE_CAN_TRANSMISSION_MODE_AUTO |1131 FE_CAN_RECOVER1132 },1133 1134 .get_tune_settings = si2165_get_tune_settings,1135 1136 .init = si2165_init,1137 .sleep = si2165_sleep,1138 1139 .set_frontend = si2165_set_frontend,1140 .read_status = si2165_read_status,1141 .read_snr = si2165_read_snr,1142 .read_ber = si2165_read_ber,1143};1144 1145static int si2165_probe(struct i2c_client *client)1146{1147 struct si2165_state *state = NULL;1148 struct si2165_platform_data *pdata = client->dev.platform_data;1149 int n;1150 int ret = 0;1151 u8 val;1152 char rev_char;1153 const char *chip_name;1154 static const struct regmap_config regmap_config = {1155 .reg_bits = 16,1156 .val_bits = 8,1157 .max_register = 0x08ff,1158 };1159 1160 /* allocate memory for the internal state */1161 state = kzalloc(sizeof(*state), GFP_KERNEL);1162 if (!state) {1163 ret = -ENOMEM;1164 goto error;1165 }1166 1167 /* create regmap */1168 state->regmap = devm_regmap_init_i2c(client, ®map_config);1169 if (IS_ERR(state->regmap)) {1170 ret = PTR_ERR(state->regmap);1171 goto error;1172 }1173 1174 /* setup the state */1175 state->client = client;1176 state->config.i2c_addr = client->addr;1177 state->config.chip_mode = pdata->chip_mode;1178 state->config.ref_freq_hz = pdata->ref_freq_hz;1179 state->config.inversion = pdata->inversion;1180 1181 if (state->config.ref_freq_hz < 4000000 ||1182 state->config.ref_freq_hz > 27000000) {1183 dev_err(&state->client->dev, "ref_freq of %d Hz not supported by this driver\n",1184 state->config.ref_freq_hz);1185 ret = -EINVAL;1186 goto error;1187 }1188 1189 /* create dvb_frontend */1190 memcpy(&state->fe.ops, &si2165_ops,1191 sizeof(struct dvb_frontend_ops));1192 state->fe.ops.release = NULL;1193 state->fe.demodulator_priv = state;1194 i2c_set_clientdata(client, state);1195 1196 /* powerup */1197 ret = si2165_writereg8(state, REG_CHIP_MODE, state->config.chip_mode);1198 if (ret < 0)1199 goto nodev_error;1200 1201 ret = si2165_readreg8(state, REG_CHIP_MODE, &val);1202 if (ret < 0)1203 goto nodev_error;1204 if (val != state->config.chip_mode)1205 goto nodev_error;1206 1207 ret = si2165_readreg8(state, REG_CHIP_REVCODE, &state->chip_revcode);1208 if (ret < 0)1209 goto nodev_error;1210 1211 ret = si2165_readreg8(state, REV_CHIP_TYPE, &state->chip_type);1212 if (ret < 0)1213 goto nodev_error;1214 1215 /* powerdown */1216 ret = si2165_writereg8(state, REG_CHIP_MODE, SI2165_MODE_OFF);1217 if (ret < 0)1218 goto nodev_error;1219 1220 if (state->chip_revcode < 26)1221 rev_char = 'A' + state->chip_revcode;1222 else1223 rev_char = '?';1224 1225 switch (state->chip_type) {1226 case 0x06:1227 chip_name = "Si2161";1228 state->has_dvbt = true;1229 break;1230 case 0x07:1231 chip_name = "Si2165";1232 state->has_dvbt = true;1233 state->has_dvbc = true;1234 break;1235 default:1236 dev_err(&state->client->dev, "Unsupported Silicon Labs chip (type %d, rev %d)\n",1237 state->chip_type, state->chip_revcode);1238 goto nodev_error;1239 }1240 1241 dev_info(&state->client->dev,1242 "Detected Silicon Labs %s-%c (type %d, rev %d)\n",1243 chip_name, rev_char, state->chip_type,1244 state->chip_revcode);1245 1246 strlcat(state->fe.ops.info.name, chip_name,1247 sizeof(state->fe.ops.info.name));1248 1249 n = 0;1250 if (state->has_dvbt) {1251 state->fe.ops.delsys[n++] = SYS_DVBT;1252 strlcat(state->fe.ops.info.name, " DVB-T",1253 sizeof(state->fe.ops.info.name));1254 }1255 if (state->has_dvbc) {1256 state->fe.ops.delsys[n++] = SYS_DVBC_ANNEX_A;1257 strlcat(state->fe.ops.info.name, " DVB-C",1258 sizeof(state->fe.ops.info.name));1259 }1260 1261 /* return fe pointer */1262 *pdata->fe = &state->fe;1263 1264 return 0;1265 1266nodev_error:1267 ret = -ENODEV;1268error:1269 kfree(state);1270 dev_dbg(&client->dev, "failed=%d\n", ret);1271 return ret;1272}1273 1274static void si2165_remove(struct i2c_client *client)1275{1276 struct si2165_state *state = i2c_get_clientdata(client);1277 1278 dev_dbg(&client->dev, "\n");1279 1280 kfree(state);1281}1282 1283static const struct i2c_device_id si2165_id_table[] = {1284 { "si2165" },1285 {}1286};1287MODULE_DEVICE_TABLE(i2c, si2165_id_table);1288 1289static struct i2c_driver si2165_driver = {1290 .driver = {1291 .name = "si2165",1292 },1293 .probe = si2165_probe,1294 .remove = si2165_remove,1295 .id_table = si2165_id_table,1296};1297 1298module_i2c_driver(si2165_driver);1299 1300MODULE_DESCRIPTION("Silicon Labs Si2165 DVB-C/-T Demodulator driver");1301MODULE_AUTHOR("Matthias Schwarzott <zzam@gentoo.org>");1302MODULE_LICENSE("GPL");1303MODULE_FIRMWARE(SI2165_FIRMWARE_REV_D);1304