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1// SPDX-License-Identifier: GPL-2.02/*3 * Driver for the ST STV0910 DVB-S/S2 demodulator.4 *5 * Copyright (C) 2014-2015 Ralph Metzler <rjkm@metzlerbros.de>6 * Marcus Metzler <mocm@metzlerbros.de>7 * developed for Digital Devices GmbH8 */9 10#include <linux/kernel.h>11#include <linux/module.h>12#include <linux/moduleparam.h>13#include <linux/init.h>14#include <linux/delay.h>15#include <linux/firmware.h>16#include <linux/i2c.h>17#include <asm/div64.h>18 19#include <media/dvb_frontend.h>20#include "stv0910.h"21#include "stv0910_regs.h"22 23#define EXT_CLOCK 3000000024#define TUNING_DELAY 20025#define BER_SRC_S 0x2026#define BER_SRC_S2 0x2027 28static LIST_HEAD(stvlist);29 30enum receive_mode { RCVMODE_NONE, RCVMODE_DVBS, RCVMODE_DVBS2, RCVMODE_AUTO };31 32enum dvbs2_fectype { DVBS2_64K, DVBS2_16K };33 34enum dvbs2_mod_cod {35 DVBS2_DUMMY_PLF, DVBS2_QPSK_1_4, DVBS2_QPSK_1_3, DVBS2_QPSK_2_5,36 DVBS2_QPSK_1_2, DVBS2_QPSK_3_5, DVBS2_QPSK_2_3, DVBS2_QPSK_3_4,37 DVBS2_QPSK_4_5, DVBS2_QPSK_5_6, DVBS2_QPSK_8_9, DVBS2_QPSK_9_10,38 DVBS2_8PSK_3_5, DVBS2_8PSK_2_3, DVBS2_8PSK_3_4, DVBS2_8PSK_5_6,39 DVBS2_8PSK_8_9, DVBS2_8PSK_9_10, DVBS2_16APSK_2_3, DVBS2_16APSK_3_4,40 DVBS2_16APSK_4_5, DVBS2_16APSK_5_6, DVBS2_16APSK_8_9, DVBS2_16APSK_9_10,41 DVBS2_32APSK_3_4, DVBS2_32APSK_4_5, DVBS2_32APSK_5_6, DVBS2_32APSK_8_9,42 DVBS2_32APSK_9_1043};44 45enum fe_stv0910_mod_cod {46 FE_DUMMY_PLF, FE_QPSK_14, FE_QPSK_13, FE_QPSK_25,47 FE_QPSK_12, FE_QPSK_35, FE_QPSK_23, FE_QPSK_34,48 FE_QPSK_45, FE_QPSK_56, FE_QPSK_89, FE_QPSK_910,49 FE_8PSK_35, FE_8PSK_23, FE_8PSK_34, FE_8PSK_56,50 FE_8PSK_89, FE_8PSK_910, FE_16APSK_23, FE_16APSK_34,51 FE_16APSK_45, FE_16APSK_56, FE_16APSK_89, FE_16APSK_910,52 FE_32APSK_34, FE_32APSK_45, FE_32APSK_56, FE_32APSK_89,53 FE_32APSK_91054};55 56enum fe_stv0910_roll_off { FE_SAT_35, FE_SAT_25, FE_SAT_20, FE_SAT_15 };57 58static inline u32 muldiv32(u32 a, u32 b, u32 c)59{60 u64 tmp64;61 62 tmp64 = (u64)a * (u64)b;63 do_div(tmp64, c);64 65 return (u32)tmp64;66}67 68struct stv_base {69 struct list_head stvlist;70 71 u8 adr;72 struct i2c_adapter *i2c;73 struct mutex i2c_lock; /* shared I2C access protect */74 struct mutex reg_lock; /* shared register write protect */75 int count;76 77 u32 extclk;78 u32 mclk;79};80 81struct stv {82 struct stv_base *base;83 struct dvb_frontend fe;84 int nr;85 u16 regoff;86 u8 i2crpt;87 u8 tscfgh;88 u8 tsgeneral;89 u8 tsspeed;90 u8 single;91 unsigned long tune_time;92 93 s32 search_range;94 u32 started;95 u32 demod_lock_time;96 enum receive_mode receive_mode;97 u32 demod_timeout;98 u32 fec_timeout;99 u32 first_time_lock;100 u8 demod_bits;101 u32 symbol_rate;102 103 u8 last_viterbi_rate;104 enum fe_code_rate puncture_rate;105 enum fe_stv0910_mod_cod mod_cod;106 enum dvbs2_fectype fectype;107 u32 pilots;108 enum fe_stv0910_roll_off feroll_off;109 110 int is_standard_broadcast;111 int is_vcm;112 113 u32 cur_scrambling_code;114 115 u32 last_bernumerator;116 u32 last_berdenominator;117 u8 berscale;118 119 u8 vth[6];120};121 122struct slookup {123 s16 value;124 u32 reg_value;125};126 127static int write_reg(struct stv *state, u16 reg, u8 val)128{129 struct i2c_adapter *adap = state->base->i2c;130 u8 data[3] = {reg >> 8, reg & 0xff, val};131 struct i2c_msg msg = {.addr = state->base->adr, .flags = 0,132 .buf = data, .len = 3};133 134 if (i2c_transfer(adap, &msg, 1) != 1) {135 dev_warn(&adap->dev, "i2c write error ([%02x] %04x: %02x)\n",136 state->base->adr, reg, val);137 return -EIO;138 }139 return 0;140}141 142static inline int i2c_read_regs16(struct i2c_adapter *adapter, u8 adr,143 u16 reg, u8 *val, int count)144{145 u8 msg[2] = {reg >> 8, reg & 0xff};146 struct i2c_msg msgs[2] = {{.addr = adr, .flags = 0,147 .buf = msg, .len = 2},148 {.addr = adr, .flags = I2C_M_RD,149 .buf = val, .len = count } };150 151 if (i2c_transfer(adapter, msgs, 2) != 2) {152 dev_warn(&adapter->dev, "i2c read error ([%02x] %04x)\n",153 adr, reg);154 return -EIO;155 }156 return 0;157}158 159static int read_reg(struct stv *state, u16 reg, u8 *val)160{161 return i2c_read_regs16(state->base->i2c, state->base->adr,162 reg, val, 1);163}164 165static int read_regs(struct stv *state, u16 reg, u8 *val, int len)166{167 return i2c_read_regs16(state->base->i2c, state->base->adr,168 reg, val, len);169}170 171static int write_shared_reg(struct stv *state, u16 reg, u8 mask, u8 val)172{173 int status;174 u8 tmp;175 176 mutex_lock(&state->base->reg_lock);177 status = read_reg(state, reg, &tmp);178 if (!status)179 status = write_reg(state, reg, (tmp & ~mask) | (val & mask));180 mutex_unlock(&state->base->reg_lock);181 return status;182}183 184static int write_field(struct stv *state, u32 field, u8 val)185{186 int status;187 u8 shift, mask, old, new;188 189 status = read_reg(state, field >> 16, &old);190 if (status)191 return status;192 mask = field & 0xff;193 shift = (field >> 12) & 0xf;194 new = ((val << shift) & mask) | (old & ~mask);195 if (new == old)196 return 0;197 return write_reg(state, field >> 16, new);198}199 200#define SET_FIELD(_reg, _val) \201 write_field(state, state->nr ? FSTV0910_P2_##_reg : \202 FSTV0910_P1_##_reg, _val)203 204#define SET_REG(_reg, _val) \205 write_reg(state, state->nr ? RSTV0910_P2_##_reg : \206 RSTV0910_P1_##_reg, _val)207 208#define GET_REG(_reg, _val) \209 read_reg(state, state->nr ? RSTV0910_P2_##_reg : \210 RSTV0910_P1_##_reg, _val)211 212static const struct slookup s1_sn_lookup[] = {213 { 0, 9242 }, /* C/N= 0dB */214 { 5, 9105 }, /* C/N= 0.5dB */215 { 10, 8950 }, /* C/N= 1.0dB */216 { 15, 8780 }, /* C/N= 1.5dB */217 { 20, 8566 }, /* C/N= 2.0dB */218 { 25, 8366 }, /* C/N= 2.5dB */219 { 30, 8146 }, /* C/N= 3.0dB */220 { 35, 7908 }, /* C/N= 3.5dB */221 { 40, 7666 }, /* C/N= 4.0dB */222 { 45, 7405 }, /* C/N= 4.5dB */223 { 50, 7136 }, /* C/N= 5.0dB */224 { 55, 6861 }, /* C/N= 5.5dB */225 { 60, 6576 }, /* C/N= 6.0dB */226 { 65, 6330 }, /* C/N= 6.5dB */227 { 70, 6048 }, /* C/N= 7.0dB */228 { 75, 5768 }, /* C/N= 7.5dB */229 { 80, 5492 }, /* C/N= 8.0dB */230 { 85, 5224 }, /* C/N= 8.5dB */231 { 90, 4959 }, /* C/N= 9.0dB */232 { 95, 4709 }, /* C/N= 9.5dB */233 { 100, 4467 }, /* C/N=10.0dB */234 { 105, 4236 }, /* C/N=10.5dB */235 { 110, 4013 }, /* C/N=11.0dB */236 { 115, 3800 }, /* C/N=11.5dB */237 { 120, 3598 }, /* C/N=12.0dB */238 { 125, 3406 }, /* C/N=12.5dB */239 { 130, 3225 }, /* C/N=13.0dB */240 { 135, 3052 }, /* C/N=13.5dB */241 { 140, 2889 }, /* C/N=14.0dB */242 { 145, 2733 }, /* C/N=14.5dB */243 { 150, 2587 }, /* C/N=15.0dB */244 { 160, 2318 }, /* C/N=16.0dB */245 { 170, 2077 }, /* C/N=17.0dB */246 { 180, 1862 }, /* C/N=18.0dB */247 { 190, 1670 }, /* C/N=19.0dB */248 { 200, 1499 }, /* C/N=20.0dB */249 { 210, 1347 }, /* C/N=21.0dB */250 { 220, 1213 }, /* C/N=22.0dB */251 { 230, 1095 }, /* C/N=23.0dB */252 { 240, 992 }, /* C/N=24.0dB */253 { 250, 900 }, /* C/N=25.0dB */254 { 260, 826 }, /* C/N=26.0dB */255 { 270, 758 }, /* C/N=27.0dB */256 { 280, 702 }, /* C/N=28.0dB */257 { 290, 653 }, /* C/N=29.0dB */258 { 300, 613 }, /* C/N=30.0dB */259 { 310, 579 }, /* C/N=31.0dB */260 { 320, 550 }, /* C/N=32.0dB */261 { 330, 526 }, /* C/N=33.0dB */262 { 350, 490 }, /* C/N=33.0dB */263 { 400, 445 }, /* C/N=40.0dB */264 { 450, 430 }, /* C/N=45.0dB */265 { 500, 426 }, /* C/N=50.0dB */266 { 510, 425 } /* C/N=51.0dB */267};268 269static const struct slookup s2_sn_lookup[] = {270 { -30, 13950 }, /* C/N=-2.5dB */271 { -25, 13580 }, /* C/N=-2.5dB */272 { -20, 13150 }, /* C/N=-2.0dB */273 { -15, 12760 }, /* C/N=-1.5dB */274 { -10, 12345 }, /* C/N=-1.0dB */275 { -5, 11900 }, /* C/N=-0.5dB */276 { 0, 11520 }, /* C/N= 0dB */277 { 5, 11080 }, /* C/N= 0.5dB */278 { 10, 10630 }, /* C/N= 1.0dB */279 { 15, 10210 }, /* C/N= 1.5dB */280 { 20, 9790 }, /* C/N= 2.0dB */281 { 25, 9390 }, /* C/N= 2.5dB */282 { 30, 8970 }, /* C/N= 3.0dB */283 { 35, 8575 }, /* C/N= 3.5dB */284 { 40, 8180 }, /* C/N= 4.0dB */285 { 45, 7800 }, /* C/N= 4.5dB */286 { 50, 7430 }, /* C/N= 5.0dB */287 { 55, 7080 }, /* C/N= 5.5dB */288 { 60, 6720 }, /* C/N= 6.0dB */289 { 65, 6320 }, /* C/N= 6.5dB */290 { 70, 6060 }, /* C/N= 7.0dB */291 { 75, 5760 }, /* C/N= 7.5dB */292 { 80, 5480 }, /* C/N= 8.0dB */293 { 85, 5200 }, /* C/N= 8.5dB */294 { 90, 4930 }, /* C/N= 9.0dB */295 { 95, 4680 }, /* C/N= 9.5dB */296 { 100, 4425 }, /* C/N=10.0dB */297 { 105, 4210 }, /* C/N=10.5dB */298 { 110, 3980 }, /* C/N=11.0dB */299 { 115, 3765 }, /* C/N=11.5dB */300 { 120, 3570 }, /* C/N=12.0dB */301 { 125, 3315 }, /* C/N=12.5dB */302 { 130, 3140 }, /* C/N=13.0dB */303 { 135, 2980 }, /* C/N=13.5dB */304 { 140, 2820 }, /* C/N=14.0dB */305 { 145, 2670 }, /* C/N=14.5dB */306 { 150, 2535 }, /* C/N=15.0dB */307 { 160, 2270 }, /* C/N=16.0dB */308 { 170, 2035 }, /* C/N=17.0dB */309 { 180, 1825 }, /* C/N=18.0dB */310 { 190, 1650 }, /* C/N=19.0dB */311 { 200, 1485 }, /* C/N=20.0dB */312 { 210, 1340 }, /* C/N=21.0dB */313 { 220, 1212 }, /* C/N=22.0dB */314 { 230, 1100 }, /* C/N=23.0dB */315 { 240, 1000 }, /* C/N=24.0dB */316 { 250, 910 }, /* C/N=25.0dB */317 { 260, 836 }, /* C/N=26.0dB */318 { 270, 772 }, /* C/N=27.0dB */319 { 280, 718 }, /* C/N=28.0dB */320 { 290, 671 }, /* C/N=29.0dB */321 { 300, 635 }, /* C/N=30.0dB */322 { 310, 602 }, /* C/N=31.0dB */323 { 320, 575 }, /* C/N=32.0dB */324 { 330, 550 }, /* C/N=33.0dB */325 { 350, 517 }, /* C/N=35.0dB */326 { 400, 480 }, /* C/N=40.0dB */327 { 450, 466 }, /* C/N=45.0dB */328 { 500, 464 }, /* C/N=50.0dB */329 { 510, 463 }, /* C/N=51.0dB */330};331 332static const struct slookup padc_lookup[] = {333 { 0, 118000 }, /* PADC= +0dBm */334 { -100, 93600 }, /* PADC= -1dBm */335 { -200, 74500 }, /* PADC= -2dBm */336 { -300, 59100 }, /* PADC= -3dBm */337 { -400, 47000 }, /* PADC= -4dBm */338 { -500, 37300 }, /* PADC= -5dBm */339 { -600, 29650 }, /* PADC= -6dBm */340 { -700, 23520 }, /* PADC= -7dBm */341 { -900, 14850 }, /* PADC= -9dBm */342 { -1100, 9380 }, /* PADC=-11dBm */343 { -1300, 5910 }, /* PADC=-13dBm */344 { -1500, 3730 }, /* PADC=-15dBm */345 { -1700, 2354 }, /* PADC=-17dBm */346 { -1900, 1485 }, /* PADC=-19dBm */347 { -2000, 1179 }, /* PADC=-20dBm */348 { -2100, 1000 }, /* PADC=-21dBm */349};350 351/*********************************************************************352 * Tracking carrier loop carrier QPSK 1/4 to 8PSK 9/10 long Frame353 *********************************************************************/354static const u8 s2car_loop[] = {355 /*356 * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff357 * 20MPon 20MPoff 30MPon 30MPoff358 */359 360 /* FE_QPSK_14 */361 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x2A, 0x1C, 0x3A, 0x3B,362 /* FE_QPSK_13 */363 0x0C, 0x3C, 0x0B, 0x3C, 0x2A, 0x2C, 0x3A, 0x0C, 0x3A, 0x2B,364 /* FE_QPSK_25 */365 0x1C, 0x3C, 0x1B, 0x3C, 0x3A, 0x1C, 0x3A, 0x3B, 0x3A, 0x2B,366 /* FE_QPSK_12 */367 0x0C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,368 /* FE_QPSK_35 */369 0x1C, 0x1C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,370 /* FE_QPSK_23 */371 0x2C, 0x2C, 0x2B, 0x1C, 0x0B, 0x2C, 0x0B, 0x0C, 0x2A, 0x2B,372 /* FE_QPSK_34 */373 0x3C, 0x2C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,374 /* FE_QPSK_45 */375 0x0D, 0x3C, 0x3B, 0x2C, 0x1B, 0x1C, 0x1B, 0x3B, 0x3A, 0x1B,376 /* FE_QPSK_56 */377 0x1D, 0x3C, 0x0C, 0x2C, 0x2B, 0x1C, 0x1B, 0x3B, 0x0B, 0x1B,378 /* FE_QPSK_89 */379 0x3D, 0x0D, 0x0C, 0x2C, 0x2B, 0x0C, 0x2B, 0x2B, 0x0B, 0x0B,380 /* FE_QPSK_910 */381 0x1E, 0x0D, 0x1C, 0x2C, 0x3B, 0x0C, 0x2B, 0x2B, 0x1B, 0x0B,382 /* FE_8PSK_35 */383 0x28, 0x09, 0x28, 0x09, 0x28, 0x09, 0x28, 0x08, 0x28, 0x27,384 /* FE_8PSK_23 */385 0x19, 0x29, 0x19, 0x29, 0x19, 0x29, 0x38, 0x19, 0x28, 0x09,386 /* FE_8PSK_34 */387 0x1A, 0x0B, 0x1A, 0x3A, 0x0A, 0x2A, 0x39, 0x2A, 0x39, 0x1A,388 /* FE_8PSK_56 */389 0x2B, 0x2B, 0x1B, 0x1B, 0x0B, 0x1B, 0x1A, 0x0B, 0x1A, 0x1A,390 /* FE_8PSK_89 */391 0x0C, 0x0C, 0x3B, 0x3B, 0x1B, 0x1B, 0x2A, 0x0B, 0x2A, 0x2A,392 /* FE_8PSK_910 */393 0x0C, 0x1C, 0x0C, 0x3B, 0x2B, 0x1B, 0x3A, 0x0B, 0x2A, 0x2A,394 395 /**********************************************************************396 * Tracking carrier loop carrier 16APSK 2/3 to 32APSK 9/10 long Frame397 **********************************************************************/398 399 /*400 * Modcod 2MPon 2MPoff 5MPon 5MPoff 10MPon 10MPoff 20MPon401 * 20MPoff 30MPon 30MPoff402 */403 404 /* FE_16APSK_23 */405 0x0A, 0x0A, 0x0A, 0x0A, 0x1A, 0x0A, 0x39, 0x0A, 0x29, 0x0A,406 /* FE_16APSK_34 */407 0x0A, 0x0A, 0x0A, 0x0A, 0x0B, 0x0A, 0x2A, 0x0A, 0x1A, 0x0A,408 /* FE_16APSK_45 */409 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,410 /* FE_16APSK_56 */411 0x0A, 0x0A, 0x0A, 0x0A, 0x1B, 0x0A, 0x3A, 0x0A, 0x2A, 0x0A,412 /* FE_16APSK_89 */413 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,414 /* FE_16APSK_910 */415 0x0A, 0x0A, 0x0A, 0x0A, 0x2B, 0x0A, 0x0B, 0x0A, 0x3A, 0x0A,416 /* FE_32APSK_34 */417 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,418 /* FE_32APSK_45 */419 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,420 /* FE_32APSK_56 */421 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,422 /* FE_32APSK_89 */423 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,424 /* FE_32APSK_910 */425 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09, 0x09,426};427 428static u8 get_optim_cloop(struct stv *state,429 enum fe_stv0910_mod_cod mod_cod, u32 pilots)430{431 int i = 0;432 433 if (mod_cod >= FE_32APSK_910)434 i = ((int)FE_32APSK_910 - (int)FE_QPSK_14) * 10;435 else if (mod_cod >= FE_QPSK_14)436 i = ((int)mod_cod - (int)FE_QPSK_14) * 10;437 438 if (state->symbol_rate <= 3000000)439 i += 0;440 else if (state->symbol_rate <= 7000000)441 i += 2;442 else if (state->symbol_rate <= 15000000)443 i += 4;444 else if (state->symbol_rate <= 25000000)445 i += 6;446 else447 i += 8;448 449 if (!pilots)450 i += 1;451 452 return s2car_loop[i];453}454 455static int get_cur_symbol_rate(struct stv *state, u32 *p_symbol_rate)456{457 int status = 0;458 u8 symb_freq0;459 u8 symb_freq1;460 u8 symb_freq2;461 u8 symb_freq3;462 u8 tim_offs0;463 u8 tim_offs1;464 u8 tim_offs2;465 u32 symbol_rate;466 s32 timing_offset;467 468 *p_symbol_rate = 0;469 if (!state->started)470 return status;471 472 read_reg(state, RSTV0910_P2_SFR3 + state->regoff, &symb_freq3);473 read_reg(state, RSTV0910_P2_SFR2 + state->regoff, &symb_freq2);474 read_reg(state, RSTV0910_P2_SFR1 + state->regoff, &symb_freq1);475 read_reg(state, RSTV0910_P2_SFR0 + state->regoff, &symb_freq0);476 read_reg(state, RSTV0910_P2_TMGREG2 + state->regoff, &tim_offs2);477 read_reg(state, RSTV0910_P2_TMGREG1 + state->regoff, &tim_offs1);478 read_reg(state, RSTV0910_P2_TMGREG0 + state->regoff, &tim_offs0);479 480 symbol_rate = ((u32)symb_freq3 << 24) | ((u32)symb_freq2 << 16) |481 ((u32)symb_freq1 << 8) | (u32)symb_freq0;482 timing_offset = ((u32)tim_offs2 << 16) | ((u32)tim_offs1 << 8) |483 (u32)tim_offs0;484 485 if ((timing_offset & (1 << 23)) != 0)486 timing_offset |= 0xFF000000; /* Sign extent */487 488 symbol_rate = (u32)(((u64)symbol_rate * state->base->mclk) >> 32);489 timing_offset = (s32)(((s64)symbol_rate * (s64)timing_offset) >> 29);490 491 *p_symbol_rate = symbol_rate + timing_offset;492 493 return 0;494}495 496static int get_signal_parameters(struct stv *state)497{498 u8 tmp;499 500 if (!state->started)501 return -EINVAL;502 503 if (state->receive_mode == RCVMODE_DVBS2) {504 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);505 state->mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);506 state->pilots = (tmp & 0x01) != 0;507 state->fectype = (enum dvbs2_fectype)((tmp & 0x02) >> 1);508 509 } else if (state->receive_mode == RCVMODE_DVBS) {510 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);511 state->puncture_rate = FEC_NONE;512 switch (tmp & 0x1F) {513 case 0x0d:514 state->puncture_rate = FEC_1_2;515 break;516 case 0x12:517 state->puncture_rate = FEC_2_3;518 break;519 case 0x15:520 state->puncture_rate = FEC_3_4;521 break;522 case 0x18:523 state->puncture_rate = FEC_5_6;524 break;525 case 0x1a:526 state->puncture_rate = FEC_7_8;527 break;528 }529 state->is_vcm = 0;530 state->is_standard_broadcast = 1;531 state->feroll_off = FE_SAT_35;532 }533 return 0;534}535 536static int tracking_optimization(struct stv *state)537{538 u8 tmp;539 540 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, &tmp);541 tmp &= ~0xC0;542 543 switch (state->receive_mode) {544 case RCVMODE_DVBS:545 tmp |= 0x40;546 break;547 case RCVMODE_DVBS2:548 tmp |= 0x80;549 break;550 default:551 tmp |= 0xC0;552 break;553 }554 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, tmp);555 556 if (state->receive_mode == RCVMODE_DVBS2) {557 /* Disable Reed-Solomon */558 write_shared_reg(state,559 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01,560 0x03);561 562 if (state->fectype == DVBS2_64K) {563 u8 aclc = get_optim_cloop(state, state->mod_cod,564 state->pilots);565 566 if (state->mod_cod <= FE_QPSK_910) {567 write_reg(state, RSTV0910_P2_ACLC2S2Q +568 state->regoff, aclc);569 } else if (state->mod_cod <= FE_8PSK_910) {570 write_reg(state, RSTV0910_P2_ACLC2S2Q +571 state->regoff, 0x2a);572 write_reg(state, RSTV0910_P2_ACLC2S28 +573 state->regoff, aclc);574 } else if (state->mod_cod <= FE_16APSK_910) {575 write_reg(state, RSTV0910_P2_ACLC2S2Q +576 state->regoff, 0x2a);577 write_reg(state, RSTV0910_P2_ACLC2S216A +578 state->regoff, aclc);579 } else if (state->mod_cod <= FE_32APSK_910) {580 write_reg(state, RSTV0910_P2_ACLC2S2Q +581 state->regoff, 0x2a);582 write_reg(state, RSTV0910_P2_ACLC2S232A +583 state->regoff, aclc);584 }585 }586 }587 return 0;588}589 590static s32 table_lookup(const struct slookup *table,591 int table_size, u32 reg_value)592{593 s32 value;594 int imin = 0;595 int imax = table_size - 1;596 int i;597 s32 reg_diff;598 599 /* Assumes Table[0].RegValue > Table[imax].RegValue */600 if (reg_value >= table[0].reg_value) {601 value = table[0].value;602 } else if (reg_value <= table[imax].reg_value) {603 value = table[imax].value;604 } else {605 while ((imax - imin) > 1) {606 i = (imax + imin) / 2;607 if ((table[imin].reg_value >= reg_value) &&608 (reg_value >= table[i].reg_value))609 imax = i;610 else611 imin = i;612 }613 614 reg_diff = table[imax].reg_value - table[imin].reg_value;615 value = table[imin].value;616 if (reg_diff != 0)617 value += ((s32)(reg_value - table[imin].reg_value) *618 (s32)(table[imax].value619 - table[imin].value))620 / (reg_diff);621 }622 623 return value;624}625 626static int get_signal_to_noise(struct stv *state, s32 *signal_to_noise)627{628 u8 data0;629 u8 data1;630 u16 data;631 int n_lookup;632 const struct slookup *lookup;633 634 *signal_to_noise = 0;635 636 if (!state->started)637 return -EINVAL;638 639 if (state->receive_mode == RCVMODE_DVBS2) {640 read_reg(state, RSTV0910_P2_NNOSPLHT1 + state->regoff,641 &data1);642 read_reg(state, RSTV0910_P2_NNOSPLHT0 + state->regoff,643 &data0);644 n_lookup = ARRAY_SIZE(s2_sn_lookup);645 lookup = s2_sn_lookup;646 } else {647 read_reg(state, RSTV0910_P2_NNOSDATAT1 + state->regoff,648 &data1);649 read_reg(state, RSTV0910_P2_NNOSDATAT0 + state->regoff,650 &data0);651 n_lookup = ARRAY_SIZE(s1_sn_lookup);652 lookup = s1_sn_lookup;653 }654 data = (((u16)data1) << 8) | (u16)data0;655 *signal_to_noise = table_lookup(lookup, n_lookup, data);656 return 0;657}658 659static int get_bit_error_rate_s(struct stv *state, u32 *bernumerator,660 u32 *berdenominator)661{662 u8 regs[3];663 664 int status = read_regs(state,665 RSTV0910_P2_ERRCNT12 + state->regoff,666 regs, 3);667 668 if (status)669 return -EINVAL;670 671 if ((regs[0] & 0x80) == 0) {672 state->last_berdenominator = 1ULL << ((state->berscale * 2) +673 10 + 3);674 state->last_bernumerator = ((u32)(regs[0] & 0x7F) << 16) |675 ((u32)regs[1] << 8) | regs[2];676 if (state->last_bernumerator < 256 && state->berscale < 6) {677 state->berscale += 1;678 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +679 state->regoff,680 0x20 | state->berscale);681 } else if (state->last_bernumerator > 1024 &&682 state->berscale > 2) {683 state->berscale -= 1;684 status = write_reg(state, RSTV0910_P2_ERRCTRL1 +685 state->regoff, 0x20 |686 state->berscale);687 }688 }689 *bernumerator = state->last_bernumerator;690 *berdenominator = state->last_berdenominator;691 return 0;692}693 694static u32 dvbs2_nbch(enum dvbs2_mod_cod mod_cod, enum dvbs2_fectype fectype)695{696 static const u32 nbch[][2] = {697 { 0, 0}, /* DUMMY_PLF */698 {16200, 3240}, /* QPSK_1_4, */699 {21600, 5400}, /* QPSK_1_3, */700 {25920, 6480}, /* QPSK_2_5, */701 {32400, 7200}, /* QPSK_1_2, */702 {38880, 9720}, /* QPSK_3_5, */703 {43200, 10800}, /* QPSK_2_3, */704 {48600, 11880}, /* QPSK_3_4, */705 {51840, 12600}, /* QPSK_4_5, */706 {54000, 13320}, /* QPSK_5_6, */707 {57600, 14400}, /* QPSK_8_9, */708 {58320, 16000}, /* QPSK_9_10, */709 {43200, 9720}, /* 8PSK_3_5, */710 {48600, 10800}, /* 8PSK_2_3, */711 {51840, 11880}, /* 8PSK_3_4, */712 {54000, 13320}, /* 8PSK_5_6, */713 {57600, 14400}, /* 8PSK_8_9, */714 {58320, 16000}, /* 8PSK_9_10, */715 {43200, 10800}, /* 16APSK_2_3, */716 {48600, 11880}, /* 16APSK_3_4, */717 {51840, 12600}, /* 16APSK_4_5, */718 {54000, 13320}, /* 16APSK_5_6, */719 {57600, 14400}, /* 16APSK_8_9, */720 {58320, 16000}, /* 16APSK_9_10 */721 {48600, 11880}, /* 32APSK_3_4, */722 {51840, 12600}, /* 32APSK_4_5, */723 {54000, 13320}, /* 32APSK_5_6, */724 {57600, 14400}, /* 32APSK_8_9, */725 {58320, 16000}, /* 32APSK_9_10 */726 };727 728 if (mod_cod >= DVBS2_QPSK_1_4 &&729 mod_cod <= DVBS2_32APSK_9_10 && fectype <= DVBS2_16K)730 return nbch[mod_cod][fectype];731 return 64800;732}733 734static int get_bit_error_rate_s2(struct stv *state, u32 *bernumerator,735 u32 *berdenominator)736{737 u8 regs[3];738 739 int status = read_regs(state, RSTV0910_P2_ERRCNT12 + state->regoff,740 regs, 3);741 742 if (status)743 return -EINVAL;744 745 if ((regs[0] & 0x80) == 0) {746 state->last_berdenominator =747 dvbs2_nbch((enum dvbs2_mod_cod)state->mod_cod,748 state->fectype) <<749 (state->berscale * 2);750 state->last_bernumerator = (((u32)regs[0] & 0x7F) << 16) |751 ((u32)regs[1] << 8) | regs[2];752 if (state->last_bernumerator < 256 && state->berscale < 6) {753 state->berscale += 1;754 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,755 0x20 | state->berscale);756 } else if (state->last_bernumerator > 1024 &&757 state->berscale > 2) {758 state->berscale -= 1;759 write_reg(state, RSTV0910_P2_ERRCTRL1 + state->regoff,760 0x20 | state->berscale);761 }762 }763 *bernumerator = state->last_bernumerator;764 *berdenominator = state->last_berdenominator;765 return status;766}767 768static int get_bit_error_rate(struct stv *state, u32 *bernumerator,769 u32 *berdenominator)770{771 *bernumerator = 0;772 *berdenominator = 1;773 774 switch (state->receive_mode) {775 case RCVMODE_DVBS:776 return get_bit_error_rate_s(state,777 bernumerator, berdenominator);778 case RCVMODE_DVBS2:779 return get_bit_error_rate_s2(state,780 bernumerator, berdenominator);781 default:782 break;783 }784 return 0;785}786 787static int set_mclock(struct stv *state, u32 master_clock)788{789 u32 idf = 1;790 u32 odf = 4;791 u32 quartz = state->base->extclk / 1000000;792 u32 fphi = master_clock / 1000000;793 u32 ndiv = (fphi * odf * idf) / quartz;794 u32 cp = 7;795 u32 fvco;796 797 if (ndiv >= 7 && ndiv <= 71)798 cp = 7;799 else if (ndiv >= 72 && ndiv <= 79)800 cp = 8;801 else if (ndiv >= 80 && ndiv <= 87)802 cp = 9;803 else if (ndiv >= 88 && ndiv <= 95)804 cp = 10;805 else if (ndiv >= 96 && ndiv <= 103)806 cp = 11;807 else if (ndiv >= 104 && ndiv <= 111)808 cp = 12;809 else if (ndiv >= 112 && ndiv <= 119)810 cp = 13;811 else if (ndiv >= 120 && ndiv <= 127)812 cp = 14;813 else if (ndiv >= 128 && ndiv <= 135)814 cp = 15;815 else if (ndiv >= 136 && ndiv <= 143)816 cp = 16;817 else if (ndiv >= 144 && ndiv <= 151)818 cp = 17;819 else if (ndiv >= 152 && ndiv <= 159)820 cp = 18;821 else if (ndiv >= 160 && ndiv <= 167)822 cp = 19;823 else if (ndiv >= 168 && ndiv <= 175)824 cp = 20;825 else if (ndiv >= 176 && ndiv <= 183)826 cp = 21;827 else if (ndiv >= 184 && ndiv <= 191)828 cp = 22;829 else if (ndiv >= 192 && ndiv <= 199)830 cp = 23;831 else if (ndiv >= 200 && ndiv <= 207)832 cp = 24;833 else if (ndiv >= 208 && ndiv <= 215)834 cp = 25;835 else if (ndiv >= 216 && ndiv <= 223)836 cp = 26;837 else if (ndiv >= 224 && ndiv <= 225)838 cp = 27;839 840 write_reg(state, RSTV0910_NCOARSE, (cp << 3) | idf);841 write_reg(state, RSTV0910_NCOARSE2, odf);842 write_reg(state, RSTV0910_NCOARSE1, ndiv);843 844 fvco = (quartz * 2 * ndiv) / idf;845 state->base->mclk = fvco / (2 * odf) * 1000000;846 847 return 0;848}849 850static int stop(struct stv *state)851{852 if (state->started) {853 u8 tmp;854 855 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,856 state->tscfgh | 0x01);857 read_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, &tmp);858 tmp &= ~0x01; /* release reset DVBS2 packet delin */859 write_reg(state, RSTV0910_P2_PDELCTRL1 + state->regoff, tmp);860 /* Blind optim*/861 write_reg(state, RSTV0910_P2_AGC2O + state->regoff, 0x5B);862 /* Stop the demod */863 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5c);864 state->started = 0;865 }866 state->receive_mode = RCVMODE_NONE;867 return 0;868}869 870static void set_pls(struct stv *state, u32 pls_code)871{872 if (pls_code == state->cur_scrambling_code)873 return;874 875 /* PLROOT2 bit 2 = gold code */876 write_reg(state, RSTV0910_P2_PLROOT0 + state->regoff,877 pls_code & 0xff);878 write_reg(state, RSTV0910_P2_PLROOT1 + state->regoff,879 (pls_code >> 8) & 0xff);880 write_reg(state, RSTV0910_P2_PLROOT2 + state->regoff,881 0x04 | ((pls_code >> 16) & 0x03));882 state->cur_scrambling_code = pls_code;883}884 885static void set_isi(struct stv *state, u32 isi)886{887 if (isi == NO_STREAM_ID_FILTER)888 return;889 if (isi == 0x80000000) {890 SET_FIELD(FORCE_CONTINUOUS, 1);891 SET_FIELD(TSOUT_NOSYNC, 1);892 } else {893 SET_FIELD(FILTER_EN, 1);894 write_reg(state, RSTV0910_P2_ISIENTRY + state->regoff,895 isi & 0xff);896 write_reg(state, RSTV0910_P2_ISIBITENA + state->regoff, 0xff);897 }898 SET_FIELD(ALGOSWRST, 1);899 SET_FIELD(ALGOSWRST, 0);900}901 902static void set_stream_modes(struct stv *state,903 struct dtv_frontend_properties *p)904{905 set_isi(state, p->stream_id);906 set_pls(state, p->scrambling_sequence_index);907}908 909static int init_search_param(struct stv *state,910 struct dtv_frontend_properties *p)911{912 SET_FIELD(FORCE_CONTINUOUS, 0);913 SET_FIELD(FRAME_MODE, 0);914 SET_FIELD(FILTER_EN, 0);915 SET_FIELD(TSOUT_NOSYNC, 0);916 SET_FIELD(TSFIFO_EMBINDVB, 0);917 SET_FIELD(TSDEL_SYNCBYTE, 0);918 SET_REG(UPLCCST0, 0xe0);919 SET_FIELD(TSINS_TOKEN, 0);920 SET_FIELD(HYSTERESIS_THRESHOLD, 0);921 SET_FIELD(ISIOBS_MODE, 1);922 923 set_stream_modes(state, p);924 return 0;925}926 927static int enable_puncture_rate(struct stv *state, enum fe_code_rate rate)928{929 u8 val;930 931 switch (rate) {932 case FEC_1_2:933 val = 0x01;934 break;935 case FEC_2_3:936 val = 0x02;937 break;938 case FEC_3_4:939 val = 0x04;940 break;941 case FEC_5_6:942 val = 0x08;943 break;944 case FEC_7_8:945 val = 0x20;946 break;947 case FEC_NONE:948 default:949 val = 0x2f;950 break;951 }952 953 return write_reg(state, RSTV0910_P2_PRVIT + state->regoff, val);954}955 956static int set_vth_default(struct stv *state)957{958 state->vth[0] = 0xd7;959 state->vth[1] = 0x85;960 state->vth[2] = 0x58;961 state->vth[3] = 0x3a;962 state->vth[4] = 0x34;963 state->vth[5] = 0x28;964 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);965 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);966 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);967 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);968 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);969 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);970 return 0;971}972 973static int set_vth(struct stv *state)974{975 static const struct slookup vthlookup_table[] = {976 {250, 8780}, /* C/N= 1.5dB */977 {100, 7405}, /* C/N= 4.5dB */978 {40, 6330}, /* C/N= 6.5dB */979 {12, 5224}, /* C/N= 8.5dB */980 {5, 4236} /* C/N=10.5dB */981 };982 983 int i;984 u8 tmp[2];985 int status = read_regs(state,986 RSTV0910_P2_NNOSDATAT1 + state->regoff,987 tmp, 2);988 u16 reg_value = (tmp[0] << 8) | tmp[1];989 s32 vth = table_lookup(vthlookup_table, ARRAY_SIZE(vthlookup_table),990 reg_value);991 992 for (i = 0; i < 6; i += 1)993 if (state->vth[i] > vth)994 state->vth[i] = vth;995 996 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 0, state->vth[0]);997 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 1, state->vth[1]);998 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 2, state->vth[2]);999 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 3, state->vth[3]);1000 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 4, state->vth[4]);1001 write_reg(state, RSTV0910_P2_VTH12 + state->regoff + 5, state->vth[5]);1002 return status;1003}1004 1005static int start(struct stv *state, struct dtv_frontend_properties *p)1006{1007 s32 freq;1008 u8 reg_dmdcfgmd;1009 u16 symb;1010 1011 if (p->symbol_rate < 100000 || p->symbol_rate > 70000000)1012 return -EINVAL;1013 1014 state->receive_mode = RCVMODE_NONE;1015 state->demod_lock_time = 0;1016 1017 /* Demod Stop */1018 if (state->started)1019 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x5C);1020 1021 init_search_param(state, p);1022 1023 if (p->symbol_rate <= 1000000) { /* SR <=1Msps */1024 state->demod_timeout = 3000;1025 state->fec_timeout = 2000;1026 } else if (p->symbol_rate <= 2000000) { /* 1Msps < SR <=2Msps */1027 state->demod_timeout = 2500;1028 state->fec_timeout = 1300;1029 } else if (p->symbol_rate <= 5000000) { /* 2Msps< SR <=5Msps */1030 state->demod_timeout = 1000;1031 state->fec_timeout = 650;1032 } else if (p->symbol_rate <= 10000000) { /* 5Msps< SR <=10Msps */1033 state->demod_timeout = 700;1034 state->fec_timeout = 350;1035 } else if (p->symbol_rate < 20000000) { /* 10Msps< SR <=20Msps */1036 state->demod_timeout = 400;1037 state->fec_timeout = 200;1038 } else { /* SR >=20Msps */1039 state->demod_timeout = 300;1040 state->fec_timeout = 200;1041 }1042 1043 /* Set the Init Symbol rate */1044 symb = muldiv32(p->symbol_rate, 65536, state->base->mclk);1045 write_reg(state, RSTV0910_P2_SFRINIT1 + state->regoff,1046 ((symb >> 8) & 0x7F));1047 write_reg(state, RSTV0910_P2_SFRINIT0 + state->regoff, (symb & 0xFF));1048 1049 state->demod_bits |= 0x80;1050 write_reg(state, RSTV0910_P2_DEMOD + state->regoff, state->demod_bits);1051 1052 /* FE_STV0910_SetSearchStandard */1053 read_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff, ®_dmdcfgmd);1054 write_reg(state, RSTV0910_P2_DMDCFGMD + state->regoff,1055 reg_dmdcfgmd |= 0xC0);1056 1057 write_shared_reg(state,1058 RSTV0910_TSTTSRS, state->nr ? 0x02 : 0x01, 0x00);1059 1060 /* Disable DSS */1061 write_reg(state, RSTV0910_P2_FECM + state->regoff, 0x00);1062 write_reg(state, RSTV0910_P2_PRVIT + state->regoff, 0x2F);1063 1064 enable_puncture_rate(state, FEC_NONE);1065 1066 /* 8PSK 3/5, 8PSK 2/3 Poff tracking optimization WA */1067 write_reg(state, RSTV0910_P2_ACLC2S2Q + state->regoff, 0x0B);1068 write_reg(state, RSTV0910_P2_ACLC2S28 + state->regoff, 0x0A);1069 write_reg(state, RSTV0910_P2_BCLC2S2Q + state->regoff, 0x84);1070 write_reg(state, RSTV0910_P2_BCLC2S28 + state->regoff, 0x84);1071 write_reg(state, RSTV0910_P2_CARHDR + state->regoff, 0x1C);1072 write_reg(state, RSTV0910_P2_CARFREQ + state->regoff, 0x79);1073 1074 write_reg(state, RSTV0910_P2_ACLC2S216A + state->regoff, 0x29);1075 write_reg(state, RSTV0910_P2_ACLC2S232A + state->regoff, 0x09);1076 write_reg(state, RSTV0910_P2_BCLC2S216A + state->regoff, 0x84);1077 write_reg(state, RSTV0910_P2_BCLC2S232A + state->regoff, 0x84);1078 1079 /*1080 * Reset CAR3, bug DVBS2->DVBS1 lock1081 * Note: The bit is only pulsed -> no lock on shared register needed1082 */1083 write_reg(state, RSTV0910_TSTRES0, state->nr ? 0x04 : 0x08);1084 write_reg(state, RSTV0910_TSTRES0, 0);1085 1086 set_vth_default(state);1087 /* Reset demod */1088 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);1089 1090 write_reg(state, RSTV0910_P2_CARCFG + state->regoff, 0x46);1091 1092 if (p->symbol_rate <= 5000000)1093 freq = (state->search_range / 2000) + 80;1094 else1095 freq = (state->search_range / 2000) + 1600;1096 freq = (freq << 16) / (state->base->mclk / 1000);1097 1098 write_reg(state, RSTV0910_P2_CFRUP1 + state->regoff,1099 (freq >> 8) & 0xff);1100 write_reg(state, RSTV0910_P2_CFRUP0 + state->regoff, (freq & 0xff));1101 /* CFR Low Setting */1102 freq = -freq;1103 write_reg(state, RSTV0910_P2_CFRLOW1 + state->regoff,1104 (freq >> 8) & 0xff);1105 write_reg(state, RSTV0910_P2_CFRLOW0 + state->regoff, (freq & 0xff));1106 1107 /* init the demod frequency offset to 0 */1108 write_reg(state, RSTV0910_P2_CFRINIT1 + state->regoff, 0);1109 write_reg(state, RSTV0910_P2_CFRINIT0 + state->regoff, 0);1110 1111 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x1F);1112 /* Trigger acq */1113 write_reg(state, RSTV0910_P2_DMDISTATE + state->regoff, 0x15);1114 1115 state->demod_lock_time += TUNING_DELAY;1116 state->started = 1;1117 1118 return 0;1119}1120 1121static int init_diseqc(struct stv *state)1122{1123 u16 offs = state->nr ? 0x40 : 0; /* Address offset */1124 u8 freq = ((state->base->mclk + 11000 * 32) / (22000 * 32));1125 1126 /* Disable receiver */1127 write_reg(state, RSTV0910_P1_DISRXCFG + offs, 0x00);1128 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0xBA); /* Reset = 1 */1129 write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3A); /* Reset = 0 */1130 write_reg(state, RSTV0910_P1_DISTXF22 + offs, freq);1131 return 0;1132}1133 1134static int probe(struct stv *state)1135{1136 u8 id;1137 1138 state->receive_mode = RCVMODE_NONE;1139 state->started = 0;1140 1141 if (read_reg(state, RSTV0910_MID, &id) < 0)1142 return -ENODEV;1143 1144 if (id != 0x51)1145 return -EINVAL;1146 1147 /* Configure the I2C repeater to off */1148 write_reg(state, RSTV0910_P1_I2CRPT, 0x24);1149 /* Configure the I2C repeater to off */1150 write_reg(state, RSTV0910_P2_I2CRPT, 0x24);1151 /* Set the I2C to oversampling ratio */1152 write_reg(state, RSTV0910_I2CCFG, 0x88); /* state->i2ccfg */1153 1154 write_reg(state, RSTV0910_OUTCFG, 0x00); /* OUTCFG */1155 write_reg(state, RSTV0910_PADCFG, 0x05); /* RFAGC Pads Dev = 05 */1156 write_reg(state, RSTV0910_SYNTCTRL, 0x02); /* SYNTCTRL */1157 write_reg(state, RSTV0910_TSGENERAL, state->tsgeneral); /* TSGENERAL */1158 write_reg(state, RSTV0910_CFGEXT, 0x02); /* CFGEXT */1159 1160 if (state->single)1161 write_reg(state, RSTV0910_GENCFG, 0x14); /* GENCFG */1162 else1163 write_reg(state, RSTV0910_GENCFG, 0x15); /* GENCFG */1164 1165 write_reg(state, RSTV0910_P1_TNRCFG2, 0x02); /* IQSWAP = 0 */1166 write_reg(state, RSTV0910_P2_TNRCFG2, 0x82); /* IQSWAP = 1 */1167 1168 write_reg(state, RSTV0910_P1_CAR3CFG, 0x02);1169 write_reg(state, RSTV0910_P2_CAR3CFG, 0x02);1170 write_reg(state, RSTV0910_P1_DMDCFG4, 0x04);1171 write_reg(state, RSTV0910_P2_DMDCFG4, 0x04);1172 1173 write_reg(state, RSTV0910_TSTRES0, 0x80); /* LDPC Reset */1174 write_reg(state, RSTV0910_TSTRES0, 0x00);1175 1176 write_reg(state, RSTV0910_P1_TSPIDFLT1, 0x00);1177 write_reg(state, RSTV0910_P2_TSPIDFLT1, 0x00);1178 1179 write_reg(state, RSTV0910_P1_TMGCFG2, 0x80);1180 write_reg(state, RSTV0910_P2_TMGCFG2, 0x80);1181 1182 set_mclock(state, 135000000);1183 1184 /* TS output */1185 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);1186 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);1187 write_reg(state, RSTV0910_P1_TSCFGM, 0xC0); /* Manual speed */1188 write_reg(state, RSTV0910_P1_TSCFGL, 0x20);1189 1190 write_reg(state, RSTV0910_P1_TSSPEED, state->tsspeed);1191 1192 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);1193 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);1194 write_reg(state, RSTV0910_P2_TSCFGM, 0xC0); /* Manual speed */1195 write_reg(state, RSTV0910_P2_TSCFGL, 0x20);1196 1197 write_reg(state, RSTV0910_P2_TSSPEED, state->tsspeed);1198 1199 /* Reset stream merger */1200 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh | 0x01);1201 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh | 0x01);1202 write_reg(state, RSTV0910_P1_TSCFGH, state->tscfgh);1203 write_reg(state, RSTV0910_P2_TSCFGH, state->tscfgh);1204 1205 write_reg(state, RSTV0910_P1_I2CRPT, state->i2crpt);1206 write_reg(state, RSTV0910_P2_I2CRPT, state->i2crpt);1207 1208 write_reg(state, RSTV0910_P1_TSINSDELM, 0x17);1209 write_reg(state, RSTV0910_P1_TSINSDELL, 0xff);1210 1211 write_reg(state, RSTV0910_P2_TSINSDELM, 0x17);1212 write_reg(state, RSTV0910_P2_TSINSDELL, 0xff);1213 1214 init_diseqc(state);1215 return 0;1216}1217 1218static int gate_ctrl(struct dvb_frontend *fe, int enable)1219{1220 struct stv *state = fe->demodulator_priv;1221 u8 i2crpt = state->i2crpt & ~0x86;1222 1223 /*1224 * mutex_lock note: Concurrent I2C gate bus accesses must be1225 * prevented (STV0910 = dual demod on a single IC with a single I2C1226 * gate/bus, and two tuners attached), similar to most (if not all)1227 * other I2C host interfaces/buses.1228 *1229 * enable=1 (open I2C gate) will grab the lock1230 * enable=0 (close I2C gate) releases the lock1231 */1232 1233 if (enable) {1234 mutex_lock(&state->base->i2c_lock);1235 i2crpt |= 0x80;1236 } else {1237 i2crpt |= 0x02;1238 }1239 1240 if (write_reg(state, state->nr ? RSTV0910_P2_I2CRPT :1241 RSTV0910_P1_I2CRPT, i2crpt) < 0) {1242 /* don't hold the I2C bus lock on failure */1243 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))1244 mutex_unlock(&state->base->i2c_lock);1245 dev_err(&state->base->i2c->dev,1246 "%s() write_reg failure (enable=%d)\n",1247 __func__, enable);1248 return -EIO;1249 }1250 1251 state->i2crpt = i2crpt;1252 1253 if (!enable)1254 if (!WARN_ON(!mutex_is_locked(&state->base->i2c_lock)))1255 mutex_unlock(&state->base->i2c_lock);1256 return 0;1257}1258 1259static void release(struct dvb_frontend *fe)1260{1261 struct stv *state = fe->demodulator_priv;1262 1263 state->base->count--;1264 if (state->base->count == 0) {1265 list_del(&state->base->stvlist);1266 kfree(state->base);1267 }1268 kfree(state);1269}1270 1271static int set_parameters(struct dvb_frontend *fe)1272{1273 int stat = 0;1274 struct stv *state = fe->demodulator_priv;1275 struct dtv_frontend_properties *p = &fe->dtv_property_cache;1276 1277 stop(state);1278 if (fe->ops.tuner_ops.set_params)1279 fe->ops.tuner_ops.set_params(fe);1280 state->symbol_rate = p->symbol_rate;1281 stat = start(state, p);1282 return stat;1283}1284 1285static int manage_matype_info(struct stv *state)1286{1287 if (!state->started)1288 return -EINVAL;1289 if (state->receive_mode == RCVMODE_DVBS2) {1290 u8 bbheader[2];1291 1292 read_regs(state, RSTV0910_P2_MATSTR1 + state->regoff,1293 bbheader, 2);1294 state->feroll_off =1295 (enum fe_stv0910_roll_off)(bbheader[0] & 0x03);1296 state->is_vcm = (bbheader[0] & 0x10) == 0;1297 state->is_standard_broadcast = (bbheader[0] & 0xFC) == 0xF0;1298 } else if (state->receive_mode == RCVMODE_DVBS) {1299 state->is_vcm = 0;1300 state->is_standard_broadcast = 1;1301 state->feroll_off = FE_SAT_35;1302 }1303 return 0;1304}1305 1306static int read_snr(struct dvb_frontend *fe)1307{1308 struct stv *state = fe->demodulator_priv;1309 struct dtv_frontend_properties *p = &fe->dtv_property_cache;1310 s32 snrval;1311 1312 if (!get_signal_to_noise(state, &snrval)) {1313 p->cnr.stat[0].scale = FE_SCALE_DECIBEL;1314 p->cnr.stat[0].svalue = 100 * snrval; /* fix scale */1315 } else {1316 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1317 }1318 1319 return 0;1320}1321 1322static int read_ber(struct dvb_frontend *fe)1323{1324 struct stv *state = fe->demodulator_priv;1325 struct dtv_frontend_properties *p = &fe->dtv_property_cache;1326 u32 n, d;1327 1328 get_bit_error_rate(state, &n, &d);1329 1330 p->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER;1331 p->pre_bit_error.stat[0].uvalue = n;1332 p->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER;1333 p->pre_bit_count.stat[0].uvalue = d;1334 1335 return 0;1336}1337 1338static void read_signal_strength(struct dvb_frontend *fe)1339{1340 struct stv *state = fe->demodulator_priv;1341 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;1342 u8 reg[2];1343 u16 agc;1344 s32 padc, power = 0;1345 int i;1346 1347 read_regs(state, RSTV0910_P2_AGCIQIN1 + state->regoff, reg, 2);1348 1349 agc = (((u32)reg[0]) << 8) | reg[1];1350 1351 for (i = 0; i < 5; i += 1) {1352 read_regs(state, RSTV0910_P2_POWERI + state->regoff, reg, 2);1353 power += (u32)reg[0] * (u32)reg[0]1354 + (u32)reg[1] * (u32)reg[1];1355 usleep_range(3000, 4000);1356 }1357 power /= 5;1358 1359 padc = table_lookup(padc_lookup, ARRAY_SIZE(padc_lookup), power) + 352;1360 1361 p->strength.stat[0].scale = FE_SCALE_DECIBEL;1362 p->strength.stat[0].svalue = (padc - agc);1363}1364 1365static int read_status(struct dvb_frontend *fe, enum fe_status *status)1366{1367 struct stv *state = fe->demodulator_priv;1368 struct dtv_frontend_properties *p = &fe->dtv_property_cache;1369 u8 dmd_state = 0;1370 u8 dstatus = 0;1371 enum receive_mode cur_receive_mode = RCVMODE_NONE;1372 u32 feclock = 0;1373 1374 *status = 0;1375 1376 read_reg(state, RSTV0910_P2_DMDSTATE + state->regoff, &dmd_state);1377 1378 if (dmd_state & 0x40) {1379 read_reg(state, RSTV0910_P2_DSTATUS + state->regoff, &dstatus);1380 if (dstatus & 0x08)1381 cur_receive_mode = (dmd_state & 0x20) ?1382 RCVMODE_DVBS : RCVMODE_DVBS2;1383 }1384 if (cur_receive_mode == RCVMODE_NONE) {1385 set_vth(state);1386 1387 /* reset signal statistics */1388 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1389 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1390 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1391 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1392 1393 return 0;1394 }1395 1396 *status |= (FE_HAS_SIGNAL1397 | FE_HAS_CARRIER1398 | FE_HAS_VITERBI1399 | FE_HAS_SYNC);1400 1401 if (state->receive_mode == RCVMODE_NONE) {1402 state->receive_mode = cur_receive_mode;1403 state->demod_lock_time = jiffies;1404 state->first_time_lock = 1;1405 1406 get_signal_parameters(state);1407 tracking_optimization(state);1408 1409 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,1410 state->tscfgh);1411 usleep_range(3000, 4000);1412 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,1413 state->tscfgh | 0x01);1414 write_reg(state, RSTV0910_P2_TSCFGH + state->regoff,1415 state->tscfgh);1416 }1417 if (dmd_state & 0x40) {1418 if (state->receive_mode == RCVMODE_DVBS2) {1419 u8 pdelstatus;1420 1421 read_reg(state,1422 RSTV0910_P2_PDELSTATUS1 + state->regoff,1423 &pdelstatus);1424 feclock = (pdelstatus & 0x02) != 0;1425 } else {1426 u8 vstatus;1427 1428 read_reg(state,1429 RSTV0910_P2_VSTATUSVIT + state->regoff,1430 &vstatus);1431 feclock = (vstatus & 0x08) != 0;1432 }1433 }1434 1435 if (feclock) {1436 *status |= FE_HAS_LOCK;1437 1438 if (state->first_time_lock) {1439 u8 tmp;1440 1441 state->first_time_lock = 0;1442 1443 manage_matype_info(state);1444 1445 if (state->receive_mode == RCVMODE_DVBS2) {1446 /*1447 * FSTV0910_P2_MANUALSX_ROLLOFF,1448 * FSTV0910_P2_MANUALS2_ROLLOFF = 01449 */1450 state->demod_bits &= ~0x84;1451 write_reg(state,1452 RSTV0910_P2_DEMOD + state->regoff,1453 state->demod_bits);1454 read_reg(state,1455 RSTV0910_P2_PDELCTRL2 + state->regoff,1456 &tmp);1457 /* reset DVBS2 packet delinator error counter */1458 tmp |= 0x40;1459 write_reg(state,1460 RSTV0910_P2_PDELCTRL2 + state->regoff,1461 tmp);1462 /* reset DVBS2 packet delinator error counter */1463 tmp &= ~0x40;1464 write_reg(state,1465 RSTV0910_P2_PDELCTRL2 + state->regoff,1466 tmp);1467 1468 state->berscale = 2;1469 state->last_bernumerator = 0;1470 state->last_berdenominator = 1;1471 /* force to PRE BCH Rate */1472 write_reg(state,1473 RSTV0910_P2_ERRCTRL1 + state->regoff,1474 BER_SRC_S2 | state->berscale);1475 } else {1476 state->berscale = 2;1477 state->last_bernumerator = 0;1478 state->last_berdenominator = 1;1479 /* force to PRE RS Rate */1480 write_reg(state,1481 RSTV0910_P2_ERRCTRL1 + state->regoff,1482 BER_SRC_S | state->berscale);1483 }1484 /* Reset the Total packet counter */1485 write_reg(state,1486 RSTV0910_P2_FBERCPT4 + state->regoff, 0x00);1487 /*1488 * Reset the packet Error counter2 (and Set it to1489 * infinite error count mode)1490 */1491 write_reg(state,1492 RSTV0910_P2_ERRCTRL2 + state->regoff, 0xc1);1493 1494 set_vth_default(state);1495 if (state->receive_mode == RCVMODE_DVBS)1496 enable_puncture_rate(state,1497 state->puncture_rate);1498 }1499 1500 /* Use highest signaled ModCod for quality */1501 if (state->is_vcm) {1502 u8 tmp;1503 enum fe_stv0910_mod_cod mod_cod;1504 1505 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff,1506 &tmp);1507 mod_cod = (enum fe_stv0910_mod_cod)((tmp & 0x7c) >> 2);1508 1509 if (mod_cod > state->mod_cod)1510 state->mod_cod = mod_cod;1511 }1512 }1513 1514 /* read signal statistics */1515 1516 /* read signal strength */1517 read_signal_strength(fe);1518 1519 /* read carrier/noise on FE_HAS_CARRIER */1520 if (*status & FE_HAS_CARRIER)1521 read_snr(fe);1522 else1523 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1524 1525 /* read ber */1526 if (*status & FE_HAS_VITERBI) {1527 read_ber(fe);1528 } else {1529 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1530 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1531 }1532 1533 return 0;1534}1535 1536static int get_frontend(struct dvb_frontend *fe,1537 struct dtv_frontend_properties *p)1538{1539 struct stv *state = fe->demodulator_priv;1540 u8 tmp;1541 u32 symbolrate;1542 1543 if (state->receive_mode == RCVMODE_DVBS2) {1544 u32 mc;1545 const enum fe_modulation modcod2mod[0x20] = {1546 QPSK, QPSK, QPSK, QPSK,1547 QPSK, QPSK, QPSK, QPSK,1548 QPSK, QPSK, QPSK, QPSK,1549 PSK_8, PSK_8, PSK_8, PSK_8,1550 PSK_8, PSK_8, APSK_16, APSK_16,1551 APSK_16, APSK_16, APSK_16, APSK_16,1552 APSK_32, APSK_32, APSK_32, APSK_32,1553 APSK_32,1554 };1555 const enum fe_code_rate modcod2fec[0x20] = {1556 FEC_NONE, FEC_NONE, FEC_NONE, FEC_2_5,1557 FEC_1_2, FEC_3_5, FEC_2_3, FEC_3_4,1558 FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,1559 FEC_3_5, FEC_2_3, FEC_3_4, FEC_5_6,1560 FEC_8_9, FEC_9_10, FEC_2_3, FEC_3_4,1561 FEC_4_5, FEC_5_6, FEC_8_9, FEC_9_10,1562 FEC_3_4, FEC_4_5, FEC_5_6, FEC_8_9,1563 FEC_9_101564 };1565 read_reg(state, RSTV0910_P2_DMDMODCOD + state->regoff, &tmp);1566 mc = ((tmp & 0x7c) >> 2);1567 p->pilot = (tmp & 0x01) ? PILOT_ON : PILOT_OFF;1568 p->modulation = modcod2mod[mc];1569 p->fec_inner = modcod2fec[mc];1570 } else if (state->receive_mode == RCVMODE_DVBS) {1571 read_reg(state, RSTV0910_P2_VITCURPUN + state->regoff, &tmp);1572 switch (tmp & 0x1F) {1573 case 0x0d:1574 p->fec_inner = FEC_1_2;1575 break;1576 case 0x12:1577 p->fec_inner = FEC_2_3;1578 break;1579 case 0x15:1580 p->fec_inner = FEC_3_4;1581 break;1582 case 0x18:1583 p->fec_inner = FEC_5_6;1584 break;1585 case 0x1a:1586 p->fec_inner = FEC_7_8;1587 break;1588 default:1589 p->fec_inner = FEC_NONE;1590 break;1591 }1592 p->rolloff = ROLLOFF_35;1593 }1594 1595 if (state->receive_mode != RCVMODE_NONE) {1596 get_cur_symbol_rate(state, &symbolrate);1597 p->symbol_rate = symbolrate;1598 }1599 return 0;1600}1601 1602static int tune(struct dvb_frontend *fe, bool re_tune,1603 unsigned int mode_flags,1604 unsigned int *delay, enum fe_status *status)1605{1606 struct stv *state = fe->demodulator_priv;1607 int r;1608 1609 if (re_tune) {1610 r = set_parameters(fe);1611 if (r)1612 return r;1613 state->tune_time = jiffies;1614 }1615 1616 r = read_status(fe, status);1617 if (r)1618 return r;1619 1620 if (*status & FE_HAS_LOCK)1621 return 0;1622 *delay = HZ;1623 1624 return 0;1625}1626 1627static enum dvbfe_algo get_algo(struct dvb_frontend *fe)1628{1629 return DVBFE_ALGO_HW;1630}1631 1632static int set_tone(struct dvb_frontend *fe, enum fe_sec_tone_mode tone)1633{1634 struct stv *state = fe->demodulator_priv;1635 u16 offs = state->nr ? 0x40 : 0;1636 1637 switch (tone) {1638 case SEC_TONE_ON:1639 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x38);1640 case SEC_TONE_OFF:1641 return write_reg(state, RSTV0910_P1_DISTXCFG + offs, 0x3a);1642 default:1643 break;1644 }1645 return -EINVAL;1646}1647 1648static int wait_dis(struct stv *state, u8 flag, u8 val)1649{1650 int i;1651 u8 stat;1652 u16 offs = state->nr ? 0x40 : 0;1653 1654 for (i = 0; i < 10; i++) {1655 read_reg(state, RSTV0910_P1_DISTXSTATUS + offs, &stat);1656 if ((stat & flag) == val)1657 return 0;1658 usleep_range(10000, 11000);1659 }1660 return -ETIMEDOUT;1661}1662 1663static int send_master_cmd(struct dvb_frontend *fe,1664 struct dvb_diseqc_master_cmd *cmd)1665{1666 struct stv *state = fe->demodulator_priv;1667 int i;1668 1669 SET_FIELD(DISEQC_MODE, 2);1670 SET_FIELD(DIS_PRECHARGE, 1);1671 for (i = 0; i < cmd->msg_len; i++) {1672 wait_dis(state, 0x40, 0x00);1673 SET_REG(DISTXFIFO, cmd->msg[i]);1674 }1675 SET_FIELD(DIS_PRECHARGE, 0);1676 wait_dis(state, 0x20, 0x20);1677 return 0;1678}1679 1680static int send_burst(struct dvb_frontend *fe, enum fe_sec_mini_cmd burst)1681{1682 struct stv *state = fe->demodulator_priv;1683 u8 value;1684 1685 if (burst == SEC_MINI_A) {1686 SET_FIELD(DISEQC_MODE, 3);1687 value = 0x00;1688 } else {1689 SET_FIELD(DISEQC_MODE, 2);1690 value = 0xFF;1691 }1692 1693 SET_FIELD(DIS_PRECHARGE, 1);1694 wait_dis(state, 0x40, 0x00);1695 SET_REG(DISTXFIFO, value);1696 SET_FIELD(DIS_PRECHARGE, 0);1697 wait_dis(state, 0x20, 0x20);1698 1699 return 0;1700}1701 1702static int sleep(struct dvb_frontend *fe)1703{1704 struct stv *state = fe->demodulator_priv;1705 1706 stop(state);1707 return 0;1708}1709 1710static const struct dvb_frontend_ops stv0910_ops = {1711 .delsys = { SYS_DVBS, SYS_DVBS2, SYS_DSS },1712 .info = {1713 .name = "ST STV0910",1714 .frequency_min_hz = 950 * MHz,1715 .frequency_max_hz = 2150 * MHz,1716 .symbol_rate_min = 100000,1717 .symbol_rate_max = 70000000,1718 .caps = FE_CAN_INVERSION_AUTO |1719 FE_CAN_FEC_AUTO |1720 FE_CAN_QPSK |1721 FE_CAN_2G_MODULATION |1722 FE_CAN_MULTISTREAM1723 },1724 .sleep = sleep,1725 .release = release,1726 .i2c_gate_ctrl = gate_ctrl,1727 .set_frontend = set_parameters,1728 .get_frontend_algo = get_algo,1729 .get_frontend = get_frontend,1730 .tune = tune,1731 .read_status = read_status,1732 .set_tone = set_tone,1733 1734 .diseqc_send_master_cmd = send_master_cmd,1735 .diseqc_send_burst = send_burst,1736};1737 1738static struct stv_base *match_base(struct i2c_adapter *i2c, u8 adr)1739{1740 struct stv_base *p;1741 1742 list_for_each_entry(p, &stvlist, stvlist)1743 if (p->i2c == i2c && p->adr == adr)1744 return p;1745 return NULL;1746}1747 1748static void stv0910_init_stats(struct stv *state)1749{1750 struct dtv_frontend_properties *p = &state->fe.dtv_property_cache;1751 1752 p->strength.len = 1;1753 p->strength.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1754 p->cnr.len = 1;1755 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1756 p->pre_bit_error.len = 1;1757 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1758 p->pre_bit_count.len = 1;1759 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE;1760}1761 1762struct dvb_frontend *stv0910_attach(struct i2c_adapter *i2c,1763 struct stv0910_cfg *cfg,1764 int nr)1765{1766 struct stv *state;1767 struct stv_base *base;1768 1769 state = kzalloc(sizeof(*state), GFP_KERNEL);1770 if (!state)1771 return NULL;1772 1773 state->tscfgh = 0x20 | (cfg->parallel ? 0 : 0x40);1774 state->tsgeneral = (cfg->parallel == 2) ? 0x02 : 0x00;1775 state->i2crpt = 0x0A | ((cfg->rptlvl & 0x07) << 4);1776 /* use safe tsspeed value if unspecified through stv0910_cfg */1777 state->tsspeed = (cfg->tsspeed ? cfg->tsspeed : 0x28);1778 state->nr = nr;1779 state->regoff = state->nr ? 0 : 0x200;1780 state->search_range = 16000000;1781 state->demod_bits = 0x10; /* Inversion : Auto with reset to 0 */1782 state->receive_mode = RCVMODE_NONE;1783 state->cur_scrambling_code = (~0U);1784 state->single = cfg->single ? 1 : 0;1785 1786 base = match_base(i2c, cfg->adr);1787 if (base) {1788 base->count++;1789 state->base = base;1790 } else {1791 base = kzalloc(sizeof(*base), GFP_KERNEL);1792 if (!base)1793 goto fail;1794 base->i2c = i2c;1795 base->adr = cfg->adr;1796 base->count = 1;1797 base->extclk = cfg->clk ? cfg->clk : 30000000;1798 1799 mutex_init(&base->i2c_lock);1800 mutex_init(&base->reg_lock);1801 state->base = base;1802 if (probe(state) < 0) {1803 dev_info(&i2c->dev, "No demod found at adr %02X on %s\n",1804 cfg->adr, dev_name(&i2c->dev));1805 kfree(base);1806 goto fail;1807 }1808 list_add(&base->stvlist, &stvlist);1809 }1810 state->fe.ops = stv0910_ops;1811 state->fe.demodulator_priv = state;1812 state->nr = nr;1813 1814 dev_info(&i2c->dev, "%s demod found at adr %02X on %s\n",1815 state->fe.ops.info.name, cfg->adr, dev_name(&i2c->dev));1816 1817 stv0910_init_stats(state);1818 1819 return &state->fe;1820 1821fail:1822 kfree(state);1823 return NULL;1824}1825EXPORT_SYMBOL_GPL(stv0910_attach);1826 1827MODULE_DESCRIPTION("ST STV0910 multistandard frontend driver");1828MODULE_AUTHOR("Ralph and Marcus Metzler, Manfred Voelkel");1829MODULE_LICENSE("GPL v2");1830