1632 lines · c
1// SPDX-License-Identifier: GPL-2.02/*3 * adv7180.c Analog Devices ADV7180 video decoder driver4 * Copyright (c) 2009 Intel Corporation5 * Copyright (C) 2013 Cogent Embedded, Inc.6 * Copyright (C) 2013 Renesas Solutions Corp.7 */8#include <linux/mod_devicetable.h>9#include <linux/module.h>10#include <linux/init.h>11#include <linux/errno.h>12#include <linux/kernel.h>13#include <linux/interrupt.h>14#include <linux/i2c.h>15#include <linux/slab.h>16#include <linux/of.h>17#include <linux/gpio/consumer.h>18#include <linux/videodev2.h>19#include <media/v4l2-ioctl.h>20#include <media/v4l2-event.h>21#include <media/v4l2-device.h>22#include <media/v4l2-ctrls.h>23#include <linux/mutex.h>24#include <linux/delay.h>25 26#define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x027#define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x128#define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x229#define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x330#define ADV7180_STD_NTSC_J 0x431#define ADV7180_STD_NTSC_M 0x532#define ADV7180_STD_PAL60 0x633#define ADV7180_STD_NTSC_443 0x734#define ADV7180_STD_PAL_BG 0x835#define ADV7180_STD_PAL_N 0x936#define ADV7180_STD_PAL_M 0xa37#define ADV7180_STD_PAL_M_PED 0xb38#define ADV7180_STD_PAL_COMB_N 0xc39#define ADV7180_STD_PAL_COMB_N_PED 0xd40#define ADV7180_STD_PAL_SECAM 0xe41#define ADV7180_STD_PAL_SECAM_PED 0xf42 43#define ADV7180_REG_INPUT_CONTROL 0x000044#define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f45 46#define ADV7182_REG_INPUT_VIDSEL 0x000247#define ADV7182_REG_INPUT_RESERVED BIT(2)48 49#define ADV7180_REG_OUTPUT_CONTROL 0x000350#define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x000451#define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC552 53#define ADV7180_REG_AUTODETECT_ENABLE 0x000754#define ADV7180_AUTODETECT_DEFAULT 0x7f55/* Contrast */56#define ADV7180_REG_CON 0x0008 /*Unsigned */57#define ADV7180_CON_MIN 058#define ADV7180_CON_DEF 12859#define ADV7180_CON_MAX 25560/* Brightness*/61#define ADV7180_REG_BRI 0x000a /*Signed */62#define ADV7180_BRI_MIN -12863#define ADV7180_BRI_DEF 064#define ADV7180_BRI_MAX 12765/* Hue */66#define ADV7180_REG_HUE 0x000b /*Signed, inverted */67#define ADV7180_HUE_MIN -12768#define ADV7180_HUE_DEF 069#define ADV7180_HUE_MAX 12870 71#define ADV7180_REG_DEF_VALUE_Y 0x000c72#define ADV7180_DEF_VAL_EN 0x173#define ADV7180_DEF_VAL_AUTO_EN 0x274#define ADV7180_REG_CTRL 0x000e75#define ADV7180_CTRL_IRQ_SPACE 0x2076 77#define ADV7180_REG_PWR_MAN 0x0f78#define ADV7180_PWR_MAN_ON 0x0479#define ADV7180_PWR_MAN_OFF 0x2480#define ADV7180_PWR_MAN_RES 0x8081 82#define ADV7180_REG_STATUS1 0x001083#define ADV7180_STATUS1_IN_LOCK 0x0184#define ADV7180_STATUS1_AUTOD_MASK 0x7085#define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x0086#define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x1087#define ADV7180_STATUS1_AUTOD_PAL_M 0x2088#define ADV7180_STATUS1_AUTOD_PAL_60 0x3089#define ADV7180_STATUS1_AUTOD_PAL_B_G 0x4090#define ADV7180_STATUS1_AUTOD_SECAM 0x5091#define ADV7180_STATUS1_AUTOD_PAL_COMB 0x6092#define ADV7180_STATUS1_AUTOD_SECAM_525 0x7093 94#define ADV7180_REG_IDENT 0x001195#define ADV7180_ID_7180 0x1896 97#define ADV7180_REG_STATUS3 0x001398#define ADV7180_REG_ANALOG_CLAMP_CTL 0x001499#define ADV7180_REG_SHAP_FILTER_CTL_1 0x0017100#define ADV7180_REG_CTRL_2 0x001d101#define ADV7180_REG_VSYNC_FIELD_CTL_1 0x0031102#define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12103#define ADV7180_REG_MANUAL_WIN_CTL_1 0x003d104#define ADV7180_REG_MANUAL_WIN_CTL_2 0x003e105#define ADV7180_REG_MANUAL_WIN_CTL_3 0x003f106#define ADV7180_REG_LOCK_CNT 0x0051107#define ADV7180_REG_CVBS_TRIM 0x0052108#define ADV7180_REG_CLAMP_ADJ 0x005a109#define ADV7180_REG_RES_CIR 0x005f110#define ADV7180_REG_DIFF_MODE 0x0060111 112#define ADV7180_REG_ICONF1 0x2040113#define ADV7180_ICONF1_ACTIVE_LOW 0x01114#define ADV7180_ICONF1_PSYNC_ONLY 0x10115#define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0116/* Saturation */117#define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */118#define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */119#define ADV7180_SAT_MIN 0120#define ADV7180_SAT_DEF 128121#define ADV7180_SAT_MAX 255122 123#define ADV7180_IRQ1_LOCK 0x01124#define ADV7180_IRQ1_UNLOCK 0x02125#define ADV7180_REG_ISR1 0x2042126#define ADV7180_REG_ICR1 0x2043127#define ADV7180_REG_IMR1 0x2044128#define ADV7180_REG_IMR2 0x2048129#define ADV7180_IRQ3_AD_CHANGE 0x08130#define ADV7180_REG_ISR3 0x204A131#define ADV7180_REG_ICR3 0x204B132#define ADV7180_REG_IMR3 0x204C133#define ADV7180_REG_IMR4 0x2050134 135#define ADV7180_REG_NTSC_V_BIT_END 0x00E6136#define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F137 138#define ADV7180_REG_VPP_SLAVE_ADDR 0xFD139#define ADV7180_REG_CSI_SLAVE_ADDR 0xFE140 141#define ADV7180_REG_ACE_CTRL1 0x4080142#define ADV7180_REG_ACE_CTRL5 0x4084143#define ADV7180_REG_FLCONTROL 0x40e0144#define ADV7180_FLCONTROL_FL_ENABLE 0x1145 146#define ADV7180_REG_RST_CLAMP 0x809c147#define ADV7180_REG_AGC_ADJ1 0x80b6148#define ADV7180_REG_AGC_ADJ2 0x80c0149 150#define ADV7180_CSI_REG_PWRDN 0x00151#define ADV7180_CSI_PWRDN 0x80152 153#define ADV7180_INPUT_CVBS_AIN1 0x00154#define ADV7180_INPUT_CVBS_AIN2 0x01155#define ADV7180_INPUT_CVBS_AIN3 0x02156#define ADV7180_INPUT_CVBS_AIN4 0x03157#define ADV7180_INPUT_CVBS_AIN5 0x04158#define ADV7180_INPUT_CVBS_AIN6 0x05159#define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06160#define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07161#define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08162#define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09163#define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a164 165#define ADV7182_INPUT_CVBS_AIN1 0x00166#define ADV7182_INPUT_CVBS_AIN2 0x01167#define ADV7182_INPUT_CVBS_AIN3 0x02168#define ADV7182_INPUT_CVBS_AIN4 0x03169#define ADV7182_INPUT_CVBS_AIN5 0x04170#define ADV7182_INPUT_CVBS_AIN6 0x05171#define ADV7182_INPUT_CVBS_AIN7 0x06172#define ADV7182_INPUT_CVBS_AIN8 0x07173#define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08174#define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09175#define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a176#define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b177#define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c178#define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d179#define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e180#define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f181#define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10182#define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11183 184#define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44185#define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42186 187#define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)188 189/* Initial number of frames to skip to avoid possible garbage */190#define ADV7180_NUM_OF_SKIP_FRAMES 2191 192struct adv7180_state;193 194#define ADV7180_FLAG_RESET_POWERED BIT(0)195#define ADV7180_FLAG_V2 BIT(1)196#define ADV7180_FLAG_MIPI_CSI2 BIT(2)197#define ADV7180_FLAG_I2P BIT(3)198 199struct adv7180_chip_info {200 unsigned int flags;201 unsigned int valid_input_mask;202 int (*set_std)(struct adv7180_state *st, unsigned int std);203 int (*select_input)(struct adv7180_state *st, unsigned int input);204 int (*init)(struct adv7180_state *state);205};206 207struct adv7180_state {208 struct v4l2_ctrl_handler ctrl_hdl;209 struct v4l2_subdev sd;210 struct media_pad pad;211 struct mutex mutex; /* mutual excl. when accessing chip */212 int irq;213 struct gpio_desc *pwdn_gpio;214 struct gpio_desc *rst_gpio;215 v4l2_std_id curr_norm;216 bool powered;217 bool streaming;218 u8 input;219 220 struct i2c_client *client;221 unsigned int register_page;222 struct i2c_client *csi_client;223 struct i2c_client *vpp_client;224 const struct adv7180_chip_info *chip_info;225 enum v4l2_field field;226 bool force_bt656_4;227};228#define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \229 struct adv7180_state, \230 ctrl_hdl)->sd)231 232static int adv7180_select_page(struct adv7180_state *state, unsigned int page)233{234 if (state->register_page != page) {235 i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,236 page);237 state->register_page = page;238 }239 240 return 0;241}242 243static int adv7180_write(struct adv7180_state *state, unsigned int reg,244 unsigned int value)245{246 lockdep_assert_held(&state->mutex);247 adv7180_select_page(state, reg >> 8);248 return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);249}250 251static int adv7180_read(struct adv7180_state *state, unsigned int reg)252{253 lockdep_assert_held(&state->mutex);254 adv7180_select_page(state, reg >> 8);255 return i2c_smbus_read_byte_data(state->client, reg & 0xff);256}257 258static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,259 unsigned int value)260{261 return i2c_smbus_write_byte_data(state->csi_client, reg, value);262}263 264static int adv7180_set_video_standard(struct adv7180_state *state,265 unsigned int std)266{267 return state->chip_info->set_std(state, std);268}269 270static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,271 unsigned int value)272{273 return i2c_smbus_write_byte_data(state->vpp_client, reg, value);274}275 276static v4l2_std_id adv7180_std_to_v4l2(u8 status1)277{278 /* in case V4L2_IN_ST_NO_SIGNAL */279 if (!(status1 & ADV7180_STATUS1_IN_LOCK))280 return V4L2_STD_UNKNOWN;281 282 switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {283 case ADV7180_STATUS1_AUTOD_NTSM_M_J:284 return V4L2_STD_NTSC;285 case ADV7180_STATUS1_AUTOD_NTSC_4_43:286 return V4L2_STD_NTSC_443;287 case ADV7180_STATUS1_AUTOD_PAL_M:288 return V4L2_STD_PAL_M;289 case ADV7180_STATUS1_AUTOD_PAL_60:290 return V4L2_STD_PAL_60;291 case ADV7180_STATUS1_AUTOD_PAL_B_G:292 return V4L2_STD_PAL;293 case ADV7180_STATUS1_AUTOD_SECAM:294 return V4L2_STD_SECAM;295 case ADV7180_STATUS1_AUTOD_PAL_COMB:296 return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;297 case ADV7180_STATUS1_AUTOD_SECAM_525:298 return V4L2_STD_SECAM;299 default:300 return V4L2_STD_UNKNOWN;301 }302}303 304static int v4l2_std_to_adv7180(v4l2_std_id std)305{306 if (std == V4L2_STD_PAL_60)307 return ADV7180_STD_PAL60;308 if (std == V4L2_STD_NTSC_443)309 return ADV7180_STD_NTSC_443;310 if (std == V4L2_STD_PAL_N)311 return ADV7180_STD_PAL_N;312 if (std == V4L2_STD_PAL_M)313 return ADV7180_STD_PAL_M;314 if (std == V4L2_STD_PAL_Nc)315 return ADV7180_STD_PAL_COMB_N;316 317 if (std & V4L2_STD_PAL)318 return ADV7180_STD_PAL_BG;319 if (std & V4L2_STD_NTSC)320 return ADV7180_STD_NTSC_M;321 if (std & V4L2_STD_SECAM)322 return ADV7180_STD_PAL_SECAM;323 324 return -EINVAL;325}326 327static u32 adv7180_status_to_v4l2(u8 status1)328{329 if (!(status1 & ADV7180_STATUS1_IN_LOCK))330 return V4L2_IN_ST_NO_SIGNAL;331 332 return 0;333}334 335static int __adv7180_status(struct adv7180_state *state, u32 *status,336 v4l2_std_id *std)337{338 int status1 = adv7180_read(state, ADV7180_REG_STATUS1);339 340 if (status1 < 0)341 return status1;342 343 if (status)344 *status = adv7180_status_to_v4l2(status1);345 if (std)346 *std = adv7180_std_to_v4l2(status1);347 348 return 0;349}350 351static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)352{353 return container_of(sd, struct adv7180_state, sd);354}355 356static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)357{358 struct adv7180_state *state = to_state(sd);359 int err = mutex_lock_interruptible(&state->mutex);360 if (err)361 return err;362 363 if (state->streaming) {364 err = -EBUSY;365 goto unlock;366 }367 368 err = adv7180_set_video_standard(state,369 ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);370 if (err)371 goto unlock;372 373 msleep(100);374 __adv7180_status(state, NULL, std);375 376 err = v4l2_std_to_adv7180(state->curr_norm);377 if (err < 0)378 goto unlock;379 380 err = adv7180_set_video_standard(state, err);381 382unlock:383 mutex_unlock(&state->mutex);384 return err;385}386 387static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,388 u32 output, u32 config)389{390 struct adv7180_state *state = to_state(sd);391 int ret = mutex_lock_interruptible(&state->mutex);392 393 if (ret)394 return ret;395 396 if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {397 ret = -EINVAL;398 goto out;399 }400 401 ret = state->chip_info->select_input(state, input);402 403 if (ret == 0)404 state->input = input;405out:406 mutex_unlock(&state->mutex);407 return ret;408}409 410static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)411{412 struct adv7180_state *state = to_state(sd);413 int ret = mutex_lock_interruptible(&state->mutex);414 if (ret)415 return ret;416 417 ret = __adv7180_status(state, status, NULL);418 mutex_unlock(&state->mutex);419 return ret;420}421 422static int adv7180_program_std(struct adv7180_state *state)423{424 int ret;425 426 ret = v4l2_std_to_adv7180(state->curr_norm);427 if (ret < 0)428 return ret;429 430 ret = adv7180_set_video_standard(state, ret);431 if (ret < 0)432 return ret;433 return 0;434}435 436static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)437{438 struct adv7180_state *state = to_state(sd);439 int ret = mutex_lock_interruptible(&state->mutex);440 441 if (ret)442 return ret;443 444 /* Make sure we can support this std */445 ret = v4l2_std_to_adv7180(std);446 if (ret < 0)447 goto out;448 449 state->curr_norm = std;450 451 ret = adv7180_program_std(state);452out:453 mutex_unlock(&state->mutex);454 return ret;455}456 457static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)458{459 struct adv7180_state *state = to_state(sd);460 461 *norm = state->curr_norm;462 463 return 0;464}465 466static int adv7180_get_frame_interval(struct v4l2_subdev *sd,467 struct v4l2_subdev_state *sd_state,468 struct v4l2_subdev_frame_interval *fi)469{470 struct adv7180_state *state = to_state(sd);471 472 /*473 * FIXME: Implement support for V4L2_SUBDEV_FORMAT_TRY, using the V4L2474 * subdev active state API.475 */476 if (fi->which != V4L2_SUBDEV_FORMAT_ACTIVE)477 return -EINVAL;478 479 if (state->curr_norm & V4L2_STD_525_60) {480 fi->interval.numerator = 1001;481 fi->interval.denominator = 30000;482 } else {483 fi->interval.numerator = 1;484 fi->interval.denominator = 25;485 }486 487 return 0;488}489 490static void adv7180_set_power_pin(struct adv7180_state *state, bool on)491{492 if (!state->pwdn_gpio)493 return;494 495 if (on) {496 gpiod_set_value_cansleep(state->pwdn_gpio, 0);497 usleep_range(5000, 10000);498 } else {499 gpiod_set_value_cansleep(state->pwdn_gpio, 1);500 }501}502 503static void adv7180_set_reset_pin(struct adv7180_state *state, bool on)504{505 if (!state->rst_gpio)506 return;507 508 if (on) {509 gpiod_set_value_cansleep(state->rst_gpio, 1);510 } else {511 gpiod_set_value_cansleep(state->rst_gpio, 0);512 usleep_range(5000, 10000);513 }514}515 516static int adv7180_set_power(struct adv7180_state *state, bool on)517{518 u8 val;519 int ret;520 521 if (on)522 val = ADV7180_PWR_MAN_ON;523 else524 val = ADV7180_PWR_MAN_OFF;525 526 ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);527 if (ret)528 return ret;529 530 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {531 if (on) {532 adv7180_csi_write(state, 0xDE, 0x02);533 adv7180_csi_write(state, 0xD2, 0xF7);534 adv7180_csi_write(state, 0xD8, 0x65);535 adv7180_csi_write(state, 0xE0, 0x09);536 adv7180_csi_write(state, 0x2C, 0x00);537 if (state->field == V4L2_FIELD_NONE)538 adv7180_csi_write(state, 0x1D, 0x80);539 adv7180_csi_write(state, 0x00, 0x00);540 } else {541 adv7180_csi_write(state, 0x00, 0x80);542 }543 }544 545 return 0;546}547 548static int adv7180_s_power(struct v4l2_subdev *sd, int on)549{550 struct adv7180_state *state = to_state(sd);551 int ret;552 553 ret = mutex_lock_interruptible(&state->mutex);554 if (ret)555 return ret;556 557 ret = adv7180_set_power(state, on);558 if (ret == 0)559 state->powered = on;560 561 mutex_unlock(&state->mutex);562 return ret;563}564 565static const char * const test_pattern_menu[] = {566 "Single color",567 "Color bars",568 "Luma ramp",569 "Boundary box",570 "Disable",571};572 573static int adv7180_test_pattern(struct adv7180_state *state, int value)574{575 unsigned int reg = 0;576 577 /* Map menu value into register value */578 if (value < 3)579 reg = value;580 if (value == 3)581 reg = 5;582 583 adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg);584 585 if (value == ARRAY_SIZE(test_pattern_menu) - 1) {586 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);587 reg &= ~ADV7180_DEF_VAL_EN;588 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);589 return 0;590 }591 592 reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);593 reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN;594 adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);595 596 return 0;597}598 599static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)600{601 struct v4l2_subdev *sd = to_adv7180_sd(ctrl);602 struct adv7180_state *state = to_state(sd);603 int ret = mutex_lock_interruptible(&state->mutex);604 int val;605 606 if (ret)607 return ret;608 val = ctrl->val;609 switch (ctrl->id) {610 case V4L2_CID_BRIGHTNESS:611 ret = adv7180_write(state, ADV7180_REG_BRI, val);612 break;613 case V4L2_CID_HUE:614 /*Hue is inverted according to HSL chart */615 ret = adv7180_write(state, ADV7180_REG_HUE, -val);616 break;617 case V4L2_CID_CONTRAST:618 ret = adv7180_write(state, ADV7180_REG_CON, val);619 break;620 case V4L2_CID_SATURATION:621 /*622 *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE623 *Let's not confuse the user, everybody understands saturation624 */625 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);626 if (ret < 0)627 break;628 ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);629 break;630 case V4L2_CID_ADV_FAST_SWITCH:631 if (ctrl->val) {632 /* ADI required write */633 adv7180_write(state, 0x80d9, 0x44);634 adv7180_write(state, ADV7180_REG_FLCONTROL,635 ADV7180_FLCONTROL_FL_ENABLE);636 } else {637 /* ADI required write */638 adv7180_write(state, 0x80d9, 0xc4);639 adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);640 }641 break;642 case V4L2_CID_TEST_PATTERN:643 ret = adv7180_test_pattern(state, val);644 break;645 default:646 ret = -EINVAL;647 }648 649 mutex_unlock(&state->mutex);650 return ret;651}652 653static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {654 .s_ctrl = adv7180_s_ctrl,655};656 657static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {658 .ops = &adv7180_ctrl_ops,659 .id = V4L2_CID_ADV_FAST_SWITCH,660 .name = "Fast Switching",661 .type = V4L2_CTRL_TYPE_BOOLEAN,662 .min = 0,663 .max = 1,664 .step = 1,665};666 667static int adv7180_init_controls(struct adv7180_state *state)668{669 v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);670 671 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,672 V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,673 ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);674 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,675 V4L2_CID_CONTRAST, ADV7180_CON_MIN,676 ADV7180_CON_MAX, 1, ADV7180_CON_DEF);677 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,678 V4L2_CID_SATURATION, ADV7180_SAT_MIN,679 ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);680 v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,681 V4L2_CID_HUE, ADV7180_HUE_MIN,682 ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);683 v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);684 685 v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl, &adv7180_ctrl_ops,686 V4L2_CID_TEST_PATTERN,687 ARRAY_SIZE(test_pattern_menu) - 1,688 0, ARRAY_SIZE(test_pattern_menu) - 1,689 test_pattern_menu);690 691 state->sd.ctrl_handler = &state->ctrl_hdl;692 if (state->ctrl_hdl.error) {693 int err = state->ctrl_hdl.error;694 695 v4l2_ctrl_handler_free(&state->ctrl_hdl);696 return err;697 }698 v4l2_ctrl_handler_setup(&state->ctrl_hdl);699 700 return 0;701}702static void adv7180_exit_controls(struct adv7180_state *state)703{704 v4l2_ctrl_handler_free(&state->ctrl_hdl);705}706 707static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,708 struct v4l2_subdev_state *sd_state,709 struct v4l2_subdev_mbus_code_enum *code)710{711 if (code->index != 0)712 return -EINVAL;713 714 code->code = MEDIA_BUS_FMT_UYVY8_2X8;715 716 return 0;717}718 719static int adv7180_mbus_fmt(struct v4l2_subdev *sd,720 struct v4l2_mbus_framefmt *fmt)721{722 struct adv7180_state *state = to_state(sd);723 724 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;725 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;726 fmt->width = 720;727 fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;728 729 if (state->field == V4L2_FIELD_ALTERNATE)730 fmt->height /= 2;731 732 return 0;733}734 735static int adv7180_set_field_mode(struct adv7180_state *state)736{737 if (!(state->chip_info->flags & ADV7180_FLAG_I2P))738 return 0;739 740 if (state->field == V4L2_FIELD_NONE) {741 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {742 adv7180_csi_write(state, 0x01, 0x20);743 adv7180_csi_write(state, 0x02, 0x28);744 adv7180_csi_write(state, 0x03, 0x38);745 adv7180_csi_write(state, 0x04, 0x30);746 adv7180_csi_write(state, 0x05, 0x30);747 adv7180_csi_write(state, 0x06, 0x80);748 adv7180_csi_write(state, 0x07, 0x70);749 adv7180_csi_write(state, 0x08, 0x50);750 }751 adv7180_vpp_write(state, 0xa3, 0x00);752 adv7180_vpp_write(state, 0x5b, 0x00);753 adv7180_vpp_write(state, 0x55, 0x80);754 } else {755 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {756 adv7180_csi_write(state, 0x01, 0x18);757 adv7180_csi_write(state, 0x02, 0x18);758 adv7180_csi_write(state, 0x03, 0x30);759 adv7180_csi_write(state, 0x04, 0x20);760 adv7180_csi_write(state, 0x05, 0x28);761 adv7180_csi_write(state, 0x06, 0x40);762 adv7180_csi_write(state, 0x07, 0x58);763 adv7180_csi_write(state, 0x08, 0x30);764 }765 adv7180_vpp_write(state, 0xa3, 0x70);766 adv7180_vpp_write(state, 0x5b, 0x80);767 adv7180_vpp_write(state, 0x55, 0x00);768 }769 770 return 0;771}772 773static int adv7180_get_pad_format(struct v4l2_subdev *sd,774 struct v4l2_subdev_state *sd_state,775 struct v4l2_subdev_format *format)776{777 struct adv7180_state *state = to_state(sd);778 779 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {780 format->format = *v4l2_subdev_state_get_format(sd_state, 0);781 } else {782 adv7180_mbus_fmt(sd, &format->format);783 format->format.field = state->field;784 }785 786 return 0;787}788 789static int adv7180_set_pad_format(struct v4l2_subdev *sd,790 struct v4l2_subdev_state *sd_state,791 struct v4l2_subdev_format *format)792{793 struct adv7180_state *state = to_state(sd);794 struct v4l2_mbus_framefmt *framefmt;795 int ret;796 797 switch (format->format.field) {798 case V4L2_FIELD_NONE:799 if (state->chip_info->flags & ADV7180_FLAG_I2P)800 break;801 fallthrough;802 default:803 format->format.field = V4L2_FIELD_ALTERNATE;804 break;805 }806 807 ret = adv7180_mbus_fmt(sd, &format->format);808 809 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {810 if (state->field != format->format.field) {811 state->field = format->format.field;812 adv7180_set_power(state, false);813 adv7180_set_field_mode(state);814 adv7180_set_power(state, true);815 }816 } else {817 framefmt = v4l2_subdev_state_get_format(sd_state, 0);818 *framefmt = format->format;819 }820 821 return ret;822}823 824static int adv7180_init_state(struct v4l2_subdev *sd,825 struct v4l2_subdev_state *sd_state)826{827 struct v4l2_subdev_format fmt = {828 .which = sd_state ? V4L2_SUBDEV_FORMAT_TRY829 : V4L2_SUBDEV_FORMAT_ACTIVE,830 };831 832 return adv7180_set_pad_format(sd, sd_state, &fmt);833}834 835static int adv7180_get_mbus_config(struct v4l2_subdev *sd,836 unsigned int pad,837 struct v4l2_mbus_config *cfg)838{839 struct adv7180_state *state = to_state(sd);840 841 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {842 cfg->type = V4L2_MBUS_CSI2_DPHY;843 cfg->bus.mipi_csi2.num_data_lanes = 1;844 cfg->bus.mipi_csi2.flags = 0;845 } else {846 /*847 * The ADV7180 sensor supports BT.601/656 output modes.848 * The BT.656 is default and not yet configurable by s/w.849 */850 cfg->bus.parallel.flags = V4L2_MBUS_MASTER |851 V4L2_MBUS_PCLK_SAMPLE_RISING |852 V4L2_MBUS_DATA_ACTIVE_HIGH;853 cfg->type = V4L2_MBUS_BT656;854 }855 856 return 0;857}858 859static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)860{861 *frames = ADV7180_NUM_OF_SKIP_FRAMES;862 863 return 0;864}865 866static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspect)867{868 struct adv7180_state *state = to_state(sd);869 870 if (state->curr_norm & V4L2_STD_525_60) {871 aspect->numerator = 11;872 aspect->denominator = 10;873 } else {874 aspect->numerator = 54;875 aspect->denominator = 59;876 }877 878 return 0;879}880 881static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)882{883 *norm = V4L2_STD_ALL;884 return 0;885}886 887static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)888{889 struct adv7180_state *state = to_state(sd);890 int ret;891 892 /* It's always safe to stop streaming, no need to take the lock */893 if (!enable) {894 state->streaming = enable;895 return 0;896 }897 898 /* Must wait until querystd released the lock */899 ret = mutex_lock_interruptible(&state->mutex);900 if (ret)901 return ret;902 state->streaming = enable;903 mutex_unlock(&state->mutex);904 return 0;905}906 907static int adv7180_subscribe_event(struct v4l2_subdev *sd,908 struct v4l2_fh *fh,909 struct v4l2_event_subscription *sub)910{911 switch (sub->type) {912 case V4L2_EVENT_SOURCE_CHANGE:913 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);914 case V4L2_EVENT_CTRL:915 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);916 default:917 return -EINVAL;918 }919}920 921static const struct v4l2_subdev_video_ops adv7180_video_ops = {922 .s_std = adv7180_s_std,923 .g_std = adv7180_g_std,924 .querystd = adv7180_querystd,925 .g_input_status = adv7180_g_input_status,926 .s_routing = adv7180_s_routing,927 .g_pixelaspect = adv7180_g_pixelaspect,928 .g_tvnorms = adv7180_g_tvnorms,929 .s_stream = adv7180_s_stream,930};931 932static const struct v4l2_subdev_core_ops adv7180_core_ops = {933 .s_power = adv7180_s_power,934 .subscribe_event = adv7180_subscribe_event,935 .unsubscribe_event = v4l2_event_subdev_unsubscribe,936};937 938static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {939 .enum_mbus_code = adv7180_enum_mbus_code,940 .set_fmt = adv7180_set_pad_format,941 .get_fmt = adv7180_get_pad_format,942 .get_frame_interval = adv7180_get_frame_interval,943 .get_mbus_config = adv7180_get_mbus_config,944};945 946static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {947 .g_skip_frames = adv7180_get_skip_frames,948};949 950static const struct v4l2_subdev_ops adv7180_ops = {951 .core = &adv7180_core_ops,952 .video = &adv7180_video_ops,953 .pad = &adv7180_pad_ops,954 .sensor = &adv7180_sensor_ops,955};956 957static const struct v4l2_subdev_internal_ops adv7180_internal_ops = {958 .init_state = adv7180_init_state,959};960 961static irqreturn_t adv7180_irq(int irq, void *devid)962{963 struct adv7180_state *state = devid;964 u8 isr3;965 966 mutex_lock(&state->mutex);967 isr3 = adv7180_read(state, ADV7180_REG_ISR3);968 /* clear */969 adv7180_write(state, ADV7180_REG_ICR3, isr3);970 971 if (isr3 & ADV7180_IRQ3_AD_CHANGE) {972 static const struct v4l2_event src_ch = {973 .type = V4L2_EVENT_SOURCE_CHANGE,974 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,975 };976 977 v4l2_subdev_notify_event(&state->sd, &src_ch);978 }979 mutex_unlock(&state->mutex);980 981 return IRQ_HANDLED;982}983 984static int adv7180_init(struct adv7180_state *state)985{986 int ret;987 988 /* ITU-R BT.656-4 compatible */989 ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,990 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);991 if (ret < 0)992 return ret;993 994 /* Manually set V bit end position in NTSC mode */995 return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,996 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);997}998 999static int adv7180_set_std(struct adv7180_state *state, unsigned int std)1000{1001 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,1002 (std << 4) | state->input);1003}1004 1005static int adv7180_select_input(struct adv7180_state *state, unsigned int input)1006{1007 int ret;1008 1009 ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);1010 if (ret < 0)1011 return ret;1012 1013 ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;1014 ret |= input;1015 return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);1016}1017 1018static int adv7182_init(struct adv7180_state *state)1019{1020 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)1021 adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,1022 ADV7180_DEFAULT_CSI_I2C_ADDR << 1);1023 1024 if (state->chip_info->flags & ADV7180_FLAG_I2P)1025 adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,1026 ADV7180_DEFAULT_VPP_I2C_ADDR << 1);1027 1028 if (state->chip_info->flags & ADV7180_FLAG_V2) {1029 /* ADI recommended writes for improved video quality */1030 adv7180_write(state, 0x0080, 0x51);1031 adv7180_write(state, 0x0081, 0x51);1032 adv7180_write(state, 0x0082, 0x68);1033 }1034 1035 /* ADI required writes */1036 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {1037 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x4e);1038 adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);1039 adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);1040 } else {1041 if (state->chip_info->flags & ADV7180_FLAG_V2) {1042 if (state->force_bt656_4) {1043 /* ITU-R BT.656-4 compatible */1044 adv7180_write(state,1045 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,1046 ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);1047 /* Manually set NEWAVMODE */1048 adv7180_write(state,1049 ADV7180_REG_VSYNC_FIELD_CTL_1,1050 ADV7180_VSYNC_FIELD_CTL_1_NEWAV);1051 /* Manually set V bit end position in NTSC mode */1052 adv7180_write(state,1053 ADV7180_REG_NTSC_V_BIT_END,1054 ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);1055 } else {1056 adv7180_write(state,1057 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,1058 0x17);1059 }1060 } else {1061 adv7180_write(state,1062 ADV7180_REG_EXTENDED_OUTPUT_CONTROL,1063 0x07);1064 }1065 adv7180_write(state, ADV7180_REG_OUTPUT_CONTROL, 0x0c);1066 adv7180_write(state, ADV7180_REG_CTRL_2, 0x40);1067 }1068 1069 adv7180_write(state, 0x0013, 0x00);1070 1071 return 0;1072}1073 1074static int adv7182_set_std(struct adv7180_state *state, unsigned int std)1075{1076 /* Failing to set the reserved bit can result in increased video noise */1077 return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL,1078 (std << 4) | ADV7182_REG_INPUT_RESERVED);1079}1080 1081enum adv7182_input_type {1082 ADV7182_INPUT_TYPE_CVBS,1083 ADV7182_INPUT_TYPE_DIFF_CVBS,1084 ADV7182_INPUT_TYPE_SVIDEO,1085 ADV7182_INPUT_TYPE_YPBPR,1086};1087 1088static enum adv7182_input_type adv7182_get_input_type(unsigned int input)1089{1090 switch (input) {1091 case ADV7182_INPUT_CVBS_AIN1:1092 case ADV7182_INPUT_CVBS_AIN2:1093 case ADV7182_INPUT_CVBS_AIN3:1094 case ADV7182_INPUT_CVBS_AIN4:1095 case ADV7182_INPUT_CVBS_AIN5:1096 case ADV7182_INPUT_CVBS_AIN6:1097 case ADV7182_INPUT_CVBS_AIN7:1098 case ADV7182_INPUT_CVBS_AIN8:1099 return ADV7182_INPUT_TYPE_CVBS;1100 case ADV7182_INPUT_SVIDEO_AIN1_AIN2:1101 case ADV7182_INPUT_SVIDEO_AIN3_AIN4:1102 case ADV7182_INPUT_SVIDEO_AIN5_AIN6:1103 case ADV7182_INPUT_SVIDEO_AIN7_AIN8:1104 return ADV7182_INPUT_TYPE_SVIDEO;1105 case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:1106 case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:1107 return ADV7182_INPUT_TYPE_YPBPR;1108 case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:1109 case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:1110 case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:1111 case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:1112 return ADV7182_INPUT_TYPE_DIFF_CVBS;1113 default: /* Will never happen */1114 return 0;1115 }1116}1117 1118/* ADI recommended writes to registers 0x52, 0x53, 0x54 */1119static unsigned int adv7182_lbias_settings[][3] = {1120 [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },1121 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },1122 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },1123 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },1124};1125 1126static unsigned int adv7280_lbias_settings[][3] = {1127 [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },1128 [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },1129 [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },1130 [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },1131};1132 1133static int adv7182_select_input(struct adv7180_state *state, unsigned int input)1134{1135 enum adv7182_input_type input_type;1136 unsigned int *lbias;1137 unsigned int i;1138 int ret;1139 1140 ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);1141 if (ret)1142 return ret;1143 1144 /* Reset clamp circuitry - ADI recommended writes */1145 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0x00);1146 adv7180_write(state, ADV7180_REG_RST_CLAMP, 0xff);1147 1148 input_type = adv7182_get_input_type(input);1149 1150 switch (input_type) {1151 case ADV7182_INPUT_TYPE_CVBS:1152 case ADV7182_INPUT_TYPE_DIFF_CVBS:1153 /* ADI recommends to use the SH1 filter */1154 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x41);1155 break;1156 default:1157 adv7180_write(state, ADV7180_REG_SHAP_FILTER_CTL_1, 0x01);1158 break;1159 }1160 1161 if (state->chip_info->flags & ADV7180_FLAG_V2)1162 lbias = adv7280_lbias_settings[input_type];1163 else1164 lbias = adv7182_lbias_settings[input_type];1165 1166 for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)1167 adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);1168 1169 if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {1170 /* ADI required writes to make differential CVBS work */1171 adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);1172 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);1173 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);1174 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);1175 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);1176 } else {1177 adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);1178 adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);1179 adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);1180 adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x9c);1181 adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0x00);1182 }1183 1184 return 0;1185}1186 1187static const struct adv7180_chip_info adv7180_info = {1188 .flags = ADV7180_FLAG_RESET_POWERED,1189 /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept1190 * all inputs and let the card driver take care of validation1191 */1192 .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |1193 BIT(ADV7180_INPUT_CVBS_AIN2) |1194 BIT(ADV7180_INPUT_CVBS_AIN3) |1195 BIT(ADV7180_INPUT_CVBS_AIN4) |1196 BIT(ADV7180_INPUT_CVBS_AIN5) |1197 BIT(ADV7180_INPUT_CVBS_AIN6) |1198 BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |1199 BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |1200 BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |1201 BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |1202 BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),1203 .init = adv7180_init,1204 .set_std = adv7180_set_std,1205 .select_input = adv7180_select_input,1206};1207 1208static const struct adv7180_chip_info adv7182_info = {1209 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |1210 BIT(ADV7182_INPUT_CVBS_AIN2) |1211 BIT(ADV7182_INPUT_CVBS_AIN3) |1212 BIT(ADV7182_INPUT_CVBS_AIN4) |1213 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |1214 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |1215 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |1216 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |1217 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),1218 .init = adv7182_init,1219 .set_std = adv7182_set_std,1220 .select_input = adv7182_select_input,1221};1222 1223static const struct adv7180_chip_info adv7280_info = {1224 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,1225 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |1226 BIT(ADV7182_INPUT_CVBS_AIN2) |1227 BIT(ADV7182_INPUT_CVBS_AIN3) |1228 BIT(ADV7182_INPUT_CVBS_AIN4) |1229 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |1230 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |1231 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),1232 .init = adv7182_init,1233 .set_std = adv7182_set_std,1234 .select_input = adv7182_select_input,1235};1236 1237static const struct adv7180_chip_info adv7280_m_info = {1238 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,1239 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |1240 BIT(ADV7182_INPUT_CVBS_AIN2) |1241 BIT(ADV7182_INPUT_CVBS_AIN3) |1242 BIT(ADV7182_INPUT_CVBS_AIN4) |1243 BIT(ADV7182_INPUT_CVBS_AIN5) |1244 BIT(ADV7182_INPUT_CVBS_AIN6) |1245 BIT(ADV7182_INPUT_CVBS_AIN7) |1246 BIT(ADV7182_INPUT_CVBS_AIN8) |1247 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |1248 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |1249 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |1250 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |1251 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |1252 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),1253 .init = adv7182_init,1254 .set_std = adv7182_set_std,1255 .select_input = adv7182_select_input,1256};1257 1258static const struct adv7180_chip_info adv7281_info = {1259 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,1260 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |1261 BIT(ADV7182_INPUT_CVBS_AIN2) |1262 BIT(ADV7182_INPUT_CVBS_AIN7) |1263 BIT(ADV7182_INPUT_CVBS_AIN8) |1264 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |1265 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |1266 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |1267 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),1268 .init = adv7182_init,1269 .set_std = adv7182_set_std,1270 .select_input = adv7182_select_input,1271};1272 1273static const struct adv7180_chip_info adv7281_m_info = {1274 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,1275 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |1276 BIT(ADV7182_INPUT_CVBS_AIN2) |1277 BIT(ADV7182_INPUT_CVBS_AIN3) |1278 BIT(ADV7182_INPUT_CVBS_AIN4) |1279 BIT(ADV7182_INPUT_CVBS_AIN7) |1280 BIT(ADV7182_INPUT_CVBS_AIN8) |1281 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |1282 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |1283 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |1284 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |1285 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |1286 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |1287 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),1288 .init = adv7182_init,1289 .set_std = adv7182_set_std,1290 .select_input = adv7182_select_input,1291};1292 1293static const struct adv7180_chip_info adv7281_ma_info = {1294 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,1295 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |1296 BIT(ADV7182_INPUT_CVBS_AIN2) |1297 BIT(ADV7182_INPUT_CVBS_AIN3) |1298 BIT(ADV7182_INPUT_CVBS_AIN4) |1299 BIT(ADV7182_INPUT_CVBS_AIN5) |1300 BIT(ADV7182_INPUT_CVBS_AIN6) |1301 BIT(ADV7182_INPUT_CVBS_AIN7) |1302 BIT(ADV7182_INPUT_CVBS_AIN8) |1303 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |1304 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |1305 BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |1306 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |1307 BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |1308 BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |1309 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |1310 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |1311 BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |1312 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),1313 .init = adv7182_init,1314 .set_std = adv7182_set_std,1315 .select_input = adv7182_select_input,1316};1317 1318static const struct adv7180_chip_info adv7282_info = {1319 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,1320 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |1321 BIT(ADV7182_INPUT_CVBS_AIN2) |1322 BIT(ADV7182_INPUT_CVBS_AIN7) |1323 BIT(ADV7182_INPUT_CVBS_AIN8) |1324 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |1325 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |1326 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |1327 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),1328 .init = adv7182_init,1329 .set_std = adv7182_set_std,1330 .select_input = adv7182_select_input,1331};1332 1333static const struct adv7180_chip_info adv7282_m_info = {1334 .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,1335 .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |1336 BIT(ADV7182_INPUT_CVBS_AIN2) |1337 BIT(ADV7182_INPUT_CVBS_AIN3) |1338 BIT(ADV7182_INPUT_CVBS_AIN4) |1339 BIT(ADV7182_INPUT_CVBS_AIN7) |1340 BIT(ADV7182_INPUT_CVBS_AIN8) |1341 BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |1342 BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |1343 BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |1344 BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |1345 BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |1346 BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),1347 .init = adv7182_init,1348 .set_std = adv7182_set_std,1349 .select_input = adv7182_select_input,1350};1351 1352static int init_device(struct adv7180_state *state)1353{1354 int ret;1355 1356 mutex_lock(&state->mutex);1357 1358 adv7180_set_power_pin(state, true);1359 adv7180_set_reset_pin(state, false);1360 1361 adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);1362 usleep_range(5000, 10000);1363 1364 ret = state->chip_info->init(state);1365 if (ret)1366 goto out_unlock;1367 1368 ret = adv7180_program_std(state);1369 if (ret)1370 goto out_unlock;1371 1372 adv7180_set_field_mode(state);1373 1374 /* register for interrupts */1375 if (state->irq > 0) {1376 /* config the Interrupt pin to be active low */1377 ret = adv7180_write(state, ADV7180_REG_ICONF1,1378 ADV7180_ICONF1_ACTIVE_LOW |1379 ADV7180_ICONF1_PSYNC_ONLY);1380 if (ret < 0)1381 goto out_unlock;1382 1383 ret = adv7180_write(state, ADV7180_REG_IMR1, 0);1384 if (ret < 0)1385 goto out_unlock;1386 1387 ret = adv7180_write(state, ADV7180_REG_IMR2, 0);1388 if (ret < 0)1389 goto out_unlock;1390 1391 /* enable AD change interrupts interrupts */1392 ret = adv7180_write(state, ADV7180_REG_IMR3,1393 ADV7180_IRQ3_AD_CHANGE);1394 if (ret < 0)1395 goto out_unlock;1396 1397 ret = adv7180_write(state, ADV7180_REG_IMR4, 0);1398 if (ret < 0)1399 goto out_unlock;1400 }1401 1402out_unlock:1403 mutex_unlock(&state->mutex);1404 1405 return ret;1406}1407 1408static int adv7180_probe(struct i2c_client *client)1409{1410 struct device_node *np = client->dev.of_node;1411 struct adv7180_state *state;1412 struct v4l2_subdev *sd;1413 int ret;1414 1415 /* Check if the adapter supports the needed features */1416 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))1417 return -EIO;1418 1419 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);1420 if (state == NULL)1421 return -ENOMEM;1422 1423 state->client = client;1424 state->field = V4L2_FIELD_ALTERNATE;1425 state->chip_info = i2c_get_match_data(client);1426 1427 state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",1428 GPIOD_OUT_HIGH);1429 if (IS_ERR(state->pwdn_gpio)) {1430 ret = PTR_ERR(state->pwdn_gpio);1431 v4l_err(client, "request for power pin failed: %d\n", ret);1432 return ret;1433 }1434 1435 state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset",1436 GPIOD_OUT_HIGH);1437 if (IS_ERR(state->rst_gpio)) {1438 ret = PTR_ERR(state->rst_gpio);1439 v4l_err(client, "request for reset pin failed: %d\n", ret);1440 return ret;1441 }1442 1443 if (of_property_read_bool(np, "adv,force-bt656-4"))1444 state->force_bt656_4 = true;1445 1446 if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {1447 state->csi_client = i2c_new_dummy_device(client->adapter,1448 ADV7180_DEFAULT_CSI_I2C_ADDR);1449 if (IS_ERR(state->csi_client))1450 return PTR_ERR(state->csi_client);1451 }1452 1453 if (state->chip_info->flags & ADV7180_FLAG_I2P) {1454 state->vpp_client = i2c_new_dummy_device(client->adapter,1455 ADV7180_DEFAULT_VPP_I2C_ADDR);1456 if (IS_ERR(state->vpp_client)) {1457 ret = PTR_ERR(state->vpp_client);1458 goto err_unregister_csi_client;1459 }1460 }1461 1462 state->irq = client->irq;1463 mutex_init(&state->mutex);1464 state->curr_norm = V4L2_STD_NTSC;1465 if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)1466 state->powered = true;1467 else1468 state->powered = false;1469 state->input = 0;1470 sd = &state->sd;1471 v4l2_i2c_subdev_init(sd, client, &adv7180_ops);1472 sd->internal_ops = &adv7180_internal_ops;1473 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;1474 1475 ret = adv7180_init_controls(state);1476 if (ret)1477 goto err_unregister_vpp_client;1478 1479 state->pad.flags = MEDIA_PAD_FL_SOURCE;1480 sd->entity.function = MEDIA_ENT_F_ATV_DECODER;1481 ret = media_entity_pads_init(&sd->entity, 1, &state->pad);1482 if (ret)1483 goto err_free_ctrl;1484 1485 ret = init_device(state);1486 if (ret)1487 goto err_media_entity_cleanup;1488 1489 if (state->irq > 0) {1490 ret = request_threaded_irq(client->irq, NULL, adv7180_irq,1491 IRQF_ONESHOT | IRQF_TRIGGER_FALLING,1492 KBUILD_MODNAME, state);1493 if (ret)1494 goto err_media_entity_cleanup;1495 }1496 1497 ret = v4l2_async_register_subdev(sd);1498 if (ret)1499 goto err_free_irq;1500 1501 mutex_lock(&state->mutex);1502 ret = adv7180_read(state, ADV7180_REG_IDENT);1503 mutex_unlock(&state->mutex);1504 if (ret < 0)1505 goto err_v4l2_async_unregister;1506 1507 v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n",1508 ret, client->addr, client->adapter->name);1509 1510 return 0;1511 1512err_v4l2_async_unregister:1513 v4l2_async_unregister_subdev(sd);1514err_free_irq:1515 if (state->irq > 0)1516 free_irq(client->irq, state);1517err_media_entity_cleanup:1518 media_entity_cleanup(&sd->entity);1519err_free_ctrl:1520 adv7180_exit_controls(state);1521err_unregister_vpp_client:1522 i2c_unregister_device(state->vpp_client);1523err_unregister_csi_client:1524 i2c_unregister_device(state->csi_client);1525 mutex_destroy(&state->mutex);1526 return ret;1527}1528 1529static void adv7180_remove(struct i2c_client *client)1530{1531 struct v4l2_subdev *sd = i2c_get_clientdata(client);1532 struct adv7180_state *state = to_state(sd);1533 1534 v4l2_async_unregister_subdev(sd);1535 1536 if (state->irq > 0)1537 free_irq(client->irq, state);1538 1539 media_entity_cleanup(&sd->entity);1540 adv7180_exit_controls(state);1541 1542 i2c_unregister_device(state->vpp_client);1543 i2c_unregister_device(state->csi_client);1544 1545 adv7180_set_reset_pin(state, true);1546 adv7180_set_power_pin(state, false);1547 1548 mutex_destroy(&state->mutex);1549}1550 1551#ifdef CONFIG_PM_SLEEP1552static int adv7180_suspend(struct device *dev)1553{1554 struct v4l2_subdev *sd = dev_get_drvdata(dev);1555 struct adv7180_state *state = to_state(sd);1556 1557 return adv7180_set_power(state, false);1558}1559 1560static int adv7180_resume(struct device *dev)1561{1562 struct v4l2_subdev *sd = dev_get_drvdata(dev);1563 struct adv7180_state *state = to_state(sd);1564 int ret;1565 1566 ret = init_device(state);1567 if (ret < 0)1568 return ret;1569 1570 ret = adv7180_set_power(state, state->powered);1571 if (ret)1572 return ret;1573 1574 return 0;1575}1576 1577static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);1578#define ADV7180_PM_OPS (&adv7180_pm_ops)1579 1580#else1581#define ADV7180_PM_OPS NULL1582#endif1583 1584static const struct i2c_device_id adv7180_id[] = {1585 { "adv7180", (kernel_ulong_t)&adv7180_info },1586 { "adv7180cp", (kernel_ulong_t)&adv7180_info },1587 { "adv7180st", (kernel_ulong_t)&adv7180_info },1588 { "adv7182", (kernel_ulong_t)&adv7182_info },1589 { "adv7280", (kernel_ulong_t)&adv7280_info },1590 { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },1591 { "adv7281", (kernel_ulong_t)&adv7281_info },1592 { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },1593 { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },1594 { "adv7282", (kernel_ulong_t)&adv7282_info },1595 { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },1596 {}1597};1598MODULE_DEVICE_TABLE(i2c, adv7180_id);1599 1600static const struct of_device_id adv7180_of_id[] = {1601 { .compatible = "adi,adv7180", &adv7180_info },1602 { .compatible = "adi,adv7180cp", &adv7180_info },1603 { .compatible = "adi,adv7180st", &adv7180_info },1604 { .compatible = "adi,adv7182", &adv7182_info },1605 { .compatible = "adi,adv7280", &adv7280_info },1606 { .compatible = "adi,adv7280-m", &adv7280_m_info },1607 { .compatible = "adi,adv7281", &adv7281_info },1608 { .compatible = "adi,adv7281-m", &adv7281_m_info },1609 { .compatible = "adi,adv7281-ma", &adv7281_ma_info },1610 { .compatible = "adi,adv7282", &adv7282_info },1611 { .compatible = "adi,adv7282-m", &adv7282_m_info },1612 {}1613};1614MODULE_DEVICE_TABLE(of, adv7180_of_id);1615 1616static struct i2c_driver adv7180_driver = {1617 .driver = {1618 .name = KBUILD_MODNAME,1619 .pm = ADV7180_PM_OPS,1620 .of_match_table = adv7180_of_id,1621 },1622 .probe = adv7180_probe,1623 .remove = adv7180_remove,1624 .id_table = adv7180_id,1625};1626 1627module_i2c_driver(adv7180_driver);1628 1629MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");1630MODULE_AUTHOR("Mocean Laboratories");1631MODULE_LICENSE("GPL v2");1632