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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * adv7842 - Analog Devices ADV7842 video decoder driver4 *5 * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved.6 */7 8/*9 * References (c = chapter, p = page):10 * REF_01 - Analog devices, ADV7842,11 * Register Settings Recommendations, Rev. 1.9, April 201112 * REF_02 - Analog devices, Software User Guide, UG-206,13 * ADV7842 I2C Register Maps, Rev. 0, November 201014 * REF_03 - Analog devices, Hardware User Guide, UG-214,15 * ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb16 * Decoder and Digitizer , Rev. 0, January 201117 */18 19 20#include <linux/kernel.h>21#include <linux/module.h>22#include <linux/slab.h>23#include <linux/i2c.h>24#include <linux/delay.h>25#include <linux/videodev2.h>26#include <linux/workqueue.h>27#include <linux/v4l2-dv-timings.h>28#include <linux/hdmi.h>29#include <media/cec.h>30#include <media/v4l2-device.h>31#include <media/v4l2-event.h>32#include <media/v4l2-ctrls.h>33#include <media/v4l2-dv-timings.h>34#include <media/i2c/adv7842.h>35 36static int debug;37module_param(debug, int, 0644);38MODULE_PARM_DESC(debug, "debug level (0-2)");39 40MODULE_DESCRIPTION("Analog Devices ADV7842 video decoder driver");41MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");42MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");43MODULE_LICENSE("GPL");44 45/* ADV7842 system clock frequency */46#define ADV7842_fsc (28636360)47 48#define ADV7842_RGB_OUT (1 << 1)49 50#define ADV7842_OP_FORMAT_SEL_8BIT (0 << 0)51#define ADV7842_OP_FORMAT_SEL_10BIT (1 << 0)52#define ADV7842_OP_FORMAT_SEL_12BIT (2 << 0)53 54#define ADV7842_OP_MODE_SEL_SDR_422 (0 << 5)55#define ADV7842_OP_MODE_SEL_DDR_422 (1 << 5)56#define ADV7842_OP_MODE_SEL_SDR_444 (2 << 5)57#define ADV7842_OP_MODE_SEL_DDR_444 (3 << 5)58#define ADV7842_OP_MODE_SEL_SDR_422_2X (4 << 5)59#define ADV7842_OP_MODE_SEL_ADI_CM (5 << 5)60 61#define ADV7842_OP_CH_SEL_GBR (0 << 5)62#define ADV7842_OP_CH_SEL_GRB (1 << 5)63#define ADV7842_OP_CH_SEL_BGR (2 << 5)64#define ADV7842_OP_CH_SEL_RGB (3 << 5)65#define ADV7842_OP_CH_SEL_BRG (4 << 5)66#define ADV7842_OP_CH_SEL_RBG (5 << 5)67 68#define ADV7842_OP_SWAP_CB_CR (1 << 0)69 70#define ADV7842_MAX_ADDRS (3)71 72/*73**********************************************************************74*75* Arrays with configuration parameters for the ADV784276*77**********************************************************************78*/79 80struct adv7842_format_info {81 u32 code;82 u8 op_ch_sel;83 bool rgb_out;84 bool swap_cb_cr;85 u8 op_format_sel;86};87 88struct adv7842_state {89 struct adv7842_platform_data pdata;90 struct v4l2_subdev sd;91 struct media_pad pads[ADV7842_PAD_SOURCE + 1];92 struct v4l2_ctrl_handler hdl;93 enum adv7842_mode mode;94 struct v4l2_dv_timings timings;95 enum adv7842_vid_std_select vid_std_select;96 97 const struct adv7842_format_info *format;98 99 v4l2_std_id norm;100 struct {101 u8 edid[512];102 u32 blocks;103 u32 present;104 } hdmi_edid;105 struct {106 u8 edid[128];107 u32 blocks;108 u32 present;109 } vga_edid;110 struct v4l2_fract aspect_ratio;111 u32 rgb_quantization_range;112 bool is_cea_format;113 struct delayed_work delayed_work_enable_hotplug;114 bool restart_stdi_once;115 bool hdmi_port_a;116 117 /* i2c clients */118 struct i2c_client *i2c_sdp_io;119 struct i2c_client *i2c_sdp;120 struct i2c_client *i2c_cp;121 struct i2c_client *i2c_vdp;122 struct i2c_client *i2c_afe;123 struct i2c_client *i2c_hdmi;124 struct i2c_client *i2c_repeater;125 struct i2c_client *i2c_edid;126 struct i2c_client *i2c_infoframe;127 struct i2c_client *i2c_cec;128 struct i2c_client *i2c_avlink;129 130 /* controls */131 struct v4l2_ctrl *detect_tx_5v_ctrl;132 struct v4l2_ctrl *analog_sampling_phase_ctrl;133 struct v4l2_ctrl *free_run_color_ctrl_manual;134 struct v4l2_ctrl *free_run_color_ctrl;135 struct v4l2_ctrl *rgb_quantization_range_ctrl;136 137 struct cec_adapter *cec_adap;138 u8 cec_addr[ADV7842_MAX_ADDRS];139 u8 cec_valid_addrs;140 bool cec_enabled_adap;141};142 143/* Unsupported timings. This device cannot support 720p30. */144static const struct v4l2_dv_timings adv7842_timings_exceptions[] = {145 V4L2_DV_BT_CEA_1280X720P30,146 { }147};148 149static bool adv7842_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)150{151 int i;152 153 for (i = 0; adv7842_timings_exceptions[i].bt.width; i++)154 if (v4l2_match_dv_timings(t, adv7842_timings_exceptions + i, 0, false))155 return false;156 return true;157}158 159struct adv7842_video_standards {160 struct v4l2_dv_timings timings;161 u8 vid_std;162 u8 v_freq;163};164 165/* sorted by number of lines */166static const struct adv7842_video_standards adv7842_prim_mode_comp[] = {167 /* { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 }, TODO flickering */168 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },169 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },170 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },171 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },172 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },173 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },174 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },175 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },176 /* TODO add 1920x1080P60_RB (CVT timing) */177 { },178};179 180/* sorted by number of lines */181static const struct adv7842_video_standards adv7842_prim_mode_gr[] = {182 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },183 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },184 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },185 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },186 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },187 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },188 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },189 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },190 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },191 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },192 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },193 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },194 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },195 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },196 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },197 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },198 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },199 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },200 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },201 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 }, /* TODO not tested */202 /* TODO add 1600X1200P60_RB (not a DMT timing) */203 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },204 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 }, /* TODO not tested */205 { },206};207 208/* sorted by number of lines */209static const struct adv7842_video_standards adv7842_prim_mode_hdmi_comp[] = {210 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },211 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },212 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },213 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },214 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },215 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },216 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },217 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },218 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },219 { },220};221 222/* sorted by number of lines */223static const struct adv7842_video_standards adv7842_prim_mode_hdmi_gr[] = {224 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },225 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },226 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },227 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },228 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },229 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },230 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },231 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },232 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },233 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },234 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },235 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },236 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },237 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },238 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },239 { },240};241 242static const struct v4l2_event adv7842_ev_fmt = {243 .type = V4L2_EVENT_SOURCE_CHANGE,244 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,245};246 247/* ----------------------------------------------------------------------- */248 249static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)250{251 return container_of(sd, struct adv7842_state, sd);252}253 254static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)255{256 return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;257}258 259static inline unsigned htotal(const struct v4l2_bt_timings *t)260{261 return V4L2_DV_BT_FRAME_WIDTH(t);262}263 264static inline unsigned vtotal(const struct v4l2_bt_timings *t)265{266 return V4L2_DV_BT_FRAME_HEIGHT(t);267}268 269 270/* ----------------------------------------------------------------------- */271 272static s32 adv_smbus_read_byte_data_check(struct i2c_client *client,273 u8 command, bool check)274{275 union i2c_smbus_data data;276 277 if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,278 I2C_SMBUS_READ, command,279 I2C_SMBUS_BYTE_DATA, &data))280 return data.byte;281 if (check)282 v4l_err(client, "error reading %02x, %02x\n",283 client->addr, command);284 return -EIO;285}286 287static s32 adv_smbus_read_byte_data(struct i2c_client *client, u8 command)288{289 int i;290 291 for (i = 0; i < 3; i++) {292 int ret = adv_smbus_read_byte_data_check(client, command, true);293 294 if (ret >= 0) {295 if (i)296 v4l_err(client, "read ok after %d retries\n", i);297 return ret;298 }299 }300 v4l_err(client, "read failed\n");301 return -EIO;302}303 304static s32 adv_smbus_write_byte_data(struct i2c_client *client,305 u8 command, u8 value)306{307 union i2c_smbus_data data;308 int err;309 int i;310 311 data.byte = value;312 for (i = 0; i < 3; i++) {313 err = i2c_smbus_xfer(client->adapter, client->addr,314 client->flags,315 I2C_SMBUS_WRITE, command,316 I2C_SMBUS_BYTE_DATA, &data);317 if (!err)318 break;319 }320 if (err < 0)321 v4l_err(client, "error writing %02x, %02x, %02x\n",322 client->addr, command, value);323 return err;324}325 326static void adv_smbus_write_byte_no_check(struct i2c_client *client,327 u8 command, u8 value)328{329 union i2c_smbus_data data;330 data.byte = value;331 332 i2c_smbus_xfer(client->adapter, client->addr,333 client->flags,334 I2C_SMBUS_WRITE, command,335 I2C_SMBUS_BYTE_DATA, &data);336}337 338/* ----------------------------------------------------------------------- */339 340static inline int io_read(struct v4l2_subdev *sd, u8 reg)341{342 struct i2c_client *client = v4l2_get_subdevdata(sd);343 344 return adv_smbus_read_byte_data(client, reg);345}346 347static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)348{349 struct i2c_client *client = v4l2_get_subdevdata(sd);350 351 return adv_smbus_write_byte_data(client, reg, val);352}353 354static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)355{356 return io_write(sd, reg, (io_read(sd, reg) & mask) | val);357}358 359static inline int io_write_clr_set(struct v4l2_subdev *sd,360 u8 reg, u8 mask, u8 val)361{362 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);363}364 365static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)366{367 struct adv7842_state *state = to_state(sd);368 369 return adv_smbus_read_byte_data(state->i2c_avlink, reg);370}371 372static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)373{374 struct adv7842_state *state = to_state(sd);375 376 return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);377}378 379static inline int cec_read(struct v4l2_subdev *sd, u8 reg)380{381 struct adv7842_state *state = to_state(sd);382 383 return adv_smbus_read_byte_data(state->i2c_cec, reg);384}385 386static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)387{388 struct adv7842_state *state = to_state(sd);389 390 return adv_smbus_write_byte_data(state->i2c_cec, reg, val);391}392 393static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)394{395 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);396}397 398static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)399{400 struct adv7842_state *state = to_state(sd);401 402 return adv_smbus_read_byte_data(state->i2c_infoframe, reg);403}404 405static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)406{407 struct adv7842_state *state = to_state(sd);408 409 return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);410}411 412static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)413{414 struct adv7842_state *state = to_state(sd);415 416 return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);417}418 419static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)420{421 struct adv7842_state *state = to_state(sd);422 423 return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);424}425 426static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)427{428 return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);429}430 431static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)432{433 struct adv7842_state *state = to_state(sd);434 435 return adv_smbus_read_byte_data(state->i2c_sdp, reg);436}437 438static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)439{440 struct adv7842_state *state = to_state(sd);441 442 return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);443}444 445static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)446{447 return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);448}449 450static inline int afe_read(struct v4l2_subdev *sd, u8 reg)451{452 struct adv7842_state *state = to_state(sd);453 454 return adv_smbus_read_byte_data(state->i2c_afe, reg);455}456 457static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)458{459 struct adv7842_state *state = to_state(sd);460 461 return adv_smbus_write_byte_data(state->i2c_afe, reg, val);462}463 464static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)465{466 return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);467}468 469static inline int rep_read(struct v4l2_subdev *sd, u8 reg)470{471 struct adv7842_state *state = to_state(sd);472 473 return adv_smbus_read_byte_data(state->i2c_repeater, reg);474}475 476static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)477{478 struct adv7842_state *state = to_state(sd);479 480 return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);481}482 483static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)484{485 return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);486}487 488static inline int edid_read(struct v4l2_subdev *sd, u8 reg)489{490 struct adv7842_state *state = to_state(sd);491 492 return adv_smbus_read_byte_data(state->i2c_edid, reg);493}494 495static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)496{497 struct adv7842_state *state = to_state(sd);498 499 return adv_smbus_write_byte_data(state->i2c_edid, reg, val);500}501 502static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)503{504 struct adv7842_state *state = to_state(sd);505 506 return adv_smbus_read_byte_data(state->i2c_hdmi, reg);507}508 509static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)510{511 struct adv7842_state *state = to_state(sd);512 513 return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);514}515 516static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)517{518 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);519}520 521static inline int cp_read(struct v4l2_subdev *sd, u8 reg)522{523 struct adv7842_state *state = to_state(sd);524 525 return adv_smbus_read_byte_data(state->i2c_cp, reg);526}527 528static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)529{530 struct adv7842_state *state = to_state(sd);531 532 return adv_smbus_write_byte_data(state->i2c_cp, reg, val);533}534 535static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)536{537 return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);538}539 540static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)541{542 struct adv7842_state *state = to_state(sd);543 544 return adv_smbus_read_byte_data(state->i2c_vdp, reg);545}546 547static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)548{549 struct adv7842_state *state = to_state(sd);550 551 return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);552}553 554static void main_reset(struct v4l2_subdev *sd)555{556 struct i2c_client *client = v4l2_get_subdevdata(sd);557 558 v4l2_dbg(1, debug, sd, "%s:\n", __func__);559 560 adv_smbus_write_byte_no_check(client, 0xff, 0x80);561 562 mdelay(5);563}564 565/* -----------------------------------------------------------------------------566 * Format helpers567 */568 569static const struct adv7842_format_info adv7842_formats[] = {570 { MEDIA_BUS_FMT_RGB888_1X24, ADV7842_OP_CH_SEL_RGB, true, false,571 ADV7842_OP_MODE_SEL_SDR_444 | ADV7842_OP_FORMAT_SEL_8BIT },572 { MEDIA_BUS_FMT_YUYV8_2X8, ADV7842_OP_CH_SEL_RGB, false, false,573 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },574 { MEDIA_BUS_FMT_YVYU8_2X8, ADV7842_OP_CH_SEL_RGB, false, true,575 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_8BIT },576 { MEDIA_BUS_FMT_YUYV10_2X10, ADV7842_OP_CH_SEL_RGB, false, false,577 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },578 { MEDIA_BUS_FMT_YVYU10_2X10, ADV7842_OP_CH_SEL_RGB, false, true,579 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_10BIT },580 { MEDIA_BUS_FMT_YUYV12_2X12, ADV7842_OP_CH_SEL_RGB, false, false,581 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },582 { MEDIA_BUS_FMT_YVYU12_2X12, ADV7842_OP_CH_SEL_RGB, false, true,583 ADV7842_OP_MODE_SEL_SDR_422 | ADV7842_OP_FORMAT_SEL_12BIT },584 { MEDIA_BUS_FMT_UYVY8_1X16, ADV7842_OP_CH_SEL_RBG, false, false,585 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },586 { MEDIA_BUS_FMT_VYUY8_1X16, ADV7842_OP_CH_SEL_RBG, false, true,587 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },588 { MEDIA_BUS_FMT_YUYV8_1X16, ADV7842_OP_CH_SEL_RGB, false, false,589 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },590 { MEDIA_BUS_FMT_YVYU8_1X16, ADV7842_OP_CH_SEL_RGB, false, true,591 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_8BIT },592 { MEDIA_BUS_FMT_UYVY10_1X20, ADV7842_OP_CH_SEL_RBG, false, false,593 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },594 { MEDIA_BUS_FMT_VYUY10_1X20, ADV7842_OP_CH_SEL_RBG, false, true,595 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },596 { MEDIA_BUS_FMT_YUYV10_1X20, ADV7842_OP_CH_SEL_RGB, false, false,597 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },598 { MEDIA_BUS_FMT_YVYU10_1X20, ADV7842_OP_CH_SEL_RGB, false, true,599 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_10BIT },600 { MEDIA_BUS_FMT_UYVY12_1X24, ADV7842_OP_CH_SEL_RBG, false, false,601 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },602 { MEDIA_BUS_FMT_VYUY12_1X24, ADV7842_OP_CH_SEL_RBG, false, true,603 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },604 { MEDIA_BUS_FMT_YUYV12_1X24, ADV7842_OP_CH_SEL_RGB, false, false,605 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },606 { MEDIA_BUS_FMT_YVYU12_1X24, ADV7842_OP_CH_SEL_RGB, false, true,607 ADV7842_OP_MODE_SEL_SDR_422_2X | ADV7842_OP_FORMAT_SEL_12BIT },608};609 610static const struct adv7842_format_info *611adv7842_format_info(struct adv7842_state *state, u32 code)612{613 unsigned int i;614 615 for (i = 0; i < ARRAY_SIZE(adv7842_formats); ++i) {616 if (adv7842_formats[i].code == code)617 return &adv7842_formats[i];618 }619 620 return NULL;621}622 623/* ----------------------------------------------------------------------- */624 625static inline bool is_analog_input(struct v4l2_subdev *sd)626{627 struct adv7842_state *state = to_state(sd);628 629 return ((state->mode == ADV7842_MODE_RGB) ||630 (state->mode == ADV7842_MODE_COMP));631}632 633static inline bool is_digital_input(struct v4l2_subdev *sd)634{635 struct adv7842_state *state = to_state(sd);636 637 return state->mode == ADV7842_MODE_HDMI;638}639 640static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {641 .type = V4L2_DV_BT_656_1120,642 /* keep this initialization for compatibility with GCC < 4.4.6 */643 .reserved = { 0 },644 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,645 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |646 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,647 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |648 V4L2_DV_BT_CAP_CUSTOM)649};650 651static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {652 .type = V4L2_DV_BT_656_1120,653 /* keep this initialization for compatibility with GCC < 4.4.6 */654 .reserved = { 0 },655 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,656 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |657 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,658 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |659 V4L2_DV_BT_CAP_CUSTOM)660};661 662static inline const struct v4l2_dv_timings_cap *663adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)664{665 return is_digital_input(sd) ? &adv7842_timings_cap_digital :666 &adv7842_timings_cap_analog;667}668 669/* ----------------------------------------------------------------------- */670 671static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)672{673 u8 reg = io_read(sd, 0x6f);674 u16 val = 0;675 676 if (reg & 0x02)677 val |= 1; /* port A */678 if (reg & 0x01)679 val |= 2; /* port B */680 return val;681}682 683static void adv7842_delayed_work_enable_hotplug(struct work_struct *work)684{685 struct delayed_work *dwork = to_delayed_work(work);686 struct adv7842_state *state = container_of(dwork,687 struct adv7842_state, delayed_work_enable_hotplug);688 struct v4l2_subdev *sd = &state->sd;689 int present = state->hdmi_edid.present;690 u8 mask = 0;691 692 v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",693 __func__, present);694 695 if (present & (0x04 << ADV7842_EDID_PORT_A))696 mask |= 0x20;697 if (present & (0x04 << ADV7842_EDID_PORT_B))698 mask |= 0x10;699 io_write_and_or(sd, 0x20, 0xcf, mask);700}701 702static int edid_write_vga_segment(struct v4l2_subdev *sd)703{704 struct i2c_client *client = v4l2_get_subdevdata(sd);705 struct adv7842_state *state = to_state(sd);706 const u8 *edid = state->vga_edid.edid;707 u32 blocks = state->vga_edid.blocks;708 int err = 0;709 int i;710 711 v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);712 713 if (!state->vga_edid.present)714 return 0;715 716 /* HPA disable on port A and B */717 io_write_and_or(sd, 0x20, 0xcf, 0x00);718 719 /* Disable I2C access to internal EDID ram from VGA DDC port */720 rep_write_and_or(sd, 0x7f, 0x7f, 0x00);721 722 /* edid segment pointer '1' for VGA port */723 rep_write_and_or(sd, 0x77, 0xef, 0x10);724 725 for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX)726 err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i,727 I2C_SMBUS_BLOCK_MAX,728 edid + i);729 if (err)730 return err;731 732 /* Calculates the checksums and enables I2C access733 * to internal EDID ram from VGA DDC port.734 */735 rep_write_and_or(sd, 0x7f, 0x7f, 0x80);736 737 for (i = 0; i < 1000; i++) {738 if (rep_read(sd, 0x79) & 0x20)739 break;740 mdelay(1);741 }742 if (i == 1000) {743 v4l_err(client, "error enabling edid on VGA port\n");744 return -EIO;745 }746 747 /* enable hotplug after 200 ms */748 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);749 750 return 0;751}752 753static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)754{755 struct i2c_client *client = v4l2_get_subdevdata(sd);756 struct adv7842_state *state = to_state(sd);757 const u8 *edid = state->hdmi_edid.edid;758 u32 blocks = state->hdmi_edid.blocks;759 unsigned int spa_loc;760 u16 pa, parent_pa;761 int err = 0;762 int i;763 764 v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",765 __func__, (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');766 767 /* HPA disable on port A and B */768 io_write_and_or(sd, 0x20, 0xcf, 0x00);769 770 /* Disable I2C access to internal EDID ram from HDMI DDC ports */771 rep_write_and_or(sd, 0x77, 0xf3, 0x00);772 773 if (!state->hdmi_edid.present) {774 cec_phys_addr_invalidate(state->cec_adap);775 return 0;776 }777 778 pa = v4l2_get_edid_phys_addr(edid, blocks * 128, &spa_loc);779 err = v4l2_phys_addr_validate(pa, &parent_pa, NULL);780 if (err)781 return err;782 783 if (!spa_loc) {784 /*785 * There is no SPA, so just set spa_loc to 128 and pa to whatever786 * data is there.787 */788 spa_loc = 128;789 pa = (edid[spa_loc] << 8) | edid[spa_loc + 1];790 }791 792 793 for (i = 0; !err && i < blocks * 128; i += I2C_SMBUS_BLOCK_MAX) {794 /* set edid segment pointer for HDMI ports */795 if (i % 256 == 0)796 rep_write_and_or(sd, 0x77, 0xef, i >= 256 ? 0x10 : 0x00);797 err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i,798 I2C_SMBUS_BLOCK_MAX, edid + i);799 }800 if (err)801 return err;802 803 if (port == ADV7842_EDID_PORT_A) {804 rep_write(sd, 0x72, pa >> 8);805 rep_write(sd, 0x73, pa & 0xff);806 } else {807 rep_write(sd, 0x74, pa >> 8);808 rep_write(sd, 0x75, pa & 0xff);809 }810 rep_write(sd, 0x76, spa_loc & 0xff);811 rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);812 813 /* Calculates the checksums and enables I2C access to internal814 * EDID ram from HDMI DDC ports815 */816 rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);817 818 for (i = 0; i < 1000; i++) {819 if (rep_read(sd, 0x7d) & state->hdmi_edid.present)820 break;821 mdelay(1);822 }823 if (i == 1000) {824 v4l_err(client, "error enabling edid on port %c\n",825 (port == ADV7842_EDID_PORT_A) ? 'A' : 'B');826 return -EIO;827 }828 cec_s_phys_addr(state->cec_adap, parent_pa, false);829 830 /* enable hotplug after 200 ms */831 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);832 833 return 0;834}835 836/* ----------------------------------------------------------------------- */837 838#ifdef CONFIG_VIDEO_ADV_DEBUG839static void adv7842_inv_register(struct v4l2_subdev *sd)840{841 v4l2_info(sd, "0x000-0x0ff: IO Map\n");842 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");843 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");844 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");845 v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");846 v4l2_info(sd, "0x500-0x5ff: SDP Map\n");847 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");848 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");849 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");850 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");851 v4l2_info(sd, "0xa00-0xaff: CP Map\n");852 v4l2_info(sd, "0xb00-0xbff: VDP Map\n");853}854 855static int adv7842_g_register(struct v4l2_subdev *sd,856 struct v4l2_dbg_register *reg)857{858 reg->size = 1;859 switch (reg->reg >> 8) {860 case 0:861 reg->val = io_read(sd, reg->reg & 0xff);862 break;863 case 1:864 reg->val = avlink_read(sd, reg->reg & 0xff);865 break;866 case 2:867 reg->val = cec_read(sd, reg->reg & 0xff);868 break;869 case 3:870 reg->val = infoframe_read(sd, reg->reg & 0xff);871 break;872 case 4:873 reg->val = sdp_io_read(sd, reg->reg & 0xff);874 break;875 case 5:876 reg->val = sdp_read(sd, reg->reg & 0xff);877 break;878 case 6:879 reg->val = afe_read(sd, reg->reg & 0xff);880 break;881 case 7:882 reg->val = rep_read(sd, reg->reg & 0xff);883 break;884 case 8:885 reg->val = edid_read(sd, reg->reg & 0xff);886 break;887 case 9:888 reg->val = hdmi_read(sd, reg->reg & 0xff);889 break;890 case 0xa:891 reg->val = cp_read(sd, reg->reg & 0xff);892 break;893 case 0xb:894 reg->val = vdp_read(sd, reg->reg & 0xff);895 break;896 default:897 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);898 adv7842_inv_register(sd);899 break;900 }901 return 0;902}903 904static int adv7842_s_register(struct v4l2_subdev *sd,905 const struct v4l2_dbg_register *reg)906{907 u8 val = reg->val & 0xff;908 909 switch (reg->reg >> 8) {910 case 0:911 io_write(sd, reg->reg & 0xff, val);912 break;913 case 1:914 avlink_write(sd, reg->reg & 0xff, val);915 break;916 case 2:917 cec_write(sd, reg->reg & 0xff, val);918 break;919 case 3:920 infoframe_write(sd, reg->reg & 0xff, val);921 break;922 case 4:923 sdp_io_write(sd, reg->reg & 0xff, val);924 break;925 case 5:926 sdp_write(sd, reg->reg & 0xff, val);927 break;928 case 6:929 afe_write(sd, reg->reg & 0xff, val);930 break;931 case 7:932 rep_write(sd, reg->reg & 0xff, val);933 break;934 case 8:935 edid_write(sd, reg->reg & 0xff, val);936 break;937 case 9:938 hdmi_write(sd, reg->reg & 0xff, val);939 break;940 case 0xa:941 cp_write(sd, reg->reg & 0xff, val);942 break;943 case 0xb:944 vdp_write(sd, reg->reg & 0xff, val);945 break;946 default:947 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);948 adv7842_inv_register(sd);949 break;950 }951 return 0;952}953#endif954 955static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)956{957 struct adv7842_state *state = to_state(sd);958 u16 cable_det = adv7842_read_cable_det(sd);959 960 v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);961 962 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);963}964 965static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,966 u8 prim_mode,967 const struct adv7842_video_standards *predef_vid_timings,968 const struct v4l2_dv_timings *timings)969{970 int i;971 972 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {973 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,974 is_digital_input(sd) ? 250000 : 1000000, false))975 continue;976 /* video std */977 io_write(sd, 0x00, predef_vid_timings[i].vid_std);978 /* v_freq and prim mode */979 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);980 return 0;981 }982 983 return -1;984}985 986static int configure_predefined_video_timings(struct v4l2_subdev *sd,987 struct v4l2_dv_timings *timings)988{989 struct adv7842_state *state = to_state(sd);990 int err;991 992 v4l2_dbg(1, debug, sd, "%s\n", __func__);993 994 /* reset to default values */995 io_write(sd, 0x16, 0x43);996 io_write(sd, 0x17, 0x5a);997 /* disable embedded syncs for auto graphics mode */998 cp_write_and_or(sd, 0x81, 0xef, 0x00);999 cp_write(sd, 0x26, 0x00);1000 cp_write(sd, 0x27, 0x00);1001 cp_write(sd, 0x28, 0x00);1002 cp_write(sd, 0x29, 0x00);1003 cp_write(sd, 0x8f, 0x40);1004 cp_write(sd, 0x90, 0x00);1005 cp_write(sd, 0xa5, 0x00);1006 cp_write(sd, 0xa6, 0x00);1007 cp_write(sd, 0xa7, 0x00);1008 cp_write(sd, 0xab, 0x00);1009 cp_write(sd, 0xac, 0x00);1010 1011 switch (state->mode) {1012 case ADV7842_MODE_COMP:1013 case ADV7842_MODE_RGB:1014 err = find_and_set_predefined_video_timings(sd,1015 0x01, adv7842_prim_mode_comp, timings);1016 if (err)1017 err = find_and_set_predefined_video_timings(sd,1018 0x02, adv7842_prim_mode_gr, timings);1019 break;1020 case ADV7842_MODE_HDMI:1021 err = find_and_set_predefined_video_timings(sd,1022 0x05, adv7842_prim_mode_hdmi_comp, timings);1023 if (err)1024 err = find_and_set_predefined_video_timings(sd,1025 0x06, adv7842_prim_mode_hdmi_gr, timings);1026 break;1027 default:1028 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",1029 __func__, state->mode);1030 err = -1;1031 break;1032 }1033 1034 1035 return err;1036}1037 1038static void configure_custom_video_timings(struct v4l2_subdev *sd,1039 const struct v4l2_bt_timings *bt)1040{1041 struct adv7842_state *state = to_state(sd);1042 struct i2c_client *client = v4l2_get_subdevdata(sd);1043 u32 width = htotal(bt);1044 u32 height = vtotal(bt);1045 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;1046 u16 cp_start_eav = width - bt->hfrontporch;1047 u16 cp_start_vbi = height - bt->vfrontporch + 1;1048 u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;1049 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?1050 ((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;1051 const u8 pll[2] = {1052 0xc0 | ((width >> 8) & 0x1f),1053 width & 0xff1054 };1055 1056 v4l2_dbg(2, debug, sd, "%s\n", __func__);1057 1058 switch (state->mode) {1059 case ADV7842_MODE_COMP:1060 case ADV7842_MODE_RGB:1061 /* auto graphics */1062 io_write(sd, 0x00, 0x07); /* video std */1063 io_write(sd, 0x01, 0x02); /* prim mode */1064 /* enable embedded syncs for auto graphics mode */1065 cp_write_and_or(sd, 0x81, 0xef, 0x10);1066 1067 /* Should only be set in auto-graphics mode [REF_02, p. 91-92] */1068 /* setup PLL_DIV_MAN_EN and PLL_DIV_RATIO */1069 /* IO-map reg. 0x16 and 0x17 should be written in sequence */1070 if (i2c_smbus_write_i2c_block_data(client, 0x16, 2, pll)) {1071 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");1072 break;1073 }1074 1075 /* active video - horizontal timing */1076 cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);1077 cp_write(sd, 0x27, (cp_start_sav & 0xff));1078 cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);1079 cp_write(sd, 0x29, (cp_start_eav & 0xff));1080 1081 /* active video - vertical timing */1082 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);1083 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |1084 ((cp_end_vbi >> 8) & 0xf));1085 cp_write(sd, 0xa7, cp_end_vbi & 0xff);1086 break;1087 case ADV7842_MODE_HDMI:1088 /* set default prim_mode/vid_std for HDMI1089 according to [REF_03, c. 4.2] */1090 io_write(sd, 0x00, 0x02); /* video std */1091 io_write(sd, 0x01, 0x06); /* prim mode */1092 break;1093 default:1094 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",1095 __func__, state->mode);1096 break;1097 }1098 1099 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);1100 cp_write(sd, 0x90, ch1_fr_ll & 0xff);1101 cp_write(sd, 0xab, (height >> 4) & 0xff);1102 cp_write(sd, 0xac, (height & 0x0f) << 4);1103}1104 1105static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)1106{1107 struct adv7842_state *state = to_state(sd);1108 u8 offset_buf[4];1109 1110 if (auto_offset) {1111 offset_a = 0x3ff;1112 offset_b = 0x3ff;1113 offset_c = 0x3ff;1114 }1115 1116 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",1117 __func__, auto_offset ? "Auto" : "Manual",1118 offset_a, offset_b, offset_c);1119 1120 offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);1121 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);1122 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);1123 offset_buf[3] = offset_c & 0x0ff;1124 1125 /* Registers must be written in this order with no i2c access in between */1126 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))1127 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);1128}1129 1130static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)1131{1132 struct adv7842_state *state = to_state(sd);1133 u8 gain_buf[4];1134 u8 gain_man = 1;1135 u8 agc_mode_man = 1;1136 1137 if (auto_gain) {1138 gain_man = 0;1139 agc_mode_man = 0;1140 gain_a = 0x100;1141 gain_b = 0x100;1142 gain_c = 0x100;1143 }1144 1145 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",1146 __func__, auto_gain ? "Auto" : "Manual",1147 gain_a, gain_b, gain_c);1148 1149 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));1150 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));1151 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));1152 gain_buf[3] = ((gain_c & 0x0ff));1153 1154 /* Registers must be written in this order with no i2c access in between */1155 if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))1156 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);1157}1158 1159static void set_rgb_quantization_range(struct v4l2_subdev *sd)1160{1161 struct adv7842_state *state = to_state(sd);1162 bool rgb_output = io_read(sd, 0x02) & 0x02;1163 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;1164 u8 y = HDMI_COLORSPACE_RGB;1165 1166 if (hdmi_signal && (io_read(sd, 0x60) & 1))1167 y = infoframe_read(sd, 0x01) >> 5;1168 1169 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",1170 __func__, state->rgb_quantization_range,1171 rgb_output, hdmi_signal);1172 1173 adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);1174 adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);1175 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);1176 1177 switch (state->rgb_quantization_range) {1178 case V4L2_DV_RGB_RANGE_AUTO:1179 if (state->mode == ADV7842_MODE_RGB) {1180 /* Receiving analog RGB signal1181 * Set RGB full range (0-255) */1182 io_write_and_or(sd, 0x02, 0x0f, 0x10);1183 break;1184 }1185 1186 if (state->mode == ADV7842_MODE_COMP) {1187 /* Receiving analog YPbPr signal1188 * Set automode */1189 io_write_and_or(sd, 0x02, 0x0f, 0xf0);1190 break;1191 }1192 1193 if (hdmi_signal) {1194 /* Receiving HDMI signal1195 * Set automode */1196 io_write_and_or(sd, 0x02, 0x0f, 0xf0);1197 break;1198 }1199 1200 /* Receiving DVI-D signal1201 * ADV7842 selects RGB limited range regardless of1202 * input format (CE/IT) in automatic mode */1203 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {1204 /* RGB limited range (16-235) */1205 io_write_and_or(sd, 0x02, 0x0f, 0x00);1206 } else {1207 /* RGB full range (0-255) */1208 io_write_and_or(sd, 0x02, 0x0f, 0x10);1209 1210 if (is_digital_input(sd) && rgb_output) {1211 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);1212 } else {1213 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);1214 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);1215 }1216 }1217 break;1218 case V4L2_DV_RGB_RANGE_LIMITED:1219 if (state->mode == ADV7842_MODE_COMP) {1220 /* YCrCb limited range (16-235) */1221 io_write_and_or(sd, 0x02, 0x0f, 0x20);1222 break;1223 }1224 1225 if (y != HDMI_COLORSPACE_RGB)1226 break;1227 1228 /* RGB limited range (16-235) */1229 io_write_and_or(sd, 0x02, 0x0f, 0x00);1230 1231 break;1232 case V4L2_DV_RGB_RANGE_FULL:1233 if (state->mode == ADV7842_MODE_COMP) {1234 /* YCrCb full range (0-255) */1235 io_write_and_or(sd, 0x02, 0x0f, 0x60);1236 break;1237 }1238 1239 if (y != HDMI_COLORSPACE_RGB)1240 break;1241 1242 /* RGB full range (0-255) */1243 io_write_and_or(sd, 0x02, 0x0f, 0x10);1244 1245 if (is_analog_input(sd) || hdmi_signal)1246 break;1247 1248 /* Adjust gain/offset for DVI-D signals only */1249 if (rgb_output) {1250 adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);1251 } else {1252 adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);1253 adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);1254 }1255 break;1256 }1257}1258 1259static int adv7842_s_ctrl(struct v4l2_ctrl *ctrl)1260{1261 struct v4l2_subdev *sd = to_sd(ctrl);1262 struct adv7842_state *state = to_state(sd);1263 1264 /* TODO SDP ctrls1265 contrast/brightness/hue/free run is acting a bit strange,1266 not sure if sdp csc is correct.1267 */1268 switch (ctrl->id) {1269 /* standard ctrls */1270 case V4L2_CID_BRIGHTNESS:1271 cp_write(sd, 0x3c, ctrl->val);1272 sdp_write(sd, 0x14, ctrl->val);1273 /* ignore lsb sdp 0x17[3:2] */1274 return 0;1275 case V4L2_CID_CONTRAST:1276 cp_write(sd, 0x3a, ctrl->val);1277 sdp_write(sd, 0x13, ctrl->val);1278 /* ignore lsb sdp 0x17[1:0] */1279 return 0;1280 case V4L2_CID_SATURATION:1281 cp_write(sd, 0x3b, ctrl->val);1282 sdp_write(sd, 0x15, ctrl->val);1283 /* ignore lsb sdp 0x17[5:4] */1284 return 0;1285 case V4L2_CID_HUE:1286 cp_write(sd, 0x3d, ctrl->val);1287 sdp_write(sd, 0x16, ctrl->val);1288 /* ignore lsb sdp 0x17[7:6] */1289 return 0;1290 /* custom ctrls */1291 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:1292 afe_write(sd, 0xc8, ctrl->val);1293 return 0;1294 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:1295 cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));1296 sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));1297 return 0;1298 case V4L2_CID_ADV_RX_FREE_RUN_COLOR: {1299 u8 R = (ctrl->val & 0xff0000) >> 16;1300 u8 G = (ctrl->val & 0x00ff00) >> 8;1301 u8 B = (ctrl->val & 0x0000ff);1302 /* RGB -> YUV, numerical approximation */1303 int Y = 66 * R + 129 * G + 25 * B;1304 int U = -38 * R - 74 * G + 112 * B;1305 int V = 112 * R - 94 * G - 18 * B;1306 1307 /* Scale down to 8 bits with rounding */1308 Y = (Y + 128) >> 8;1309 U = (U + 128) >> 8;1310 V = (V + 128) >> 8;1311 /* make U,V positive */1312 Y += 16;1313 U += 128;1314 V += 128;1315 1316 v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);1317 v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);1318 1319 /* CP */1320 cp_write(sd, 0xc1, R);1321 cp_write(sd, 0xc0, G);1322 cp_write(sd, 0xc2, B);1323 /* SDP */1324 sdp_write(sd, 0xde, Y);1325 sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));1326 return 0;1327 }1328 case V4L2_CID_DV_RX_RGB_RANGE:1329 state->rgb_quantization_range = ctrl->val;1330 set_rgb_quantization_range(sd);1331 return 0;1332 }1333 return -EINVAL;1334}1335 1336static int adv7842_g_volatile_ctrl(struct v4l2_ctrl *ctrl)1337{1338 struct v4l2_subdev *sd = to_sd(ctrl);1339 1340 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {1341 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;1342 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))1343 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;1344 return 0;1345 }1346 return -EINVAL;1347}1348 1349static inline bool no_power(struct v4l2_subdev *sd)1350{1351 return io_read(sd, 0x0c) & 0x24;1352}1353 1354static inline bool no_cp_signal(struct v4l2_subdev *sd)1355{1356 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);1357}1358 1359static inline bool is_hdmi(struct v4l2_subdev *sd)1360{1361 return hdmi_read(sd, 0x05) & 0x80;1362}1363 1364static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)1365{1366 struct adv7842_state *state = to_state(sd);1367 1368 *status = 0;1369 1370 if (io_read(sd, 0x0c) & 0x24)1371 *status |= V4L2_IN_ST_NO_POWER;1372 1373 if (state->mode == ADV7842_MODE_SDP) {1374 /* status from SDP block */1375 if (!(sdp_read(sd, 0x5A) & 0x01))1376 *status |= V4L2_IN_ST_NO_SIGNAL;1377 1378 v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",1379 __func__, *status);1380 return 0;1381 }1382 /* status from CP block */1383 if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||1384 !(cp_read(sd, 0xb1) & 0x80))1385 /* TODO channel 2 */1386 *status |= V4L2_IN_ST_NO_SIGNAL;1387 1388 if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))1389 *status |= V4L2_IN_ST_NO_SIGNAL;1390 1391 v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",1392 __func__, *status);1393 1394 return 0;1395}1396 1397struct stdi_readback {1398 u16 bl, lcf, lcvs;1399 u8 hs_pol, vs_pol;1400 bool interlaced;1401};1402 1403static int stdi2dv_timings(struct v4l2_subdev *sd,1404 struct stdi_readback *stdi,1405 struct v4l2_dv_timings *timings)1406{1407 struct adv7842_state *state = to_state(sd);1408 u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;1409 u32 pix_clk;1410 int i;1411 1412 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {1413 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;1414 1415 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],1416 adv7842_get_dv_timings_cap(sd),1417 adv7842_check_dv_timings, NULL))1418 continue;1419 if (vtotal(bt) != stdi->lcf + 1)1420 continue;1421 if (bt->vsync != stdi->lcvs)1422 continue;1423 1424 pix_clk = hfreq * htotal(bt);1425 1426 if ((pix_clk < bt->pixelclock + 1000000) &&1427 (pix_clk > bt->pixelclock - 1000000)) {1428 *timings = v4l2_dv_timings_presets[i];1429 return 0;1430 }1431 }1432 1433 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,1434 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |1435 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),1436 false, timings))1437 return 0;1438 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,1439 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |1440 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),1441 false, state->aspect_ratio, timings))1442 return 0;1443 1444 v4l2_dbg(2, debug, sd,1445 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",1446 __func__, stdi->lcvs, stdi->lcf, stdi->bl,1447 stdi->hs_pol, stdi->vs_pol);1448 return -1;1449}1450 1451static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)1452{1453 u32 status;1454 1455 adv7842_g_input_status(sd, &status);1456 if (status & V4L2_IN_ST_NO_SIGNAL) {1457 v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);1458 return -ENOLINK;1459 }1460 1461 stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);1462 stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);1463 stdi->lcvs = cp_read(sd, 0xb3) >> 3;1464 1465 if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {1466 stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?1467 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');1468 stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?1469 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');1470 } else {1471 stdi->hs_pol = 'x';1472 stdi->vs_pol = 'x';1473 }1474 stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;1475 1476 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {1477 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);1478 return -ENOLINK;1479 }1480 1481 v4l2_dbg(2, debug, sd,1482 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",1483 __func__, stdi->lcf, stdi->bl, stdi->lcvs,1484 stdi->hs_pol, stdi->vs_pol,1485 stdi->interlaced ? "interlaced" : "progressive");1486 1487 return 0;1488}1489 1490static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,1491 struct v4l2_enum_dv_timings *timings)1492{1493 if (timings->pad != 0)1494 return -EINVAL;1495 1496 return v4l2_enum_dv_timings_cap(timings,1497 adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);1498}1499 1500static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,1501 struct v4l2_dv_timings_cap *cap)1502{1503 if (cap->pad != 0)1504 return -EINVAL;1505 1506 *cap = *adv7842_get_dv_timings_cap(sd);1507 return 0;1508}1509 1510/* Fill the optional fields .standards and .flags in struct v4l2_dv_timings1511 if the format is listed in adv7842_timings[] */1512static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,1513 struct v4l2_dv_timings *timings)1514{1515 v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),1516 is_digital_input(sd) ? 250000 : 1000000,1517 adv7842_check_dv_timings, NULL);1518 timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS;1519}1520 1521static int adv7842_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad,1522 struct v4l2_dv_timings *timings)1523{1524 struct adv7842_state *state = to_state(sd);1525 struct v4l2_bt_timings *bt = &timings->bt;1526 struct stdi_readback stdi = { 0 };1527 1528 v4l2_dbg(1, debug, sd, "%s:\n", __func__);1529 1530 if (pad != 0)1531 return -EINVAL;1532 1533 memset(timings, 0, sizeof(struct v4l2_dv_timings));1534 1535 /* SDP block */1536 if (state->mode == ADV7842_MODE_SDP)1537 return -ENODATA;1538 1539 /* read STDI */1540 if (read_stdi(sd, &stdi)) {1541 state->restart_stdi_once = true;1542 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);1543 return -ENOLINK;1544 }1545 bt->interlaced = stdi.interlaced ?1546 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;1547 bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |1548 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT;1549 1550 if (is_digital_input(sd)) {1551 u32 freq;1552 1553 timings->type = V4L2_DV_BT_656_1120;1554 1555 bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);1556 bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);1557 freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;1558 freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);1559 if (is_hdmi(sd)) {1560 /* adjust for deep color mode */1561 freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);1562 }1563 bt->pixelclock = freq;1564 bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +1565 hdmi_read(sd, 0x21);1566 bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +1567 hdmi_read(sd, 0x23);1568 bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +1569 hdmi_read(sd, 0x25);1570 bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +1571 hdmi_read(sd, 0x2b)) / 2;1572 bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +1573 hdmi_read(sd, 0x2f)) / 2;1574 bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +1575 hdmi_read(sd, 0x33)) / 2;1576 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |1577 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);1578 if (bt->interlaced == V4L2_DV_INTERLACED) {1579 bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +1580 hdmi_read(sd, 0x0c);1581 bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +1582 hdmi_read(sd, 0x2d)) / 2;1583 bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +1584 hdmi_read(sd, 0x31)) / 2;1585 bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +1586 hdmi_read(sd, 0x35)) / 2;1587 } else {1588 bt->il_vfrontporch = 0;1589 bt->il_vsync = 0;1590 bt->il_vbackporch = 0;1591 }1592 adv7842_fill_optional_dv_timings_fields(sd, timings);1593 if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) &&1594 freq < bt->pixelclock) {1595 u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000;1596 u32 delta_freq = abs(freq - reduced_freq);1597 1598 if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2)1599 timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS;1600 }1601 } else {1602 /* find format1603 * Since LCVS values are inaccurate [REF_03, p. 339-340],1604 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.1605 */1606 if (!stdi2dv_timings(sd, &stdi, timings))1607 goto found;1608 stdi.lcvs += 1;1609 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);1610 if (!stdi2dv_timings(sd, &stdi, timings))1611 goto found;1612 stdi.lcvs -= 2;1613 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);1614 if (stdi2dv_timings(sd, &stdi, timings)) {1615 /*1616 * The STDI block may measure wrong values, especially1617 * for lcvs and lcf. If the driver can not find any1618 * valid timing, the STDI block is restarted to measure1619 * the video timings again. The function will return an1620 * error, but the restart of STDI will generate a new1621 * STDI interrupt and the format detection process will1622 * restart.1623 */1624 if (state->restart_stdi_once) {1625 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);1626 /* TODO restart STDI for Sync Channel 2 */1627 /* enter one-shot mode */1628 cp_write_and_or(sd, 0x86, 0xf9, 0x00);1629 /* trigger STDI restart */1630 cp_write_and_or(sd, 0x86, 0xf9, 0x04);1631 /* reset to continuous mode */1632 cp_write_and_or(sd, 0x86, 0xf9, 0x02);1633 state->restart_stdi_once = false;1634 return -ENOLINK;1635 }1636 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);1637 return -ERANGE;1638 }1639 state->restart_stdi_once = true;1640 }1641found:1642 1643 if (debug > 1)1644 v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",1645 timings, true);1646 return 0;1647}1648 1649static int adv7842_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,1650 struct v4l2_dv_timings *timings)1651{1652 struct adv7842_state *state = to_state(sd);1653 struct v4l2_bt_timings *bt;1654 int err;1655 1656 v4l2_dbg(1, debug, sd, "%s:\n", __func__);1657 1658 if (pad != 0)1659 return -EINVAL;1660 1661 if (state->mode == ADV7842_MODE_SDP)1662 return -ENODATA;1663 1664 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {1665 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);1666 return 0;1667 }1668 1669 bt = &timings->bt;1670 1671 if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),1672 adv7842_check_dv_timings, NULL))1673 return -ERANGE;1674 1675 adv7842_fill_optional_dv_timings_fields(sd, timings);1676 1677 state->timings = *timings;1678 1679 cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);1680 1681 /* Use prim_mode and vid_std when available */1682 err = configure_predefined_video_timings(sd, timings);1683 if (err) {1684 /* custom settings when the video format1685 does not have prim_mode/vid_std */1686 configure_custom_video_timings(sd, bt);1687 }1688 1689 set_rgb_quantization_range(sd);1690 1691 1692 if (debug > 1)1693 v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",1694 timings, true);1695 return 0;1696}1697 1698static int adv7842_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,1699 struct v4l2_dv_timings *timings)1700{1701 struct adv7842_state *state = to_state(sd);1702 1703 if (pad != 0)1704 return -EINVAL;1705 1706 if (state->mode == ADV7842_MODE_SDP)1707 return -ENODATA;1708 *timings = state->timings;1709 return 0;1710}1711 1712static void enable_input(struct v4l2_subdev *sd)1713{1714 struct adv7842_state *state = to_state(sd);1715 1716 set_rgb_quantization_range(sd);1717 switch (state->mode) {1718 case ADV7842_MODE_SDP:1719 case ADV7842_MODE_COMP:1720 case ADV7842_MODE_RGB:1721 io_write(sd, 0x15, 0xb0); /* Disable Tristate of Pins (no audio) */1722 break;1723 case ADV7842_MODE_HDMI:1724 hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */1725 io_write(sd, 0x15, 0xa0); /* Disable Tristate of Pins */1726 hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */1727 break;1728 default:1729 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",1730 __func__, state->mode);1731 break;1732 }1733}1734 1735static void disable_input(struct v4l2_subdev *sd)1736{1737 hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */1738 msleep(16); /* 512 samples with >= 32 kHz sample rate [REF_03, c. 8.29] */1739 io_write(sd, 0x15, 0xbe); /* Tristate all outputs from video core */1740 hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */1741}1742 1743static void sdp_csc_coeff(struct v4l2_subdev *sd,1744 const struct adv7842_sdp_csc_coeff *c)1745{1746 /* csc auto/manual */1747 sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);1748 1749 if (!c->manual)1750 return;1751 1752 /* csc scaling */1753 sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);1754 1755 /* A coeff */1756 sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);1757 sdp_io_write(sd, 0xe1, c->A1);1758 sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);1759 sdp_io_write(sd, 0xe3, c->A2);1760 sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);1761 sdp_io_write(sd, 0xe5, c->A3);1762 1763 /* A scale */1764 sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);1765 sdp_io_write(sd, 0xe7, c->A4);1766 1767 /* B coeff */1768 sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);1769 sdp_io_write(sd, 0xe9, c->B1);1770 sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);1771 sdp_io_write(sd, 0xeb, c->B2);1772 sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);1773 sdp_io_write(sd, 0xed, c->B3);1774 1775 /* B scale */1776 sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);1777 sdp_io_write(sd, 0xef, c->B4);1778 1779 /* C coeff */1780 sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);1781 sdp_io_write(sd, 0xf1, c->C1);1782 sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);1783 sdp_io_write(sd, 0xf3, c->C2);1784 sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);1785 sdp_io_write(sd, 0xf5, c->C3);1786 1787 /* C scale */1788 sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);1789 sdp_io_write(sd, 0xf7, c->C4);1790}1791 1792static void select_input(struct v4l2_subdev *sd,1793 enum adv7842_vid_std_select vid_std_select)1794{1795 struct adv7842_state *state = to_state(sd);1796 1797 switch (state->mode) {1798 case ADV7842_MODE_SDP:1799 io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */1800 io_write(sd, 0x01, 0); /* prim mode */1801 /* enable embedded syncs for auto graphics mode */1802 cp_write_and_or(sd, 0x81, 0xef, 0x10);1803 1804 afe_write(sd, 0x00, 0x00); /* power up ADC */1805 afe_write(sd, 0xc8, 0x00); /* phase control */1806 1807 io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */1808 /* script says register 0xde, which don't exist in manual */1809 1810 /* Manual analog input muxing mode, CVBS (6.4)*/1811 afe_write_and_or(sd, 0x02, 0x7f, 0x80);1812 if (vid_std_select == ADV7842_SDP_VID_STD_CVBS_SD_4x1) {1813 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/1814 afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/1815 } else {1816 afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/1817 afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/1818 }1819 afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */1820 afe_write(sd, 0x12, 0x63); /* ADI recommend write */1821 1822 sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */1823 sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */1824 1825 /* SDP recommended settings */1826 sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */1827 sdp_write(sd, 0x01, 0x00); /* Pedestal Off */1828 1829 sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */1830 sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */1831 sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */1832 sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */1833 sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */1834 sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */1835 sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */1836 1837 /* deinterlacer enabled and 3D comb */1838 sdp_write_and_or(sd, 0x12, 0xf6, 0x09);1839 1840 break;1841 1842 case ADV7842_MODE_COMP:1843 case ADV7842_MODE_RGB:1844 /* Automatic analog input muxing mode */1845 afe_write_and_or(sd, 0x02, 0x7f, 0x00);1846 /* set mode and select free run resolution */1847 io_write(sd, 0x00, vid_std_select); /* video std */1848 io_write(sd, 0x01, 0x02); /* prim mode */1849 cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs1850 for auto graphics mode */1851 1852 afe_write(sd, 0x00, 0x00); /* power up ADC */1853 afe_write(sd, 0xc8, 0x00); /* phase control */1854 if (state->mode == ADV7842_MODE_COMP) {1855 /* force to YCrCb */1856 io_write_and_or(sd, 0x02, 0x0f, 0x60);1857 } else {1858 /* force to RGB */1859 io_write_and_or(sd, 0x02, 0x0f, 0x10);1860 }1861 1862 /* set ADI recommended settings for digitizer */1863 /* "ADV7842 Register Settings Recommendations1864 * (rev. 1.8, November 2010)" p. 9. */1865 afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */1866 afe_write(sd, 0x12, 0x63); /* ADC Range improvement */1867 1868 /* set to default gain for RGB */1869 cp_write(sd, 0x73, 0x10);1870 cp_write(sd, 0x74, 0x04);1871 cp_write(sd, 0x75, 0x01);1872 cp_write(sd, 0x76, 0x00);1873 1874 cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */1875 cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */1876 cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */1877 break;1878 1879 case ADV7842_MODE_HDMI:1880 /* Automatic analog input muxing mode */1881 afe_write_and_or(sd, 0x02, 0x7f, 0x00);1882 /* set mode and select free run resolution */1883 if (state->hdmi_port_a)1884 hdmi_write(sd, 0x00, 0x02); /* select port A */1885 else1886 hdmi_write(sd, 0x00, 0x03); /* select port B */1887 io_write(sd, 0x00, vid_std_select); /* video std */1888 io_write(sd, 0x01, 5); /* prim mode */1889 cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs1890 for auto graphics mode */1891 1892 /* set ADI recommended settings for HDMI: */1893 /* "ADV7842 Register Settings Recommendations1894 * (rev. 1.8, November 2010)" p. 3. */1895 hdmi_write(sd, 0xc0, 0x00);1896 hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */1897 hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */1898 hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */1899 hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */1900 hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */1901 hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */1902 hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */1903 hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */1904 hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,1905 Improve robustness */1906 hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */1907 hdmi_write(sd, 0x85, 0x1f); /* equaliser */1908 hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */1909 hdmi_write(sd, 0x89, 0x04); /* equaliser */1910 hdmi_write(sd, 0x8a, 0x1e); /* equaliser */1911 hdmi_write(sd, 0x93, 0x04); /* equaliser */1912 hdmi_write(sd, 0x94, 0x1e); /* equaliser */1913 hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */1914 hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */1915 hdmi_write(sd, 0x9d, 0x02); /* equaliser */1916 1917 afe_write(sd, 0x00, 0xff); /* power down ADC */1918 afe_write(sd, 0xc8, 0x40); /* phase control */1919 1920 /* set to default gain for HDMI */1921 cp_write(sd, 0x73, 0x10);1922 cp_write(sd, 0x74, 0x04);1923 cp_write(sd, 0x75, 0x01);1924 cp_write(sd, 0x76, 0x00);1925 1926 /* reset ADI recommended settings for digitizer */1927 /* "ADV7842 Register Settings Recommendations1928 * (rev. 2.5, June 2010)" p. 17. */1929 afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */1930 afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */1931 cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */1932 1933 /* CP coast control */1934 cp_write(sd, 0xc3, 0x33); /* Component mode */1935 1936 /* color space conversion, autodetect color space */1937 io_write_and_or(sd, 0x02, 0x0f, 0xf0);1938 break;1939 1940 default:1941 v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",1942 __func__, state->mode);1943 break;1944 }1945}1946 1947static int adv7842_s_routing(struct v4l2_subdev *sd,1948 u32 input, u32 output, u32 config)1949{1950 struct adv7842_state *state = to_state(sd);1951 1952 v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);1953 1954 switch (input) {1955 case ADV7842_SELECT_HDMI_PORT_A:1956 state->mode = ADV7842_MODE_HDMI;1957 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;1958 state->hdmi_port_a = true;1959 break;1960 case ADV7842_SELECT_HDMI_PORT_B:1961 state->mode = ADV7842_MODE_HDMI;1962 state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;1963 state->hdmi_port_a = false;1964 break;1965 case ADV7842_SELECT_VGA_COMP:1966 state->mode = ADV7842_MODE_COMP;1967 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;1968 break;1969 case ADV7842_SELECT_VGA_RGB:1970 state->mode = ADV7842_MODE_RGB;1971 state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;1972 break;1973 case ADV7842_SELECT_SDP_CVBS:1974 state->mode = ADV7842_MODE_SDP;1975 state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;1976 break;1977 case ADV7842_SELECT_SDP_YC:1978 state->mode = ADV7842_MODE_SDP;1979 state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;1980 break;1981 default:1982 return -EINVAL;1983 }1984 1985 disable_input(sd);1986 select_input(sd, state->vid_std_select);1987 enable_input(sd);1988 1989 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);1990 1991 return 0;1992}1993 1994static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,1995 struct v4l2_subdev_state *sd_state,1996 struct v4l2_subdev_mbus_code_enum *code)1997{1998 if (code->index >= ARRAY_SIZE(adv7842_formats))1999 return -EINVAL;2000 code->code = adv7842_formats[code->index].code;2001 return 0;2002}2003 2004static void adv7842_fill_format(struct adv7842_state *state,2005 struct v4l2_mbus_framefmt *format)2006{2007 memset(format, 0, sizeof(*format));2008 2009 format->width = state->timings.bt.width;2010 format->height = state->timings.bt.height;2011 format->field = V4L2_FIELD_NONE;2012 format->colorspace = V4L2_COLORSPACE_SRGB;2013 2014 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)2015 format->colorspace = (state->timings.bt.height <= 576) ?2016 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;2017}2018 2019/*2020 * Compute the op_ch_sel value required to obtain on the bus the component order2021 * corresponding to the selected format taking into account bus reordering2022 * applied by the board at the output of the device.2023 *2024 * The following table gives the op_ch_value from the format component order2025 * (expressed as op_ch_sel value in column) and the bus reordering (expressed as2026 * adv7842_bus_order value in row).2027 *2028 * | GBR(0) GRB(1) BGR(2) RGB(3) BRG(4) RBG(5)2029 * ----------+-------------------------------------------------2030 * RGB (NOP) | GBR GRB BGR RGB BRG RBG2031 * GRB (1-2) | BGR RGB GBR GRB RBG BRG2032 * RBG (2-3) | GRB GBR BRG RBG BGR RGB2033 * BGR (1-3) | RBG BRG RGB BGR GRB GBR2034 * BRG (ROR) | BRG RBG GRB GBR RGB BGR2035 * GBR (ROL) | RGB BGR RBG BRG GBR GRB2036 */2037static unsigned int adv7842_op_ch_sel(struct adv7842_state *state)2038{2039#define _SEL(a, b, c, d, e, f) { \2040 ADV7842_OP_CH_SEL_##a, ADV7842_OP_CH_SEL_##b, ADV7842_OP_CH_SEL_##c, \2041 ADV7842_OP_CH_SEL_##d, ADV7842_OP_CH_SEL_##e, ADV7842_OP_CH_SEL_##f }2042#define _BUS(x) [ADV7842_BUS_ORDER_##x]2043 2044 static const unsigned int op_ch_sel[6][6] = {2045 _BUS(RGB) /* NOP */ = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),2046 _BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),2047 _BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),2048 _BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),2049 _BUS(BRG) /* ROR */ = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),2050 _BUS(GBR) /* ROL */ = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),2051 };2052 2053 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];2054}2055 2056static void adv7842_setup_format(struct adv7842_state *state)2057{2058 struct v4l2_subdev *sd = &state->sd;2059 2060 io_write_clr_set(sd, 0x02, 0x02,2061 state->format->rgb_out ? ADV7842_RGB_OUT : 0);2062 io_write(sd, 0x03, state->format->op_format_sel |2063 state->pdata.op_format_mode_sel);2064 io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));2065 io_write_clr_set(sd, 0x05, 0x01,2066 state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);2067 set_rgb_quantization_range(sd);2068}2069 2070static int adv7842_get_format(struct v4l2_subdev *sd,2071 struct v4l2_subdev_state *sd_state,2072 struct v4l2_subdev_format *format)2073{2074 struct adv7842_state *state = to_state(sd);2075 2076 if (format->pad != ADV7842_PAD_SOURCE)2077 return -EINVAL;2078 2079 if (state->mode == ADV7842_MODE_SDP) {2080 /* SPD block */2081 if (!(sdp_read(sd, 0x5a) & 0x01))2082 return -EINVAL;2083 format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;2084 format->format.width = 720;2085 /* valid signal */2086 if (state->norm & V4L2_STD_525_60)2087 format->format.height = 480;2088 else2089 format->format.height = 576;2090 format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;2091 return 0;2092 }2093 2094 adv7842_fill_format(state, &format->format);2095 2096 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {2097 struct v4l2_mbus_framefmt *fmt;2098 2099 fmt = v4l2_subdev_state_get_format(sd_state, format->pad);2100 format->format.code = fmt->code;2101 } else {2102 format->format.code = state->format->code;2103 }2104 2105 return 0;2106}2107 2108static int adv7842_set_format(struct v4l2_subdev *sd,2109 struct v4l2_subdev_state *sd_state,2110 struct v4l2_subdev_format *format)2111{2112 struct adv7842_state *state = to_state(sd);2113 const struct adv7842_format_info *info;2114 2115 if (format->pad != ADV7842_PAD_SOURCE)2116 return -EINVAL;2117 2118 if (state->mode == ADV7842_MODE_SDP)2119 return adv7842_get_format(sd, sd_state, format);2120 2121 info = adv7842_format_info(state, format->format.code);2122 if (info == NULL)2123 info = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);2124 2125 adv7842_fill_format(state, &format->format);2126 format->format.code = info->code;2127 2128 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {2129 struct v4l2_mbus_framefmt *fmt;2130 2131 fmt = v4l2_subdev_state_get_format(sd_state, format->pad);2132 fmt->code = format->format.code;2133 } else {2134 state->format = info;2135 adv7842_setup_format(state);2136 }2137 2138 return 0;2139}2140 2141static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)2142{2143 if (enable) {2144 /* Enable SSPD, STDI and CP locked/unlocked interrupts */2145 io_write(sd, 0x46, 0x9c);2146 /* ESDP_50HZ_DET interrupt */2147 io_write(sd, 0x5a, 0x10);2148 /* Enable CABLE_DET_A/B_ST (+5v) interrupt */2149 io_write(sd, 0x73, 0x03);2150 /* Enable V_LOCKED and DE_REGEN_LCK interrupts */2151 io_write(sd, 0x78, 0x03);2152 /* Enable SDP Standard Detection Change and SDP Video Detected */2153 io_write(sd, 0xa0, 0x09);2154 /* Enable HDMI_MODE interrupt */2155 io_write(sd, 0x69, 0x08);2156 } else {2157 io_write(sd, 0x46, 0x0);2158 io_write(sd, 0x5a, 0x0);2159 io_write(sd, 0x73, 0x0);2160 io_write(sd, 0x78, 0x0);2161 io_write(sd, 0xa0, 0x0);2162 io_write(sd, 0x69, 0x0);2163 }2164}2165 2166#if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)2167static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)2168{2169 struct adv7842_state *state = to_state(sd);2170 2171 if ((cec_read(sd, 0x11) & 0x01) == 0) {2172 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);2173 return;2174 }2175 2176 if (tx_raw_status & 0x02) {2177 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",2178 __func__);2179 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,2180 1, 0, 0, 0);2181 return;2182 }2183 if (tx_raw_status & 0x04) {2184 u8 status;2185 u8 nack_cnt;2186 u8 low_drive_cnt;2187 2188 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);2189 /*2190 * We set this status bit since this hardware performs2191 * retransmissions.2192 */2193 status = CEC_TX_STATUS_MAX_RETRIES;2194 nack_cnt = cec_read(sd, 0x14) & 0xf;2195 if (nack_cnt)2196 status |= CEC_TX_STATUS_NACK;2197 low_drive_cnt = cec_read(sd, 0x14) >> 4;2198 if (low_drive_cnt)2199 status |= CEC_TX_STATUS_LOW_DRIVE;2200 cec_transmit_done(state->cec_adap, status,2201 0, nack_cnt, low_drive_cnt, 0);2202 return;2203 }2204 if (tx_raw_status & 0x01) {2205 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);2206 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);2207 return;2208 }2209}2210 2211static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)2212{2213 u8 cec_irq;2214 2215 /* cec controller */2216 cec_irq = io_read(sd, 0x93) & 0x0f;2217 if (!cec_irq)2218 return;2219 2220 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);2221 adv7842_cec_tx_raw_status(sd, cec_irq);2222 if (cec_irq & 0x08) {2223 struct adv7842_state *state = to_state(sd);2224 struct cec_msg msg;2225 2226 msg.len = cec_read(sd, 0x25) & 0x1f;2227 if (msg.len > CEC_MAX_MSG_SIZE)2228 msg.len = CEC_MAX_MSG_SIZE;2229 2230 if (msg.len) {2231 u8 i;2232 2233 for (i = 0; i < msg.len; i++)2234 msg.msg[i] = cec_read(sd, i + 0x15);2235 cec_write(sd, 0x26, 0x01); /* re-enable rx */2236 cec_received_msg(state->cec_adap, &msg);2237 }2238 }2239 2240 io_write(sd, 0x94, cec_irq);2241 2242 if (handled)2243 *handled = true;2244}2245 2246static int adv7842_cec_adap_enable(struct cec_adapter *adap, bool enable)2247{2248 struct adv7842_state *state = cec_get_drvdata(adap);2249 struct v4l2_subdev *sd = &state->sd;2250 2251 if (!state->cec_enabled_adap && enable) {2252 cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */2253 cec_write(sd, 0x2c, 0x01); /* cec soft reset */2254 cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */2255 /* enabled irqs: */2256 /* tx: ready */2257 /* tx: arbitration lost */2258 /* tx: retry timeout */2259 /* rx: ready */2260 io_write_clr_set(sd, 0x96, 0x0f, 0x0f);2261 cec_write(sd, 0x26, 0x01); /* enable rx */2262 } else if (state->cec_enabled_adap && !enable) {2263 /* disable cec interrupts */2264 io_write_clr_set(sd, 0x96, 0x0f, 0x00);2265 /* disable address mask 1-3 */2266 cec_write_clr_set(sd, 0x27, 0x70, 0x00);2267 /* power down cec section */2268 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);2269 state->cec_valid_addrs = 0;2270 }2271 state->cec_enabled_adap = enable;2272 return 0;2273}2274 2275static int adv7842_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)2276{2277 struct adv7842_state *state = cec_get_drvdata(adap);2278 struct v4l2_subdev *sd = &state->sd;2279 unsigned int i, free_idx = ADV7842_MAX_ADDRS;2280 2281 if (!state->cec_enabled_adap)2282 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;2283 2284 if (addr == CEC_LOG_ADDR_INVALID) {2285 cec_write_clr_set(sd, 0x27, 0x70, 0);2286 state->cec_valid_addrs = 0;2287 return 0;2288 }2289 2290 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {2291 bool is_valid = state->cec_valid_addrs & (1 << i);2292 2293 if (free_idx == ADV7842_MAX_ADDRS && !is_valid)2294 free_idx = i;2295 if (is_valid && state->cec_addr[i] == addr)2296 return 0;2297 }2298 if (i == ADV7842_MAX_ADDRS) {2299 i = free_idx;2300 if (i == ADV7842_MAX_ADDRS)2301 return -ENXIO;2302 }2303 state->cec_addr[i] = addr;2304 state->cec_valid_addrs |= 1 << i;2305 2306 switch (i) {2307 case 0:2308 /* enable address mask 0 */2309 cec_write_clr_set(sd, 0x27, 0x10, 0x10);2310 /* set address for mask 0 */2311 cec_write_clr_set(sd, 0x28, 0x0f, addr);2312 break;2313 case 1:2314 /* enable address mask 1 */2315 cec_write_clr_set(sd, 0x27, 0x20, 0x20);2316 /* set address for mask 1 */2317 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);2318 break;2319 case 2:2320 /* enable address mask 2 */2321 cec_write_clr_set(sd, 0x27, 0x40, 0x40);2322 /* set address for mask 1 */2323 cec_write_clr_set(sd, 0x29, 0x0f, addr);2324 break;2325 }2326 return 0;2327}2328 2329static int adv7842_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,2330 u32 signal_free_time, struct cec_msg *msg)2331{2332 struct adv7842_state *state = cec_get_drvdata(adap);2333 struct v4l2_subdev *sd = &state->sd;2334 u8 len = msg->len;2335 unsigned int i;2336 2337 /*2338 * The number of retries is the number of attempts - 1, but retry2339 * at least once. It's not clear if a value of 0 is allowed, so2340 * let's do at least one retry.2341 */2342 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);2343 2344 if (len > 16) {2345 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);2346 return -EINVAL;2347 }2348 2349 /* write data */2350 for (i = 0; i < len; i++)2351 cec_write(sd, i, msg->msg[i]);2352 2353 /* set length (data + header) */2354 cec_write(sd, 0x10, len);2355 /* start transmit, enable tx */2356 cec_write(sd, 0x11, 0x01);2357 return 0;2358}2359 2360static const struct cec_adap_ops adv7842_cec_adap_ops = {2361 .adap_enable = adv7842_cec_adap_enable,2362 .adap_log_addr = adv7842_cec_adap_log_addr,2363 .adap_transmit = adv7842_cec_adap_transmit,2364};2365#endif2366 2367static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)2368{2369 struct adv7842_state *state = to_state(sd);2370 u8 fmt_change_cp, fmt_change_digital, fmt_change_sdp;2371 u8 irq_status[6];2372 2373 adv7842_irq_enable(sd, false);2374 2375 /* read status */2376 irq_status[0] = io_read(sd, 0x43);2377 irq_status[1] = io_read(sd, 0x57);2378 irq_status[2] = io_read(sd, 0x70);2379 irq_status[3] = io_read(sd, 0x75);2380 irq_status[4] = io_read(sd, 0x9d);2381 irq_status[5] = io_read(sd, 0x66);2382 2383 /* and clear */2384 if (irq_status[0])2385 io_write(sd, 0x44, irq_status[0]);2386 if (irq_status[1])2387 io_write(sd, 0x58, irq_status[1]);2388 if (irq_status[2])2389 io_write(sd, 0x71, irq_status[2]);2390 if (irq_status[3])2391 io_write(sd, 0x76, irq_status[3]);2392 if (irq_status[4])2393 io_write(sd, 0x9e, irq_status[4]);2394 if (irq_status[5])2395 io_write(sd, 0x67, irq_status[5]);2396 2397 adv7842_irq_enable(sd, true);2398 2399 v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,2400 irq_status[0], irq_status[1], irq_status[2],2401 irq_status[3], irq_status[4], irq_status[5]);2402 2403 /* format change CP */2404 fmt_change_cp = irq_status[0] & 0x9c;2405 2406 /* format change SDP */2407 if (state->mode == ADV7842_MODE_SDP)2408 fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);2409 else2410 fmt_change_sdp = 0;2411 2412 /* digital format CP */2413 if (is_digital_input(sd))2414 fmt_change_digital = irq_status[3] & 0x03;2415 else2416 fmt_change_digital = 0;2417 2418 /* format change */2419 if (fmt_change_cp || fmt_change_digital || fmt_change_sdp) {2420 v4l2_dbg(1, debug, sd,2421 "%s: fmt_change_cp = 0x%x, fmt_change_digital = 0x%x, fmt_change_sdp = 0x%x\n",2422 __func__, fmt_change_cp, fmt_change_digital,2423 fmt_change_sdp);2424 v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);2425 if (handled)2426 *handled = true;2427 }2428 2429 /* HDMI/DVI mode */2430 if (irq_status[5] & 0x08) {2431 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,2432 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");2433 set_rgb_quantization_range(sd);2434 if (handled)2435 *handled = true;2436 }2437 2438#if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)2439 /* cec */2440 adv7842_cec_isr(sd, handled);2441#endif2442 2443 /* tx 5v detect */2444 if (irq_status[2] & 0x3) {2445 v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);2446 adv7842_s_detect_tx_5v_ctrl(sd);2447 if (handled)2448 *handled = true;2449 }2450 return 0;2451}2452 2453static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)2454{2455 struct adv7842_state *state = to_state(sd);2456 u32 blocks = 0;2457 u8 *data = NULL;2458 2459 memset(edid->reserved, 0, sizeof(edid->reserved));2460 2461 switch (edid->pad) {2462 case ADV7842_EDID_PORT_A:2463 case ADV7842_EDID_PORT_B:2464 if (state->hdmi_edid.present & (0x04 << edid->pad)) {2465 data = state->hdmi_edid.edid;2466 blocks = state->hdmi_edid.blocks;2467 }2468 break;2469 case ADV7842_EDID_PORT_VGA:2470 if (state->vga_edid.present) {2471 data = state->vga_edid.edid;2472 blocks = state->vga_edid.blocks;2473 }2474 break;2475 default:2476 return -EINVAL;2477 }2478 2479 if (edid->start_block == 0 && edid->blocks == 0) {2480 edid->blocks = blocks;2481 return 0;2482 }2483 2484 if (!data)2485 return -ENODATA;2486 2487 if (edid->start_block >= blocks)2488 return -EINVAL;2489 2490 if (edid->start_block + edid->blocks > blocks)2491 edid->blocks = blocks - edid->start_block;2492 2493 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);2494 2495 return 0;2496}2497 2498/*2499 * If the VGA_EDID_ENABLE bit is set (Repeater Map 0x7f, bit 7), then2500 * the first two blocks of the EDID are for the HDMI, and the first block2501 * of segment 1 (i.e. the third block of the EDID) is for VGA.2502 * So if a VGA EDID is installed, then the maximum size of the HDMI EDID2503 * is 2 blocks.2504 */2505static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)2506{2507 struct adv7842_state *state = to_state(sd);2508 unsigned int max_blocks = e->pad == ADV7842_EDID_PORT_VGA ? 1 : 4;2509 int err = 0;2510 2511 memset(e->reserved, 0, sizeof(e->reserved));2512 2513 if (e->pad > ADV7842_EDID_PORT_VGA)2514 return -EINVAL;2515 if (e->start_block != 0)2516 return -EINVAL;2517 if (e->pad < ADV7842_EDID_PORT_VGA && state->vga_edid.blocks)2518 max_blocks = 2;2519 if (e->pad == ADV7842_EDID_PORT_VGA && state->hdmi_edid.blocks > 2)2520 return -EBUSY;2521 if (e->blocks > max_blocks) {2522 e->blocks = max_blocks;2523 return -E2BIG;2524 }2525 2526 /* todo, per edid */2527 if (e->blocks)2528 state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],2529 e->edid[0x16]);2530 2531 switch (e->pad) {2532 case ADV7842_EDID_PORT_VGA:2533 memset(state->vga_edid.edid, 0, sizeof(state->vga_edid.edid));2534 state->vga_edid.blocks = e->blocks;2535 state->vga_edid.present = e->blocks ? 0x1 : 0x0;2536 if (e->blocks)2537 memcpy(state->vga_edid.edid, e->edid, 128);2538 err = edid_write_vga_segment(sd);2539 break;2540 case ADV7842_EDID_PORT_A:2541 case ADV7842_EDID_PORT_B:2542 memset(state->hdmi_edid.edid, 0, sizeof(state->hdmi_edid.edid));2543 state->hdmi_edid.blocks = e->blocks;2544 if (e->blocks) {2545 state->hdmi_edid.present |= 0x04 << e->pad;2546 memcpy(state->hdmi_edid.edid, e->edid, 128 * e->blocks);2547 } else {2548 state->hdmi_edid.present &= ~(0x04 << e->pad);2549 adv7842_s_detect_tx_5v_ctrl(sd);2550 }2551 err = edid_write_hdmi_segment(sd, e->pad);2552 break;2553 default:2554 return -EINVAL;2555 }2556 if (err < 0)2557 v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);2558 return err;2559}2560 2561struct adv7842_cfg_read_infoframe {2562 const char *desc;2563 u8 present_mask;2564 u8 head_addr;2565 u8 payload_addr;2566};2567 2568static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_infoframe *cri)2569{2570 int i;2571 u8 buffer[32];2572 union hdmi_infoframe frame;2573 u8 len;2574 struct i2c_client *client = v4l2_get_subdevdata(sd);2575 struct device *dev = &client->dev;2576 2577 if (!(io_read(sd, 0x60) & cri->present_mask)) {2578 v4l2_info(sd, "%s infoframe not received\n", cri->desc);2579 return;2580 }2581 2582 for (i = 0; i < 3; i++)2583 buffer[i] = infoframe_read(sd, cri->head_addr + i);2584 2585 len = buffer[2] + 1;2586 2587 if (len + 3 > sizeof(buffer)) {2588 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);2589 return;2590 }2591 2592 for (i = 0; i < len; i++)2593 buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);2594 2595 if (hdmi_infoframe_unpack(&frame, buffer, len + 3) < 0) {2596 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);2597 return;2598 }2599 2600 hdmi_infoframe_log(KERN_INFO, dev, &frame);2601}2602 2603static void adv7842_log_infoframes(struct v4l2_subdev *sd)2604{2605 int i;2606 static const struct adv7842_cfg_read_infoframe cri[] = {2607 { "AVI", 0x01, 0xe0, 0x00 },2608 { "Audio", 0x02, 0xe3, 0x1c },2609 { "SDP", 0x04, 0xe6, 0x2a },2610 { "Vendor", 0x10, 0xec, 0x54 }2611 };2612 2613 if (!(hdmi_read(sd, 0x05) & 0x80)) {2614 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");2615 return;2616 }2617 2618 for (i = 0; i < ARRAY_SIZE(cri); i++)2619 log_infoframe(sd, &cri[i]);2620}2621 2622#if 02623/* Let's keep it here for now, as it could be useful for debug */2624static const char * const prim_mode_txt[] = {2625 "SDP",2626 "Component",2627 "Graphics",2628 "Reserved",2629 "CVBS & HDMI AUDIO",2630 "HDMI-Comp",2631 "HDMI-GR",2632 "Reserved",2633 "Reserved",2634 "Reserved",2635 "Reserved",2636 "Reserved",2637 "Reserved",2638 "Reserved",2639 "Reserved",2640 "Reserved",2641};2642#endif2643 2644static int adv7842_sdp_log_status(struct v4l2_subdev *sd)2645{2646 /* SDP (Standard definition processor) block */2647 u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;2648 2649 v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");2650 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",2651 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);2652 2653 v4l2_info(sd, "SDP: free run: %s\n",2654 (sdp_read(sd, 0x56) & 0x01) ? "on" : "off");2655 v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?2656 "valid SD/PR signal detected" : "invalid/no signal");2657 if (sdp_signal_detected) {2658 static const char * const sdp_std_txt[] = {2659 "NTSC-M/J",2660 "1?",2661 "NTSC-443",2662 "60HzSECAM",2663 "PAL-M",2664 "5?",2665 "PAL-60",2666 "7?", "8?", "9?", "a?", "b?",2667 "PAL-CombN",2668 "d?",2669 "PAL-BGHID",2670 "SECAM"2671 };2672 v4l2_info(sd, "SDP: standard %s\n",2673 sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);2674 v4l2_info(sd, "SDP: %s\n",2675 (sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");2676 v4l2_info(sd, "SDP: %s\n",2677 (sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");2678 v4l2_info(sd, "SDP: deinterlacer %s\n",2679 (sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");2680 v4l2_info(sd, "SDP: csc %s mode\n",2681 (sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");2682 }2683 return 0;2684}2685 2686static int adv7842_cp_log_status(struct v4l2_subdev *sd)2687{2688 /* CP block */2689 struct adv7842_state *state = to_state(sd);2690 struct v4l2_dv_timings timings;2691 u8 reg_io_0x02 = io_read(sd, 0x02);2692 u8 reg_io_0x21 = io_read(sd, 0x21);2693 u8 reg_rep_0x77 = rep_read(sd, 0x77);2694 u8 reg_rep_0x7d = rep_read(sd, 0x7d);2695 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;2696 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;2697 bool audio_mute = io_read(sd, 0x65) & 0x40;2698 2699 static const char * const csc_coeff_sel_rb[16] = {2700 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",2701 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",2702 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",2703 "reserved", "reserved", "reserved", "reserved", "manual"2704 };2705 static const char * const input_color_space_txt[16] = {2706 "RGB limited range (16-235)", "RGB full range (0-255)",2707 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",2708 "xvYCC Bt.601", "xvYCC Bt.709",2709 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",2710 "invalid", "invalid", "invalid", "invalid", "invalid",2711 "invalid", "invalid", "automatic"2712 };2713 static const char * const rgb_quantization_range_txt[] = {2714 "Automatic",2715 "RGB limited range (16-235)",2716 "RGB full range (0-255)",2717 };2718 static const char * const deep_color_mode_txt[4] = {2719 "8-bits per channel",2720 "10-bits per channel",2721 "12-bits per channel",2722 "16-bits per channel (not supported)"2723 };2724 2725 v4l2_info(sd, "-----Chip status-----\n");2726 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");2727 v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",2728 state->hdmi_port_a ? "A" : "B");2729 v4l2_info(sd, "EDID A %s, B %s\n",2730 ((reg_rep_0x7d & 0x04) && (reg_rep_0x77 & 0x04)) ?2731 "enabled" : "disabled",2732 ((reg_rep_0x7d & 0x08) && (reg_rep_0x77 & 0x08)) ?2733 "enabled" : "disabled");2734 v4l2_info(sd, "HPD A %s, B %s\n",2735 reg_io_0x21 & 0x02 ? "enabled" : "disabled",2736 reg_io_0x21 & 0x01 ? "enabled" : "disabled");2737 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?2738 "enabled" : "disabled");2739 if (state->cec_enabled_adap) {2740 int i;2741 2742 for (i = 0; i < ADV7842_MAX_ADDRS; i++) {2743 bool is_valid = state->cec_valid_addrs & (1 << i);2744 2745 if (is_valid)2746 v4l2_info(sd, "CEC Logical Address: 0x%x\n",2747 state->cec_addr[i]);2748 }2749 }2750 2751 v4l2_info(sd, "-----Signal status-----\n");2752 if (state->hdmi_port_a) {2753 v4l2_info(sd, "Cable detected (+5V power): %s\n",2754 io_read(sd, 0x6f) & 0x02 ? "true" : "false");2755 v4l2_info(sd, "TMDS signal detected: %s\n",2756 (io_read(sd, 0x6a) & 0x02) ? "true" : "false");2757 v4l2_info(sd, "TMDS signal locked: %s\n",2758 (io_read(sd, 0x6a) & 0x20) ? "true" : "false");2759 } else {2760 v4l2_info(sd, "Cable detected (+5V power):%s\n",2761 io_read(sd, 0x6f) & 0x01 ? "true" : "false");2762 v4l2_info(sd, "TMDS signal detected: %s\n",2763 (io_read(sd, 0x6a) & 0x01) ? "true" : "false");2764 v4l2_info(sd, "TMDS signal locked: %s\n",2765 (io_read(sd, 0x6a) & 0x10) ? "true" : "false");2766 }2767 v4l2_info(sd, "CP free run: %s\n",2768 (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));2769 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",2770 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,2771 (io_read(sd, 0x01) & 0x70) >> 4);2772 2773 v4l2_info(sd, "-----Video Timings-----\n");2774 if (no_cp_signal(sd)) {2775 v4l2_info(sd, "STDI: not locked\n");2776 } else {2777 u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);2778 u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);2779 u32 lcvs = cp_read(sd, 0xb3) >> 3;2780 u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);2781 char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?2782 ((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');2783 char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?2784 ((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');2785 v4l2_info(sd,2786 "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",2787 lcf, bl, lcvs, fcl,2788 (cp_read(sd, 0xb1) & 0x40) ?2789 "interlaced" : "progressive",2790 hs_pol, vs_pol);2791 }2792 if (adv7842_query_dv_timings(sd, 0, &timings))2793 v4l2_info(sd, "No video detected\n");2794 else2795 v4l2_print_dv_timings(sd->name, "Detected format: ",2796 &timings, true);2797 v4l2_print_dv_timings(sd->name, "Configured format: ",2798 &state->timings, true);2799 2800 if (no_cp_signal(sd))2801 return 0;2802 2803 v4l2_info(sd, "-----Color space-----\n");2804 v4l2_info(sd, "RGB quantization range ctrl: %s\n",2805 rgb_quantization_range_txt[state->rgb_quantization_range]);2806 v4l2_info(sd, "Input color space: %s\n",2807 input_color_space_txt[reg_io_0x02 >> 4]);2808 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",2809 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",2810 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?2811 "(16-235)" : "(0-255)",2812 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");2813 v4l2_info(sd, "Color space conversion: %s\n",2814 csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);2815 2816 if (!is_digital_input(sd))2817 return 0;2818 2819 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");2820 v4l2_info(sd, "HDCP encrypted content: %s\n",2821 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");2822 v4l2_info(sd, "HDCP keys read: %s%s\n",2823 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",2824 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");2825 if (!is_hdmi(sd))2826 return 0;2827 2828 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",2829 audio_pll_locked ? "locked" : "not locked",2830 audio_sample_packet_detect ? "detected" : "not detected",2831 audio_mute ? "muted" : "enabled");2832 if (audio_pll_locked && audio_sample_packet_detect) {2833 v4l2_info(sd, "Audio format: %s\n",2834 (hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");2835 }2836 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +2837 (hdmi_read(sd, 0x5c) << 8) +2838 (hdmi_read(sd, 0x5d) & 0xf0));2839 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +2840 (hdmi_read(sd, 0x5e) << 8) +2841 hdmi_read(sd, 0x5f));2842 v4l2_info(sd, "AV Mute: %s\n",2843 (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");2844 v4l2_info(sd, "Deep color mode: %s\n",2845 deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);2846 2847 adv7842_log_infoframes(sd);2848 2849 return 0;2850}2851 2852static int adv7842_log_status(struct v4l2_subdev *sd)2853{2854 struct adv7842_state *state = to_state(sd);2855 2856 if (state->mode == ADV7842_MODE_SDP)2857 return adv7842_sdp_log_status(sd);2858 return adv7842_cp_log_status(sd);2859}2860 2861static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)2862{2863 struct adv7842_state *state = to_state(sd);2864 2865 v4l2_dbg(1, debug, sd, "%s:\n", __func__);2866 2867 if (state->mode != ADV7842_MODE_SDP)2868 return -ENODATA;2869 2870 if (!(sdp_read(sd, 0x5A) & 0x01)) {2871 *std = 0;2872 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);2873 return 0;2874 }2875 2876 switch (sdp_read(sd, 0x52) & 0x0f) {2877 case 0:2878 /* NTSC-M/J */2879 *std &= V4L2_STD_NTSC;2880 break;2881 case 2:2882 /* NTSC-443 */2883 *std &= V4L2_STD_NTSC_443;2884 break;2885 case 3:2886 /* 60HzSECAM */2887 *std &= V4L2_STD_SECAM;2888 break;2889 case 4:2890 /* PAL-M */2891 *std &= V4L2_STD_PAL_M;2892 break;2893 case 6:2894 /* PAL-60 */2895 *std &= V4L2_STD_PAL_60;2896 break;2897 case 0xc:2898 /* PAL-CombN */2899 *std &= V4L2_STD_PAL_Nc;2900 break;2901 case 0xe:2902 /* PAL-BGHID */2903 *std &= V4L2_STD_PAL;2904 break;2905 case 0xf:2906 /* SECAM */2907 *std &= V4L2_STD_SECAM;2908 break;2909 default:2910 *std &= V4L2_STD_ALL;2911 break;2912 }2913 return 0;2914}2915 2916static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)2917{2918 if (s && s->adjust) {2919 sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);2920 sdp_io_write(sd, 0x95, s->hs_beg & 0xff);2921 sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);2922 sdp_io_write(sd, 0x97, s->hs_width & 0xff);2923 sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);2924 sdp_io_write(sd, 0x99, s->de_beg & 0xff);2925 sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);2926 sdp_io_write(sd, 0x9b, s->de_end & 0xff);2927 sdp_io_write(sd, 0xa8, s->vs_beg_o);2928 sdp_io_write(sd, 0xa9, s->vs_beg_e);2929 sdp_io_write(sd, 0xaa, s->vs_end_o);2930 sdp_io_write(sd, 0xab, s->vs_end_e);2931 sdp_io_write(sd, 0xac, s->de_v_beg_o);2932 sdp_io_write(sd, 0xad, s->de_v_beg_e);2933 sdp_io_write(sd, 0xae, s->de_v_end_o);2934 sdp_io_write(sd, 0xaf, s->de_v_end_e);2935 } else {2936 /* set to default */2937 sdp_io_write(sd, 0x94, 0x00);2938 sdp_io_write(sd, 0x95, 0x00);2939 sdp_io_write(sd, 0x96, 0x00);2940 sdp_io_write(sd, 0x97, 0x20);2941 sdp_io_write(sd, 0x98, 0x00);2942 sdp_io_write(sd, 0x99, 0x00);2943 sdp_io_write(sd, 0x9a, 0x00);2944 sdp_io_write(sd, 0x9b, 0x00);2945 sdp_io_write(sd, 0xa8, 0x04);2946 sdp_io_write(sd, 0xa9, 0x04);2947 sdp_io_write(sd, 0xaa, 0x04);2948 sdp_io_write(sd, 0xab, 0x04);2949 sdp_io_write(sd, 0xac, 0x04);2950 sdp_io_write(sd, 0xad, 0x04);2951 sdp_io_write(sd, 0xae, 0x04);2952 sdp_io_write(sd, 0xaf, 0x04);2953 }2954}2955 2956static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)2957{2958 struct adv7842_state *state = to_state(sd);2959 struct adv7842_platform_data *pdata = &state->pdata;2960 2961 v4l2_dbg(1, debug, sd, "%s:\n", __func__);2962 2963 if (state->mode != ADV7842_MODE_SDP)2964 return -ENODATA;2965 2966 if (norm & V4L2_STD_625_50)2967 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);2968 else if (norm & V4L2_STD_525_60)2969 adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);2970 else2971 adv7842_s_sdp_io(sd, NULL);2972 2973 if (norm & V4L2_STD_ALL) {2974 state->norm = norm;2975 return 0;2976 }2977 return -EINVAL;2978}2979 2980static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)2981{2982 struct adv7842_state *state = to_state(sd);2983 2984 v4l2_dbg(1, debug, sd, "%s:\n", __func__);2985 2986 if (state->mode != ADV7842_MODE_SDP)2987 return -ENODATA;2988 2989 *norm = state->norm;2990 return 0;2991}2992 2993/* ----------------------------------------------------------------------- */2994 2995static int adv7842_core_init(struct v4l2_subdev *sd)2996{2997 struct adv7842_state *state = to_state(sd);2998 struct adv7842_platform_data *pdata = &state->pdata;2999 hdmi_write(sd, 0x48,3000 (pdata->disable_pwrdnb ? 0x80 : 0) |3001 (pdata->disable_cable_det_rst ? 0x40 : 0));3002 3003 disable_input(sd);3004 3005 /*3006 * Disable I2C access to internal EDID ram from HDMI DDC ports3007 * Disable auto edid enable when leaving powerdown mode3008 */3009 rep_write_and_or(sd, 0x77, 0xd3, 0x20);3010 3011 /* power */3012 io_write(sd, 0x0c, 0x42); /* Power up part and power down VDP */3013 io_write(sd, 0x15, 0x80); /* Power up pads */3014 3015 /* video format */3016 io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);3017 io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |3018 pdata->insert_av_codes << 2 |3019 pdata->replicate_av_codes << 1);3020 adv7842_setup_format(state);3021 3022 /* HDMI audio */3023 hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */3024 3025 /* Drive strength */3026 io_write_and_or(sd, 0x14, 0xc0,3027 pdata->dr_str_data << 4 |3028 pdata->dr_str_clk << 2 |3029 pdata->dr_str_sync);3030 3031 /* HDMI free run */3032 cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |3033 (pdata->hdmi_free_run_mode << 1));3034 3035 /* SPD free run */3036 sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |3037 (pdata->sdp_free_run_cbar_en << 1) |3038 (pdata->sdp_free_run_man_col_en << 2) |3039 (pdata->sdp_free_run_auto << 3));3040 3041 /* TODO from platform data */3042 cp_write(sd, 0x69, 0x14); /* Enable CP CSC */3043 io_write(sd, 0x06, 0xa6); /* positive VS and HS and DE */3044 cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */3045 afe_write(sd, 0xb5, 0x01); /* Setting MCLK to 256Fs */3046 3047 afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */3048 io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);3049 3050 sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);3051 3052 /* todo, improve settings for sdram */3053 if (pdata->sd_ram_size >= 128) {3054 sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */3055 if (pdata->sd_ram_ddr) {3056 /* SDP setup for the AD eval board */3057 sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */3058 sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */3059 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */3060 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */3061 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */3062 } else {3063 sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/3064 sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */3065 sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,3066 depends on memory */3067 sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */3068 sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */3069 sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */3070 sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */3071 }3072 } else {3073 /*3074 * Manual UG-214, rev 0 is bit confusing on this bit3075 * but a '1' disables any signal if the Ram is active.3076 */3077 sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */3078 }3079 3080 select_input(sd, pdata->vid_std_select);3081 3082 enable_input(sd);3083 3084 if (pdata->hpa_auto) {3085 /* HPA auto, HPA 0.5s after Edid set and Cable detect */3086 hdmi_write(sd, 0x69, 0x5c);3087 } else {3088 /* HPA manual */3089 hdmi_write(sd, 0x69, 0xa3);3090 /* HPA disable on port A and B */3091 io_write_and_or(sd, 0x20, 0xcf, 0x00);3092 }3093 3094 /* LLC */3095 io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);3096 io_write(sd, 0x33, 0x40);3097 3098 /* interrupts */3099 io_write(sd, 0x40, 0xf2); /* Configure INT1 */3100 3101 adv7842_irq_enable(sd, true);3102 3103 return v4l2_ctrl_handler_setup(sd->ctrl_handler);3104}3105 3106/* ----------------------------------------------------------------------- */3107 3108static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)3109{3110 /*3111 * From ADV784x external Memory test.pdf3112 *3113 * Reset must just been performed before running test.3114 * Recommended to reset after test.3115 */3116 int i;3117 int pass = 0;3118 int fail = 0;3119 int complete = 0;3120 3121 io_write(sd, 0x00, 0x01); /* Program SDP 4x1 */3122 io_write(sd, 0x01, 0x00); /* Program SDP mode */3123 afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */3124 afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */3125 afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */3126 afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */3127 afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */3128 afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */3129 io_write(sd, 0x0C, 0x40); /* Power up ADV7844 */3130 io_write(sd, 0x15, 0xBA); /* Enable outputs */3131 sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */3132 io_write(sd, 0xFF, 0x04); /* Reset memory controller */3133 3134 usleep_range(5000, 6000);3135 3136 sdp_write(sd, 0x12, 0x00); /* Disable 3D Comb, Frame TBC & 3DNR */3137 sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */3138 sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */3139 sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */3140 sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */3141 sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */3142 sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */3143 sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */3144 sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */3145 sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */3146 sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */3147 3148 usleep_range(5000, 6000);3149 3150 sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */3151 sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */3152 3153 msleep(20);3154 3155 for (i = 0; i < 10; i++) {3156 u8 result = sdp_io_read(sd, 0xdb);3157 if (result & 0x10) {3158 complete++;3159 if (result & 0x20)3160 fail++;3161 else3162 pass++;3163 }3164 msleep(20);3165 }3166 3167 v4l2_dbg(1, debug, sd,3168 "Ram Test: completed %d of %d: pass %d, fail %d\n",3169 complete, i, pass, fail);3170 3171 if (!complete || fail)3172 return -EIO;3173 return 0;3174}3175 3176static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,3177 struct adv7842_platform_data *pdata)3178{3179 io_write(sd, 0xf1, pdata->i2c_sdp << 1);3180 io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);3181 io_write(sd, 0xf3, pdata->i2c_avlink << 1);3182 io_write(sd, 0xf4, pdata->i2c_cec << 1);3183 io_write(sd, 0xf5, pdata->i2c_infoframe << 1);3184 3185 io_write(sd, 0xf8, pdata->i2c_afe << 1);3186 io_write(sd, 0xf9, pdata->i2c_repeater << 1);3187 io_write(sd, 0xfa, pdata->i2c_edid << 1);3188 io_write(sd, 0xfb, pdata->i2c_hdmi << 1);3189 3190 io_write(sd, 0xfd, pdata->i2c_cp << 1);3191 io_write(sd, 0xfe, pdata->i2c_vdp << 1);3192}3193 3194static int adv7842_command_ram_test(struct v4l2_subdev *sd)3195{3196 struct i2c_client *client = v4l2_get_subdevdata(sd);3197 struct adv7842_state *state = to_state(sd);3198 struct adv7842_platform_data *pdata = client->dev.platform_data;3199 struct v4l2_dv_timings timings;3200 int ret = 0;3201 3202 if (!pdata)3203 return -ENODEV;3204 3205 if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {3206 v4l2_info(sd, "no sdram or no ddr sdram\n");3207 return -EINVAL;3208 }3209 3210 main_reset(sd);3211 3212 adv7842_rewrite_i2c_addresses(sd, pdata);3213 3214 /* run ram test */3215 ret = adv7842_ddr_ram_test(sd);3216 3217 main_reset(sd);3218 3219 adv7842_rewrite_i2c_addresses(sd, pdata);3220 3221 /* and re-init chip and state */3222 adv7842_core_init(sd);3223 3224 disable_input(sd);3225 3226 select_input(sd, state->vid_std_select);3227 3228 enable_input(sd);3229 3230 edid_write_vga_segment(sd);3231 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);3232 edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);3233 3234 timings = state->timings;3235 3236 memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));3237 3238 adv7842_s_dv_timings(sd, 0, &timings);3239 3240 return ret;3241}3242 3243static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)3244{3245 switch (cmd) {3246 case ADV7842_CMD_RAM_TEST:3247 return adv7842_command_ram_test(sd);3248 }3249 return -ENOTTY;3250}3251 3252static int adv7842_subscribe_event(struct v4l2_subdev *sd,3253 struct v4l2_fh *fh,3254 struct v4l2_event_subscription *sub)3255{3256 switch (sub->type) {3257 case V4L2_EVENT_SOURCE_CHANGE:3258 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);3259 case V4L2_EVENT_CTRL:3260 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);3261 default:3262 return -EINVAL;3263 }3264}3265 3266static int adv7842_registered(struct v4l2_subdev *sd)3267{3268 struct adv7842_state *state = to_state(sd);3269 struct i2c_client *client = v4l2_get_subdevdata(sd);3270 int err;3271 3272 err = cec_register_adapter(state->cec_adap, &client->dev);3273 if (err)3274 cec_delete_adapter(state->cec_adap);3275 return err;3276}3277 3278static void adv7842_unregistered(struct v4l2_subdev *sd)3279{3280 struct adv7842_state *state = to_state(sd);3281 3282 cec_unregister_adapter(state->cec_adap);3283}3284 3285/* ----------------------------------------------------------------------- */3286 3287static const struct v4l2_ctrl_ops adv7842_ctrl_ops = {3288 .s_ctrl = adv7842_s_ctrl,3289 .g_volatile_ctrl = adv7842_g_volatile_ctrl,3290};3291 3292static const struct v4l2_subdev_core_ops adv7842_core_ops = {3293 .log_status = adv7842_log_status,3294 .ioctl = adv7842_ioctl,3295 .interrupt_service_routine = adv7842_isr,3296 .subscribe_event = adv7842_subscribe_event,3297 .unsubscribe_event = v4l2_event_subdev_unsubscribe,3298#ifdef CONFIG_VIDEO_ADV_DEBUG3299 .g_register = adv7842_g_register,3300 .s_register = adv7842_s_register,3301#endif3302};3303 3304static const struct v4l2_subdev_video_ops adv7842_video_ops = {3305 .g_std = adv7842_g_std,3306 .s_std = adv7842_s_std,3307 .s_routing = adv7842_s_routing,3308 .querystd = adv7842_querystd,3309 .g_input_status = adv7842_g_input_status,3310};3311 3312static const struct v4l2_subdev_pad_ops adv7842_pad_ops = {3313 .enum_mbus_code = adv7842_enum_mbus_code,3314 .get_fmt = adv7842_get_format,3315 .set_fmt = adv7842_set_format,3316 .get_edid = adv7842_get_edid,3317 .set_edid = adv7842_set_edid,3318 .s_dv_timings = adv7842_s_dv_timings,3319 .g_dv_timings = adv7842_g_dv_timings,3320 .query_dv_timings = adv7842_query_dv_timings,3321 .enum_dv_timings = adv7842_enum_dv_timings,3322 .dv_timings_cap = adv7842_dv_timings_cap,3323};3324 3325static const struct v4l2_subdev_ops adv7842_ops = {3326 .core = &adv7842_core_ops,3327 .video = &adv7842_video_ops,3328 .pad = &adv7842_pad_ops,3329};3330 3331static const struct v4l2_subdev_internal_ops adv7842_int_ops = {3332 .registered = adv7842_registered,3333 .unregistered = adv7842_unregistered,3334};3335 3336/* -------------------------- custom ctrls ---------------------------------- */3337 3338static const struct v4l2_ctrl_config adv7842_ctrl_analog_sampling_phase = {3339 .ops = &adv7842_ctrl_ops,3340 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,3341 .name = "Analog Sampling Phase",3342 .type = V4L2_CTRL_TYPE_INTEGER,3343 .min = 0,3344 .max = 0x1f,3345 .step = 1,3346 .def = 0,3347};3348 3349static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color_manual = {3350 .ops = &adv7842_ctrl_ops,3351 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,3352 .name = "Free Running Color, Manual",3353 .type = V4L2_CTRL_TYPE_BOOLEAN,3354 .max = 1,3355 .step = 1,3356 .def = 1,3357};3358 3359static const struct v4l2_ctrl_config adv7842_ctrl_free_run_color = {3360 .ops = &adv7842_ctrl_ops,3361 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,3362 .name = "Free Running Color",3363 .type = V4L2_CTRL_TYPE_INTEGER,3364 .max = 0xffffff,3365 .step = 0x1,3366};3367 3368 3369static void adv7842_unregister_clients(struct v4l2_subdev *sd)3370{3371 struct adv7842_state *state = to_state(sd);3372 i2c_unregister_device(state->i2c_avlink);3373 i2c_unregister_device(state->i2c_cec);3374 i2c_unregister_device(state->i2c_infoframe);3375 i2c_unregister_device(state->i2c_sdp_io);3376 i2c_unregister_device(state->i2c_sdp);3377 i2c_unregister_device(state->i2c_afe);3378 i2c_unregister_device(state->i2c_repeater);3379 i2c_unregister_device(state->i2c_edid);3380 i2c_unregister_device(state->i2c_hdmi);3381 i2c_unregister_device(state->i2c_cp);3382 i2c_unregister_device(state->i2c_vdp);3383 3384 state->i2c_avlink = NULL;3385 state->i2c_cec = NULL;3386 state->i2c_infoframe = NULL;3387 state->i2c_sdp_io = NULL;3388 state->i2c_sdp = NULL;3389 state->i2c_afe = NULL;3390 state->i2c_repeater = NULL;3391 state->i2c_edid = NULL;3392 state->i2c_hdmi = NULL;3393 state->i2c_cp = NULL;3394 state->i2c_vdp = NULL;3395}3396 3397static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,3398 u8 addr, u8 io_reg)3399{3400 struct i2c_client *client = v4l2_get_subdevdata(sd);3401 struct i2c_client *cp;3402 3403 io_write(sd, io_reg, addr << 1);3404 3405 if (addr == 0) {3406 v4l2_err(sd, "no %s i2c addr configured\n", desc);3407 return NULL;3408 }3409 3410 cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1);3411 if (IS_ERR(cp)) {3412 v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n",3413 desc, addr, PTR_ERR(cp));3414 cp = NULL;3415 }3416 3417 return cp;3418}3419 3420static int adv7842_register_clients(struct v4l2_subdev *sd)3421{3422 struct adv7842_state *state = to_state(sd);3423 struct adv7842_platform_data *pdata = &state->pdata;3424 3425 state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);3426 state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);3427 state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);3428 state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);3429 state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);3430 state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);3431 state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);3432 state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);3433 state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);3434 state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);3435 state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);3436 3437 if (!state->i2c_avlink ||3438 !state->i2c_cec ||3439 !state->i2c_infoframe ||3440 !state->i2c_sdp_io ||3441 !state->i2c_sdp ||3442 !state->i2c_afe ||3443 !state->i2c_repeater ||3444 !state->i2c_edid ||3445 !state->i2c_hdmi ||3446 !state->i2c_cp ||3447 !state->i2c_vdp)3448 return -1;3449 3450 return 0;3451}3452 3453static int adv7842_probe(struct i2c_client *client)3454{3455 struct adv7842_state *state;3456 static const struct v4l2_dv_timings cea640x480 =3457 V4L2_DV_BT_CEA_640X480P59_94;3458 struct adv7842_platform_data *pdata = client->dev.platform_data;3459 struct v4l2_ctrl_handler *hdl;3460 struct v4l2_ctrl *ctrl;3461 struct v4l2_subdev *sd;3462 unsigned int i;3463 u16 rev;3464 int err;3465 3466 /* Check if the adapter supports the needed features */3467 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))3468 return -EIO;3469 3470 v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",3471 client->addr << 1);3472 3473 if (!pdata) {3474 v4l_err(client, "No platform data!\n");3475 return -ENODEV;3476 }3477 3478 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);3479 if (!state)3480 return -ENOMEM;3481 3482 /* platform data */3483 state->pdata = *pdata;3484 state->timings = cea640x480;3485 state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);3486 3487 sd = &state->sd;3488 v4l2_i2c_subdev_init(sd, client, &adv7842_ops);3489 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;3490 sd->internal_ops = &adv7842_int_ops;3491 state->mode = pdata->mode;3492 3493 state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;3494 state->restart_stdi_once = true;3495 3496 /* i2c access to adv7842? */3497 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |3498 adv_smbus_read_byte_data_check(client, 0xeb, false);3499 if (rev != 0x2012) {3500 v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);3501 rev = adv_smbus_read_byte_data_check(client, 0xea, false) << 8 |3502 adv_smbus_read_byte_data_check(client, 0xeb, false);3503 }3504 if (rev != 0x2012) {3505 v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",3506 client->addr << 1, rev);3507 return -ENODEV;3508 }3509 3510 if (pdata->chip_reset)3511 main_reset(sd);3512 3513 /* control handlers */3514 hdl = &state->hdl;3515 v4l2_ctrl_handler_init(hdl, 6);3516 3517 /* add in ascending ID order */3518 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,3519 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);3520 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,3521 V4L2_CID_CONTRAST, 0, 255, 1, 128);3522 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,3523 V4L2_CID_SATURATION, 0, 255, 1, 128);3524 v4l2_ctrl_new_std(hdl, &adv7842_ctrl_ops,3525 V4L2_CID_HUE, 0, 128, 1, 0);3526 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,3527 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,3528 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);3529 if (ctrl)3530 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;3531 3532 /* custom controls */3533 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,3534 V4L2_CID_DV_RX_POWER_PRESENT, 0, 3, 0, 0);3535 state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,3536 &adv7842_ctrl_analog_sampling_phase, NULL);3537 state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,3538 &adv7842_ctrl_free_run_color_manual, NULL);3539 state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,3540 &adv7842_ctrl_free_run_color, NULL);3541 state->rgb_quantization_range_ctrl =3542 v4l2_ctrl_new_std_menu(hdl, &adv7842_ctrl_ops,3543 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,3544 0, V4L2_DV_RGB_RANGE_AUTO);3545 sd->ctrl_handler = hdl;3546 if (hdl->error) {3547 err = hdl->error;3548 goto err_hdl;3549 }3550 if (adv7842_s_detect_tx_5v_ctrl(sd)) {3551 err = -ENODEV;3552 goto err_hdl;3553 }3554 3555 if (adv7842_register_clients(sd) < 0) {3556 err = -ENOMEM;3557 v4l2_err(sd, "failed to create all i2c clients\n");3558 goto err_i2c;3559 }3560 3561 3562 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,3563 adv7842_delayed_work_enable_hotplug);3564 3565 sd->entity.function = MEDIA_ENT_F_DV_DECODER;3566 for (i = 0; i < ADV7842_PAD_SOURCE; ++i)3567 state->pads[i].flags = MEDIA_PAD_FL_SINK;3568 state->pads[ADV7842_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;3569 err = media_entity_pads_init(&sd->entity, ADV7842_PAD_SOURCE + 1,3570 state->pads);3571 if (err)3572 goto err_work_queues;3573 3574 err = adv7842_core_init(sd);3575 if (err)3576 goto err_entity;3577 3578#if IS_ENABLED(CONFIG_VIDEO_ADV7842_CEC)3579 state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops,3580 state, dev_name(&client->dev),3581 CEC_CAP_DEFAULTS, ADV7842_MAX_ADDRS);3582 err = PTR_ERR_OR_ZERO(state->cec_adap);3583 if (err)3584 goto err_entity;3585#endif3586 3587 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,3588 client->addr << 1, client->adapter->name);3589 return 0;3590 3591err_entity:3592 media_entity_cleanup(&sd->entity);3593err_work_queues:3594 cancel_delayed_work(&state->delayed_work_enable_hotplug);3595err_i2c:3596 adv7842_unregister_clients(sd);3597err_hdl:3598 v4l2_ctrl_handler_free(hdl);3599 return err;3600}3601 3602/* ----------------------------------------------------------------------- */3603 3604static void adv7842_remove(struct i2c_client *client)3605{3606 struct v4l2_subdev *sd = i2c_get_clientdata(client);3607 struct adv7842_state *state = to_state(sd);3608 3609 adv7842_irq_enable(sd, false);3610 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);3611 v4l2_device_unregister_subdev(sd);3612 media_entity_cleanup(&sd->entity);3613 adv7842_unregister_clients(sd);3614 v4l2_ctrl_handler_free(sd->ctrl_handler);3615}3616 3617/* ----------------------------------------------------------------------- */3618 3619static const struct i2c_device_id adv7842_id[] = {3620 { "adv7842" },3621 { }3622};3623MODULE_DEVICE_TABLE(i2c, adv7842_id);3624 3625/* ----------------------------------------------------------------------- */3626 3627static struct i2c_driver adv7842_driver = {3628 .driver = {3629 .name = "adv7842",3630 },3631 .probe = adv7842_probe,3632 .remove = adv7842_remove,3633 .id_table = adv7842_id,3634};3635 3636module_i2c_driver(adv7842_driver);3637