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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * drivers/media/i2c/ccs-pll.h4 *5 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator6 *7 * Copyright (C) 2020 Intel Corporation8 * Copyright (C) 2012 Nokia Corporation9 * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>10 */11 12#ifndef CCS_PLL_H13#define CCS_PLL_H14 15#include <linux/bits.h>16 17/* CSI-2 or CCP-2 */18#define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x0019#define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x0120 21/* Old SMIA and implementation specific flags */22/* op pix clock is for all lanes in total normally */23#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0)24#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1)25/* CCS PLL flags */26#define CCS_PLL_FLAG_LANE_SPEED_MODEL BIT(2)27#define CCS_PLL_FLAG_LINK_DECOUPLED BIT(3)28#define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER BIT(4)29#define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV BIT(5)30#define CCS_PLL_FLAG_FIFO_DERATING BIT(6)31#define CCS_PLL_FLAG_FIFO_OVERRATING BIT(7)32#define CCS_PLL_FLAG_DUAL_PLL BIT(8)33#define CCS_PLL_FLAG_OP_SYS_DDR BIT(9)34#define CCS_PLL_FLAG_OP_PIX_DDR BIT(10)35 36/**37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)38 *39 * A single branch front-end of the CCS PLL tree.40 *41 * @pre_pll_clk_div: Pre-PLL clock divisor42 * @pll_multiplier: PLL multiplier43 * @pll_ip_clk_freq_hz: PLL input clock frequency44 * @pll_op_clk_freq_hz: PLL output clock frequency45 */46struct ccs_pll_branch_fr {47 u16 pre_pll_clk_div;48 u16 pll_multiplier;49 u32 pll_ip_clk_freq_hz;50 u32 pll_op_clk_freq_hz;51};52 53/**54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)55 *56 * A single branch back-end of the CCS PLL tree.57 *58 * @sys_clk_div: System clock divider59 * @pix_clk_div: Pixel clock divider60 * @sys_clk_freq_hz: System clock frequency61 * @pix_clk_freq_hz: Pixel clock frequency62 */63struct ccs_pll_branch_bk {64 u16 sys_clk_div;65 u16 pix_clk_div;66 u32 sys_clk_freq_hz;67 u32 pix_clk_freq_hz;68};69 70/**71 * struct ccs_pll - Full CCS PLL configuration72 *73 * All information required to calculate CCS PLL configuration.74 *75 * @bus_type: Type of the data bus, CCS_PLL_BUS_TYPE_* (input)76 * @op_lanes: Number of operational lanes (input)77 * @vt_lanes: Number of video timing lanes (input)78 * @csi2: CSI-2 related parameters79 * @csi2.lanes: The number of the CSI-2 data lanes (input)80 * @binning_vertical: Vertical binning factor (input)81 * @binning_horizontal: Horizontal binning factor (input)82 * @scale_m: Downscaling factor, M component, [16, max] (input)83 * @scale_n: Downscaling factor, N component, typically 16 (input)84 * @bits_per_pixel: Bits per pixel on the output data bus (input)85 * @op_bits_per_lane: Number of bits per OP lane (input)86 * @flags: CCS_PLL_FLAG_* (input)87 * @link_freq: Chosen link frequency (input)88 * @ext_clk_freq_hz: External clock frequency, i.e. the sensor's input clock89 * (input)90 * @vt_fr: Video timing front-end configuration (output)91 * @vt_bk: Video timing back-end configuration (output)92 * @op_fr: Operational timing front-end configuration (output)93 * @op_bk: Operational timing back-end configuration (output)94 * @pixel_rate_csi: Pixel rate on the output data bus (output)95 * @pixel_rate_pixel_array: Nominal pixel rate in the sensor's pixel array96 * (output)97 */98struct ccs_pll {99 /* input values */100 u8 bus_type;101 u8 op_lanes;102 u8 vt_lanes;103 struct {104 u8 lanes;105 } csi2;106 u8 binning_horizontal;107 u8 binning_vertical;108 u8 scale_m;109 u8 scale_n;110 u8 bits_per_pixel;111 u8 op_bits_per_lane;112 u16 flags;113 u32 link_freq;114 u32 ext_clk_freq_hz;115 116 /* output values */117 struct ccs_pll_branch_fr vt_fr;118 struct ccs_pll_branch_bk vt_bk;119 struct ccs_pll_branch_fr op_fr;120 struct ccs_pll_branch_bk op_bk;121 122 u32 pixel_rate_csi;123 u32 pixel_rate_pixel_array;124};125 126/**127 * struct ccs_pll_branch_limits_fr - CCS PLL front-end limits128 *129 * @min_pre_pll_clk_div: Minimum pre-PLL clock divider130 * @max_pre_pll_clk_div: Maximum pre-PLL clock divider131 * @min_pll_ip_clk_freq_hz: Minimum PLL input clock frequency132 * @max_pll_ip_clk_freq_hz: Maximum PLL input clock frequency133 * @min_pll_multiplier: Minimum PLL multiplier134 * @max_pll_multiplier: Maximum PLL multiplier135 * @min_pll_op_clk_freq_hz: Minimum PLL output clock frequency136 * @max_pll_op_clk_freq_hz: Maximum PLL output clock frequency137 */138struct ccs_pll_branch_limits_fr {139 u16 min_pre_pll_clk_div;140 u16 max_pre_pll_clk_div;141 u32 min_pll_ip_clk_freq_hz;142 u32 max_pll_ip_clk_freq_hz;143 u16 min_pll_multiplier;144 u16 max_pll_multiplier;145 u32 min_pll_op_clk_freq_hz;146 u32 max_pll_op_clk_freq_hz;147};148 149/**150 * struct ccs_pll_branch_limits_bk - CCS PLL back-end limits151 *152 * @min_sys_clk_div: Minimum system clock divider153 * @max_sys_clk_div: Maximum system clock divider154 * @min_sys_clk_freq_hz: Minimum system clock frequency155 * @max_sys_clk_freq_hz: Maximum system clock frequency156 * @min_pix_clk_div: Minimum pixel clock divider157 * @max_pix_clk_div: Maximum pixel clock divider158 * @min_pix_clk_freq_hz: Minimum pixel clock frequency159 * @max_pix_clk_freq_hz: Maximum pixel clock frequency160 */161struct ccs_pll_branch_limits_bk {162 u16 min_sys_clk_div;163 u16 max_sys_clk_div;164 u32 min_sys_clk_freq_hz;165 u32 max_sys_clk_freq_hz;166 u16 min_pix_clk_div;167 u16 max_pix_clk_div;168 u32 min_pix_clk_freq_hz;169 u32 max_pix_clk_freq_hz;170};171 172/**173 * struct ccs_pll_limits - CCS PLL limits174 *175 * @min_ext_clk_freq_hz: Minimum external clock frequency176 * @max_ext_clk_freq_hz: Maximum external clock frequency177 * @vt_fr: Video timing front-end limits178 * @vt_bk: Video timing back-end limits179 * @op_fr: Operational timing front-end limits180 * @op_bk: Operational timing back-end limits181 * @min_line_length_pck_bin: Minimum line length in pixels, with binning182 * @min_line_length_pck: Minimum line length in pixels without binning183 */184struct ccs_pll_limits {185 /* Strict PLL limits */186 u32 min_ext_clk_freq_hz;187 u32 max_ext_clk_freq_hz;188 189 struct ccs_pll_branch_limits_fr vt_fr;190 struct ccs_pll_branch_limits_bk vt_bk;191 struct ccs_pll_branch_limits_fr op_fr;192 struct ccs_pll_branch_limits_bk op_bk;193 194 /* Other relevant limits */195 u32 min_line_length_pck_bin;196 u32 min_line_length_pck;197};198 199struct device;200 201/**202 * ccs_pll_calculate - Calculate CCS PLL configuration based on input parameters203 *204 * @dev: Device pointer, used for printing messages205 * @limits: Limits specific to the sensor206 * @pll: Given PLL configuration207 *208 * Calculate the CCS PLL configuration based on the limits as well as given209 * device specific, system specific or user configured input data.210 */211int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *limits,212 struct ccs_pll *pll);213 214#endif /* CCS_PLL_H */215