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1// SPDX-License-Identifier: GPL-2.02/*3 * V4L2 Support for the IMX2834 *5 * Diagonal 15.86 mm (Type 1) CMOS Image Sensor with Square Pixel for Color6 * Cameras.7 *8 * Copyright (C) 2024 Ideas on Board Oy.9 *10 * Based on Sony IMX283 driver prepared by Will Whang11 *12 * Based on Sony imx477 camera driver13 * Copyright (C) 2019-2020 Raspberry Pi (Trading) Ltd14 */15 16#include <linux/array_size.h>17#include <linux/bitops.h>18#include <linux/container_of.h>19#include <linux/clk.h>20#include <linux/delay.h>21#include <linux/err.h>22#include <linux/gpio/consumer.h>23#include <linux/i2c.h>24#include <linux/minmax.h>25#include <linux/module.h>26#include <linux/mutex.h>27#include <linux/pm_runtime.h>28#include <linux/property.h>29#include <linux/regulator/consumer.h>30#include <linux/types.h>31#include <linux/units.h>32#include <media/v4l2-cci.h>33#include <media/v4l2-ctrls.h>34#include <media/v4l2-device.h>35#include <media/v4l2-event.h>36#include <media/v4l2-fwnode.h>37#include <media/v4l2-mediabus.h>38 39/* Chip ID */40#define IMX283_REG_CHIP_ID CCI_REG8(0x3000)41#define IMX283_CHIP_ID 0x0b // Default power on state42 43#define IMX283_REG_STANDBY CCI_REG8(0x3000)44#define IMX283_ACTIVE 045#define IMX283_STANDBY BIT(0)46#define IMX283_STBLOGIC BIT(1)47#define IMX283_STBMIPI BIT(2)48#define IMX283_STBDV BIT(3)49#define IMX283_SLEEP BIT(4)50 51#define IMX283_REG_CLAMP CCI_REG8(0x3001)52#define IMX283_CLPSQRST BIT(4)53 54#define IMX283_REG_PLSTMG08 CCI_REG8(0x3003)55#define IMX283_PLSTMG08_VAL 0x7756 57#define IMX283_REG_MDSEL1 CCI_REG8(0x3004)58#define IMX283_REG_MDSEL2 CCI_REG8(0x3005)59#define IMX283_REG_MDSEL3 CCI_REG8(0x3006)60#define IMX283_MDSEL3_VCROP_EN BIT(5)61#define IMX283_REG_MDSEL4 CCI_REG8(0x3007)62#define IMX283_MDSEL4_VCROP_EN (BIT(4) | BIT(6))63 64#define IMX283_REG_SVR CCI_REG16_LE(0x3009)65 66#define IMX283_REG_HTRIMMING CCI_REG8(0x300b)67#define IMX283_MDVREV BIT(0) /* VFLIP */68#define IMX283_HTRIMMING_EN BIT(4)69 70#define IMX283_REG_VWINPOS CCI_REG16_LE(0x300f)71#define IMX283_REG_VWIDCUT CCI_REG16_LE(0x3011)72 73#define IMX283_REG_MDSEL7 CCI_REG16_LE(0x3013)74 75/* CSI Clock Configuration */76#define IMX283_REG_TCLKPOST CCI_REG8(0x3018)77#define IMX283_REG_THSPREPARE CCI_REG8(0x301a)78#define IMX283_REG_THSZERO CCI_REG8(0x301c)79#define IMX283_REG_THSTRAIL CCI_REG8(0x301e)80#define IMX283_REG_TCLKTRAIL CCI_REG8(0x3020)81#define IMX283_REG_TCLKPREPARE CCI_REG8(0x3022)82#define IMX283_REG_TCLKZERO CCI_REG16_LE(0x3024)83#define IMX283_REG_TLPX CCI_REG8(0x3026)84#define IMX283_REG_THSEXIT CCI_REG8(0x3028)85#define IMX283_REG_TCLKPRE CCI_REG8(0x302a)86#define IMX283_REG_SYSMODE CCI_REG8(0x3104)87 88#define IMX283_REG_Y_OUT_SIZE CCI_REG16_LE(0x302f)89#define IMX283_REG_WRITE_VSIZE CCI_REG16_LE(0x3031)90#define IMX283_REG_OB_SIZE_V CCI_REG8(0x3033)91 92/* HMAX internal HBLANK */93#define IMX283_REG_HMAX CCI_REG16_LE(0x3036)94#define IMX283_HMAX_MAX (BIT(16) - 1)95 96/* VMAX internal VBLANK */97#define IMX283_REG_VMAX CCI_REG24_LE(0x3038)98#define IMX283_VMAX_MAX (BIT(16) - 1)99 100/* SHR internal */101#define IMX283_REG_SHR CCI_REG16_LE(0x303b)102#define IMX283_SHR_MIN 11103 104/*105 * Analog gain control106 * Gain [dB] = -20log{(2048 - value [10:0]) /2048}107 * Range: 0dB to approximately +27dB108 */109#define IMX283_REG_ANALOG_GAIN CCI_REG16_LE(0x3042)110#define IMX283_ANA_GAIN_MIN 0111#define IMX283_ANA_GAIN_MAX 1957112#define IMX283_ANA_GAIN_STEP 1113#define IMX283_ANA_GAIN_DEFAULT 0x0114 115/*116 * Digital gain control117 * Gain [dB] = value * 6118 * Range: 0dB to +18db119 */120#define IMX283_REG_DIGITAL_GAIN CCI_REG8(0x3044)121#define IMX283_DGTL_GAIN_MIN 0122#define IMX283_DGTL_GAIN_MAX 3123#define IMX283_DGTL_GAIN_DEFAULT 0124#define IMX283_DGTL_GAIN_STEP 1125 126#define IMX283_REG_HTRIMMING_START CCI_REG16_LE(0x3058)127#define IMX283_REG_HTRIMMING_END CCI_REG16_LE(0x305a)128 129#define IMX283_REG_MDSEL18 CCI_REG16_LE(0x30f6)130 131/* Master Mode Operation Control */132#define IMX283_REG_XMSTA CCI_REG8(0x3105)133#define IMX283_XMSTA BIT(0)134 135#define IMX283_REG_SYNCDRV CCI_REG8(0x3107)136#define IMX283_SYNCDRV_XHS_XVS (0xa0 | 0x02)137#define IMX283_SYNCDRV_HIZ (0xa0 | 0x03)138 139/* PLL Standby */140#define IMX283_REG_STBPL CCI_REG8(0x320b)141#define IMX283_STBPL_NORMAL 0x00142#define IMX283_STBPL_STANDBY 0x03143 144/* Input Frequency Setting */145#define IMX283_REG_PLRD1 CCI_REG8(0x36c1)146#define IMX283_REG_PLRD2 CCI_REG16_LE(0x36c2)147#define IMX283_REG_PLRD3 CCI_REG8(0x36f7)148#define IMX283_REG_PLRD4 CCI_REG8(0x36f8)149 150#define IMX283_REG_PLSTMG02 CCI_REG8(0x36aa)151#define IMX283_PLSTMG02_VAL 0x00152 153#define IMX283_REG_EBD_X_OUT_SIZE CCI_REG16_LE(0x3a54)154 155/* Test pattern generator */156#define IMX283_REG_TPG_CTRL CCI_REG8(0x3156)157#define IMX283_TPG_CTRL_CLKEN BIT(0)158#define IMX283_TPG_CTRL_PATEN BIT(4)159 160#define IMX283_REG_TPG_PAT CCI_REG8(0x3157)161#define IMX283_TPG_PAT_ALL_000 0x00162#define IMX283_TPG_PAT_ALL_FFF 0x01163#define IMX283_TPG_PAT_ALL_555 0x02164#define IMX283_TPG_PAT_ALL_AAA 0x03165#define IMX283_TPG_PAT_H_COLOR_BARS 0x0a166#define IMX283_TPG_PAT_V_COLOR_BARS 0x0b167 168/* Exposure control */169#define IMX283_EXPOSURE_MIN 52170#define IMX283_EXPOSURE_STEP 1171#define IMX283_EXPOSURE_DEFAULT 1000172#define IMX283_EXPOSURE_MAX 49865173 174#define IMAGE_PAD 0175 176#define IMX283_XCLR_MIN_DELAY_US (1 * USEC_PER_MSEC)177#define IMX283_XCLR_DELAY_RANGE_US (1 * USEC_PER_MSEC)178 179/* IMX283 native and active pixel array size. */180static const struct v4l2_rect imx283_native_area = {181 .top = 0,182 .left = 0,183 .width = 5592,184 .height = 3710,185};186 187static const struct v4l2_rect imx283_active_area = {188 .top = 40,189 .left = 108,190 .width = 5472,191 .height = 3648,192};193 194struct imx283_reg_list {195 unsigned int num_of_regs;196 const struct cci_reg_sequence *regs;197};198 199/* Mode : resolution and related config values */200struct imx283_mode {201 unsigned int mode;202 203 /* Bits per pixel */204 unsigned int bpp;205 206 /* Frame width */207 unsigned int width;208 209 /* Frame height */210 unsigned int height;211 212 /*213 * Minimum horizontal timing in pixel-units214 *215 * Note that HMAX is written in 72MHz units, and the datasheet assumes a216 * 720MHz link frequency. Convert datasheet values with the following:217 *218 * For 12 bpp modes (480Mbps) convert with:219 * hmax = [hmax in 72MHz units] * 480 / 72220 *221 * For 10 bpp modes (576Mbps) convert with:222 * hmax = [hmax in 72MHz units] * 576 / 72223 */224 u32 min_hmax;225 226 /* minimum V-timing in lines */227 u32 min_vmax;228 229 /* default H-timing */230 u32 default_hmax;231 232 /* default V-timing */233 u32 default_vmax;234 235 /* minimum SHR */236 u32 min_shr;237 238 /*239 * Per-mode vertical crop constants used to calculate values240 * of IMX283REG_WIDCUT and IMX283_REG_VWINPOS.241 */242 u32 veff;243 u32 vst;244 u32 vct;245 246 /* Horizontal and vertical binning ratio */247 u8 hbin_ratio;248 u8 vbin_ratio;249 250 /* Optical Blanking */251 u32 horizontal_ob;252 u32 vertical_ob;253 254 /* Analog crop rectangle. */255 struct v4l2_rect crop;256};257 258struct imx283_input_frequency {259 unsigned int mhz;260 unsigned int reg_count;261 struct cci_reg_sequence regs[4];262};263 264static const struct imx283_input_frequency imx283_frequencies[] = {265 {266 .mhz = 6 * HZ_PER_MHZ,267 .reg_count = 4,268 .regs = {269 { IMX283_REG_PLRD1, 0x00 },270 { IMX283_REG_PLRD2, 0x00f0 },271 { IMX283_REG_PLRD3, 0x00 },272 { IMX283_REG_PLRD4, 0xc0 },273 },274 },275 {276 .mhz = 12 * HZ_PER_MHZ,277 .reg_count = 4,278 .regs = {279 { IMX283_REG_PLRD1, 0x01 },280 { IMX283_REG_PLRD2, 0x00f0 },281 { IMX283_REG_PLRD3, 0x01 },282 { IMX283_REG_PLRD4, 0xc0 },283 },284 },285 {286 .mhz = 18 * HZ_PER_MHZ,287 .reg_count = 4,288 .regs = {289 { IMX283_REG_PLRD1, 0x01 },290 { IMX283_REG_PLRD2, 0x00a0 },291 { IMX283_REG_PLRD3, 0x01 },292 { IMX283_REG_PLRD4, 0x80 },293 },294 },295 {296 .mhz = 24 * HZ_PER_MHZ,297 .reg_count = 4,298 .regs = {299 { IMX283_REG_PLRD1, 0x02 },300 { IMX283_REG_PLRD2, 0x00f0 },301 { IMX283_REG_PLRD3, 0x02 },302 { IMX283_REG_PLRD4, 0xc0 },303 },304 },305};306 307enum imx283_modes {308 IMX283_MODE_0,309 IMX283_MODE_1,310 IMX283_MODE_1A,311 IMX283_MODE_1S,312 IMX283_MODE_2,313 IMX283_MODE_2A,314 IMX283_MODE_3,315 IMX283_MODE_4,316 IMX283_MODE_5,317 IMX283_MODE_6,318};319 320struct imx283_readout_mode {321 u8 mdsel1;322 u8 mdsel2;323 u8 mdsel3;324 u8 mdsel4;325};326 327static const struct imx283_readout_mode imx283_readout_modes[] = {328 /* All pixel scan modes */329 [IMX283_MODE_0] = { 0x04, 0x03, 0x10, 0x00 }, /* 12 bit */330 [IMX283_MODE_1] = { 0x04, 0x01, 0x00, 0x00 }, /* 10 bit */331 [IMX283_MODE_1A] = { 0x04, 0x01, 0x20, 0x50 }, /* 10 bit */332 [IMX283_MODE_1S] = { 0x04, 0x41, 0x20, 0x50 }, /* 10 bit */333 334 /* Horizontal / Vertical 2/2-line binning */335 [IMX283_MODE_2] = { 0x0d, 0x11, 0x50, 0x00 }, /* 12 bit */336 [IMX283_MODE_2A] = { 0x0d, 0x11, 0x70, 0x50 }, /* 12 bit */337 338 /* Horizontal / Vertical 3/3-line binning */339 [IMX283_MODE_3] = { 0x1e, 0x18, 0x10, 0x00 }, /* 12 bit */340 341 /* Vertical 2/9 subsampling, horizontal 3 binning cropping */342 [IMX283_MODE_4] = { 0x29, 0x18, 0x30, 0x50 }, /* 12 bit */343 344 /* Vertical 2/19 subsampling binning, horizontal 3 binning */345 [IMX283_MODE_5] = { 0x2d, 0x18, 0x10, 0x00 }, /* 12 bit */346 347 /* Vertical 2 binning horizontal 2/4, subsampling 16:9 cropping */348 [IMX283_MODE_6] = { 0x18, 0x21, 0x00, 0x09 }, /* 10 bit */349 350 /*351 * New modes should make sure the offset period is complied.352 * See imx283_exposure() for reference.353 */354};355 356static const struct cci_reg_sequence mipi_data_rate_1440Mbps[] = {357 /* The default register settings provide the 1440Mbps rate */358 { CCI_REG8(0x36c5), 0x00 }, /* Undocumented */359 { CCI_REG8(0x3ac4), 0x00 }, /* Undocumented */360 361 { IMX283_REG_STBPL, 0x00 },362 { IMX283_REG_TCLKPOST, 0xa7 },363 { IMX283_REG_THSPREPARE, 0x6f },364 { IMX283_REG_THSZERO, 0x9f },365 { IMX283_REG_THSTRAIL, 0x5f },366 { IMX283_REG_TCLKTRAIL, 0x5f },367 { IMX283_REG_TCLKPREPARE, 0x6f },368 { IMX283_REG_TCLKZERO, 0x017f },369 { IMX283_REG_TLPX, 0x4f },370 { IMX283_REG_THSEXIT, 0x47 },371 { IMX283_REG_TCLKPRE, 0x07 },372 { IMX283_REG_SYSMODE, 0x02 },373};374 375static const struct cci_reg_sequence mipi_data_rate_720Mbps[] = {376 /* Undocumented Additions "For 720MBps" Setting */377 { CCI_REG8(0x36c5), 0x01 }, /* Undocumented */378 { CCI_REG8(0x3ac4), 0x01 }, /* Undocumented */379 380 { IMX283_REG_STBPL, 0x00 },381 { IMX283_REG_TCLKPOST, 0x77 },382 { IMX283_REG_THSPREPARE, 0x37 },383 { IMX283_REG_THSZERO, 0x67 },384 { IMX283_REG_THSTRAIL, 0x37 },385 { IMX283_REG_TCLKTRAIL, 0x37 },386 { IMX283_REG_TCLKPREPARE, 0x37 },387 { IMX283_REG_TCLKZERO, 0xdf },388 { IMX283_REG_TLPX, 0x2f },389 { IMX283_REG_THSEXIT, 0x47 },390 { IMX283_REG_TCLKPRE, 0x0f },391 { IMX283_REG_SYSMODE, 0x02 },392};393 394static const s64 link_frequencies[] = {395 720 * HZ_PER_MHZ, /* 1440 Mbps lane data rate */396 360 * HZ_PER_MHZ, /* 720 Mbps data lane rate */397};398 399static const struct imx283_reg_list link_freq_reglist[] = {400 { /* 720 MHz */401 .num_of_regs = ARRAY_SIZE(mipi_data_rate_1440Mbps),402 .regs = mipi_data_rate_1440Mbps,403 },404 { /* 360 MHz */405 .num_of_regs = ARRAY_SIZE(mipi_data_rate_720Mbps),406 .regs = mipi_data_rate_720Mbps,407 },408};409 410/* Mode configs */411static const struct imx283_mode supported_modes_12bit[] = {412 {413 /* 20MPix 21.40 fps readout mode 0 */414 .mode = IMX283_MODE_0,415 .bpp = 12,416 .width = 5472,417 .height = 3648,418 .min_hmax = 5914, /* 887 @ 480MHz/72MHz */419 .min_vmax = 3793, /* Lines */420 421 .veff = 3694,422 .vst = 0,423 .vct = 0,424 425 .hbin_ratio = 1,426 .vbin_ratio = 1,427 428 /* 20.00 FPS */429 .default_hmax = 6000, /* 900 @ 480MHz/72MHz */430 .default_vmax = 4000,431 432 .min_shr = 11,433 .horizontal_ob = 96,434 .vertical_ob = 16,435 .crop = {436 .top = 40,437 .left = 108,438 .width = 5472,439 .height = 3648,440 },441 },442 {443 /*444 * Readout mode 2 : 2/2 binned mode (2736x1824)445 */446 .mode = IMX283_MODE_2,447 .bpp = 12,448 .width = 2736,449 .height = 1824,450 .min_hmax = 2414, /* Pixels (362 * 480MHz/72MHz + padding) */451 .min_vmax = 3840, /* Lines */452 453 /* 50.00 FPS */454 .default_hmax = 2500, /* 375 @ 480MHz/72Mhz */455 .default_vmax = 3840,456 457 .veff = 1824,458 .vst = 0,459 .vct = 0,460 461 .hbin_ratio = 2,462 .vbin_ratio = 2,463 464 .min_shr = 12,465 .horizontal_ob = 48,466 .vertical_ob = 4,467 468 .crop = {469 .top = 40,470 .left = 108,471 .width = 5472,472 .height = 3648,473 },474 },475 {476 /*477 * Readout mode 3 : 3/3 binned mode (1824x1216)478 */479 .mode = IMX283_MODE_3,480 .bpp = 12,481 .width = 1824,482 .height = 1216,483 .min_hmax = 1894, /* Pixels (284 * 480MHz/72MHz + padding) */484 .min_vmax = 4200, /* Lines */485 486 /* 60.00 fps */487 .default_hmax = 1900, /* 285 @ 480MHz/72Mhz */488 .default_vmax = 4200,489 490 .veff = 1234,491 .vst = 0,492 .vct = 0,493 494 .hbin_ratio = 3,495 .vbin_ratio = 3,496 497 .min_shr = 16,498 .horizontal_ob = 32,499 .vertical_ob = 4,500 501 .crop = {502 .top = 40,503 .left = 108,504 .width = 5472,505 .height = 3648,506 },507 },508};509 510static const struct imx283_mode supported_modes_10bit[] = {511 {512 /* 20MPix 25.48 fps readout mode 1 */513 .mode = IMX283_MODE_1,514 .bpp = 10,515 .width = 5472,516 .height = 3648,517 .min_hmax = 5960, /* 745 @ 576MHz / 72MHz */518 .min_vmax = 3793,519 520 /* 25.00 FPS */521 .default_hmax = 6000, /* 750 @ 576MHz / 72MHz */522 .default_vmax = 3840,523 524 .min_shr = 10,525 .horizontal_ob = 96,526 .vertical_ob = 16,527 .crop = {528 .top = 40,529 .left = 108,530 .width = 5472,531 .height = 3648,532 },533 },534};535 536static const u32 imx283_mbus_codes[] = {537 MEDIA_BUS_FMT_SRGGB12_1X12,538 MEDIA_BUS_FMT_SRGGB10_1X10,539};540 541/* regulator supplies */542static const char *const imx283_supply_name[] = {543 "vadd", /* Analog (2.9V) supply */544 "vdd1", /* Supply Voltage 2 (1.8V) supply */545 "vdd2", /* Supply Voltage 3 (1.2V) supply */546};547 548struct imx283 {549 struct device *dev;550 struct regmap *cci;551 552 const struct imx283_input_frequency *freq;553 554 struct v4l2_subdev sd;555 struct media_pad pad;556 557 struct clk *xclk;558 559 struct gpio_desc *reset_gpio;560 struct regulator_bulk_data supplies[ARRAY_SIZE(imx283_supply_name)];561 562 /* V4L2 Controls */563 struct v4l2_ctrl_handler ctrl_handler;564 struct v4l2_ctrl *exposure;565 struct v4l2_ctrl *vblank;566 struct v4l2_ctrl *hblank;567 struct v4l2_ctrl *vflip;568 569 unsigned long link_freq_bitmap;570 571 u16 hmax;572 u32 vmax;573};574 575static inline struct imx283 *to_imx283(struct v4l2_subdev *sd)576{577 return container_of_const(sd, struct imx283, sd);578}579 580static inline void get_mode_table(unsigned int code,581 const struct imx283_mode **mode_list,582 unsigned int *num_modes)583{584 switch (code) {585 case MEDIA_BUS_FMT_SRGGB12_1X12:586 case MEDIA_BUS_FMT_SGRBG12_1X12:587 case MEDIA_BUS_FMT_SGBRG12_1X12:588 case MEDIA_BUS_FMT_SBGGR12_1X12:589 *mode_list = supported_modes_12bit;590 *num_modes = ARRAY_SIZE(supported_modes_12bit);591 break;592 593 case MEDIA_BUS_FMT_SRGGB10_1X10:594 case MEDIA_BUS_FMT_SGRBG10_1X10:595 case MEDIA_BUS_FMT_SGBRG10_1X10:596 case MEDIA_BUS_FMT_SBGGR10_1X10:597 *mode_list = supported_modes_10bit;598 *num_modes = ARRAY_SIZE(supported_modes_10bit);599 break;600 default:601 *mode_list = NULL;602 *num_modes = 0;603 break;604 }605}606 607/* Calculate the Pixel Rate based on the current mode */608static u64 imx283_pixel_rate(struct imx283 *imx283,609 const struct imx283_mode *mode)610{611 u64 link_frequency = link_frequencies[__ffs(imx283->link_freq_bitmap)];612 unsigned int bpp = mode->bpp;613 const unsigned int ddr = 2; /* Double Data Rate */614 const unsigned int lanes = 4; /* Only 4 lane support */615 u64 numerator = link_frequency * ddr * lanes;616 617 do_div(numerator, bpp);618 619 return numerator;620}621 622/* Convert from a variable pixel_rate to 72 MHz clock cycles */623static u64 imx283_internal_clock(unsigned int pixel_rate, unsigned int pixels)624{625 /*626 * Determine the following operation without overflow:627 * pixels = 72 Mhz / pixel_rate628 *629 * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz)630 * can easily overflow this calculation, so pre-divide to simplify.631 */632 const u32 iclk_pre = 72;633 const u32 pclk_pre = pixel_rate / HZ_PER_MHZ;634 u64 numerator = pixels * iclk_pre;635 636 do_div(numerator, pclk_pre);637 638 return numerator;639}640 641/* Internal clock (72MHz) to Pixel Rate clock (Variable) */642static u64 imx283_iclk_to_pix(unsigned int pixel_rate, unsigned int cycles)643{644 /*645 * Determine the following operation without overflow:646 * cycles * pixel_rate / 72 MHz647 *648 * The internal clock at 72MHz and Pixel Rate (between 240 and 576MHz)649 * can easily overflow this calculation, so pre-divide to simplify.650 */651 const u32 iclk_pre = 72;652 const u32 pclk_pre = pixel_rate / HZ_PER_MHZ;653 u64 numerator = cycles * pclk_pre;654 655 do_div(numerator, iclk_pre);656 657 return numerator;658}659 660/* Determine the exposure based on current hmax, vmax and a given SHR */661static u32 imx283_exposure(struct imx283 *imx283,662 const struct imx283_mode *mode, u64 shr)663{664 u32 svr = 0; /* SVR feature is not currently supported */665 u32 offset;666 u64 numerator;667 668 /* Number of clocks per internal offset period */669 offset = mode->mode == IMX283_MODE_0 ? 209 : 157;670 numerator = (imx283->vmax * (svr + 1) - shr) * imx283->hmax + offset;671 672 do_div(numerator, imx283->hmax);673 674 return clamp(numerator, 0, U32_MAX);675}676 677static void imx283_exposure_limits(struct imx283 *imx283,678 const struct imx283_mode *mode,679 s64 *min_exposure, s64 *max_exposure)680{681 u32 svr = 0; /* SVR feature is not currently supported */682 u64 min_shr = mode->min_shr;683 /* Global Shutter is not supported */684 u64 max_shr = (svr + 1) * imx283->vmax - 4;685 686 max_shr = min(max_shr, BIT(16) - 1);687 688 *min_exposure = imx283_exposure(imx283, mode, max_shr);689 *max_exposure = imx283_exposure(imx283, mode, min_shr);690}691 692/*693 * Integration Time [s] = [ {VMAX x (SVR + 1) – (SHR)} x HMAX + offset ]694 * / [ 72 x 10^6 ]695 */696static u32 imx283_shr(struct imx283 *imx283, const struct imx283_mode *mode,697 u32 exposure)698{699 u32 svr = 0; /* SVR feature is not currently supported */700 u32 offset;701 u64 temp;702 703 /* Number of clocks per internal offset period */704 offset = mode->mode == IMX283_MODE_0 ? 209 : 157;705 temp = ((u64)exposure * imx283->hmax - offset);706 do_div(temp, imx283->hmax);707 708 return (imx283->vmax * (svr + 1) - temp);709}710 711static const char * const imx283_tpg_menu[] = {712 "Disabled",713 "All 000h",714 "All FFFh",715 "All 555h",716 "All AAAh",717 "Horizontal color bars",718 "Vertical color bars",719};720 721static const int imx283_tpg_val[] = {722 IMX283_TPG_PAT_ALL_000,723 IMX283_TPG_PAT_ALL_000,724 IMX283_TPG_PAT_ALL_FFF,725 IMX283_TPG_PAT_ALL_555,726 IMX283_TPG_PAT_ALL_AAA,727 IMX283_TPG_PAT_H_COLOR_BARS,728 IMX283_TPG_PAT_V_COLOR_BARS,729};730 731static int imx283_update_test_pattern(struct imx283 *imx283, u32 pattern_index)732{733 int ret;734 735 if (pattern_index >= ARRAY_SIZE(imx283_tpg_val))736 return -EINVAL;737 738 if (!pattern_index)739 return cci_write(imx283->cci, IMX283_REG_TPG_CTRL, 0x00, NULL);740 741 ret = cci_write(imx283->cci, IMX283_REG_TPG_PAT,742 imx283_tpg_val[pattern_index], NULL);743 if (ret)744 return ret;745 746 return cci_write(imx283->cci, IMX283_REG_TPG_CTRL,747 IMX283_TPG_CTRL_CLKEN | IMX283_TPG_CTRL_PATEN, NULL);748}749 750static int imx283_set_ctrl(struct v4l2_ctrl *ctrl)751{752 struct imx283 *imx283 = container_of(ctrl->handler, struct imx283,753 ctrl_handler);754 const struct imx283_mode *mode;755 struct v4l2_mbus_framefmt *fmt;756 const struct imx283_mode *mode_list;757 struct v4l2_subdev_state *state;758 unsigned int num_modes;759 u64 shr, pixel_rate;760 int ret = 0;761 762 state = v4l2_subdev_get_locked_active_state(&imx283->sd);763 fmt = v4l2_subdev_state_get_format(state, 0);764 765 get_mode_table(fmt->code, &mode_list, &num_modes);766 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height,767 fmt->width, fmt->height);768 769 /*770 * The VBLANK control may change the limits of usable exposure, so check771 * and adjust if necessary.772 */773 if (ctrl->id == V4L2_CID_VBLANK) {774 /* Honour the VBLANK limits when setting exposure. */775 s64 current_exposure, max_exposure, min_exposure;776 777 imx283->vmax = mode->height + ctrl->val;778 779 imx283_exposure_limits(imx283, mode,780 &min_exposure, &max_exposure);781 782 current_exposure = imx283->exposure->val;783 current_exposure = clamp(current_exposure, min_exposure,784 max_exposure);785 786 __v4l2_ctrl_modify_range(imx283->exposure, min_exposure,787 max_exposure, 1, current_exposure);788 }789 790 /*791 * Applying V4L2 control value only happens792 * when power is up for streaming793 */794 if (!pm_runtime_get_if_active(imx283->dev))795 return 0;796 797 switch (ctrl->id) {798 case V4L2_CID_EXPOSURE:799 shr = imx283_shr(imx283, mode, ctrl->val);800 dev_dbg(imx283->dev, "V4L2_CID_EXPOSURE : %d - SHR: %lld\n",801 ctrl->val, shr);802 ret = cci_write(imx283->cci, IMX283_REG_SHR, shr, NULL);803 break;804 805 case V4L2_CID_HBLANK:806 pixel_rate = imx283_pixel_rate(imx283, mode);807 imx283->hmax = imx283_internal_clock(pixel_rate, mode->width + ctrl->val);808 dev_dbg(imx283->dev, "V4L2_CID_HBLANK : %d HMAX : %u\n",809 ctrl->val, imx283->hmax);810 ret = cci_write(imx283->cci, IMX283_REG_HMAX, imx283->hmax, NULL);811 break;812 813 case V4L2_CID_VBLANK:814 imx283->vmax = mode->height + ctrl->val;815 dev_dbg(imx283->dev, "V4L2_CID_VBLANK : %d VMAX : %u\n",816 ctrl->val, imx283->vmax);817 ret = cci_write(imx283->cci, IMX283_REG_VMAX, imx283->vmax, NULL);818 break;819 820 case V4L2_CID_ANALOGUE_GAIN:821 ret = cci_write(imx283->cci, IMX283_REG_ANALOG_GAIN, ctrl->val, NULL);822 break;823 824 case V4L2_CID_DIGITAL_GAIN:825 ret = cci_write(imx283->cci, IMX283_REG_DIGITAL_GAIN, ctrl->val, NULL);826 break;827 828 case V4L2_CID_VFLIP:829 /*830 * VFLIP is managed by BIT(0) of IMX283_REG_HTRIMMING address, hence831 * both need to be set simultaneously.832 */833 if (ctrl->val) {834 cci_write(imx283->cci, IMX283_REG_HTRIMMING,835 IMX283_HTRIMMING_EN | IMX283_MDVREV, &ret);836 } else {837 cci_write(imx283->cci, IMX283_REG_HTRIMMING,838 IMX283_HTRIMMING_EN, &ret);839 }840 break;841 842 case V4L2_CID_TEST_PATTERN:843 ret = imx283_update_test_pattern(imx283, ctrl->val);844 break;845 846 default:847 dev_err(imx283->dev, "ctrl(id:0x%x, val:0x%x) is not handled\n",848 ctrl->id, ctrl->val);849 break;850 }851 852 pm_runtime_put(imx283->dev);853 854 return ret;855}856 857static const struct v4l2_ctrl_ops imx283_ctrl_ops = {858 .s_ctrl = imx283_set_ctrl,859};860 861static int imx283_enum_mbus_code(struct v4l2_subdev *sd,862 struct v4l2_subdev_state *sd_state,863 struct v4l2_subdev_mbus_code_enum *code)864{865 if (code->index >= ARRAY_SIZE(imx283_mbus_codes))866 return -EINVAL;867 868 code->code = imx283_mbus_codes[code->index];869 870 return 0;871}872 873static int imx283_enum_frame_size(struct v4l2_subdev *sd,874 struct v4l2_subdev_state *sd_state,875 struct v4l2_subdev_frame_size_enum *fse)876{877 const struct imx283_mode *mode_list;878 unsigned int num_modes;879 880 get_mode_table(fse->code, &mode_list, &num_modes);881 882 if (fse->index >= num_modes)883 return -EINVAL;884 885 fse->min_width = mode_list[fse->index].width;886 fse->max_width = fse->min_width;887 fse->min_height = mode_list[fse->index].height;888 fse->max_height = fse->min_height;889 890 return 0;891}892 893static void imx283_update_image_pad_format(struct imx283 *imx283,894 const struct imx283_mode *mode,895 struct v4l2_mbus_framefmt *format)896{897 format->width = mode->width;898 format->height = mode->height;899 format->field = V4L2_FIELD_NONE;900 format->colorspace = V4L2_COLORSPACE_RAW;901 format->ycbcr_enc = V4L2_YCBCR_ENC_601;902 format->quantization = V4L2_QUANTIZATION_FULL_RANGE;903 format->xfer_func = V4L2_XFER_FUNC_NONE;904}905 906static int imx283_init_state(struct v4l2_subdev *sd,907 struct v4l2_subdev_state *state)908{909 struct imx283 *imx283 = to_imx283(sd);910 struct v4l2_mbus_framefmt *format;911 const struct imx283_mode *mode;912 struct v4l2_rect *crop;913 914 /* Initialize try_fmt */915 format = v4l2_subdev_state_get_format(state, IMAGE_PAD);916 917 mode = &supported_modes_12bit[0];918 format->code = MEDIA_BUS_FMT_SRGGB12_1X12;919 imx283_update_image_pad_format(imx283, mode, format);920 921 /* Initialize crop rectangle to mode default */922 crop = v4l2_subdev_state_get_crop(state, IMAGE_PAD);923 *crop = mode->crop;924 925 return 0;926}927 928static void imx283_set_framing_limits(struct imx283 *imx283,929 const struct imx283_mode *mode)930{931 u64 pixel_rate = imx283_pixel_rate(imx283, mode);932 u64 min_hblank, max_hblank, def_hblank;933 934 /* Initialise hmax and vmax for exposure calculations */935 imx283->hmax = imx283_internal_clock(pixel_rate, mode->default_hmax);936 imx283->vmax = mode->default_vmax;937 938 /*939 * Horizontal Blanking940 * Convert the HMAX_MAX (72MHz) to Pixel rate values for HBLANK_MAX941 */942 min_hblank = mode->min_hmax - mode->width;943 max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width;944 def_hblank = mode->default_hmax - mode->width;945 __v4l2_ctrl_modify_range(imx283->hblank, min_hblank, max_hblank, 1,946 def_hblank);947 __v4l2_ctrl_s_ctrl(imx283->hblank, def_hblank);948 949 /* Vertical Blanking */950 __v4l2_ctrl_modify_range(imx283->vblank, mode->min_vmax - mode->height,951 IMX283_VMAX_MAX - mode->height, 1,952 mode->default_vmax - mode->height);953 __v4l2_ctrl_s_ctrl(imx283->vblank, mode->default_vmax - mode->height);954}955 956static int imx283_set_pad_format(struct v4l2_subdev *sd,957 struct v4l2_subdev_state *sd_state,958 struct v4l2_subdev_format *fmt)959{960 struct v4l2_mbus_framefmt *format;961 const struct imx283_mode *mode;962 struct imx283 *imx283 = to_imx283(sd);963 const struct imx283_mode *mode_list;964 unsigned int num_modes;965 966 get_mode_table(fmt->format.code, &mode_list, &num_modes);967 968 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height,969 fmt->format.width, fmt->format.height);970 971 fmt->format.width = mode->width;972 fmt->format.height = mode->height;973 fmt->format.field = V4L2_FIELD_NONE;974 fmt->format.colorspace = V4L2_COLORSPACE_RAW;975 fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601;976 fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE;977 fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;978 979 format = v4l2_subdev_state_get_format(sd_state, 0);980 981 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)982 imx283_set_framing_limits(imx283, mode);983 984 *format = fmt->format;985 986 return 0;987}988 989static int imx283_standby_cancel(struct imx283 *imx283)990{991 unsigned int link_freq_idx;992 int ret = 0;993 994 cci_write(imx283->cci, IMX283_REG_STANDBY,995 IMX283_STBLOGIC | IMX283_STBDV, &ret);996 997 /* Configure PLL clocks based on the xclk */998 cci_multi_reg_write(imx283->cci, imx283->freq->regs,999 imx283->freq->reg_count, &ret);1000 1001 dev_dbg(imx283->dev, "Using clk freq %ld MHz",1002 imx283->freq->mhz / HZ_PER_MHZ);1003 1004 /* Initialise communication */1005 cci_write(imx283->cci, IMX283_REG_PLSTMG08, IMX283_PLSTMG08_VAL, &ret);1006 cci_write(imx283->cci, IMX283_REG_PLSTMG02, IMX283_PLSTMG02_VAL, &ret);1007 1008 /* Enable PLL */1009 cci_write(imx283->cci, IMX283_REG_STBPL, IMX283_STBPL_NORMAL, &ret);1010 1011 /* Configure the MIPI link speed */1012 link_freq_idx = __ffs(imx283->link_freq_bitmap);1013 cci_multi_reg_write(imx283->cci, link_freq_reglist[link_freq_idx].regs,1014 link_freq_reglist[link_freq_idx].num_of_regs,1015 &ret);1016 1017 /* 1st Stabilisation period of 1 ms or more */1018 usleep_range(1000, 2000);1019 1020 /* Activate */1021 cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_ACTIVE, &ret);1022 1023 /* 2nd Stabilisation period of 19ms or more */1024 usleep_range(19000, 20000);1025 1026 cci_write(imx283->cci, IMX283_REG_CLAMP, IMX283_CLPSQRST, &ret);1027 cci_write(imx283->cci, IMX283_REG_XMSTA, 0, &ret);1028 cci_write(imx283->cci, IMX283_REG_SYNCDRV, IMX283_SYNCDRV_XHS_XVS, &ret);1029 1030 return ret;1031}1032 1033/* Start streaming */1034static int imx283_start_streaming(struct imx283 *imx283,1035 struct v4l2_subdev_state *state)1036{1037 const struct imx283_readout_mode *readout;1038 const struct imx283_mode *mode;1039 const struct v4l2_mbus_framefmt *fmt;1040 const struct imx283_mode *mode_list;1041 unsigned int num_modes;1042 u32 v_widcut;1043 s32 v_pos;1044 u32 write_v_size;1045 u32 y_out_size;1046 int ret = 0;1047 1048 fmt = v4l2_subdev_state_get_format(state, 0);1049 get_mode_table(fmt->code, &mode_list, &num_modes);1050 mode = v4l2_find_nearest_size(mode_list, num_modes, width, height,1051 fmt->width, fmt->height);1052 1053 ret = imx283_standby_cancel(imx283);1054 if (ret) {1055 dev_err(imx283->dev, "failed to cancel standby\n");1056 return ret;1057 }1058 1059 /*1060 * Set the readout mode registers.1061 * MDSEL3 and MDSEL4 are updated to enable Arbitrary Vertical Cropping.1062 */1063 readout = &imx283_readout_modes[mode->mode];1064 cci_write(imx283->cci, IMX283_REG_MDSEL1, readout->mdsel1, &ret);1065 cci_write(imx283->cci, IMX283_REG_MDSEL2, readout->mdsel2, &ret);1066 cci_write(imx283->cci, IMX283_REG_MDSEL3,1067 readout->mdsel3 | IMX283_MDSEL3_VCROP_EN, &ret);1068 cci_write(imx283->cci, IMX283_REG_MDSEL4,1069 readout->mdsel4 | IMX283_MDSEL4_VCROP_EN, &ret);1070 1071 /* Mode 1S specific entries from the Readout Drive Mode Tables */1072 if (mode->mode == IMX283_MODE_1S) {1073 cci_write(imx283->cci, IMX283_REG_MDSEL7, 0x01, &ret);1074 cci_write(imx283->cci, IMX283_REG_MDSEL18, 0x1098, &ret);1075 }1076 1077 if (ret) {1078 dev_err(imx283->dev, "failed to set readout\n");1079 return ret;1080 }1081 1082 /* Initialise SVR. Unsupported for now - Always 0 */1083 cci_write(imx283->cci, IMX283_REG_SVR, 0x00, &ret);1084 1085 dev_dbg(imx283->dev, "Mode: Size %d x %d\n", mode->width, mode->height);1086 dev_dbg(imx283->dev, "Analogue Crop (in the mode) %d,%d %dx%d\n",1087 mode->crop.left,1088 mode->crop.top,1089 mode->crop.width,1090 mode->crop.height);1091 1092 y_out_size = mode->crop.height / mode->vbin_ratio;1093 write_v_size = y_out_size + mode->vertical_ob;1094 /*1095 * cropping start position = (VWINPOS – Vst) × 21096 * cropping width = Veff – (VWIDCUT – Vct) × 21097 */1098 v_pos = imx283->vflip->val ?1099 ((-mode->crop.top / mode->vbin_ratio) / 2) + mode->vst :1100 ((mode->crop.top / mode->vbin_ratio) / 2) + mode->vst;1101 v_widcut = ((mode->veff - y_out_size) / 2) + mode->vct;1102 1103 cci_write(imx283->cci, IMX283_REG_Y_OUT_SIZE, y_out_size, &ret);1104 cci_write(imx283->cci, IMX283_REG_WRITE_VSIZE, write_v_size, &ret);1105 cci_write(imx283->cci, IMX283_REG_VWIDCUT, v_widcut, &ret);1106 cci_write(imx283->cci, IMX283_REG_VWINPOS, v_pos, &ret);1107 1108 cci_write(imx283->cci, IMX283_REG_OB_SIZE_V, mode->vertical_ob, &ret);1109 1110 /* TODO: Validate mode->crop is fully contained within imx283_native_area */1111 cci_write(imx283->cci, IMX283_REG_HTRIMMING_START, mode->crop.left, &ret);1112 cci_write(imx283->cci, IMX283_REG_HTRIMMING_END,1113 mode->crop.left + mode->crop.width, &ret);1114 1115 /* Disable embedded data */1116 cci_write(imx283->cci, IMX283_REG_EBD_X_OUT_SIZE, 0, &ret);1117 1118 /* Apply customized values from controls (HMAX/VMAX/SHR) */1119 ret = __v4l2_ctrl_handler_setup(imx283->sd.ctrl_handler);1120 1121 return ret;1122}1123 1124static int imx283_enable_streams(struct v4l2_subdev *sd,1125 struct v4l2_subdev_state *state, u32 pad,1126 u64 streams_mask)1127{1128 struct imx283 *imx283 = to_imx283(sd);1129 int ret;1130 1131 if (pad != IMAGE_PAD)1132 return -EINVAL;1133 1134 ret = pm_runtime_get_sync(imx283->dev);1135 if (ret < 0) {1136 pm_runtime_put_noidle(imx283->dev);1137 return ret;1138 }1139 1140 ret = imx283_start_streaming(imx283, state);1141 if (ret)1142 goto err_rpm_put;1143 1144 return 0;1145 1146err_rpm_put:1147 pm_runtime_mark_last_busy(imx283->dev);1148 pm_runtime_put_autosuspend(imx283->dev);1149 1150 return ret;1151}1152 1153static int imx283_disable_streams(struct v4l2_subdev *sd,1154 struct v4l2_subdev_state *state, u32 pad,1155 u64 streams_mask)1156{1157 struct imx283 *imx283 = to_imx283(sd);1158 int ret;1159 1160 if (pad != IMAGE_PAD)1161 return -EINVAL;1162 1163 ret = cci_write(imx283->cci, IMX283_REG_STANDBY, IMX283_STBLOGIC, NULL);1164 if (ret)1165 dev_err(imx283->dev, "Failed to stop stream\n");1166 1167 pm_runtime_mark_last_busy(imx283->dev);1168 pm_runtime_put_autosuspend(imx283->dev);1169 1170 return ret;1171}1172 1173/* Power/clock management functions */1174static int imx283_power_on(struct imx283 *imx283)1175{1176 int ret;1177 1178 ret = regulator_bulk_enable(ARRAY_SIZE(imx283_supply_name),1179 imx283->supplies);1180 if (ret) {1181 dev_err(imx283->dev, "failed to enable regulators\n");1182 return ret;1183 }1184 1185 ret = clk_prepare_enable(imx283->xclk);1186 if (ret) {1187 dev_err(imx283->dev, "failed to enable clock\n");1188 goto reg_off;1189 }1190 1191 gpiod_set_value_cansleep(imx283->reset_gpio, 0);1192 1193 usleep_range(IMX283_XCLR_MIN_DELAY_US,1194 IMX283_XCLR_MIN_DELAY_US + IMX283_XCLR_DELAY_RANGE_US);1195 1196 return 0;1197 1198reg_off:1199 regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies);1200 return ret;1201}1202 1203static int imx283_power_off(struct imx283 *imx283)1204{1205 gpiod_set_value_cansleep(imx283->reset_gpio, 1);1206 regulator_bulk_disable(ARRAY_SIZE(imx283_supply_name), imx283->supplies);1207 clk_disable_unprepare(imx283->xclk);1208 1209 return 0;1210}1211 1212static int imx283_runtime_resume(struct device *dev)1213{1214 struct v4l2_subdev *sd = dev_get_drvdata(dev);1215 struct imx283 *imx283 = to_imx283(sd);1216 1217 return imx283_power_on(imx283);1218}1219 1220static int imx283_runtime_suspend(struct device *dev)1221{1222 struct v4l2_subdev *sd = dev_get_drvdata(dev);1223 struct imx283 *imx283 = to_imx283(sd);1224 1225 imx283_power_off(imx283);1226 1227 return 0;1228}1229 1230static int imx283_get_regulators(struct imx283 *imx283)1231{1232 unsigned int i;1233 1234 for (i = 0; i < ARRAY_SIZE(imx283_supply_name); i++)1235 imx283->supplies[i].supply = imx283_supply_name[i];1236 1237 return devm_regulator_bulk_get(imx283->dev,1238 ARRAY_SIZE(imx283_supply_name),1239 imx283->supplies);1240}1241 1242/* Verify chip ID */1243static int imx283_identify_module(struct imx283 *imx283)1244{1245 int ret;1246 u64 val;1247 1248 ret = cci_read(imx283->cci, IMX283_REG_CHIP_ID, &val, NULL);1249 if (ret) {1250 dev_err(imx283->dev, "failed to read chip id %x, with error %d\n",1251 IMX283_CHIP_ID, ret);1252 return ret;1253 }1254 1255 if (val != IMX283_CHIP_ID) {1256 dev_err(imx283->dev, "chip id mismatch: %x!=%llx\n",1257 IMX283_CHIP_ID, val);1258 return -EIO;1259 }1260 1261 return 0;1262}1263 1264static int imx283_get_selection(struct v4l2_subdev *sd,1265 struct v4l2_subdev_state *sd_state,1266 struct v4l2_subdev_selection *sel)1267{1268 switch (sel->target) {1269 case V4L2_SEL_TGT_CROP: {1270 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0);1271 return 0;1272 }1273 1274 case V4L2_SEL_TGT_NATIVE_SIZE:1275 sel->r = imx283_native_area;1276 return 0;1277 1278 case V4L2_SEL_TGT_CROP_DEFAULT:1279 case V4L2_SEL_TGT_CROP_BOUNDS:1280 sel->r = imx283_active_area;1281 return 0;1282 default:1283 return -EINVAL;1284 }1285}1286 1287static const struct v4l2_subdev_core_ops imx283_core_ops = {1288 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,1289 .unsubscribe_event = v4l2_event_subdev_unsubscribe,1290};1291 1292static const struct v4l2_subdev_video_ops imx283_video_ops = {1293 .s_stream = v4l2_subdev_s_stream_helper,1294};1295 1296static const struct v4l2_subdev_pad_ops imx283_pad_ops = {1297 .enum_mbus_code = imx283_enum_mbus_code,1298 .get_fmt = v4l2_subdev_get_fmt,1299 .set_fmt = imx283_set_pad_format,1300 .get_selection = imx283_get_selection,1301 .enum_frame_size = imx283_enum_frame_size,1302 .enable_streams = imx283_enable_streams,1303 .disable_streams = imx283_disable_streams,1304};1305 1306static const struct v4l2_subdev_internal_ops imx283_internal_ops = {1307 .init_state = imx283_init_state,1308};1309 1310static const struct v4l2_subdev_ops imx283_subdev_ops = {1311 .core = &imx283_core_ops,1312 .video = &imx283_video_ops,1313 .pad = &imx283_pad_ops,1314};1315 1316/* Initialize control handlers */1317static int imx283_init_controls(struct imx283 *imx283)1318{1319 struct v4l2_ctrl_handler *ctrl_hdlr;1320 struct v4l2_fwnode_device_properties props;1321 struct v4l2_ctrl *link_freq;1322 const struct imx283_mode *mode = &supported_modes_12bit[0];1323 u64 min_hblank, max_hblank, def_hblank;1324 u64 pixel_rate;1325 int ret;1326 1327 ctrl_hdlr = &imx283->ctrl_handler;1328 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 16);1329 if (ret)1330 return ret;1331 1332 /*1333 * Create the controls here, but mode specific limits are setup1334 * in the imx283_set_framing_limits() call below.1335 */1336 1337 /* By default, PIXEL_RATE is read only */1338 pixel_rate = imx283_pixel_rate(imx283, mode);1339 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,1340 V4L2_CID_PIXEL_RATE, pixel_rate,1341 pixel_rate, 1, pixel_rate);1342 1343 link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &imx283_ctrl_ops,1344 V4L2_CID_LINK_FREQ,1345 __fls(imx283->link_freq_bitmap),1346 __ffs(imx283->link_freq_bitmap),1347 link_frequencies);1348 if (link_freq)1349 link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;1350 1351 /* Initialise vblank/hblank/exposure based on the current mode. */1352 imx283->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,1353 V4L2_CID_VBLANK,1354 mode->min_vmax - mode->height,1355 IMX283_VMAX_MAX, 1,1356 mode->default_vmax - mode->height);1357 1358 min_hblank = mode->min_hmax - mode->width;1359 max_hblank = imx283_iclk_to_pix(pixel_rate, IMX283_HMAX_MAX) - mode->width;1360 def_hblank = mode->default_hmax - mode->width;1361 imx283->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,1362 V4L2_CID_HBLANK, min_hblank, max_hblank,1363 1, def_hblank);1364 1365 imx283->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops,1366 V4L2_CID_EXPOSURE,1367 IMX283_EXPOSURE_MIN,1368 IMX283_EXPOSURE_MAX,1369 IMX283_EXPOSURE_STEP,1370 IMX283_EXPOSURE_DEFAULT);1371 1372 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,1373 IMX283_ANA_GAIN_MIN, IMX283_ANA_GAIN_MAX,1374 IMX283_ANA_GAIN_STEP, IMX283_ANA_GAIN_DEFAULT);1375 1376 v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_DIGITAL_GAIN,1377 IMX283_DGTL_GAIN_MIN, IMX283_DGTL_GAIN_MAX,1378 IMX283_DGTL_GAIN_STEP, IMX283_DGTL_GAIN_DEFAULT);1379 1380 imx283->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &imx283_ctrl_ops, V4L2_CID_VFLIP,1381 0, 1, 1, 0);1382 if (imx283->vflip)1383 imx283->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT;1384 1385 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &imx283_ctrl_ops,1386 V4L2_CID_TEST_PATTERN,1387 ARRAY_SIZE(imx283_tpg_menu) - 1,1388 0, 0, imx283_tpg_menu);1389 1390 if (ctrl_hdlr->error) {1391 ret = ctrl_hdlr->error;1392 dev_err(imx283->dev, "control init failed (%d)\n", ret);1393 goto error;1394 }1395 1396 ret = v4l2_fwnode_device_parse(imx283->dev, &props);1397 if (ret)1398 goto error;1399 1400 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &imx283_ctrl_ops,1401 &props);1402 if (ret)1403 goto error;1404 1405 imx283->sd.ctrl_handler = ctrl_hdlr;1406 1407 mutex_lock(imx283->ctrl_handler.lock);1408 1409 /* Setup exposure and frame/line length limits. */1410 imx283_set_framing_limits(imx283, mode);1411 1412 mutex_unlock(imx283->ctrl_handler.lock);1413 1414 return 0;1415 1416error:1417 v4l2_ctrl_handler_free(ctrl_hdlr);1418 1419 return ret;1420}1421 1422static int imx283_parse_endpoint(struct imx283 *imx283)1423{1424 struct fwnode_handle *fwnode;1425 struct v4l2_fwnode_endpoint bus_cfg = {1426 .bus_type = V4L2_MBUS_CSI2_DPHY1427 };1428 struct fwnode_handle *ep;1429 int ret;1430 1431 fwnode = dev_fwnode(imx283->dev);1432 ep = fwnode_graph_get_next_endpoint(fwnode, NULL);1433 if (!ep) {1434 dev_err(imx283->dev, "Failed to get next endpoint\n");1435 return -ENXIO;1436 }1437 1438 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);1439 fwnode_handle_put(ep);1440 if (ret)1441 return ret;1442 1443 if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {1444 dev_err(imx283->dev,1445 "number of CSI2 data lanes %d is not supported\n",1446 bus_cfg.bus.mipi_csi2.num_data_lanes);1447 ret = -EINVAL;1448 goto done_endpoint_free;1449 }1450 1451 ret = v4l2_link_freq_to_bitmap(imx283->dev, bus_cfg.link_frequencies,1452 bus_cfg.nr_of_link_frequencies,1453 link_frequencies, ARRAY_SIZE(link_frequencies),1454 &imx283->link_freq_bitmap);1455 1456done_endpoint_free:1457 v4l2_fwnode_endpoint_free(&bus_cfg);1458 1459 return ret;1460};1461 1462static int imx283_probe(struct i2c_client *client)1463{1464 struct imx283 *imx283;1465 unsigned int i;1466 unsigned int xclk_freq;1467 int ret;1468 1469 imx283 = devm_kzalloc(&client->dev, sizeof(*imx283), GFP_KERNEL);1470 if (!imx283)1471 return -ENOMEM;1472 1473 imx283->dev = &client->dev;1474 1475 v4l2_i2c_subdev_init(&imx283->sd, client, &imx283_subdev_ops);1476 1477 imx283->cci = devm_cci_regmap_init_i2c(client, 16);1478 if (IS_ERR(imx283->cci)) {1479 ret = PTR_ERR(imx283->cci);1480 dev_err(imx283->dev, "failed to initialize CCI: %d\n", ret);1481 return ret;1482 }1483 1484 /* Get system clock (xclk) */1485 imx283->xclk = devm_clk_get(imx283->dev, NULL);1486 if (IS_ERR(imx283->xclk)) {1487 return dev_err_probe(imx283->dev, PTR_ERR(imx283->xclk),1488 "failed to get xclk\n");1489 }1490 1491 xclk_freq = clk_get_rate(imx283->xclk);1492 for (i = 0; i < ARRAY_SIZE(imx283_frequencies); i++) {1493 if (xclk_freq == imx283_frequencies[i].mhz) {1494 imx283->freq = &imx283_frequencies[i];1495 break;1496 }1497 }1498 if (!imx283->freq) {1499 dev_err(imx283->dev, "xclk frequency unsupported: %d Hz\n", xclk_freq);1500 return -EINVAL;1501 }1502 1503 ret = imx283_get_regulators(imx283);1504 if (ret) {1505 return dev_err_probe(imx283->dev, ret,1506 "failed to get regulators\n");1507 }1508 1509 ret = imx283_parse_endpoint(imx283);1510 if (ret) {1511 dev_err(imx283->dev, "failed to parse endpoint configuration\n");1512 return ret;1513 }1514 1515 /* Request optional enable pin */1516 imx283->reset_gpio = devm_gpiod_get_optional(imx283->dev, "reset",1517 GPIOD_OUT_LOW);1518 if (IS_ERR(imx283->reset_gpio))1519 return dev_err_probe(imx283->dev, PTR_ERR(imx283->reset_gpio),1520 "failed to get reset GPIO\n");1521 1522 /*1523 * The sensor must be powered for imx283_identify_module()1524 * to be able to read the CHIP_ID register1525 */1526 ret = imx283_power_on(imx283);1527 if (ret)1528 return ret;1529 1530 ret = imx283_identify_module(imx283);1531 if (ret)1532 goto error_power_off;1533 1534 /*1535 * Enable runtime PM with autosuspend. As the device has been powered1536 * manually, mark it as active, and increase the usage count without1537 * resuming the device.1538 */1539 pm_runtime_set_active(imx283->dev);1540 pm_runtime_get_noresume(imx283->dev);1541 pm_runtime_enable(imx283->dev);1542 pm_runtime_set_autosuspend_delay(imx283->dev, 1000);1543 pm_runtime_use_autosuspend(imx283->dev);1544 1545 /* This needs the pm runtime to be registered. */1546 ret = imx283_init_controls(imx283);1547 if (ret)1548 goto error_pm;1549 1550 /* Initialize subdev */1551 imx283->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |1552 V4L2_SUBDEV_FL_HAS_EVENTS;1553 imx283->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;1554 imx283->sd.internal_ops = &imx283_internal_ops;1555 1556 /* Initialize source pads */1557 imx283->pad.flags = MEDIA_PAD_FL_SOURCE;1558 1559 ret = media_entity_pads_init(&imx283->sd.entity, 1, &imx283->pad);1560 if (ret) {1561 dev_err(imx283->dev, "failed to init entity pads: %d\n", ret);1562 goto error_handler_free;1563 }1564 1565 imx283->sd.state_lock = imx283->ctrl_handler.lock;1566 ret = v4l2_subdev_init_finalize(&imx283->sd);1567 if (ret < 0) {1568 dev_err(imx283->dev, "subdev init error: %d\n", ret);1569 goto error_media_entity;1570 }1571 1572 ret = v4l2_async_register_subdev_sensor(&imx283->sd);1573 if (ret < 0) {1574 dev_err(imx283->dev, "failed to register sensor sub-device: %d\n", ret);1575 goto error_subdev_cleanup;1576 }1577 1578 /*1579 * Decrease the PM usage count. The device will get suspended after the1580 * autosuspend delay, turning the power off.1581 */1582 pm_runtime_mark_last_busy(imx283->dev);1583 pm_runtime_put_autosuspend(imx283->dev);1584 1585 return 0;1586 1587error_subdev_cleanup:1588 v4l2_subdev_cleanup(&imx283->sd);1589 1590error_media_entity:1591 media_entity_cleanup(&imx283->sd.entity);1592 1593error_handler_free:1594 v4l2_ctrl_handler_free(imx283->sd.ctrl_handler);1595 1596error_pm:1597 pm_runtime_disable(imx283->dev);1598 pm_runtime_set_suspended(imx283->dev);1599error_power_off:1600 imx283_power_off(imx283);1601 1602 return ret;1603}1604 1605static void imx283_remove(struct i2c_client *client)1606{1607 struct v4l2_subdev *sd = i2c_get_clientdata(client);1608 struct imx283 *imx283 = to_imx283(sd);1609 1610 v4l2_async_unregister_subdev(sd);1611 v4l2_subdev_cleanup(&imx283->sd);1612 media_entity_cleanup(&sd->entity);1613 v4l2_ctrl_handler_free(imx283->sd.ctrl_handler);1614 1615 pm_runtime_disable(imx283->dev);1616 if (!pm_runtime_status_suspended(imx283->dev))1617 imx283_power_off(imx283);1618 pm_runtime_set_suspended(imx283->dev);1619}1620 1621static DEFINE_RUNTIME_DEV_PM_OPS(imx283_pm_ops, imx283_runtime_suspend,1622 imx283_runtime_resume, NULL);1623 1624static const struct of_device_id imx283_dt_ids[] = {1625 { .compatible = "sony,imx283" },1626 { /* sentinel */ }1627};1628MODULE_DEVICE_TABLE(of, imx283_dt_ids);1629 1630static struct i2c_driver imx283_i2c_driver = {1631 .driver = {1632 .name = "imx283",1633 .pm = pm_ptr(&imx283_pm_ops),1634 .of_match_table = imx283_dt_ids,1635 },1636 .probe = imx283_probe,1637 .remove = imx283_remove,1638};1639module_i2c_driver(imx283_i2c_driver);1640 1641MODULE_AUTHOR("Will Whang <will@willwhang.com>");1642MODULE_AUTHOR("Kieran Bingham <kieran.bingham@ideasonboard.com>");1643MODULE_AUTHOR("Umang Jain <umang.jain@ideasonboard.com>");1644MODULE_DESCRIPTION("Sony IMX283 Sensor Driver");1645MODULE_LICENSE("GPL");1646