1480 lines · c
1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Driver for the Sony IMX415 CMOS Image Sensor.4 *5 * Copyright (C) 2023 WolfVision GmbH.6 */7 8#include <linux/clk.h>9#include <linux/gpio/consumer.h>10#include <linux/i2c.h>11#include <linux/module.h>12#include <linux/of.h>13#include <linux/pm_runtime.h>14#include <linux/regmap.h>15#include <linux/regulator/consumer.h>16#include <linux/slab.h>17#include <linux/videodev2.h>18 19#include <media/v4l2-cci.h>20#include <media/v4l2-ctrls.h>21#include <media/v4l2-fwnode.h>22#include <media/v4l2-subdev.h>23 24#define IMX415_PIXEL_ARRAY_TOP 025#define IMX415_PIXEL_ARRAY_LEFT 026#define IMX415_PIXEL_ARRAY_WIDTH 386427#define IMX415_PIXEL_ARRAY_HEIGHT 219228#define IMX415_PIXEL_ARRAY_VBLANK 5829 30#define IMX415_NUM_CLK_PARAM_REGS 1131 32#define IMX415_MODE CCI_REG8(0x3000)33#define IMX415_MODE_OPERATING (0)34#define IMX415_MODE_STANDBY BIT(0)35#define IMX415_REGHOLD CCI_REG8(0x3001)36#define IMX415_REGHOLD_INVALID (0)37#define IMX415_REGHOLD_VALID BIT(0)38#define IMX415_XMSTA CCI_REG8(0x3002)39#define IMX415_XMSTA_START (0)40#define IMX415_XMSTA_STOP BIT(0)41#define IMX415_BCWAIT_TIME CCI_REG16_LE(0x3008)42#define IMX415_CPWAIT_TIME CCI_REG16_LE(0x300a)43#define IMX415_WINMODE CCI_REG8(0x301c)44#define IMX415_ADDMODE CCI_REG8(0x3022)45#define IMX415_REVERSE CCI_REG8(0x3030)46#define IMX415_HREVERSE_SHIFT (0)47#define IMX415_VREVERSE_SHIFT BIT(0)48#define IMX415_ADBIT CCI_REG8(0x3031)49#define IMX415_MDBIT CCI_REG8(0x3032)50#define IMX415_SYS_MODE CCI_REG8(0x3033)51#define IMX415_OUTSEL CCI_REG8(0x30c0)52#define IMX415_DRV CCI_REG8(0x30c1)53#define IMX415_VMAX CCI_REG24_LE(0x3024)54#define IMX415_HMAX CCI_REG16_LE(0x3028)55#define IMX415_SHR0 CCI_REG24_LE(0x3050)56#define IMX415_GAIN_PCG_0 CCI_REG16_LE(0x3090)57#define IMX415_AGAIN_MIN 058#define IMX415_AGAIN_MAX 10059#define IMX415_AGAIN_STEP 160#define IMX415_BLKLEVEL CCI_REG16_LE(0x30e2)61#define IMX415_BLKLEVEL_DEFAULT 5062#define IMX415_TPG_EN_DUOUT CCI_REG8(0x30e4)63#define IMX415_TPG_PATSEL_DUOUT CCI_REG8(0x30e6)64#define IMX415_TPG_COLORWIDTH CCI_REG8(0x30e8)65#define IMX415_TESTCLKEN_MIPI CCI_REG8(0x3110)66#define IMX415_INCKSEL1 CCI_REG8(0x3115)67#define IMX415_INCKSEL2 CCI_REG8(0x3116)68#define IMX415_INCKSEL3 CCI_REG16_LE(0x3118)69#define IMX415_INCKSEL4 CCI_REG16_LE(0x311a)70#define IMX415_INCKSEL5 CCI_REG8(0x311e)71#define IMX415_DIG_CLP_MODE CCI_REG8(0x32c8)72#define IMX415_WRJ_OPEN CCI_REG8(0x3390)73#define IMX415_SENSOR_INFO CCI_REG16_LE(0x3f12)74#define IMX415_SENSOR_INFO_MASK 0xfff75#define IMX415_CHIP_ID 0x51476#define IMX415_LANEMODE CCI_REG16_LE(0x4001)77#define IMX415_LANEMODE_2 178#define IMX415_LANEMODE_4 379#define IMX415_TXCLKESC_FREQ CCI_REG16_LE(0x4004)80#define IMX415_INCKSEL6 CCI_REG8(0x400c)81#define IMX415_TCLKPOST CCI_REG16_LE(0x4018)82#define IMX415_TCLKPREPARE CCI_REG16_LE(0x401a)83#define IMX415_TCLKTRAIL CCI_REG16_LE(0x401c)84#define IMX415_TCLKZERO CCI_REG16_LE(0x401e)85#define IMX415_THSPREPARE CCI_REG16_LE(0x4020)86#define IMX415_THSZERO CCI_REG16_LE(0x4022)87#define IMX415_THSTRAIL CCI_REG16_LE(0x4024)88#define IMX415_THSEXIT CCI_REG16_LE(0x4026)89#define IMX415_TLPX CCI_REG16_LE(0x4028)90#define IMX415_INCKSEL7 CCI_REG8(0x4074)91 92static const char *const imx415_supply_names[] = {93 "dvdd",94 "ovdd",95 "avdd",96};97 98/*99 * The IMX415 data sheet uses lane rates but v4l2 uses link frequency to100 * describe MIPI CSI-2 speed. This driver uses lane rates wherever possible101 * and converts them to link frequencies by a factor of two when needed.102 */103static const s64 link_freq_menu_items[] = {104 594000000 / 2, 720000000 / 2, 891000000 / 2,105 1440000000 / 2, 1485000000 / 2,106};107 108struct imx415_clk_params {109 u64 lane_rate;110 u64 inck;111 struct cci_reg_sequence regs[IMX415_NUM_CLK_PARAM_REGS];112};113 114/* INCK Settings - includes all lane rate and INCK dependent registers */115static const struct imx415_clk_params imx415_clk_params[] = {116 {117 .lane_rate = 594000000UL,118 .inck = 27000000,119 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },120 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },121 .regs[2] = { IMX415_SYS_MODE, 0x7 },122 .regs[3] = { IMX415_INCKSEL1, 0x00 },123 .regs[4] = { IMX415_INCKSEL2, 0x23 },124 .regs[5] = { IMX415_INCKSEL3, 0x084 },125 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },126 .regs[7] = { IMX415_INCKSEL5, 0x23 },127 .regs[8] = { IMX415_INCKSEL6, 0x0 },128 .regs[9] = { IMX415_INCKSEL7, 0x1 },129 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },130 },131 {132 .lane_rate = 594000000UL,133 .inck = 37125000,134 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },135 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },136 .regs[2] = { IMX415_SYS_MODE, 0x7 },137 .regs[3] = { IMX415_INCKSEL1, 0x00 },138 .regs[4] = { IMX415_INCKSEL2, 0x24 },139 .regs[5] = { IMX415_INCKSEL3, 0x080 },140 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },141 .regs[7] = { IMX415_INCKSEL5, 0x24 },142 .regs[8] = { IMX415_INCKSEL6, 0x0 },143 .regs[9] = { IMX415_INCKSEL7, 0x1 },144 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0984 },145 },146 {147 .lane_rate = 594000000UL,148 .inck = 74250000,149 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },150 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },151 .regs[2] = { IMX415_SYS_MODE, 0x7 },152 .regs[3] = { IMX415_INCKSEL1, 0x00 },153 .regs[4] = { IMX415_INCKSEL2, 0x28 },154 .regs[5] = { IMX415_INCKSEL3, 0x080 },155 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },156 .regs[7] = { IMX415_INCKSEL5, 0x28 },157 .regs[8] = { IMX415_INCKSEL6, 0x0 },158 .regs[9] = { IMX415_INCKSEL7, 0x1 },159 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },160 },161 {162 .lane_rate = 720000000UL,163 .inck = 24000000,164 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 },165 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B },166 .regs[2] = { IMX415_SYS_MODE, 0x9 },167 .regs[3] = { IMX415_INCKSEL1, 0x00 },168 .regs[4] = { IMX415_INCKSEL2, 0x23 },169 .regs[5] = { IMX415_INCKSEL3, 0x0B4 },170 .regs[6] = { IMX415_INCKSEL4, 0x0FC },171 .regs[7] = { IMX415_INCKSEL5, 0x23 },172 .regs[8] = { IMX415_INCKSEL6, 0x0 },173 .regs[9] = { IMX415_INCKSEL7, 0x1 },174 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },175 },176 {177 .lane_rate = 720000000UL,178 .inck = 72000000,179 .regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },180 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },181 .regs[2] = { IMX415_SYS_MODE, 0x9 },182 .regs[3] = { IMX415_INCKSEL1, 0x00 },183 .regs[4] = { IMX415_INCKSEL2, 0x28 },184 .regs[5] = { IMX415_INCKSEL3, 0x0A0 },185 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },186 .regs[7] = { IMX415_INCKSEL5, 0x28 },187 .regs[8] = { IMX415_INCKSEL6, 0x0 },188 .regs[9] = { IMX415_INCKSEL7, 0x1 },189 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },190 },191 {192 .lane_rate = 891000000UL,193 .inck = 27000000,194 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },195 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },196 .regs[2] = { IMX415_SYS_MODE, 0x5 },197 .regs[3] = { IMX415_INCKSEL1, 0x00 },198 .regs[4] = { IMX415_INCKSEL2, 0x23 },199 .regs[5] = { IMX415_INCKSEL3, 0x0C6 },200 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },201 .regs[7] = { IMX415_INCKSEL5, 0x23 },202 .regs[8] = { IMX415_INCKSEL6, 0x0 },203 .regs[9] = { IMX415_INCKSEL7, 0x1 },204 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },205 },206 {207 .lane_rate = 891000000UL,208 .inck = 37125000,209 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },210 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },211 .regs[2] = { IMX415_SYS_MODE, 0x5 },212 .regs[3] = { IMX415_INCKSEL1, 0x00 },213 .regs[4] = { IMX415_INCKSEL2, 0x24 },214 .regs[5] = { IMX415_INCKSEL3, 0x0C0 },215 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },216 .regs[7] = { IMX415_INCKSEL5, 0x24 },217 .regs[8] = { IMX415_INCKSEL6, 0x0 },218 .regs[9] = { IMX415_INCKSEL7, 0x1 },219 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },220 },221 {222 .lane_rate = 891000000UL,223 .inck = 74250000,224 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },225 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },226 .regs[2] = { IMX415_SYS_MODE, 0x5 },227 .regs[3] = { IMX415_INCKSEL1, 0x00 },228 .regs[4] = { IMX415_INCKSEL2, 0x28 },229 .regs[5] = { IMX415_INCKSEL3, 0x0C0 },230 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },231 .regs[7] = { IMX415_INCKSEL5, 0x28 },232 .regs[8] = { IMX415_INCKSEL6, 0x0 },233 .regs[9] = { IMX415_INCKSEL7, 0x1 },234 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },235 },236 {237 .lane_rate = 1440000000UL,238 .inck = 24000000,239 .regs[0] = { IMX415_BCWAIT_TIME, 0x054 },240 .regs[1] = { IMX415_CPWAIT_TIME, 0x03B },241 .regs[2] = { IMX415_SYS_MODE, 0x8 },242 .regs[3] = { IMX415_INCKSEL1, 0x00 },243 .regs[4] = { IMX415_INCKSEL2, 0x23 },244 .regs[5] = { IMX415_INCKSEL3, 0x0B4 },245 .regs[6] = { IMX415_INCKSEL4, 0x0FC },246 .regs[7] = { IMX415_INCKSEL5, 0x23 },247 .regs[8] = { IMX415_INCKSEL6, 0x1 },248 .regs[9] = { IMX415_INCKSEL7, 0x0 },249 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },250 },251 {252 .lane_rate = 1440000000UL,253 .inck = 72000000,254 .regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },255 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },256 .regs[2] = { IMX415_SYS_MODE, 0x8 },257 .regs[3] = { IMX415_INCKSEL1, 0x00 },258 .regs[4] = { IMX415_INCKSEL2, 0x28 },259 .regs[5] = { IMX415_INCKSEL3, 0x0A0 },260 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },261 .regs[7] = { IMX415_INCKSEL5, 0x28 },262 .regs[8] = { IMX415_INCKSEL6, 0x1 },263 .regs[9] = { IMX415_INCKSEL7, 0x0 },264 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },265 },266 {267 .lane_rate = 1485000000UL,268 .inck = 27000000,269 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },270 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },271 .regs[2] = { IMX415_SYS_MODE, 0x8 },272 .regs[3] = { IMX415_INCKSEL1, 0x00 },273 .regs[4] = { IMX415_INCKSEL2, 0x23 },274 .regs[5] = { IMX415_INCKSEL3, 0x0A5 },275 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },276 .regs[7] = { IMX415_INCKSEL5, 0x23 },277 .regs[8] = { IMX415_INCKSEL6, 0x1 },278 .regs[9] = { IMX415_INCKSEL7, 0x0 },279 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },280 },281 {282 .lane_rate = 1485000000UL,283 .inck = 37125000,284 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },285 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },286 .regs[2] = { IMX415_SYS_MODE, 0x8 },287 .regs[3] = { IMX415_INCKSEL1, 0x00 },288 .regs[4] = { IMX415_INCKSEL2, 0x24 },289 .regs[5] = { IMX415_INCKSEL3, 0x0A0 },290 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },291 .regs[7] = { IMX415_INCKSEL5, 0x24 },292 .regs[8] = { IMX415_INCKSEL6, 0x1 },293 .regs[9] = { IMX415_INCKSEL7, 0x0 },294 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },295 },296 {297 .lane_rate = 1485000000UL,298 .inck = 74250000,299 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },300 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },301 .regs[2] = { IMX415_SYS_MODE, 0x8 },302 .regs[3] = { IMX415_INCKSEL1, 0x00 },303 .regs[4] = { IMX415_INCKSEL2, 0x28 },304 .regs[5] = { IMX415_INCKSEL3, 0x0A0 },305 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },306 .regs[7] = { IMX415_INCKSEL5, 0x28 },307 .regs[8] = { IMX415_INCKSEL6, 0x1 },308 .regs[9] = { IMX415_INCKSEL7, 0x0 },309 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },310 },311 {312 .lane_rate = 1782000000UL,313 .inck = 27000000,314 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },315 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },316 .regs[2] = { IMX415_SYS_MODE, 0x4 },317 .regs[3] = { IMX415_INCKSEL1, 0x00 },318 .regs[4] = { IMX415_INCKSEL2, 0x23 },319 .regs[5] = { IMX415_INCKSEL3, 0x0C6 },320 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },321 .regs[7] = { IMX415_INCKSEL5, 0x23 },322 .regs[8] = { IMX415_INCKSEL6, 0x1 },323 .regs[9] = { IMX415_INCKSEL7, 0x0 },324 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },325 },326 {327 .lane_rate = 1782000000UL,328 .inck = 37125000,329 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },330 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },331 .regs[2] = { IMX415_SYS_MODE, 0x4 },332 .regs[3] = { IMX415_INCKSEL1, 0x00 },333 .regs[4] = { IMX415_INCKSEL2, 0x24 },334 .regs[5] = { IMX415_INCKSEL3, 0x0C0 },335 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },336 .regs[7] = { IMX415_INCKSEL5, 0x24 },337 .regs[8] = { IMX415_INCKSEL6, 0x1 },338 .regs[9] = { IMX415_INCKSEL7, 0x0 },339 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },340 },341 {342 .lane_rate = 1782000000UL,343 .inck = 74250000,344 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },345 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },346 .regs[2] = { IMX415_SYS_MODE, 0x4 },347 .regs[3] = { IMX415_INCKSEL1, 0x00 },348 .regs[4] = { IMX415_INCKSEL2, 0x28 },349 .regs[5] = { IMX415_INCKSEL3, 0x0C0 },350 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },351 .regs[7] = { IMX415_INCKSEL5, 0x28 },352 .regs[8] = { IMX415_INCKSEL6, 0x1 },353 .regs[9] = { IMX415_INCKSEL7, 0x0 },354 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },355 },356 {357 .lane_rate = 2079000000UL,358 .inck = 27000000,359 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },360 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },361 .regs[2] = { IMX415_SYS_MODE, 0x2 },362 .regs[3] = { IMX415_INCKSEL1, 0x00 },363 .regs[4] = { IMX415_INCKSEL2, 0x23 },364 .regs[5] = { IMX415_INCKSEL3, 0x0E7 },365 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },366 .regs[7] = { IMX415_INCKSEL5, 0x23 },367 .regs[8] = { IMX415_INCKSEL6, 0x1 },368 .regs[9] = { IMX415_INCKSEL7, 0x0 },369 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },370 },371 {372 .lane_rate = 2079000000UL,373 .inck = 37125000,374 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },375 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },376 .regs[2] = { IMX415_SYS_MODE, 0x2 },377 .regs[3] = { IMX415_INCKSEL1, 0x00 },378 .regs[4] = { IMX415_INCKSEL2, 0x24 },379 .regs[5] = { IMX415_INCKSEL3, 0x0E0 },380 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },381 .regs[7] = { IMX415_INCKSEL5, 0x24 },382 .regs[8] = { IMX415_INCKSEL6, 0x1 },383 .regs[9] = { IMX415_INCKSEL7, 0x0 },384 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },385 },386 {387 .lane_rate = 2079000000UL,388 .inck = 74250000,389 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },390 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },391 .regs[2] = { IMX415_SYS_MODE, 0x2 },392 .regs[3] = { IMX415_INCKSEL1, 0x00 },393 .regs[4] = { IMX415_INCKSEL2, 0x28 },394 .regs[5] = { IMX415_INCKSEL3, 0x0E0 },395 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },396 .regs[7] = { IMX415_INCKSEL5, 0x28 },397 .regs[8] = { IMX415_INCKSEL6, 0x1 },398 .regs[9] = { IMX415_INCKSEL7, 0x0 },399 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },400 },401 {402 .lane_rate = 2376000000UL,403 .inck = 27000000,404 .regs[0] = { IMX415_BCWAIT_TIME, 0x05D },405 .regs[1] = { IMX415_CPWAIT_TIME, 0x042 },406 .regs[2] = { IMX415_SYS_MODE, 0x0 },407 .regs[3] = { IMX415_INCKSEL1, 0x00 },408 .regs[4] = { IMX415_INCKSEL2, 0x23 },409 .regs[5] = { IMX415_INCKSEL3, 0x108 },410 .regs[6] = { IMX415_INCKSEL4, 0x0E7 },411 .regs[7] = { IMX415_INCKSEL5, 0x23 },412 .regs[8] = { IMX415_INCKSEL6, 0x1 },413 .regs[9] = { IMX415_INCKSEL7, 0x0 },414 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },415 },416 {417 .lane_rate = 2376000000UL,418 .inck = 37125000,419 .regs[0] = { IMX415_BCWAIT_TIME, 0x07F },420 .regs[1] = { IMX415_CPWAIT_TIME, 0x05B },421 .regs[2] = { IMX415_SYS_MODE, 0x0 },422 .regs[3] = { IMX415_INCKSEL1, 0x00 },423 .regs[4] = { IMX415_INCKSEL2, 0x24 },424 .regs[5] = { IMX415_INCKSEL3, 0x100 },425 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },426 .regs[7] = { IMX415_INCKSEL5, 0x24 },427 .regs[8] = { IMX415_INCKSEL6, 0x1 },428 .regs[9] = { IMX415_INCKSEL7, 0x0 },429 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },430 },431 {432 .lane_rate = 2376000000UL,433 .inck = 74250000,434 .regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },435 .regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },436 .regs[2] = { IMX415_SYS_MODE, 0x0 },437 .regs[3] = { IMX415_INCKSEL1, 0x00 },438 .regs[4] = { IMX415_INCKSEL2, 0x28 },439 .regs[5] = { IMX415_INCKSEL3, 0x100 },440 .regs[6] = { IMX415_INCKSEL4, 0x0E0 },441 .regs[7] = { IMX415_INCKSEL5, 0x28 },442 .regs[8] = { IMX415_INCKSEL6, 0x1 },443 .regs[9] = { IMX415_INCKSEL7, 0x0 },444 .regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },445 },446};447 448/* all-pixel 2-lane 720 Mbps 15.74 Hz mode */449static const struct cci_reg_sequence imx415_mode_2_720[] = {450 { IMX415_VMAX, 0x08CA },451 { IMX415_HMAX, 0x07F0 },452 { IMX415_LANEMODE, IMX415_LANEMODE_2 },453 { IMX415_TCLKPOST, 0x006F },454 { IMX415_TCLKPREPARE, 0x002F },455 { IMX415_TCLKTRAIL, 0x002F },456 { IMX415_TCLKZERO, 0x00BF },457 { IMX415_THSPREPARE, 0x002F },458 { IMX415_THSZERO, 0x0057 },459 { IMX415_THSTRAIL, 0x002F },460 { IMX415_THSEXIT, 0x004F },461 { IMX415_TLPX, 0x0027 },462};463 464/* all-pixel 2-lane 1440 Mbps 30.01 Hz mode */465static const struct cci_reg_sequence imx415_mode_2_1440[] = {466 { IMX415_VMAX, 0x08CA },467 { IMX415_HMAX, 0x042A },468 { IMX415_LANEMODE, IMX415_LANEMODE_2 },469 { IMX415_TCLKPOST, 0x009F },470 { IMX415_TCLKPREPARE, 0x0057 },471 { IMX415_TCLKTRAIL, 0x0057 },472 { IMX415_TCLKZERO, 0x0187 },473 { IMX415_THSPREPARE, 0x005F },474 { IMX415_THSZERO, 0x00A7 },475 { IMX415_THSTRAIL, 0x005F },476 { IMX415_THSEXIT, 0x0097 },477 { IMX415_TLPX, 0x004F },478};479 480/* all-pixel 4-lane 891 Mbps 30 Hz mode */481static const struct cci_reg_sequence imx415_mode_4_891[] = {482 { IMX415_VMAX, 0x08CA },483 { IMX415_HMAX, 0x044C },484 { IMX415_LANEMODE, IMX415_LANEMODE_4 },485 { IMX415_TCLKPOST, 0x007F },486 { IMX415_TCLKPREPARE, 0x0037 },487 { IMX415_TCLKTRAIL, 0x0037 },488 { IMX415_TCLKZERO, 0x00F7 },489 { IMX415_THSPREPARE, 0x003F },490 { IMX415_THSZERO, 0x006F },491 { IMX415_THSTRAIL, 0x003F },492 { IMX415_THSEXIT, 0x005F },493 { IMX415_TLPX, 0x002F },494};495 496struct imx415_mode_reg_list {497 u32 num_of_regs;498 const struct cci_reg_sequence *regs;499};500 501/*502 * Mode : number of lanes, lane rate and frame rate dependent settings503 *504 * pixel_rate and hmax_pix are needed to calculate hblank for the v4l2 ctrl505 * interface. These values can not be found in the data sheet and should be506 * treated as virtual values. Use following table when adding new modes.507 *508 * lane_rate lanes fps hmax_pix pixel_rate509 *510 * 594 2 10.000 4400 99000000511 * 891 2 15.000 4400 148500000512 * 720 2 15.748 4064 144000000513 * 1782 2 30.000 4400 297000000514 * 2079 2 30.000 4400 297000000515 * 1440 2 30.019 4510 304615385516 *517 * 594 4 20.000 5500 247500000518 * 594 4 25.000 4400 247500000519 * 720 4 25.000 4400 247500000520 * 720 4 30.019 4510 304615385521 * 891 4 30.000 4400 297000000522 * 1440 4 30.019 4510 304615385523 * 1440 4 60.038 4510 609230769524 * 1485 4 60.000 4400 594000000525 * 1782 4 60.000 4400 594000000526 * 2079 4 60.000 4400 594000000527 * 2376 4 90.164 4392 891000000528 */529struct imx415_mode {530 u64 lane_rate;531 u32 lanes;532 u32 hmax_pix;533 u64 pixel_rate;534 struct imx415_mode_reg_list reg_list;535};536 537/* mode configs */538static const struct imx415_mode supported_modes[] = {539 {540 .lane_rate = 720000000,541 .lanes = 2,542 .hmax_pix = 4064,543 .pixel_rate = 144000000,544 .reg_list = {545 .num_of_regs = ARRAY_SIZE(imx415_mode_2_720),546 .regs = imx415_mode_2_720,547 },548 },549 {550 .lane_rate = 1440000000,551 .lanes = 2,552 .hmax_pix = 4510,553 .pixel_rate = 304615385,554 .reg_list = {555 .num_of_regs = ARRAY_SIZE(imx415_mode_2_1440),556 .regs = imx415_mode_2_1440,557 },558 },559 {560 .lane_rate = 891000000,561 .lanes = 4,562 .hmax_pix = 4400,563 .pixel_rate = 297000000,564 .reg_list = {565 .num_of_regs = ARRAY_SIZE(imx415_mode_4_891),566 .regs = imx415_mode_4_891,567 },568 },569};570 571static const char *const imx415_test_pattern_menu[] = {572 "disabled",573 "solid black",574 "solid white",575 "solid dark gray",576 "solid light gray",577 "stripes light/dark grey",578 "stripes dark/light grey",579 "stripes black/dark grey",580 "stripes dark grey/black",581 "stripes black/white",582 "stripes white/black",583 "horizontal color bar",584 "vertical color bar",585};586 587struct imx415 {588 struct device *dev;589 struct clk *clk;590 struct regulator_bulk_data supplies[ARRAY_SIZE(imx415_supply_names)];591 struct gpio_desc *reset;592 struct regmap *regmap;593 594 const struct imx415_clk_params *clk_params;595 596 struct v4l2_subdev subdev;597 struct media_pad pad;598 599 struct v4l2_ctrl_handler ctrls;600 struct v4l2_ctrl *vblank;601 struct v4l2_ctrl *hflip;602 struct v4l2_ctrl *vflip;603 604 unsigned int cur_mode;605 unsigned int num_data_lanes;606};607 608/*609 * This table includes fixed register settings and a bunch of undocumented610 * registers that have to be set to another value than default.611 */612static const struct cci_reg_sequence imx415_init_table[] = {613 /* use all-pixel readout mode, no flip */614 { IMX415_WINMODE, 0x00 },615 { IMX415_ADDMODE, 0x00 },616 { IMX415_REVERSE, 0x00 },617 /* use RAW 10-bit mode */618 { IMX415_ADBIT, 0x00 },619 { IMX415_MDBIT, 0x00 },620 /* output VSYNC on XVS and low on XHS */621 { IMX415_OUTSEL, 0x22 },622 { IMX415_DRV, 0x00 },623 624 /* SONY magic registers */625 { CCI_REG8(0x32D4), 0x21 },626 { CCI_REG8(0x32EC), 0xA1 },627 { CCI_REG8(0x3452), 0x7F },628 { CCI_REG8(0x3453), 0x03 },629 { CCI_REG8(0x358A), 0x04 },630 { CCI_REG8(0x35A1), 0x02 },631 { CCI_REG8(0x36BC), 0x0C },632 { CCI_REG8(0x36CC), 0x53 },633 { CCI_REG8(0x36CD), 0x00 },634 { CCI_REG8(0x36CE), 0x3C },635 { CCI_REG8(0x36D0), 0x8C },636 { CCI_REG8(0x36D1), 0x00 },637 { CCI_REG8(0x36D2), 0x71 },638 { CCI_REG8(0x36D4), 0x3C },639 { CCI_REG8(0x36D6), 0x53 },640 { CCI_REG8(0x36D7), 0x00 },641 { CCI_REG8(0x36D8), 0x71 },642 { CCI_REG8(0x36DA), 0x8C },643 { CCI_REG8(0x36DB), 0x00 },644 { CCI_REG8(0x3724), 0x02 },645 { CCI_REG8(0x3726), 0x02 },646 { CCI_REG8(0x3732), 0x02 },647 { CCI_REG8(0x3734), 0x03 },648 { CCI_REG8(0x3736), 0x03 },649 { CCI_REG8(0x3742), 0x03 },650 { CCI_REG8(0x3862), 0xE0 },651 { CCI_REG8(0x38CC), 0x30 },652 { CCI_REG8(0x38CD), 0x2F },653 { CCI_REG8(0x395C), 0x0C },654 { CCI_REG8(0x3A42), 0xD1 },655 { CCI_REG8(0x3A4C), 0x77 },656 { CCI_REG8(0x3AE0), 0x02 },657 { CCI_REG8(0x3AEC), 0x0C },658 { CCI_REG8(0x3B00), 0x2E },659 { CCI_REG8(0x3B06), 0x29 },660 { CCI_REG8(0x3B98), 0x25 },661 { CCI_REG8(0x3B99), 0x21 },662 { CCI_REG8(0x3B9B), 0x13 },663 { CCI_REG8(0x3B9C), 0x13 },664 { CCI_REG8(0x3B9D), 0x13 },665 { CCI_REG8(0x3B9E), 0x13 },666 { CCI_REG8(0x3BA1), 0x00 },667 { CCI_REG8(0x3BA2), 0x06 },668 { CCI_REG8(0x3BA3), 0x0B },669 { CCI_REG8(0x3BA4), 0x10 },670 { CCI_REG8(0x3BA5), 0x14 },671 { CCI_REG8(0x3BA6), 0x18 },672 { CCI_REG8(0x3BA7), 0x1A },673 { CCI_REG8(0x3BA8), 0x1A },674 { CCI_REG8(0x3BA9), 0x1A },675 { CCI_REG8(0x3BAC), 0xED },676 { CCI_REG8(0x3BAD), 0x01 },677 { CCI_REG8(0x3BAE), 0xF6 },678 { CCI_REG8(0x3BAF), 0x02 },679 { CCI_REG8(0x3BB0), 0xA2 },680 { CCI_REG8(0x3BB1), 0x03 },681 { CCI_REG8(0x3BB2), 0xE0 },682 { CCI_REG8(0x3BB3), 0x03 },683 { CCI_REG8(0x3BB4), 0xE0 },684 { CCI_REG8(0x3BB5), 0x03 },685 { CCI_REG8(0x3BB6), 0xE0 },686 { CCI_REG8(0x3BB7), 0x03 },687 { CCI_REG8(0x3BB8), 0xE0 },688 { CCI_REG8(0x3BBA), 0xE0 },689 { CCI_REG8(0x3BBC), 0xDA },690 { CCI_REG8(0x3BBE), 0x88 },691 { CCI_REG8(0x3BC0), 0x44 },692 { CCI_REG8(0x3BC2), 0x7B },693 { CCI_REG8(0x3BC4), 0xA2 },694 { CCI_REG8(0x3BC8), 0xBD },695 { CCI_REG8(0x3BCA), 0xBD },696};697 698static inline struct imx415 *to_imx415(struct v4l2_subdev *sd)699{700 return container_of(sd, struct imx415, subdev);701}702 703static int imx415_set_testpattern(struct imx415 *sensor, int val)704{705 int ret = 0;706 707 if (val) {708 cci_write(sensor->regmap, IMX415_BLKLEVEL, 0x00, &ret);709 cci_write(sensor->regmap, IMX415_TPG_EN_DUOUT, 0x01, &ret);710 cci_write(sensor->regmap, IMX415_TPG_PATSEL_DUOUT,711 val - 1, &ret);712 cci_write(sensor->regmap, IMX415_TPG_COLORWIDTH, 0x01, &ret);713 cci_write(sensor->regmap, IMX415_TESTCLKEN_MIPI, 0x20, &ret);714 cci_write(sensor->regmap, IMX415_DIG_CLP_MODE, 0x00, &ret);715 cci_write(sensor->regmap, IMX415_WRJ_OPEN, 0x00, &ret);716 } else {717 cci_write(sensor->regmap, IMX415_BLKLEVEL,718 IMX415_BLKLEVEL_DEFAULT, &ret);719 cci_write(sensor->regmap, IMX415_TPG_EN_DUOUT, 0x00, &ret);720 cci_write(sensor->regmap, IMX415_TESTCLKEN_MIPI, 0x00, &ret);721 cci_write(sensor->regmap, IMX415_DIG_CLP_MODE, 0x01, &ret);722 cci_write(sensor->regmap, IMX415_WRJ_OPEN, 0x01, &ret);723 }724 return 0;725}726 727static int imx415_s_ctrl(struct v4l2_ctrl *ctrl)728{729 struct imx415 *sensor = container_of(ctrl->handler, struct imx415,730 ctrls);731 const struct v4l2_mbus_framefmt *format;732 struct v4l2_subdev_state *state;733 unsigned int vmax;734 unsigned int flip;735 int ret;736 737 if (!pm_runtime_get_if_in_use(sensor->dev))738 return 0;739 740 state = v4l2_subdev_get_locked_active_state(&sensor->subdev);741 format = v4l2_subdev_state_get_format(state, 0);742 743 switch (ctrl->id) {744 case V4L2_CID_EXPOSURE:745 /* clamp the exposure value to VMAX. */746 vmax = format->height + sensor->vblank->cur.val;747 ctrl->val = min_t(int, ctrl->val, vmax);748 ret = cci_write(sensor->regmap, IMX415_SHR0,749 vmax - ctrl->val, NULL);750 break;751 752 case V4L2_CID_ANALOGUE_GAIN:753 /* analogue gain in 0.3 dB step size */754 ret = cci_write(sensor->regmap, IMX415_GAIN_PCG_0,755 ctrl->val, NULL);756 break;757 758 case V4L2_CID_HFLIP:759 case V4L2_CID_VFLIP:760 flip = (sensor->hflip->val << IMX415_HREVERSE_SHIFT) |761 (sensor->vflip->val << IMX415_VREVERSE_SHIFT);762 ret = cci_write(sensor->regmap, IMX415_REVERSE, flip, NULL);763 break;764 765 case V4L2_CID_TEST_PATTERN:766 ret = imx415_set_testpattern(sensor, ctrl->val);767 break;768 769 default:770 ret = -EINVAL;771 break;772 }773 774 pm_runtime_put(sensor->dev);775 776 return ret;777}778 779static const struct v4l2_ctrl_ops imx415_ctrl_ops = {780 .s_ctrl = imx415_s_ctrl,781};782 783static int imx415_ctrls_init(struct imx415 *sensor)784{785 struct v4l2_fwnode_device_properties props;786 struct v4l2_ctrl *ctrl;787 u64 pixel_rate = supported_modes[sensor->cur_mode].pixel_rate;788 u64 lane_rate = supported_modes[sensor->cur_mode].lane_rate;789 u32 exposure_max = IMX415_PIXEL_ARRAY_HEIGHT +790 IMX415_PIXEL_ARRAY_VBLANK - 8;791 u32 hblank;792 unsigned int i;793 int ret;794 795 ret = v4l2_fwnode_device_parse(sensor->dev, &props);796 if (ret < 0)797 return ret;798 799 v4l2_ctrl_handler_init(&sensor->ctrls, 10);800 801 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); ++i) {802 if (lane_rate == link_freq_menu_items[i] * 2)803 break;804 }805 if (i == ARRAY_SIZE(link_freq_menu_items)) {806 return dev_err_probe(sensor->dev, -EINVAL,807 "lane rate %llu not supported\n",808 lane_rate);809 }810 811 ctrl = v4l2_ctrl_new_int_menu(&sensor->ctrls, &imx415_ctrl_ops,812 V4L2_CID_LINK_FREQ,813 ARRAY_SIZE(link_freq_menu_items) - 1, i,814 link_freq_menu_items);815 816 if (ctrl)817 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;818 819 v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops, V4L2_CID_EXPOSURE,820 4, exposure_max, 1, exposure_max);821 822 v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,823 V4L2_CID_ANALOGUE_GAIN, IMX415_AGAIN_MIN,824 IMX415_AGAIN_MAX, IMX415_AGAIN_STEP,825 IMX415_AGAIN_MIN);826 827 hblank = supported_modes[sensor->cur_mode].hmax_pix -828 IMX415_PIXEL_ARRAY_WIDTH;829 ctrl = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,830 V4L2_CID_HBLANK, hblank, hblank, 1, hblank);831 if (ctrl)832 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;833 834 sensor->vblank = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,835 V4L2_CID_VBLANK,836 IMX415_PIXEL_ARRAY_VBLANK,837 IMX415_PIXEL_ARRAY_VBLANK, 1,838 IMX415_PIXEL_ARRAY_VBLANK);839 if (sensor->vblank)840 sensor->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;841 842 /*843 * The pixel rate used here is a virtual value and can be used for844 * calculating the frame rate together with hblank. It may not845 * necessarily be the physically correct pixel clock.846 */847 v4l2_ctrl_new_std(&sensor->ctrls, NULL, V4L2_CID_PIXEL_RATE, pixel_rate,848 pixel_rate, 1, pixel_rate);849 850 sensor->hflip = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,851 V4L2_CID_HFLIP, 0, 1, 1, 0);852 sensor->vflip = v4l2_ctrl_new_std(&sensor->ctrls, &imx415_ctrl_ops,853 V4L2_CID_VFLIP, 0, 1, 1, 0);854 855 v4l2_ctrl_new_std_menu_items(&sensor->ctrls, &imx415_ctrl_ops,856 V4L2_CID_TEST_PATTERN,857 ARRAY_SIZE(imx415_test_pattern_menu) - 1,858 0, 0, imx415_test_pattern_menu);859 860 v4l2_ctrl_new_fwnode_properties(&sensor->ctrls, &imx415_ctrl_ops,861 &props);862 863 if (sensor->ctrls.error) {864 dev_err_probe(sensor->dev, sensor->ctrls.error,865 "failed to add controls\n");866 v4l2_ctrl_handler_free(&sensor->ctrls);867 return sensor->ctrls.error;868 }869 sensor->subdev.ctrl_handler = &sensor->ctrls;870 871 return 0;872}873 874static int imx415_set_mode(struct imx415 *sensor, int mode)875{876 int ret = 0;877 878 if (mode >= ARRAY_SIZE(supported_modes)) {879 dev_err(sensor->dev, "Mode %d not supported\n", mode);880 return -EINVAL;881 }882 883 cci_multi_reg_write(sensor->regmap,884 supported_modes[mode].reg_list.regs,885 supported_modes[mode].reg_list.num_of_regs,886 &ret);887 888 cci_multi_reg_write(sensor->regmap,889 sensor->clk_params->regs,890 IMX415_NUM_CLK_PARAM_REGS,891 &ret);892 893 return 0;894}895 896static int imx415_setup(struct imx415 *sensor, struct v4l2_subdev_state *state)897{898 int ret;899 900 ret = cci_multi_reg_write(sensor->regmap,901 imx415_init_table,902 ARRAY_SIZE(imx415_init_table),903 NULL);904 if (ret)905 return ret;906 907 return imx415_set_mode(sensor, sensor->cur_mode);908}909 910static int imx415_wakeup(struct imx415 *sensor)911{912 int ret;913 914 ret = cci_write(sensor->regmap, IMX415_MODE,915 IMX415_MODE_OPERATING, NULL);916 if (ret)917 return ret;918 919 /*920 * According to the datasheet we have to wait at least 63 us after921 * leaving standby mode. But this doesn't work even after 30 ms.922 * So probably this should be 63 ms and therefore we wait for 80 ms.923 */924 msleep(80);925 926 return 0;927}928 929static int imx415_stream_on(struct imx415 *sensor)930{931 int ret;932 933 ret = imx415_wakeup(sensor);934 return cci_write(sensor->regmap, IMX415_XMSTA,935 IMX415_XMSTA_START, &ret);936}937 938static int imx415_stream_off(struct imx415 *sensor)939{940 int ret;941 942 ret = cci_write(sensor->regmap, IMX415_XMSTA,943 IMX415_XMSTA_STOP, NULL);944 return cci_write(sensor->regmap, IMX415_MODE,945 IMX415_MODE_STANDBY, &ret);946}947 948static int imx415_s_stream(struct v4l2_subdev *sd, int enable)949{950 struct imx415 *sensor = to_imx415(sd);951 struct v4l2_subdev_state *state;952 int ret;953 954 state = v4l2_subdev_lock_and_get_active_state(sd);955 956 if (!enable) {957 ret = imx415_stream_off(sensor);958 959 pm_runtime_mark_last_busy(sensor->dev);960 pm_runtime_put_autosuspend(sensor->dev);961 962 goto unlock;963 }964 965 ret = pm_runtime_resume_and_get(sensor->dev);966 if (ret < 0)967 goto unlock;968 969 ret = imx415_setup(sensor, state);970 if (ret)971 goto err_pm;972 973 ret = __v4l2_ctrl_handler_setup(&sensor->ctrls);974 if (ret < 0)975 goto err_pm;976 977 ret = imx415_stream_on(sensor);978 if (ret)979 goto err_pm;980 981 ret = 0;982 983unlock:984 v4l2_subdev_unlock_state(state);985 986 return ret;987 988err_pm:989 /*990 * In case of error, turn the power off synchronously as the device991 * likely has no other chance to recover.992 */993 pm_runtime_put_sync(sensor->dev);994 995 goto unlock;996}997 998static int imx415_enum_mbus_code(struct v4l2_subdev *sd,999 struct v4l2_subdev_state *state,1000 struct v4l2_subdev_mbus_code_enum *code)1001{1002 if (code->index != 0)1003 return -EINVAL;1004 1005 code->code = MEDIA_BUS_FMT_SGBRG10_1X10;1006 1007 return 0;1008}1009 1010static int imx415_enum_frame_size(struct v4l2_subdev *sd,1011 struct v4l2_subdev_state *state,1012 struct v4l2_subdev_frame_size_enum *fse)1013{1014 const struct v4l2_mbus_framefmt *format;1015 1016 format = v4l2_subdev_state_get_format(state, fse->pad);1017 1018 if (fse->index > 0 || fse->code != format->code)1019 return -EINVAL;1020 1021 fse->min_width = IMX415_PIXEL_ARRAY_WIDTH;1022 fse->max_width = fse->min_width;1023 fse->min_height = IMX415_PIXEL_ARRAY_HEIGHT;1024 fse->max_height = fse->min_height;1025 return 0;1026}1027 1028static int imx415_set_format(struct v4l2_subdev *sd,1029 struct v4l2_subdev_state *state,1030 struct v4l2_subdev_format *fmt)1031{1032 struct v4l2_mbus_framefmt *format;1033 1034 format = v4l2_subdev_state_get_format(state, fmt->pad);1035 1036 format->width = fmt->format.width;1037 format->height = fmt->format.height;1038 format->code = MEDIA_BUS_FMT_SGBRG10_1X10;1039 format->field = V4L2_FIELD_NONE;1040 format->colorspace = V4L2_COLORSPACE_RAW;1041 format->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;1042 format->quantization = V4L2_QUANTIZATION_DEFAULT;1043 format->xfer_func = V4L2_XFER_FUNC_NONE;1044 1045 fmt->format = *format;1046 return 0;1047}1048 1049static int imx415_get_selection(struct v4l2_subdev *sd,1050 struct v4l2_subdev_state *sd_state,1051 struct v4l2_subdev_selection *sel)1052{1053 switch (sel->target) {1054 case V4L2_SEL_TGT_CROP:1055 case V4L2_SEL_TGT_CROP_DEFAULT:1056 case V4L2_SEL_TGT_CROP_BOUNDS:1057 sel->r.top = IMX415_PIXEL_ARRAY_TOP;1058 sel->r.left = IMX415_PIXEL_ARRAY_LEFT;1059 sel->r.width = IMX415_PIXEL_ARRAY_WIDTH;1060 sel->r.height = IMX415_PIXEL_ARRAY_HEIGHT;1061 1062 return 0;1063 }1064 1065 return -EINVAL;1066}1067 1068static int imx415_init_state(struct v4l2_subdev *sd,1069 struct v4l2_subdev_state *state)1070{1071 struct v4l2_subdev_format format = {1072 .format = {1073 .width = IMX415_PIXEL_ARRAY_WIDTH,1074 .height = IMX415_PIXEL_ARRAY_HEIGHT,1075 },1076 };1077 1078 imx415_set_format(sd, state, &format);1079 1080 return 0;1081}1082 1083static const struct v4l2_subdev_video_ops imx415_subdev_video_ops = {1084 .s_stream = imx415_s_stream,1085};1086 1087static const struct v4l2_subdev_pad_ops imx415_subdev_pad_ops = {1088 .enum_mbus_code = imx415_enum_mbus_code,1089 .enum_frame_size = imx415_enum_frame_size,1090 .get_fmt = v4l2_subdev_get_fmt,1091 .set_fmt = imx415_set_format,1092 .get_selection = imx415_get_selection,1093};1094 1095static const struct v4l2_subdev_ops imx415_subdev_ops = {1096 .video = &imx415_subdev_video_ops,1097 .pad = &imx415_subdev_pad_ops,1098};1099 1100static const struct v4l2_subdev_internal_ops imx415_internal_ops = {1101 .init_state = imx415_init_state,1102};1103 1104static int imx415_subdev_init(struct imx415 *sensor)1105{1106 struct i2c_client *client = to_i2c_client(sensor->dev);1107 int ret;1108 1109 v4l2_i2c_subdev_init(&sensor->subdev, client, &imx415_subdev_ops);1110 sensor->subdev.internal_ops = &imx415_internal_ops;1111 1112 ret = imx415_ctrls_init(sensor);1113 if (ret)1114 return ret;1115 1116 sensor->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |1117 V4L2_SUBDEV_FL_HAS_EVENTS;1118 sensor->pad.flags = MEDIA_PAD_FL_SOURCE;1119 sensor->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;1120 ret = media_entity_pads_init(&sensor->subdev.entity, 1, &sensor->pad);1121 if (ret < 0) {1122 v4l2_ctrl_handler_free(&sensor->ctrls);1123 return ret;1124 }1125 1126 sensor->subdev.state_lock = sensor->subdev.ctrl_handler->lock;1127 v4l2_subdev_init_finalize(&sensor->subdev);1128 1129 return 0;1130}1131 1132static void imx415_subdev_cleanup(struct imx415 *sensor)1133{1134 media_entity_cleanup(&sensor->subdev.entity);1135 v4l2_ctrl_handler_free(&sensor->ctrls);1136}1137 1138static int imx415_power_on(struct imx415 *sensor)1139{1140 int ret;1141 1142 ret = regulator_bulk_enable(ARRAY_SIZE(sensor->supplies),1143 sensor->supplies);1144 if (ret < 0)1145 return ret;1146 1147 gpiod_set_value_cansleep(sensor->reset, 0);1148 1149 udelay(1);1150 1151 ret = clk_prepare_enable(sensor->clk);1152 if (ret < 0)1153 goto err_reset;1154 1155 /*1156 * Data sheet states that 20 us are required before communication start,1157 * but this doesn't work in all cases. Use 100 us to be on the safe1158 * side.1159 */1160 usleep_range(100, 200);1161 1162 return 0;1163 1164err_reset:1165 gpiod_set_value_cansleep(sensor->reset, 1);1166 regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), sensor->supplies);1167 return ret;1168}1169 1170static void imx415_power_off(struct imx415 *sensor)1171{1172 clk_disable_unprepare(sensor->clk);1173 gpiod_set_value_cansleep(sensor->reset, 1);1174 regulator_bulk_disable(ARRAY_SIZE(sensor->supplies), sensor->supplies);1175}1176 1177static int imx415_identify_model(struct imx415 *sensor)1178{1179 int model, ret;1180 u64 chip_id;1181 1182 /*1183 * While most registers can be read when the sensor is in standby, this1184 * is not the case of the sensor info register :-(1185 */1186 ret = imx415_wakeup(sensor);1187 if (ret)1188 return dev_err_probe(sensor->dev, ret,1189 "failed to get sensor out of standby\n");1190 1191 ret = cci_read(sensor->regmap, IMX415_SENSOR_INFO, &chip_id, NULL);1192 if (ret < 0) {1193 dev_err_probe(sensor->dev, ret,1194 "failed to read sensor information\n");1195 goto done;1196 }1197 1198 model = chip_id & IMX415_SENSOR_INFO_MASK;1199 1200 switch (model) {1201 case IMX415_CHIP_ID:1202 dev_info(sensor->dev, "Detected IMX415 image sensor\n");1203 break;1204 default:1205 ret = dev_err_probe(sensor->dev, -ENODEV,1206 "invalid device model 0x%04x\n", model);1207 goto done;1208 }1209 1210 ret = 0;1211 1212done:1213 cci_write(sensor->regmap, IMX415_MODE, IMX415_MODE_STANDBY, &ret);1214 return ret;1215}1216 1217static int imx415_check_inck(unsigned long inck, u64 link_frequency)1218{1219 unsigned int i;1220 1221 for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {1222 if ((imx415_clk_params[i].lane_rate == link_frequency * 2) &&1223 imx415_clk_params[i].inck == inck)1224 break;1225 }1226 1227 if (i == ARRAY_SIZE(imx415_clk_params))1228 return -EINVAL;1229 else1230 return 0;1231}1232 1233static int imx415_parse_hw_config(struct imx415 *sensor)1234{1235 struct v4l2_fwnode_endpoint bus_cfg = {1236 .bus_type = V4L2_MBUS_CSI2_DPHY,1237 };1238 struct fwnode_handle *ep;1239 u64 lane_rate;1240 unsigned long inck;1241 unsigned int i, j;1242 int ret;1243 1244 for (i = 0; i < ARRAY_SIZE(sensor->supplies); ++i)1245 sensor->supplies[i].supply = imx415_supply_names[i];1246 1247 ret = devm_regulator_bulk_get(sensor->dev, ARRAY_SIZE(sensor->supplies),1248 sensor->supplies);1249 if (ret)1250 return dev_err_probe(sensor->dev, ret,1251 "failed to get supplies\n");1252 1253 sensor->reset = devm_gpiod_get_optional(sensor->dev, "reset",1254 GPIOD_OUT_HIGH);1255 if (IS_ERR(sensor->reset))1256 return dev_err_probe(sensor->dev, PTR_ERR(sensor->reset),1257 "failed to get reset GPIO\n");1258 1259 sensor->clk = devm_clk_get(sensor->dev, "inck");1260 if (IS_ERR(sensor->clk))1261 return dev_err_probe(sensor->dev, PTR_ERR(sensor->clk),1262 "failed to get clock\n");1263 1264 ep = fwnode_graph_get_next_endpoint(dev_fwnode(sensor->dev), NULL);1265 if (!ep)1266 return -ENXIO;1267 1268 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);1269 fwnode_handle_put(ep);1270 if (ret)1271 return ret;1272 1273 switch (bus_cfg.bus.mipi_csi2.num_data_lanes) {1274 case 2:1275 case 4:1276 sensor->num_data_lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;1277 break;1278 default:1279 ret = dev_err_probe(sensor->dev, -EINVAL,1280 "invalid number of CSI2 data lanes %d\n",1281 bus_cfg.bus.mipi_csi2.num_data_lanes);1282 goto done_endpoint_free;1283 }1284 1285 if (!bus_cfg.nr_of_link_frequencies) {1286 ret = dev_err_probe(sensor->dev, -EINVAL,1287 "no link frequencies defined");1288 goto done_endpoint_free;1289 }1290 1291 /*1292 * Check if there exists a sensor mode defined for current INCK,1293 * number of lanes and given lane rates.1294 */1295 inck = clk_get_rate(sensor->clk);1296 for (i = 0; i < bus_cfg.nr_of_link_frequencies; ++i) {1297 if (imx415_check_inck(inck, bus_cfg.link_frequencies[i])) {1298 dev_dbg(sensor->dev,1299 "INCK %lu Hz not supported for this link freq",1300 inck);1301 continue;1302 }1303 1304 for (j = 0; j < ARRAY_SIZE(supported_modes); ++j) {1305 if (sensor->num_data_lanes != supported_modes[j].lanes)1306 continue;1307 if (bus_cfg.link_frequencies[i] * 2 !=1308 supported_modes[j].lane_rate)1309 continue;1310 sensor->cur_mode = j;1311 break;1312 }1313 if (j < ARRAY_SIZE(supported_modes))1314 break;1315 }1316 if (i == bus_cfg.nr_of_link_frequencies) {1317 ret = dev_err_probe(sensor->dev, -EINVAL,1318 "no valid sensor mode defined\n");1319 goto done_endpoint_free;1320 }1321 1322 lane_rate = supported_modes[sensor->cur_mode].lane_rate;1323 for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {1324 if (lane_rate == imx415_clk_params[i].lane_rate &&1325 inck == imx415_clk_params[i].inck) {1326 sensor->clk_params = &imx415_clk_params[i];1327 break;1328 }1329 }1330 if (i == ARRAY_SIZE(imx415_clk_params)) {1331 ret = dev_err_probe(sensor->dev, -EINVAL,1332 "Mode %d not supported\n",1333 sensor->cur_mode);1334 goto done_endpoint_free;1335 }1336 1337 ret = 0;1338 dev_dbg(sensor->dev, "clock: %lu Hz, lane_rate: %llu bps, lanes: %d\n",1339 inck, lane_rate, sensor->num_data_lanes);1340 1341done_endpoint_free:1342 v4l2_fwnode_endpoint_free(&bus_cfg);1343 1344 return ret;1345}1346 1347static int imx415_probe(struct i2c_client *client)1348{1349 struct imx415 *sensor;1350 int ret;1351 1352 sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL);1353 if (!sensor)1354 return -ENOMEM;1355 1356 sensor->dev = &client->dev;1357 1358 ret = imx415_parse_hw_config(sensor);1359 if (ret)1360 return ret;1361 1362 sensor->regmap = devm_cci_regmap_init_i2c(client, 16);1363 if (IS_ERR(sensor->regmap))1364 return PTR_ERR(sensor->regmap);1365 1366 /*1367 * Enable power management. The driver supports runtime PM, but needs to1368 * work when runtime PM is disabled in the kernel. To that end, power1369 * the sensor on manually here, identify it, and fully initialize it.1370 */1371 ret = imx415_power_on(sensor);1372 if (ret)1373 return ret;1374 1375 ret = imx415_identify_model(sensor);1376 if (ret)1377 goto err_power;1378 1379 ret = imx415_subdev_init(sensor);1380 if (ret)1381 goto err_power;1382 1383 /*1384 * Enable runtime PM. As the device has been powered manually, mark it1385 * as active, and increase the usage count without resuming the device.1386 */1387 pm_runtime_set_active(sensor->dev);1388 pm_runtime_get_noresume(sensor->dev);1389 pm_runtime_enable(sensor->dev);1390 1391 ret = v4l2_async_register_subdev_sensor(&sensor->subdev);1392 if (ret < 0)1393 goto err_pm;1394 1395 /*1396 * Finally, enable autosuspend and decrease the usage count. The device1397 * will get suspended after the autosuspend delay, turning the power1398 * off.1399 */1400 pm_runtime_set_autosuspend_delay(sensor->dev, 1000);1401 pm_runtime_use_autosuspend(sensor->dev);1402 pm_runtime_put_autosuspend(sensor->dev);1403 1404 return 0;1405 1406err_pm:1407 pm_runtime_disable(sensor->dev);1408 pm_runtime_put_noidle(sensor->dev);1409 imx415_subdev_cleanup(sensor);1410err_power:1411 imx415_power_off(sensor);1412 return ret;1413}1414 1415static void imx415_remove(struct i2c_client *client)1416{1417 struct v4l2_subdev *subdev = i2c_get_clientdata(client);1418 struct imx415 *sensor = to_imx415(subdev);1419 1420 v4l2_async_unregister_subdev(subdev);1421 1422 imx415_subdev_cleanup(sensor);1423 1424 /*1425 * Disable runtime PM. In case runtime PM is disabled in the kernel,1426 * make sure to turn power off manually.1427 */1428 pm_runtime_disable(sensor->dev);1429 if (!pm_runtime_status_suspended(sensor->dev))1430 imx415_power_off(sensor);1431 pm_runtime_set_suspended(sensor->dev);1432}1433 1434static int imx415_runtime_resume(struct device *dev)1435{1436 struct i2c_client *client = to_i2c_client(dev);1437 struct v4l2_subdev *subdev = i2c_get_clientdata(client);1438 struct imx415 *sensor = to_imx415(subdev);1439 1440 return imx415_power_on(sensor);1441}1442 1443static int imx415_runtime_suspend(struct device *dev)1444{1445 struct i2c_client *client = to_i2c_client(dev);1446 struct v4l2_subdev *subdev = i2c_get_clientdata(client);1447 struct imx415 *sensor = to_imx415(subdev);1448 1449 imx415_power_off(sensor);1450 1451 return 0;1452}1453 1454static DEFINE_RUNTIME_DEV_PM_OPS(imx415_pm_ops, imx415_runtime_suspend,1455 imx415_runtime_resume, NULL);1456 1457static const struct of_device_id imx415_of_match[] = {1458 { .compatible = "sony,imx415" },1459 { /* sentinel */ }1460};1461 1462MODULE_DEVICE_TABLE(of, imx415_of_match);1463 1464static struct i2c_driver imx415_driver = {1465 .probe = imx415_probe,1466 .remove = imx415_remove,1467 .driver = {1468 .name = "imx415",1469 .of_match_table = imx415_of_match,1470 .pm = pm_ptr(&imx415_pm_ops),1471 },1472};1473 1474module_i2c_driver(imx415_driver);1475 1476MODULE_DESCRIPTION("Sony IMX415 image sensor driver");1477MODULE_AUTHOR("Gerald Loacker <gerald.loacker@wolfvision.net>");1478MODULE_AUTHOR("Michael Riesch <michael.riesch@wolfvision.net>");1479MODULE_LICENSE("GPL");1480