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1// SPDX-License-Identifier: GPL-2.0-or-later2/*3 * Video Capture Driver (Video for Linux 1/2)4 * for the Matrox Marvel G200,G400 and Rainbow Runner-G series5 *6 * This module is an interface to the KS0127 video decoder chip.7 *8 * Copyright (C) 1999 Ryan Drake <stiletto@mediaone.net>9 *10 *****************************************************************************11 *12 * Modified and extended by13 * Mike Bernson <mike@mlb.org>14 * Gerard v.d. Horst15 * Leon van Stuivenberg <l.vanstuivenberg@chello.nl>16 * Gernot Ziegler <gz@lysator.liu.se>17 *18 * Version History:19 * V1.0 Ryan Drake Initial version by Ryan Drake20 * V1.1 Gerard v.d. Horst Added some debugoutput, reset the video-standard21 */22 23#include <linux/init.h>24#include <linux/module.h>25#include <linux/delay.h>26#include <linux/errno.h>27#include <linux/kernel.h>28#include <linux/i2c.h>29#include <linux/videodev2.h>30#include <linux/slab.h>31#include <media/v4l2-device.h>32#include "ks0127.h"33 34MODULE_DESCRIPTION("KS0127 video decoder driver");35MODULE_AUTHOR("Ryan Drake");36MODULE_LICENSE("GPL");37 38/* Addresses */39#define I2C_KS0127_ADDON 0xD840#define I2C_KS0127_ONBOARD 0xDA41 42 43/* ks0127 control registers */44#define KS_STAT 0x0045#define KS_CMDA 0x0146#define KS_CMDB 0x0247#define KS_CMDC 0x0348#define KS_CMDD 0x0449#define KS_HAVB 0x0550#define KS_HAVE 0x0651#define KS_HS1B 0x0752#define KS_HS1E 0x0853#define KS_HS2B 0x0954#define KS_HS2E 0x0a55#define KS_AGC 0x0b56#define KS_HXTRA 0x0c57#define KS_CDEM 0x0d58#define KS_PORTAB 0x0e59#define KS_LUMA 0x0f60#define KS_CON 0x1061#define KS_BRT 0x1162#define KS_CHROMA 0x1263#define KS_CHROMB 0x1364#define KS_DEMOD 0x1465#define KS_SAT 0x1566#define KS_HUE 0x1667#define KS_VERTIA 0x1768#define KS_VERTIB 0x1869#define KS_VERTIC 0x1970#define KS_HSCLL 0x1a71#define KS_HSCLH 0x1b72#define KS_VSCLL 0x1c73#define KS_VSCLH 0x1d74#define KS_OFMTA 0x1e75#define KS_OFMTB 0x1f76#define KS_VBICTL 0x2077#define KS_CCDAT2 0x2178#define KS_CCDAT1 0x2279#define KS_VBIL30 0x2380#define KS_VBIL74 0x2481#define KS_VBIL118 0x2582#define KS_VBIL1512 0x2683#define KS_TTFRAM 0x2784#define KS_TESTA 0x2885#define KS_UVOFFH 0x2986#define KS_UVOFFL 0x2a87#define KS_UGAIN 0x2b88#define KS_VGAIN 0x2c89#define KS_VAVB 0x2d90#define KS_VAVE 0x2e91#define KS_CTRACK 0x2f92#define KS_POLCTL 0x3093#define KS_REFCOD 0x3194#define KS_INVALY 0x3295#define KS_INVALU 0x3396#define KS_INVALV 0x3497#define KS_UNUSEY 0x3598#define KS_UNUSEU 0x3699#define KS_UNUSEV 0x37100#define KS_USRSAV 0x38101#define KS_USREAV 0x39102#define KS_SHS1A 0x3a103#define KS_SHS1B 0x3b104#define KS_SHS1C 0x3c105#define KS_CMDE 0x3d106#define KS_VSDEL 0x3e107#define KS_CMDF 0x3f108#define KS_GAMMA0 0x40109#define KS_GAMMA1 0x41110#define KS_GAMMA2 0x42111#define KS_GAMMA3 0x43112#define KS_GAMMA4 0x44113#define KS_GAMMA5 0x45114#define KS_GAMMA6 0x46115#define KS_GAMMA7 0x47116#define KS_GAMMA8 0x48117#define KS_GAMMA9 0x49118#define KS_GAMMA10 0x4a119#define KS_GAMMA11 0x4b120#define KS_GAMMA12 0x4c121#define KS_GAMMA13 0x4d122#define KS_GAMMA14 0x4e123#define KS_GAMMA15 0x4f124#define KS_GAMMA16 0x50125#define KS_GAMMA17 0x51126#define KS_GAMMA18 0x52127#define KS_GAMMA19 0x53128#define KS_GAMMA20 0x54129#define KS_GAMMA21 0x55130#define KS_GAMMA22 0x56131#define KS_GAMMA23 0x57132#define KS_GAMMA24 0x58133#define KS_GAMMA25 0x59134#define KS_GAMMA26 0x5a135#define KS_GAMMA27 0x5b136#define KS_GAMMA28 0x5c137#define KS_GAMMA29 0x5d138#define KS_GAMMA30 0x5e139#define KS_GAMMA31 0x5f140#define KS_GAMMAD0 0x60141#define KS_GAMMAD1 0x61142#define KS_GAMMAD2 0x62143#define KS_GAMMAD3 0x63144#define KS_GAMMAD4 0x64145#define KS_GAMMAD5 0x65146#define KS_GAMMAD6 0x66147#define KS_GAMMAD7 0x67148#define KS_GAMMAD8 0x68149#define KS_GAMMAD9 0x69150#define KS_GAMMAD10 0x6a151#define KS_GAMMAD11 0x6b152#define KS_GAMMAD12 0x6c153#define KS_GAMMAD13 0x6d154#define KS_GAMMAD14 0x6e155#define KS_GAMMAD15 0x6f156#define KS_GAMMAD16 0x70157#define KS_GAMMAD17 0x71158#define KS_GAMMAD18 0x72159#define KS_GAMMAD19 0x73160#define KS_GAMMAD20 0x74161#define KS_GAMMAD21 0x75162#define KS_GAMMAD22 0x76163#define KS_GAMMAD23 0x77164#define KS_GAMMAD24 0x78165#define KS_GAMMAD25 0x79166#define KS_GAMMAD26 0x7a167#define KS_GAMMAD27 0x7b168#define KS_GAMMAD28 0x7c169#define KS_GAMMAD29 0x7d170#define KS_GAMMAD30 0x7e171#define KS_GAMMAD31 0x7f172 173 174/****************************************************************************175* mga_dev : represents one ks0127 chip.176****************************************************************************/177 178struct ks0127 {179 struct v4l2_subdev sd;180 v4l2_std_id norm;181 u8 regs[256];182};183 184static inline struct ks0127 *to_ks0127(struct v4l2_subdev *sd)185{186 return container_of(sd, struct ks0127, sd);187}188 189 190static int debug; /* insmod parameter */191 192module_param(debug, int, 0);193MODULE_PARM_DESC(debug, "Debug output");194 195static u8 reg_defaults[64];196 197static void init_reg_defaults(void)198{199 static int initialized;200 u8 *table = reg_defaults;201 202 if (initialized)203 return;204 initialized = 1;205 206 table[KS_CMDA] = 0x2c; /* VSE=0, CCIR 601, autodetect standard */207 table[KS_CMDB] = 0x12; /* VALIGN=0, AGC control and input */208 table[KS_CMDC] = 0x00; /* Test options */209 /* clock & input select, write 1 to PORTA */210 table[KS_CMDD] = 0x01;211 table[KS_HAVB] = 0x00; /* HAV Start Control */212 table[KS_HAVE] = 0x00; /* HAV End Control */213 table[KS_HS1B] = 0x10; /* HS1 Start Control */214 table[KS_HS1E] = 0x00; /* HS1 End Control */215 table[KS_HS2B] = 0x00; /* HS2 Start Control */216 table[KS_HS2E] = 0x00; /* HS2 End Control */217 table[KS_AGC] = 0x53; /* Manual setting for AGC */218 table[KS_HXTRA] = 0x00; /* Extra Bits for HAV and HS1/2 */219 table[KS_CDEM] = 0x00; /* Chroma Demodulation Control */220 table[KS_PORTAB] = 0x0f; /* port B is input, port A output GPPORT */221 table[KS_LUMA] = 0x01; /* Luma control */222 table[KS_CON] = 0x00; /* Contrast Control */223 table[KS_BRT] = 0x00; /* Brightness Control */224 table[KS_CHROMA] = 0x2a; /* Chroma control A */225 table[KS_CHROMB] = 0x90; /* Chroma control B */226 table[KS_DEMOD] = 0x00; /* Chroma Demodulation Control & Status */227 table[KS_SAT] = 0x00; /* Color Saturation Control*/228 table[KS_HUE] = 0x00; /* Hue Control */229 table[KS_VERTIA] = 0x00; /* Vertical Processing Control A */230 /* Vertical Processing Control B, luma 1 line delayed */231 table[KS_VERTIB] = 0x12;232 table[KS_VERTIC] = 0x0b; /* Vertical Processing Control C */233 table[KS_HSCLL] = 0x00; /* Horizontal Scaling Ratio Low */234 table[KS_HSCLH] = 0x00; /* Horizontal Scaling Ratio High */235 table[KS_VSCLL] = 0x00; /* Vertical Scaling Ratio Low */236 table[KS_VSCLH] = 0x00; /* Vertical Scaling Ratio High */237 /* 16 bit YCbCr 4:2:2 output; I can't make the bt866 like 8 bit /Sam */238 table[KS_OFMTA] = 0x30;239 table[KS_OFMTB] = 0x00; /* Output Control B */240 /* VBI Decoder Control; 4bit fmt: avoid Y overflow */241 table[KS_VBICTL] = 0x5d;242 table[KS_CCDAT2] = 0x00; /* Read Only register */243 table[KS_CCDAT1] = 0x00; /* Read Only register */244 table[KS_VBIL30] = 0xa8; /* VBI data decoding options */245 table[KS_VBIL74] = 0xaa; /* VBI data decoding options */246 table[KS_VBIL118] = 0x2a; /* VBI data decoding options */247 table[KS_VBIL1512] = 0x00; /* VBI data decoding options */248 table[KS_TTFRAM] = 0x00; /* Teletext frame alignment pattern */249 table[KS_TESTA] = 0x00; /* test register, shouldn't be written */250 table[KS_UVOFFH] = 0x00; /* UV Offset Adjustment High */251 table[KS_UVOFFL] = 0x00; /* UV Offset Adjustment Low */252 table[KS_UGAIN] = 0x00; /* U Component Gain Adjustment */253 table[KS_VGAIN] = 0x00; /* V Component Gain Adjustment */254 table[KS_VAVB] = 0x07; /* VAV Begin */255 table[KS_VAVE] = 0x00; /* VAV End */256 table[KS_CTRACK] = 0x00; /* Chroma Tracking Control */257 table[KS_POLCTL] = 0x41; /* Timing Signal Polarity Control */258 table[KS_REFCOD] = 0x80; /* Reference Code Insertion Control */259 table[KS_INVALY] = 0x10; /* Invalid Y Code */260 table[KS_INVALU] = 0x80; /* Invalid U Code */261 table[KS_INVALV] = 0x80; /* Invalid V Code */262 table[KS_UNUSEY] = 0x10; /* Unused Y Code */263 table[KS_UNUSEU] = 0x80; /* Unused U Code */264 table[KS_UNUSEV] = 0x80; /* Unused V Code */265 table[KS_USRSAV] = 0x00; /* reserved */266 table[KS_USREAV] = 0x00; /* reserved */267 table[KS_SHS1A] = 0x00; /* User Defined SHS1 A */268 /* User Defined SHS1 B, ALT656=1 on 0127B */269 table[KS_SHS1B] = 0x80;270 table[KS_SHS1C] = 0x00; /* User Defined SHS1 C */271 table[KS_CMDE] = 0x00; /* Command Register E */272 table[KS_VSDEL] = 0x00; /* VS Delay Control */273 /* Command Register F, update -immediately- */274 /* (there might come no vsync)*/275 table[KS_CMDF] = 0x02;276}277 278 279/* We need to manually read because of a bug in the KS0127 chip.280 *281 * An explanation from kayork@mail.utexas.edu:282 *283 * During I2C reads, the KS0127 only samples for a stop condition284 * during the place where the acknowledge bit should be. Any standard285 * I2C implementation (correctly) throws in another clock transition286 * at the 9th bit, and the KS0127 will not recognize the stop condition287 * and will continue to clock out data.288 *289 * So we have to do the read ourself. Big deal.290 * workaround in i2c-algo-bit291 */292 293 294static u8 ks0127_read(struct v4l2_subdev *sd, u8 reg)295{296 struct i2c_client *client = v4l2_get_subdevdata(sd);297 char val = 0;298 struct i2c_msg msgs[] = {299 {300 .addr = client->addr,301 .len = sizeof(reg),302 .buf = ®303 },304 {305 .addr = client->addr,306 .flags = I2C_M_RD | I2C_M_NO_RD_ACK,307 .len = sizeof(val),308 .buf = &val309 }310 };311 int ret;312 313 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));314 if (ret != ARRAY_SIZE(msgs))315 v4l2_dbg(1, debug, sd, "read error\n");316 317 return val;318}319 320 321static void ks0127_write(struct v4l2_subdev *sd, u8 reg, u8 val)322{323 struct i2c_client *client = v4l2_get_subdevdata(sd);324 struct ks0127 *ks = to_ks0127(sd);325 char msg[] = { reg, val };326 327 if (i2c_master_send(client, msg, sizeof(msg)) != sizeof(msg))328 v4l2_dbg(1, debug, sd, "write error\n");329 330 ks->regs[reg] = val;331}332 333 334/* generic bit-twiddling */335static void ks0127_and_or(struct v4l2_subdev *sd, u8 reg, u8 and_v, u8 or_v)336{337 struct ks0127 *ks = to_ks0127(sd);338 339 u8 val = ks->regs[reg];340 val = (val & and_v) | or_v;341 ks0127_write(sd, reg, val);342}343 344 345 346/****************************************************************************347* ks0127 private api348****************************************************************************/349static void ks0127_init(struct v4l2_subdev *sd)350{351 u8 *table = reg_defaults;352 int i;353 354 v4l2_dbg(1, debug, sd, "reset\n");355 msleep(1);356 357 /* initialize all registers to known values */358 /* (except STAT, 0x21, 0x22, TEST and 0x38,0x39) */359 360 for (i = 1; i < 33; i++)361 ks0127_write(sd, i, table[i]);362 363 for (i = 35; i < 40; i++)364 ks0127_write(sd, i, table[i]);365 366 for (i = 41; i < 56; i++)367 ks0127_write(sd, i, table[i]);368 369 for (i = 58; i < 64; i++)370 ks0127_write(sd, i, table[i]);371 372 373 if ((ks0127_read(sd, KS_STAT) & 0x80) == 0) {374 v4l2_dbg(1, debug, sd, "ks0122s found\n");375 return;376 }377 378 switch (ks0127_read(sd, KS_CMDE) & 0x0f) {379 case 0:380 v4l2_dbg(1, debug, sd, "ks0127 found\n");381 break;382 383 case 9:384 v4l2_dbg(1, debug, sd, "ks0127B Revision A found\n");385 break;386 387 default:388 v4l2_dbg(1, debug, sd, "unknown revision\n");389 break;390 }391}392 393static int ks0127_s_routing(struct v4l2_subdev *sd,394 u32 input, u32 output, u32 config)395{396 struct ks0127 *ks = to_ks0127(sd);397 398 switch (input) {399 case KS_INPUT_COMPOSITE_1:400 case KS_INPUT_COMPOSITE_2:401 case KS_INPUT_COMPOSITE_3:402 case KS_INPUT_COMPOSITE_4:403 case KS_INPUT_COMPOSITE_5:404 case KS_INPUT_COMPOSITE_6:405 v4l2_dbg(1, debug, sd,406 "s_routing %d: Composite\n", input);407 /* autodetect 50/60 Hz */408 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x00);409 /* VSE=0 */410 ks0127_and_or(sd, KS_CMDA, ~0x40, 0x00);411 /* set input line */412 ks0127_and_or(sd, KS_CMDB, 0xb0, input);413 /* non-freerunning mode */414 ks0127_and_or(sd, KS_CMDC, 0x70, 0x0a);415 /* analog input */416 ks0127_and_or(sd, KS_CMDD, 0x03, 0x00);417 /* enable chroma demodulation */418 ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x00);419 /* chroma trap, HYBWR=1 */420 ks0127_and_or(sd, KS_LUMA, 0x00,421 (reg_defaults[KS_LUMA])|0x0c);422 /* scaler fullbw, luma comb off */423 ks0127_and_or(sd, KS_VERTIA, 0x08, 0x81);424 /* manual chroma comb .25 .5 .25 */425 ks0127_and_or(sd, KS_VERTIC, 0x0f, 0x90);426 427 /* chroma path delay */428 ks0127_and_or(sd, KS_CHROMB, 0x0f, 0x90);429 430 ks0127_write(sd, KS_UGAIN, reg_defaults[KS_UGAIN]);431 ks0127_write(sd, KS_VGAIN, reg_defaults[KS_VGAIN]);432 ks0127_write(sd, KS_UVOFFH, reg_defaults[KS_UVOFFH]);433 ks0127_write(sd, KS_UVOFFL, reg_defaults[KS_UVOFFL]);434 break;435 436 case KS_INPUT_SVIDEO_1:437 case KS_INPUT_SVIDEO_2:438 case KS_INPUT_SVIDEO_3:439 v4l2_dbg(1, debug, sd,440 "s_routing %d: S-Video\n", input);441 /* autodetect 50/60 Hz */442 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x00);443 /* VSE=0 */444 ks0127_and_or(sd, KS_CMDA, ~0x40, 0x00);445 /* set input line */446 ks0127_and_or(sd, KS_CMDB, 0xb0, input);447 /* non-freerunning mode */448 ks0127_and_or(sd, KS_CMDC, 0x70, 0x0a);449 /* analog input */450 ks0127_and_or(sd, KS_CMDD, 0x03, 0x00);451 /* enable chroma demodulation */452 ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x00);453 ks0127_and_or(sd, KS_LUMA, 0x00,454 reg_defaults[KS_LUMA]);455 /* disable luma comb */456 ks0127_and_or(sd, KS_VERTIA, 0x08,457 (reg_defaults[KS_VERTIA]&0xf0)|0x01);458 ks0127_and_or(sd, KS_VERTIC, 0x0f,459 reg_defaults[KS_VERTIC]&0xf0);460 461 ks0127_and_or(sd, KS_CHROMB, 0x0f,462 reg_defaults[KS_CHROMB]&0xf0);463 464 ks0127_write(sd, KS_UGAIN, reg_defaults[KS_UGAIN]);465 ks0127_write(sd, KS_VGAIN, reg_defaults[KS_VGAIN]);466 ks0127_write(sd, KS_UVOFFH, reg_defaults[KS_UVOFFH]);467 ks0127_write(sd, KS_UVOFFL, reg_defaults[KS_UVOFFL]);468 break;469 470 case KS_INPUT_YUV656:471 v4l2_dbg(1, debug, sd, "s_routing 15: YUV656\n");472 if (ks->norm & V4L2_STD_525_60)473 /* force 60 Hz */474 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x03);475 else476 /* force 50 Hz */477 ks0127_and_or(sd, KS_CMDA, 0xfc, 0x02);478 479 ks0127_and_or(sd, KS_CMDA, 0xff, 0x40); /* VSE=1 */480 /* set input line and VALIGN */481 ks0127_and_or(sd, KS_CMDB, 0xb0, (input | 0x40));482 /* freerunning mode, */483 /* TSTGEN = 1 TSTGFR=11 TSTGPH=0 TSTGPK=0 VMEM=1*/484 ks0127_and_or(sd, KS_CMDC, 0x70, 0x87);485 /* digital input, SYNDIR = 0 INPSL=01 CLKDIR=0 EAV=0 */486 ks0127_and_or(sd, KS_CMDD, 0x03, 0x08);487 /* disable chroma demodulation */488 ks0127_and_or(sd, KS_CTRACK, 0xcf, 0x30);489 /* HYPK =01 CTRAP = 0 HYBWR=0 PED=1 RGBH=1 UNIT=1 */490 ks0127_and_or(sd, KS_LUMA, 0x00, 0x71);491 ks0127_and_or(sd, KS_VERTIC, 0x0f,492 reg_defaults[KS_VERTIC]&0xf0);493 494 /* scaler fullbw, luma comb off */495 ks0127_and_or(sd, KS_VERTIA, 0x08, 0x81);496 497 ks0127_and_or(sd, KS_CHROMB, 0x0f,498 reg_defaults[KS_CHROMB]&0xf0);499 500 ks0127_and_or(sd, KS_CON, 0x00, 0x00);501 ks0127_and_or(sd, KS_BRT, 0x00, 32); /* spec: 34 */502 /* spec: 229 (e5) */503 ks0127_and_or(sd, KS_SAT, 0x00, 0xe8);504 ks0127_and_or(sd, KS_HUE, 0x00, 0);505 506 ks0127_and_or(sd, KS_UGAIN, 0x00, 238);507 ks0127_and_or(sd, KS_VGAIN, 0x00, 0x00);508 509 /*UOFF:0x30, VOFF:0x30, TSTCGN=1 */510 ks0127_and_or(sd, KS_UVOFFH, 0x00, 0x4f);511 ks0127_and_or(sd, KS_UVOFFL, 0x00, 0x00);512 break;513 514 default:515 v4l2_dbg(1, debug, sd,516 "s_routing: Unknown input %d\n", input);517 break;518 }519 520 /* hack: CDMLPF sometimes spontaneously switches on; */521 /* force back off */522 ks0127_write(sd, KS_DEMOD, reg_defaults[KS_DEMOD]);523 return 0;524}525 526static int ks0127_s_std(struct v4l2_subdev *sd, v4l2_std_id std)527{528 struct ks0127 *ks = to_ks0127(sd);529 530 /* Set to automatic SECAM/Fsc mode */531 ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x00);532 533 ks->norm = std;534 if (std & V4L2_STD_NTSC) {535 v4l2_dbg(1, debug, sd,536 "s_std: NTSC_M\n");537 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x20);538 } else if (std & V4L2_STD_PAL_N) {539 v4l2_dbg(1, debug, sd,540 "s_std: NTSC_N (fixme)\n");541 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x40);542 } else if (std & V4L2_STD_PAL) {543 v4l2_dbg(1, debug, sd,544 "s_std: PAL_N\n");545 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x20);546 } else if (std & V4L2_STD_PAL_M) {547 v4l2_dbg(1, debug, sd,548 "s_std: PAL_M (fixme)\n");549 ks0127_and_or(sd, KS_CHROMA, 0x9f, 0x40);550 } else if (std & V4L2_STD_SECAM) {551 v4l2_dbg(1, debug, sd,552 "s_std: SECAM\n");553 554 /* set to secam autodetection */555 ks0127_and_or(sd, KS_CHROMA, 0xdf, 0x20);556 ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x00);557 schedule_timeout_interruptible(HZ/10+1);558 559 /* did it autodetect? */560 if (!(ks0127_read(sd, KS_DEMOD) & 0x40))561 /* force to secam mode */562 ks0127_and_or(sd, KS_DEMOD, 0xf0, 0x0f);563 } else {564 v4l2_dbg(1, debug, sd, "s_std: Unknown norm %llx\n",565 (unsigned long long)std);566 }567 return 0;568}569 570static int ks0127_s_stream(struct v4l2_subdev *sd, int enable)571{572 v4l2_dbg(1, debug, sd, "s_stream(%d)\n", enable);573 if (enable) {574 /* All output pins on */575 ks0127_and_or(sd, KS_OFMTA, 0xcf, 0x30);576 /* Obey the OEN pin */577 ks0127_and_or(sd, KS_CDEM, 0x7f, 0x00);578 } else {579 /* Video output pins off */580 ks0127_and_or(sd, KS_OFMTA, 0xcf, 0x00);581 /* Ignore the OEN pin */582 ks0127_and_or(sd, KS_CDEM, 0x7f, 0x80);583 }584 return 0;585}586 587static int ks0127_status(struct v4l2_subdev *sd, u32 *pstatus, v4l2_std_id *pstd)588{589 int stat = V4L2_IN_ST_NO_SIGNAL;590 u8 status;591 v4l2_std_id std = pstd ? *pstd : V4L2_STD_ALL;592 593 status = ks0127_read(sd, KS_STAT);594 if (!(status & 0x20)) /* NOVID not set */595 stat = 0;596 if (!(status & 0x01)) { /* CLOCK set */597 stat |= V4L2_IN_ST_NO_COLOR;598 std = V4L2_STD_UNKNOWN;599 } else {600 if ((status & 0x08)) /* PALDET set */601 std &= V4L2_STD_PAL;602 else603 std &= V4L2_STD_NTSC;604 }605 if ((status & 0x10)) /* PALDET set */606 std &= V4L2_STD_525_60;607 else608 std &= V4L2_STD_625_50;609 if (pstd)610 *pstd = std;611 if (pstatus)612 *pstatus = stat;613 return 0;614}615 616static int ks0127_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)617{618 v4l2_dbg(1, debug, sd, "querystd\n");619 return ks0127_status(sd, NULL, std);620}621 622static int ks0127_g_input_status(struct v4l2_subdev *sd, u32 *status)623{624 v4l2_dbg(1, debug, sd, "g_input_status\n");625 return ks0127_status(sd, status, NULL);626}627 628/* ----------------------------------------------------------------------- */629 630static const struct v4l2_subdev_video_ops ks0127_video_ops = {631 .s_std = ks0127_s_std,632 .s_routing = ks0127_s_routing,633 .s_stream = ks0127_s_stream,634 .querystd = ks0127_querystd,635 .g_input_status = ks0127_g_input_status,636};637 638static const struct v4l2_subdev_ops ks0127_ops = {639 .video = &ks0127_video_ops,640};641 642/* ----------------------------------------------------------------------- */643 644 645static int ks0127_probe(struct i2c_client *client)646{647 struct ks0127 *ks;648 struct v4l2_subdev *sd;649 650 v4l_info(client, "%s chip found @ 0x%x (%s)\n",651 client->addr == (I2C_KS0127_ADDON >> 1) ? "addon" : "on-board",652 client->addr << 1, client->adapter->name);653 654 ks = devm_kzalloc(&client->dev, sizeof(*ks), GFP_KERNEL);655 if (ks == NULL)656 return -ENOMEM;657 sd = &ks->sd;658 v4l2_i2c_subdev_init(sd, client, &ks0127_ops);659 660 /* power up */661 init_reg_defaults();662 ks0127_write(sd, KS_CMDA, 0x2c);663 mdelay(10);664 665 /* reset the device */666 ks0127_init(sd);667 return 0;668}669 670static void ks0127_remove(struct i2c_client *client)671{672 struct v4l2_subdev *sd = i2c_get_clientdata(client);673 674 v4l2_device_unregister_subdev(sd);675 ks0127_write(sd, KS_OFMTA, 0x20); /* tristate */676 ks0127_write(sd, KS_CMDA, 0x2c | 0x80); /* power down */677}678 679static const struct i2c_device_id ks0127_id[] = {680 { "ks0127" },681 { "ks0127b" },682 { "ks0122s" },683 { }684};685MODULE_DEVICE_TABLE(i2c, ks0127_id);686 687static struct i2c_driver ks0127_driver = {688 .driver = {689 .name = "ks0127",690 },691 .probe = ks0127_probe,692 .remove = ks0127_remove,693 .id_table = ks0127_id,694};695 696module_i2c_driver(ks0127_driver);697