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1// SPDX-License-Identifier: GPL-2.02/*3 * Maxim GMSL2 Serializer Driver4 *5 * Copyright (C) 2024 Collabora Ltd.6 */7 8#include <linux/bitfield.h>9#include <linux/clk.h>10#include <linux/clk-provider.h>11#include <linux/delay.h>12#include <linux/fwnode.h>13#include <linux/gpio/driver.h>14#include <linux/i2c-mux.h>15#include <linux/i2c.h>16#include <linux/regmap.h>17 18#include <media/v4l2-cci.h>19#include <media/v4l2-ctrls.h>20#include <media/v4l2-fwnode.h>21#include <media/v4l2-subdev.h>22 23#define MAX96717_DEVICE_ID 0xbf24#define MAX96717F_DEVICE_ID 0xc825#define MAX96717_PORTS 226#define MAX96717_PAD_SINK 027#define MAX96717_PAD_SOURCE 128#define MAX96717_CSI_NLANES 429 30#define MAX96717_DEFAULT_CLKOUT_RATE 24000000UL31 32/* DEV */33#define MAX96717_REG3 CCI_REG8(0x3)34#define MAX96717_RCLKSEL GENMASK(1, 0)35#define RCLKSEL_REF_PLL CCI_REG8(0x3)36#define MAX96717_REG6 CCI_REG8(0x6)37#define RCLKEN BIT(5)38#define MAX96717_DEV_ID CCI_REG8(0xd)39#define MAX96717_DEV_REV CCI_REG8(0xe)40#define MAX96717_DEV_REV_MASK GENMASK(3, 0)41 42/* VID_TX Z */43#define MAX96717_VIDEO_TX0 CCI_REG8(0x110)44#define MAX96717_VIDEO_AUTO_BPP BIT(3)45#define MAX96717_VIDEO_TX2 CCI_REG8(0x112)46#define MAX96717_VIDEO_PCLKDET BIT(7)47 48/* VTX_Z */49#define MAX96717_VTX0 CCI_REG8(0x24e)50#define MAX96717_VTX1 CCI_REG8(0x24f)51#define MAX96717_PATTERN_CLK_FREQ GENMASK(3, 1)52#define MAX96717_VTX_VS_DLY CCI_REG24(0x250)53#define MAX96717_VTX_VS_HIGH CCI_REG24(0x253)54#define MAX96717_VTX_VS_LOW CCI_REG24(0x256)55#define MAX96717_VTX_V2H CCI_REG24(0x259)56#define MAX96717_VTX_HS_HIGH CCI_REG16(0x25c)57#define MAX96717_VTX_HS_LOW CCI_REG16(0x25e)58#define MAX96717_VTX_HS_CNT CCI_REG16(0x260)59#define MAX96717_VTX_V2D CCI_REG24(0x262)60#define MAX96717_VTX_DE_HIGH CCI_REG16(0x265)61#define MAX96717_VTX_DE_LOW CCI_REG16(0x267)62#define MAX96717_VTX_DE_CNT CCI_REG16(0x269)63#define MAX96717_VTX29 CCI_REG8(0x26b)64#define MAX96717_VTX_MODE GENMASK(1, 0)65#define MAX96717_VTX_GRAD_INC CCI_REG8(0x26c)66#define MAX96717_VTX_CHKB_COLOR_A CCI_REG24(0x26d)67#define MAX96717_VTX_CHKB_COLOR_B CCI_REG24(0x270)68#define MAX96717_VTX_CHKB_RPT_CNT_A CCI_REG8(0x273)69#define MAX96717_VTX_CHKB_RPT_CNT_B CCI_REG8(0x274)70#define MAX96717_VTX_CHKB_ALT CCI_REG8(0x275)71 72/* GPIO */73#define MAX96717_NUM_GPIO 1174#define MAX96717_GPIO_REG_A(gpio) CCI_REG8(0x2be + (gpio) * 3)75#define MAX96717_GPIO_OUT BIT(4)76#define MAX96717_GPIO_IN BIT(3)77#define MAX96717_GPIO_RX_EN BIT(2)78#define MAX96717_GPIO_TX_EN BIT(1)79#define MAX96717_GPIO_OUT_DIS BIT(0)80 81/* FRONTTOP */82/* MAX96717 only have CSI port 'B' */83#define MAX96717_FRONTOP0 CCI_REG8(0x308)84#define MAX96717_START_PORT_B BIT(5)85 86/* MIPI_RX */87#define MAX96717_MIPI_RX1 CCI_REG8(0x331)88#define MAX96717_MIPI_LANES_CNT GENMASK(5, 4)89#define MAX96717_MIPI_RX2 CCI_REG8(0x332) /* phy1 Lanes map */90#define MAX96717_PHY2_LANES_MAP GENMASK(7, 4)91#define MAX96717_MIPI_RX3 CCI_REG8(0x333) /* phy2 Lanes map */92#define MAX96717_PHY1_LANES_MAP GENMASK(3, 0)93#define MAX96717_MIPI_RX4 CCI_REG8(0x334) /* phy1 lane polarities */94#define MAX96717_PHY1_LANES_POL GENMASK(6, 4)95#define MAX96717_MIPI_RX5 CCI_REG8(0x335) /* phy2 lane polarities */96#define MAX96717_PHY2_LANES_POL GENMASK(2, 0)97 98/* MIPI_RX_EXT */99#define MAX96717_MIPI_RX_EXT11 CCI_REG8(0x383)100#define MAX96717_TUN_MODE BIT(7)101 102/* REF_VTG */103#define REF_VTG0 CCI_REG8(0x3f0)104#define REFGEN_PREDEF_EN BIT(6)105#define REFGEN_PREDEF_FREQ_MASK GENMASK(5, 4)106#define REFGEN_PREDEF_FREQ_ALT BIT(3)107#define REFGEN_RST BIT(1)108#define REFGEN_EN BIT(0)109 110/* MISC */111#define PIO_SLEW_1 CCI_REG8(0x570)112 113enum max96717_vpg_mode {114 MAX96717_VPG_DISABLED = 0,115 MAX96717_VPG_CHECKERBOARD = 1,116 MAX96717_VPG_GRADIENT = 2,117};118 119struct max96717_priv {120 struct i2c_client *client;121 struct regmap *regmap;122 struct i2c_mux_core *mux;123 struct v4l2_mbus_config_mipi_csi2 mipi_csi2;124 struct v4l2_subdev sd;125 struct media_pad pads[MAX96717_PORTS];126 struct v4l2_ctrl_handler ctrl_handler;127 struct v4l2_async_notifier notifier;128 struct v4l2_subdev *source_sd;129 u16 source_sd_pad;130 u64 enabled_source_streams;131 u8 pll_predef_index;132 struct clk_hw clk_hw;133 struct gpio_chip gpio_chip;134 enum max96717_vpg_mode pattern;135};136 137static inline struct max96717_priv *sd_to_max96717(struct v4l2_subdev *sd)138{139 return container_of(sd, struct max96717_priv, sd);140}141 142static inline struct max96717_priv *clk_hw_to_max96717(struct clk_hw *hw)143{144 return container_of(hw, struct max96717_priv, clk_hw);145}146 147static int max96717_i2c_mux_select(struct i2c_mux_core *mux, u32 chan)148{149 return 0;150}151 152static int max96717_i2c_mux_init(struct max96717_priv *priv)153{154 priv->mux = i2c_mux_alloc(priv->client->adapter, &priv->client->dev,155 1, 0, I2C_MUX_LOCKED | I2C_MUX_GATE,156 max96717_i2c_mux_select, NULL);157 if (!priv->mux)158 return -ENOMEM;159 160 return i2c_mux_add_adapter(priv->mux, 0, 0);161}162 163static inline int max96717_start_csi(struct max96717_priv *priv, bool start)164{165 return cci_update_bits(priv->regmap, MAX96717_FRONTOP0,166 MAX96717_START_PORT_B,167 start ? MAX96717_START_PORT_B : 0, NULL);168}169 170static int max96717_apply_patgen_timing(struct max96717_priv *priv,171 struct v4l2_subdev_state *state)172{173 struct v4l2_mbus_framefmt *fmt =174 v4l2_subdev_state_get_format(state, MAX96717_PAD_SOURCE);175 const u32 h_active = fmt->width;176 const u32 h_fp = 88;177 const u32 h_sw = 44;178 const u32 h_bp = 148;179 u32 h_tot;180 const u32 v_active = fmt->height;181 const u32 v_fp = 4;182 const u32 v_sw = 5;183 const u32 v_bp = 36;184 u32 v_tot;185 int ret = 0;186 187 h_tot = h_active + h_fp + h_sw + h_bp;188 v_tot = v_active + v_fp + v_sw + v_bp;189 190 /* 75 Mhz pixel clock */191 cci_update_bits(priv->regmap, MAX96717_VTX1,192 MAX96717_PATTERN_CLK_FREQ, 0xa, &ret);193 194 dev_info(&priv->client->dev, "height: %d width: %d\n", fmt->height,195 fmt->width);196 197 cci_write(priv->regmap, MAX96717_VTX_VS_DLY, 0, &ret);198 cci_write(priv->regmap, MAX96717_VTX_VS_HIGH, v_sw * h_tot, &ret);199 cci_write(priv->regmap, MAX96717_VTX_VS_LOW,200 (v_active + v_fp + v_bp) * h_tot, &ret);201 cci_write(priv->regmap, MAX96717_VTX_HS_HIGH, h_sw, &ret);202 cci_write(priv->regmap, MAX96717_VTX_HS_LOW, h_active + h_fp + h_bp,203 &ret);204 cci_write(priv->regmap, MAX96717_VTX_V2D,205 h_tot * (v_sw + v_bp) + (h_sw + h_bp), &ret);206 cci_write(priv->regmap, MAX96717_VTX_HS_CNT, v_tot, &ret);207 cci_write(priv->regmap, MAX96717_VTX_DE_HIGH, h_active, &ret);208 cci_write(priv->regmap, MAX96717_VTX_DE_LOW, h_fp + h_sw + h_bp,209 &ret);210 cci_write(priv->regmap, MAX96717_VTX_DE_CNT, v_active, &ret);211 /* B G R */212 cci_write(priv->regmap, MAX96717_VTX_CHKB_COLOR_A, 0xfecc00, &ret);213 /* B G R */214 cci_write(priv->regmap, MAX96717_VTX_CHKB_COLOR_B, 0x006aa7, &ret);215 cci_write(priv->regmap, MAX96717_VTX_CHKB_RPT_CNT_A, 0x3c, &ret);216 cci_write(priv->regmap, MAX96717_VTX_CHKB_RPT_CNT_B, 0x3c, &ret);217 cci_write(priv->regmap, MAX96717_VTX_CHKB_ALT, 0x3c, &ret);218 cci_write(priv->regmap, MAX96717_VTX_GRAD_INC, 0x10, &ret);219 220 return ret;221}222 223static int max96717_apply_patgen(struct max96717_priv *priv,224 struct v4l2_subdev_state *state)225{226 unsigned int val;227 int ret = 0;228 229 if (priv->pattern)230 ret = max96717_apply_patgen_timing(priv, state);231 232 cci_write(priv->regmap, MAX96717_VTX0, priv->pattern ? 0xfb : 0,233 &ret);234 235 val = FIELD_PREP(MAX96717_VTX_MODE, priv->pattern);236 cci_update_bits(priv->regmap, MAX96717_VTX29, MAX96717_VTX_MODE,237 val, &ret);238 return ret;239}240 241static int max96717_s_ctrl(struct v4l2_ctrl *ctrl)242{243 struct max96717_priv *priv =244 container_of(ctrl->handler, struct max96717_priv, ctrl_handler);245 int ret;246 247 switch (ctrl->id) {248 case V4L2_CID_TEST_PATTERN:249 if (priv->enabled_source_streams)250 return -EBUSY;251 priv->pattern = ctrl->val;252 break;253 default:254 return -EINVAL;255 }256 257 /* Use bpp from bpp register */258 ret = cci_update_bits(priv->regmap, MAX96717_VIDEO_TX0,259 MAX96717_VIDEO_AUTO_BPP,260 priv->pattern ? 0 : MAX96717_VIDEO_AUTO_BPP,261 NULL);262 263 /*264 * Pattern generator doesn't work with tunnel mode.265 * Needs RGB color format and deserializer tunnel mode must be disabled.266 */267 return cci_update_bits(priv->regmap, MAX96717_MIPI_RX_EXT11,268 MAX96717_TUN_MODE,269 priv->pattern ? 0 : MAX96717_TUN_MODE, &ret);270}271 272static const char * const max96717_test_pattern[] = {273 "Disabled",274 "Checkerboard",275 "Gradient"276};277 278static const struct v4l2_ctrl_ops max96717_ctrl_ops = {279 .s_ctrl = max96717_s_ctrl,280};281 282static int max96717_gpiochip_get(struct gpio_chip *gpiochip,283 unsigned int offset)284{285 struct max96717_priv *priv = gpiochip_get_data(gpiochip);286 u64 val;287 int ret;288 289 ret = cci_read(priv->regmap, MAX96717_GPIO_REG_A(offset),290 &val, NULL);291 if (ret)292 return ret;293 294 if (val & MAX96717_GPIO_OUT_DIS)295 return !!(val & MAX96717_GPIO_IN);296 else297 return !!(val & MAX96717_GPIO_OUT);298}299 300static void max96717_gpiochip_set(struct gpio_chip *gpiochip,301 unsigned int offset, int value)302{303 struct max96717_priv *priv = gpiochip_get_data(gpiochip);304 305 cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset),306 MAX96717_GPIO_OUT, MAX96717_GPIO_OUT, NULL);307}308 309static int max96717_gpio_get_direction(struct gpio_chip *gpiochip,310 unsigned int offset)311{312 struct max96717_priv *priv = gpiochip_get_data(gpiochip);313 u64 val;314 int ret;315 316 ret = cci_read(priv->regmap, MAX96717_GPIO_REG_A(offset), &val, NULL);317 if (ret < 0)318 return ret;319 320 return !!(val & MAX96717_GPIO_OUT_DIS);321}322 323static int max96717_gpio_direction_out(struct gpio_chip *gpiochip,324 unsigned int offset, int value)325{326 struct max96717_priv *priv = gpiochip_get_data(gpiochip);327 328 return cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset),329 MAX96717_GPIO_OUT_DIS | MAX96717_GPIO_OUT,330 value ? MAX96717_GPIO_OUT : 0, NULL);331}332 333static int max96717_gpio_direction_in(struct gpio_chip *gpiochip,334 unsigned int offset)335{336 struct max96717_priv *priv = gpiochip_get_data(gpiochip);337 338 return cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(offset),339 MAX96717_GPIO_OUT_DIS, MAX96717_GPIO_OUT_DIS,340 NULL);341}342 343static int max96717_gpiochip_probe(struct max96717_priv *priv)344{345 struct device *dev = &priv->client->dev;346 struct gpio_chip *gc = &priv->gpio_chip;347 int i, ret = 0;348 349 gc->label = dev_name(dev);350 gc->parent = dev;351 gc->owner = THIS_MODULE;352 gc->ngpio = MAX96717_NUM_GPIO;353 gc->base = -1;354 gc->can_sleep = true;355 gc->get_direction = max96717_gpio_get_direction;356 gc->direction_input = max96717_gpio_direction_in;357 gc->direction_output = max96717_gpio_direction_out;358 gc->set = max96717_gpiochip_set;359 gc->get = max96717_gpiochip_get;360 gc->of_gpio_n_cells = 2;361 362 /* Disable GPIO forwarding */363 for (i = 0; i < gc->ngpio; i++)364 cci_update_bits(priv->regmap, MAX96717_GPIO_REG_A(i),365 MAX96717_GPIO_RX_EN | MAX96717_GPIO_TX_EN,366 0, &ret);367 368 if (ret)369 return ret;370 371 ret = devm_gpiochip_add_data(dev, gc, priv);372 if (ret) {373 dev_err(dev, "Unable to create gpio_chip\n");374 return ret;375 }376 377 return 0;378}379 380static int _max96717_set_routing(struct v4l2_subdev *sd,381 struct v4l2_subdev_state *state,382 struct v4l2_subdev_krouting *routing)383{384 static const struct v4l2_mbus_framefmt format = {385 .width = 1280,386 .height = 1080,387 .code = MEDIA_BUS_FMT_Y8_1X8,388 .field = V4L2_FIELD_NONE,389 };390 int ret;391 392 ret = v4l2_subdev_routing_validate(sd, routing,393 V4L2_SUBDEV_ROUTING_ONLY_1_TO_1);394 if (ret)395 return ret;396 397 ret = v4l2_subdev_set_routing_with_fmt(sd, state, routing, &format);398 if (ret)399 return ret;400 401 return 0;402}403 404static int max96717_set_routing(struct v4l2_subdev *sd,405 struct v4l2_subdev_state *state,406 enum v4l2_subdev_format_whence which,407 struct v4l2_subdev_krouting *routing)408{409 struct max96717_priv *priv = sd_to_max96717(sd);410 411 if (which == V4L2_SUBDEV_FORMAT_ACTIVE && priv->enabled_source_streams)412 return -EBUSY;413 414 return _max96717_set_routing(sd, state, routing);415}416 417static int max96717_set_fmt(struct v4l2_subdev *sd,418 struct v4l2_subdev_state *state,419 struct v4l2_subdev_format *format)420{421 struct max96717_priv *priv = sd_to_max96717(sd);422 struct v4l2_mbus_framefmt *fmt;423 u64 stream_source_mask;424 425 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE &&426 priv->enabled_source_streams)427 return -EBUSY;428 429 /* No transcoding, source and sink formats must match. */430 if (format->pad == MAX96717_PAD_SOURCE)431 return v4l2_subdev_get_fmt(sd, state, format);432 433 /* Set sink format */434 fmt = v4l2_subdev_state_get_format(state, format->pad, format->stream);435 if (!fmt)436 return -EINVAL;437 438 *fmt = format->format;439 440 /* Propagate to source format */441 fmt = v4l2_subdev_state_get_opposite_stream_format(state, format->pad,442 format->stream);443 if (!fmt)444 return -EINVAL;445 *fmt = format->format;446 447 stream_source_mask = BIT(format->stream);448 449 return v4l2_subdev_state_xlate_streams(state, MAX96717_PAD_SOURCE,450 MAX96717_PAD_SINK,451 &stream_source_mask);452}453 454static int max96717_init_state(struct v4l2_subdev *sd,455 struct v4l2_subdev_state *state)456{457 struct v4l2_subdev_route routes[] = {458 {459 .sink_pad = MAX96717_PAD_SINK,460 .sink_stream = 0,461 .source_pad = MAX96717_PAD_SOURCE,462 .source_stream = 0,463 .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,464 },465 };466 struct v4l2_subdev_krouting routing = {467 .num_routes = ARRAY_SIZE(routes),468 .routes = routes,469 };470 471 return _max96717_set_routing(sd, state, &routing);472}473 474static bool max96717_pipe_pclkdet(struct max96717_priv *priv)475{476 u64 val = 0;477 478 cci_read(priv->regmap, MAX96717_VIDEO_TX2, &val, NULL);479 480 return val & MAX96717_VIDEO_PCLKDET;481}482 483static int max96717_log_status(struct v4l2_subdev *sd)484{485 struct max96717_priv *priv = sd_to_max96717(sd);486 struct device *dev = &priv->client->dev;487 488 dev_info(dev, "Serializer: max96717\n");489 dev_info(dev, "Pipe: pclkdet:%d\n", max96717_pipe_pclkdet(priv));490 491 return 0;492}493 494static int max96717_enable_streams(struct v4l2_subdev *sd,495 struct v4l2_subdev_state *state, u32 pad,496 u64 streams_mask)497{498 struct max96717_priv *priv = sd_to_max96717(sd);499 u64 sink_streams;500 int ret;501 502 if (!priv->enabled_source_streams)503 max96717_start_csi(priv, true);504 505 ret = max96717_apply_patgen(priv, state);506 if (ret)507 goto stop_csi;508 509 if (!priv->pattern) {510 sink_streams =511 v4l2_subdev_state_xlate_streams(state,512 MAX96717_PAD_SOURCE,513 MAX96717_PAD_SINK,514 &streams_mask);515 516 ret = v4l2_subdev_enable_streams(priv->source_sd,517 priv->source_sd_pad,518 sink_streams);519 if (ret)520 goto stop_csi;521 }522 523 priv->enabled_source_streams |= streams_mask;524 525 return 0;526 527stop_csi:528 if (!priv->enabled_source_streams)529 max96717_start_csi(priv, false);530 531 return ret;532}533 534static int max96717_disable_streams(struct v4l2_subdev *sd,535 struct v4l2_subdev_state *state, u32 pad,536 u64 streams_mask)537{538 struct max96717_priv *priv = sd_to_max96717(sd);539 u64 sink_streams;540 541 /*542 * Stop the CSI receiver first then the source,543 * otherwise the device may become unresponsive544 * while holding the I2C bus low.545 */546 priv->enabled_source_streams &= ~streams_mask;547 if (!priv->enabled_source_streams)548 max96717_start_csi(priv, false);549 550 if (!priv->pattern) {551 int ret;552 553 sink_streams =554 v4l2_subdev_state_xlate_streams(state,555 MAX96717_PAD_SOURCE,556 MAX96717_PAD_SINK,557 &streams_mask);558 559 ret = v4l2_subdev_disable_streams(priv->source_sd,560 priv->source_sd_pad,561 sink_streams);562 if (ret)563 return ret;564 }565 566 return 0;567}568 569static const struct v4l2_subdev_pad_ops max96717_pad_ops = {570 .enable_streams = max96717_enable_streams,571 .disable_streams = max96717_disable_streams,572 .set_routing = max96717_set_routing,573 .get_fmt = v4l2_subdev_get_fmt,574 .set_fmt = max96717_set_fmt,575};576 577static const struct v4l2_subdev_core_ops max96717_subdev_core_ops = {578 .log_status = max96717_log_status,579};580 581static const struct v4l2_subdev_internal_ops max96717_internal_ops = {582 .init_state = max96717_init_state,583};584 585static const struct v4l2_subdev_ops max96717_subdev_ops = {586 .core = &max96717_subdev_core_ops,587 .pad = &max96717_pad_ops,588};589 590static const struct media_entity_operations max96717_entity_ops = {591 .link_validate = v4l2_subdev_link_validate,592};593 594static int max96717_notify_bound(struct v4l2_async_notifier *notifier,595 struct v4l2_subdev *source_subdev,596 struct v4l2_async_connection *asd)597{598 struct max96717_priv *priv = sd_to_max96717(notifier->sd);599 struct device *dev = &priv->client->dev;600 int ret;601 602 ret = media_entity_get_fwnode_pad(&source_subdev->entity,603 source_subdev->fwnode,604 MEDIA_PAD_FL_SOURCE);605 if (ret < 0) {606 dev_err(dev, "Failed to find pad for %s\n",607 source_subdev->name);608 return ret;609 }610 611 priv->source_sd = source_subdev;612 priv->source_sd_pad = ret;613 614 ret = media_create_pad_link(&source_subdev->entity, priv->source_sd_pad,615 &priv->sd.entity, 0,616 MEDIA_LNK_FL_ENABLED |617 MEDIA_LNK_FL_IMMUTABLE);618 if (ret) {619 dev_err(dev, "Unable to link %s:%u -> %s:0\n",620 source_subdev->name, priv->source_sd_pad,621 priv->sd.name);622 return ret;623 }624 625 return 0;626}627 628static const struct v4l2_async_notifier_operations max96717_notify_ops = {629 .bound = max96717_notify_bound,630};631 632static int max96717_v4l2_notifier_register(struct max96717_priv *priv)633{634 struct device *dev = &priv->client->dev;635 struct v4l2_async_connection *asd;636 struct fwnode_handle *ep_fwnode;637 int ret;638 639 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),640 MAX96717_PAD_SINK, 0, 0);641 if (!ep_fwnode) {642 dev_err(dev, "No graph endpoint\n");643 return -ENODEV;644 }645 646 v4l2_async_subdev_nf_init(&priv->notifier, &priv->sd);647 648 asd = v4l2_async_nf_add_fwnode_remote(&priv->notifier, ep_fwnode,649 struct v4l2_async_connection);650 651 fwnode_handle_put(ep_fwnode);652 653 if (IS_ERR(asd)) {654 dev_err(dev, "Failed to add subdev: %ld", PTR_ERR(asd));655 v4l2_async_nf_cleanup(&priv->notifier);656 return PTR_ERR(asd);657 }658 659 priv->notifier.ops = &max96717_notify_ops;660 661 ret = v4l2_async_nf_register(&priv->notifier);662 if (ret) {663 dev_err(dev, "Failed to register subdev_notifier");664 v4l2_async_nf_cleanup(&priv->notifier);665 return ret;666 }667 668 return 0;669}670 671static int max96717_subdev_init(struct max96717_priv *priv)672{673 struct device *dev = &priv->client->dev;674 int ret;675 676 v4l2_i2c_subdev_init(&priv->sd, priv->client, &max96717_subdev_ops);677 priv->sd.internal_ops = &max96717_internal_ops;678 679 v4l2_ctrl_handler_init(&priv->ctrl_handler, 1);680 priv->sd.ctrl_handler = &priv->ctrl_handler;681 682 v4l2_ctrl_new_std_menu_items(&priv->ctrl_handler,683 &max96717_ctrl_ops,684 V4L2_CID_TEST_PATTERN,685 ARRAY_SIZE(max96717_test_pattern) - 1,686 0, 0, max96717_test_pattern);687 if (priv->ctrl_handler.error) {688 ret = priv->ctrl_handler.error;689 goto err_free_ctrl;690 }691 692 priv->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_STREAMS;693 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;694 priv->sd.entity.ops = &max96717_entity_ops;695 696 priv->pads[MAX96717_PAD_SINK].flags = MEDIA_PAD_FL_SINK;697 priv->pads[MAX96717_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;698 699 ret = media_entity_pads_init(&priv->sd.entity, 2, priv->pads);700 if (ret)701 return dev_err_probe(dev, ret, "Failed to init pads\n");702 703 ret = v4l2_subdev_init_finalize(&priv->sd);704 if (ret) {705 dev_err_probe(dev, ret,706 "v4l2 subdev init finalized failed\n");707 goto err_entity_cleanup;708 }709 ret = max96717_v4l2_notifier_register(priv);710 if (ret) {711 dev_err_probe(dev, ret,712 "v4l2 subdev notifier register failed\n");713 goto err_free_state;714 }715 716 ret = v4l2_async_register_subdev(&priv->sd);717 if (ret) {718 dev_err_probe(dev, ret, "v4l2_async_register_subdev error\n");719 goto err_unreg_notif;720 }721 722 return 0;723 724err_unreg_notif:725 v4l2_async_nf_unregister(&priv->notifier);726 v4l2_async_nf_cleanup(&priv->notifier);727err_free_state:728 v4l2_subdev_cleanup(&priv->sd);729err_entity_cleanup:730 media_entity_cleanup(&priv->sd.entity);731err_free_ctrl:732 v4l2_ctrl_handler_free(&priv->ctrl_handler);733 734 return ret;735}736 737static void max96717_subdev_uninit(struct max96717_priv *priv)738{739 v4l2_async_unregister_subdev(&priv->sd);740 v4l2_async_nf_unregister(&priv->notifier);741 v4l2_async_nf_cleanup(&priv->notifier);742 v4l2_subdev_cleanup(&priv->sd);743 media_entity_cleanup(&priv->sd.entity);744 v4l2_ctrl_handler_free(&priv->ctrl_handler);745}746 747struct max96717_pll_predef_freq {748 unsigned long freq;749 bool is_alt;750 u8 val;751};752 753static const struct max96717_pll_predef_freq max96717_predef_freqs[] = {754 { 13500000, true, 0 }, { 19200000, false, 0 },755 { 24000000, true, 1 }, { 27000000, false, 1 },756 { 37125000, false, 2 }, { 74250000, false, 3 },757};758 759static unsigned long760max96717_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)761{762 struct max96717_priv *priv = clk_hw_to_max96717(hw);763 764 return max96717_predef_freqs[priv->pll_predef_index].freq;765}766 767static unsigned int max96717_clk_find_best_index(struct max96717_priv *priv,768 unsigned long rate)769{770 unsigned int i, idx = 0;771 unsigned long diff_new, diff_old = U32_MAX;772 773 for (i = 0; i < ARRAY_SIZE(max96717_predef_freqs); i++) {774 diff_new = abs(rate - max96717_predef_freqs[i].freq);775 if (diff_new < diff_old) {776 diff_old = diff_new;777 idx = i;778 }779 }780 781 return idx;782}783 784static long max96717_clk_round_rate(struct clk_hw *hw, unsigned long rate,785 unsigned long *parent_rate)786{787 struct max96717_priv *priv = clk_hw_to_max96717(hw);788 struct device *dev = &priv->client->dev;789 unsigned int idx;790 791 idx = max96717_clk_find_best_index(priv, rate);792 793 if (rate != max96717_predef_freqs[idx].freq) {794 dev_warn(dev, "Request CLK freq:%lu, found CLK freq:%lu\n",795 rate, max96717_predef_freqs[idx].freq);796 }797 798 return max96717_predef_freqs[idx].freq;799}800 801static int max96717_clk_set_rate(struct clk_hw *hw, unsigned long rate,802 unsigned long parent_rate)803{804 struct max96717_priv *priv = clk_hw_to_max96717(hw);805 unsigned int val, idx;806 int ret = 0;807 808 idx = max96717_clk_find_best_index(priv, rate);809 810 val = FIELD_PREP(REFGEN_PREDEF_FREQ_MASK,811 max96717_predef_freqs[idx].val);812 813 if (max96717_predef_freqs[idx].is_alt)814 val |= REFGEN_PREDEF_FREQ_ALT;815 816 val |= REFGEN_RST | REFGEN_PREDEF_EN;817 818 cci_write(priv->regmap, REF_VTG0, val, &ret);819 cci_update_bits(priv->regmap, REF_VTG0, REFGEN_RST | REFGEN_EN,820 REFGEN_EN, &ret);821 if (ret)822 return ret;823 824 priv->pll_predef_index = idx;825 826 return 0;827}828 829static int max96717_clk_prepare(struct clk_hw *hw)830{831 struct max96717_priv *priv = clk_hw_to_max96717(hw);832 833 return cci_update_bits(priv->regmap, MAX96717_REG6, RCLKEN,834 RCLKEN, NULL);835}836 837static void max96717_clk_unprepare(struct clk_hw *hw)838{839 struct max96717_priv *priv = clk_hw_to_max96717(hw);840 841 cci_update_bits(priv->regmap, MAX96717_REG6, RCLKEN, 0, NULL);842}843 844static const struct clk_ops max96717_clk_ops = {845 .prepare = max96717_clk_prepare,846 .unprepare = max96717_clk_unprepare,847 .set_rate = max96717_clk_set_rate,848 .recalc_rate = max96717_clk_recalc_rate,849 .round_rate = max96717_clk_round_rate,850};851 852static int max96717_register_clkout(struct max96717_priv *priv)853{854 struct device *dev = &priv->client->dev;855 struct clk_init_data init = { .ops = &max96717_clk_ops };856 int ret;857 858 init.name = kasprintf(GFP_KERNEL, "max96717.%s.clk_out", dev_name(dev));859 if (!init.name)860 return -ENOMEM;861 862 /* RCLKSEL Reference PLL output */863 ret = cci_update_bits(priv->regmap, MAX96717_REG3, MAX96717_RCLKSEL,864 MAX96717_RCLKSEL, NULL);865 /* MFP4 fastest slew rate */866 cci_update_bits(priv->regmap, PIO_SLEW_1, BIT(5) | BIT(4), 0, &ret);867 if (ret)868 goto free_init_name;869 870 priv->clk_hw.init = &init;871 872 /* Initialize to 24 MHz */873 ret = max96717_clk_set_rate(&priv->clk_hw,874 MAX96717_DEFAULT_CLKOUT_RATE, 0);875 if (ret < 0)876 goto free_init_name;877 878 ret = devm_clk_hw_register(dev, &priv->clk_hw);879 kfree(init.name);880 if (ret)881 return dev_err_probe(dev, ret, "Cannot register clock HW\n");882 883 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,884 &priv->clk_hw);885 if (ret)886 return dev_err_probe(dev, ret,887 "Cannot add OF clock provider\n");888 889 return 0;890 891free_init_name:892 kfree(init.name);893 return ret;894}895 896static int max96717_init_csi_lanes(struct max96717_priv *priv)897{898 struct v4l2_mbus_config_mipi_csi2 *mipi = &priv->mipi_csi2;899 unsigned long lanes_used = 0;900 unsigned int nlanes, lane, val = 0;901 int ret;902 903 nlanes = mipi->num_data_lanes;904 905 ret = cci_update_bits(priv->regmap, MAX96717_MIPI_RX1,906 MAX96717_MIPI_LANES_CNT,907 FIELD_PREP(MAX96717_MIPI_LANES_CNT,908 nlanes - 1), NULL);909 910 /* lanes polarity */911 for (lane = 0; lane < nlanes + 1; lane++) {912 if (!mipi->lane_polarities[lane])913 continue;914 /* Clock lane */915 if (lane == 0)916 val |= BIT(2);917 else if (lane < 3)918 val |= BIT(lane - 1);919 else920 val |= BIT(lane);921 }922 923 cci_update_bits(priv->regmap, MAX96717_MIPI_RX5,924 MAX96717_PHY2_LANES_POL,925 FIELD_PREP(MAX96717_PHY2_LANES_POL, val), &ret);926 927 cci_update_bits(priv->regmap, MAX96717_MIPI_RX4,928 MAX96717_PHY1_LANES_POL,929 FIELD_PREP(MAX96717_PHY1_LANES_POL,930 val >> 3), &ret);931 /* lanes mapping */932 for (lane = 0, val = 0; lane < nlanes; lane++) {933 val |= (mipi->data_lanes[lane] - 1) << (lane * 2);934 lanes_used |= BIT(mipi->data_lanes[lane] - 1);935 }936 937 /*938 * Unused lanes need to be mapped as well to not have939 * the same lanes mapped twice.940 */941 for (; lane < MAX96717_CSI_NLANES; lane++) {942 unsigned int idx = find_first_zero_bit(&lanes_used,943 MAX96717_CSI_NLANES);944 945 val |= idx << (lane * 2);946 lanes_used |= BIT(idx);947 }948 949 cci_update_bits(priv->regmap, MAX96717_MIPI_RX3,950 MAX96717_PHY1_LANES_MAP,951 FIELD_PREP(MAX96717_PHY1_LANES_MAP, val), &ret);952 953 return cci_update_bits(priv->regmap, MAX96717_MIPI_RX2,954 MAX96717_PHY2_LANES_MAP,955 FIELD_PREP(MAX96717_PHY2_LANES_MAP, val >> 4),956 &ret);957}958 959static int max96717_hw_init(struct max96717_priv *priv)960{961 struct device *dev = &priv->client->dev;962 u64 dev_id, val;963 int ret;964 965 ret = cci_read(priv->regmap, MAX96717_DEV_ID, &dev_id, NULL);966 if (ret)967 return dev_err_probe(dev, ret,968 "Fail to read the device id\n");969 970 if (dev_id != MAX96717_DEVICE_ID && dev_id != MAX96717F_DEVICE_ID)971 return dev_err_probe(dev, -EOPNOTSUPP,972 "Unsupported device id got %x\n", (u8)dev_id);973 974 ret = cci_read(priv->regmap, MAX96717_DEV_REV, &val, NULL);975 if (ret)976 return dev_err_probe(dev, ret,977 "Fail to read device revision");978 979 dev_dbg(dev, "Found %x (rev %lx)\n", (u8)dev_id,980 (u8)val & MAX96717_DEV_REV_MASK);981 982 ret = cci_read(priv->regmap, MAX96717_MIPI_RX_EXT11, &val, NULL);983 if (ret)984 return dev_err_probe(dev, ret,985 "Fail to read mipi rx extension");986 987 if (!(val & MAX96717_TUN_MODE))988 return dev_err_probe(dev, -EOPNOTSUPP,989 "Only supporting tunnel mode");990 991 return max96717_init_csi_lanes(priv);992}993 994static int max96717_parse_dt(struct max96717_priv *priv)995{996 struct device *dev = &priv->client->dev;997 struct v4l2_fwnode_endpoint vep = { .bus_type = V4L2_MBUS_CSI2_DPHY };998 struct fwnode_handle *ep_fwnode;999 unsigned char num_data_lanes;1000 int ret;1001 1002 ep_fwnode = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev),1003 MAX96717_PAD_SINK, 0, 0);1004 if (!ep_fwnode)1005 return dev_err_probe(dev, -ENOENT, "no endpoint found\n");1006 1007 ret = v4l2_fwnode_endpoint_parse(ep_fwnode, &vep);1008 1009 fwnode_handle_put(ep_fwnode);1010 1011 if (ret < 0)1012 return dev_err_probe(dev, ret, "Failed to parse sink endpoint");1013 1014 num_data_lanes = vep.bus.mipi_csi2.num_data_lanes;1015 if (num_data_lanes < 1 || num_data_lanes > MAX96717_CSI_NLANES)1016 return dev_err_probe(dev, -EINVAL,1017 "Invalid data lanes must be 1 to 4\n");1018 1019 priv->mipi_csi2 = vep.bus.mipi_csi2;1020 1021 return 0;1022}1023 1024static int max96717_probe(struct i2c_client *client)1025{1026 struct device *dev = &client->dev;1027 struct max96717_priv *priv;1028 int ret;1029 1030 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);1031 if (!priv)1032 return -ENOMEM;1033 1034 priv->client = client;1035 priv->regmap = devm_cci_regmap_init_i2c(client, 16);1036 if (IS_ERR(priv->regmap)) {1037 ret = PTR_ERR(priv->regmap);1038 return dev_err_probe(dev, ret, "Failed to init regmap\n");1039 }1040 1041 ret = max96717_parse_dt(priv);1042 if (ret)1043 return dev_err_probe(dev, ret, "Failed to parse the dt\n");1044 1045 ret = max96717_hw_init(priv);1046 if (ret)1047 return dev_err_probe(dev, ret,1048 "Failed to initialize the hardware\n");1049 1050 ret = max96717_gpiochip_probe(priv);1051 if (ret)1052 return dev_err_probe(&client->dev, ret,1053 "Failed to init gpiochip\n");1054 1055 ret = max96717_register_clkout(priv);1056 if (ret)1057 return dev_err_probe(dev, ret, "Failed to register clkout\n");1058 1059 ret = max96717_subdev_init(priv);1060 if (ret)1061 return dev_err_probe(dev, ret,1062 "Failed to initialize v4l2 subdev\n");1063 1064 ret = max96717_i2c_mux_init(priv);1065 if (ret) {1066 dev_err_probe(dev, ret, "failed to add remote i2c adapter\n");1067 max96717_subdev_uninit(priv);1068 }1069 1070 return ret;1071}1072 1073static void max96717_remove(struct i2c_client *client)1074{1075 struct v4l2_subdev *sd = i2c_get_clientdata(client);1076 struct max96717_priv *priv = sd_to_max96717(sd);1077 1078 max96717_subdev_uninit(priv);1079 i2c_mux_del_adapters(priv->mux);1080}1081 1082static const struct of_device_id max96717_of_ids[] = {1083 { .compatible = "maxim,max96717f" },1084 { }1085};1086MODULE_DEVICE_TABLE(of, max96717_of_ids);1087 1088static struct i2c_driver max96717_i2c_driver = {1089 .driver = {1090 .name = "max96717",1091 .of_match_table = max96717_of_ids,1092 },1093 .probe = max96717_probe,1094 .remove = max96717_remove,1095};1096 1097module_i2c_driver(max96717_i2c_driver);1098 1099MODULE_DESCRIPTION("Maxim GMSL2 MAX96717 Serializer Driver");1100MODULE_AUTHOR("Julien Massot <julien.massot@collabora.com>");1101MODULE_LICENSE("GPL");1102