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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * tc358743 - Toshiba HDMI to CSI-2 bridge - register names and bit masks4 *5 * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights6 * reserved.7 */8 9/*10 * References (c = chapter, p = page):11 * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.6012 */13 14/* Bit masks has prefix 'MASK_' and options after '_'. */15 16#ifndef __TC358743_REGS_H17#define __TC358743_REGS_H18 19#define CHIPID 0x000020#define MASK_CHIPID 0xff0021#define MASK_REVID 0x00ff22 23#define SYSCTL 0x000224#define MASK_IRRST 0x080025#define MASK_CECRST 0x040026#define MASK_CTXRST 0x020027#define MASK_HDMIRST 0x010028#define MASK_SLEEP 0x000129 30#define CONFCTL 0x000431#define MASK_PWRISO 0x800032#define MASK_ACLKOPT 0x100033#define MASK_AUDCHNUM 0x0c0034#define MASK_AUDCHNUM_8 0x000035#define MASK_AUDCHNUM_6 0x040036#define MASK_AUDCHNUM_4 0x080037#define MASK_AUDCHNUM_2 0x0c0038#define MASK_AUDCHSEL 0x020039#define MASK_I2SDLYOPT 0x010040#define MASK_YCBCRFMT 0x00c041#define MASK_YCBCRFMT_444 0x000042#define MASK_YCBCRFMT_422_12_BIT 0x004043#define MASK_YCBCRFMT_COLORBAR 0x008044#define MASK_YCBCRFMT_422_8_BIT 0x00c045#define MASK_INFRMEN 0x002046#define MASK_AUDOUTSEL 0x001847#define MASK_AUDOUTSEL_CSI 0x000048#define MASK_AUDOUTSEL_I2S 0x001049#define MASK_AUDOUTSEL_TDM 0x001850#define MASK_AUTOINDEX 0x000451#define MASK_ABUFEN 0x000252#define MASK_VBUFEN 0x000153 54#define FIFOCTL 0x000655 56#define INTSTATUS 0x001457#define MASK_AMUTE_INT 0x040058#define MASK_HDMI_INT 0x020059#define MASK_CSI_INT 0x010060#define MASK_SYS_INT 0x002061#define MASK_CEC_EINT 0x001062#define MASK_CEC_TINT 0x000863#define MASK_CEC_RINT 0x000464#define MASK_IR_EINT 0x000265#define MASK_IR_DINT 0x000166 67#define INTMASK 0x001668#define MASK_AMUTE_MSK 0x040069#define MASK_HDMI_MSK 0x020070#define MASK_CSI_MSK 0x010071#define MASK_SYS_MSK 0x002072#define MASK_CEC_EMSK 0x001073#define MASK_CEC_TMSK 0x000874#define MASK_CEC_RMSK 0x000475#define MASK_IR_EMSK 0x000276#define MASK_IR_DMSK 0x000177 78#define INTFLAG 0x001879#define INTSYSSTATUS 0x001A80 81#define PLLCTL0 0x002082#define MASK_PLL_PRD 0xf00083#define SET_PLL_PRD(prd) ((((prd) - 1) << 12) &\84 MASK_PLL_PRD)85#define MASK_PLL_FBD 0x01ff86#define SET_PLL_FBD(fbd) (((fbd) - 1) & MASK_PLL_FBD)87 88#define PLLCTL1 0x002289#define MASK_PLL_FRS 0x0c0090#define SET_PLL_FRS(frs) (((frs) << 10) & MASK_PLL_FRS)91#define MASK_PLL_LBWS 0x030092#define MASK_LFBREN 0x004093#define MASK_BYPCKEN 0x002094#define MASK_CKEN 0x001095#define MASK_RESETB 0x000296#define MASK_PLL_EN 0x000197 98#define CLW_CNTRL 0x014099#define MASK_CLW_LANEDISABLE 0x0001100 101#define D0W_CNTRL 0x0144102#define MASK_D0W_LANEDISABLE 0x0001103 104#define D1W_CNTRL 0x0148105#define MASK_D1W_LANEDISABLE 0x0001106 107#define D2W_CNTRL 0x014C108#define MASK_D2W_LANEDISABLE 0x0001109 110#define D3W_CNTRL 0x0150111#define MASK_D3W_LANEDISABLE 0x0001112 113#define STARTCNTRL 0x0204114#define MASK_START 0x00000001115 116#define LINEINITCNT 0x0210117#define LPTXTIMECNT 0x0214118#define TCLK_HEADERCNT 0x0218119#define TCLK_TRAILCNT 0x021C120#define THS_HEADERCNT 0x0220121#define TWAKEUP 0x0224122#define TCLK_POSTCNT 0x0228123#define THS_TRAILCNT 0x022C124#define HSTXVREGCNT 0x0230125 126#define HSTXVREGEN 0x0234127#define MASK_D3M_HSTXVREGEN 0x0010128#define MASK_D2M_HSTXVREGEN 0x0008129#define MASK_D1M_HSTXVREGEN 0x0004130#define MASK_D0M_HSTXVREGEN 0x0002131#define MASK_CLM_HSTXVREGEN 0x0001132 133 134#define TXOPTIONCNTRL 0x0238135#define MASK_CONTCLKMODE 0x00000001136 137#define CSI_CONTROL 0x040C138#define MASK_CSI_MODE 0x8000139#define MASK_HTXTOEN 0x0400140#define MASK_TXHSMD 0x0080141#define MASK_HSCKMD 0x0020142#define MASK_NOL 0x0006143#define MASK_NOL_1 0x0000144#define MASK_NOL_2 0x0002145#define MASK_NOL_3 0x0004146#define MASK_NOL_4 0x0006147#define MASK_EOTDIS 0x0001148 149#define CSI_INT 0x0414150#define MASK_INTHLT 0x00000008151#define MASK_INTER 0x00000004152 153#define CSI_INT_ENA 0x0418154#define MASK_IENHLT 0x00000008155#define MASK_IENER 0x00000004156 157#define CSI_ERR 0x044C158#define MASK_INER 0x00000200159#define MASK_WCER 0x00000100160#define MASK_QUNK 0x00000010161#define MASK_TXBRK 0x00000002162 163#define CSI_ERR_INTENA 0x0450164#define CSI_ERR_HALT 0x0454165 166#define CSI_CONFW 0x0500167#define MASK_MODE 0xe0000000168#define MASK_MODE_SET 0xa0000000169#define MASK_MODE_CLEAR 0xc0000000170#define MASK_ADDRESS 0x1f000000171#define MASK_ADDRESS_CSI_CONTROL 0x03000000172#define MASK_ADDRESS_CSI_INT_ENA 0x06000000173#define MASK_ADDRESS_CSI_ERR_INTENA 0x14000000174#define MASK_ADDRESS_CSI_ERR_HALT 0x15000000175#define MASK_DATA 0x0000ffff176 177#define CSI_INT_CLR 0x050C178#define MASK_ICRER 0x00000004179 180#define CSI_START 0x0518181#define MASK_STRT 0x00000001182 183/* *** CEC (32 bit) *** */184#define CECHCLK 0x0028 /* 16 bits */185#define MASK_CECHCLK (0x7ff << 0)186 187#define CECLCLK 0x002a /* 16 bits */188#define MASK_CECLCLK (0x7ff << 0)189 190#define CECEN 0x0600191#define MASK_CECEN 0x0001192 193#define CECADD 0x0604194#define CECRST 0x0608195#define MASK_CECRESET 0x0001196 197#define CECREN 0x060c198#define MASK_CECREN 0x0001199 200#define CECRCTL1 0x0614201#define MASK_CECACKDIS (1 << 24)202#define MASK_CECHNC (3 << 20)203#define MASK_CECLNC (7 << 16)204#define MASK_CECMIN (7 << 12)205#define MASK_CECMAX (7 << 8)206#define MASK_CECDAT (7 << 4)207#define MASK_CECTOUT (3 << 2)208#define MASK_CECRIHLD (1 << 1)209#define MASK_CECOTH (1 << 0)210 211#define CECRCTL2 0x0618212#define MASK_CECSWAV3 (7 << 12)213#define MASK_CECSWAV2 (7 << 8)214#define MASK_CECSWAV1 (7 << 4)215#define MASK_CECSWAV0 (7 << 0)216 217#define CECRCTL3 0x061c218#define MASK_CECWAV3 (7 << 20)219#define MASK_CECWAV2 (7 << 16)220#define MASK_CECWAV1 (7 << 12)221#define MASK_CECWAV0 (7 << 8)222#define MASK_CECACKEI (1 << 4)223#define MASK_CECMINEI (1 << 3)224#define MASK_CECMAXEI (1 << 2)225#define MASK_CECRSTEI (1 << 1)226#define MASK_CECWAVEI (1 << 0)227 228#define CECTEN 0x0620229#define MASK_CECTBUSY (1 << 1)230#define MASK_CECTEN (1 << 0)231 232#define CECTCTL 0x0628233#define MASK_CECSTRS (7 << 20)234#define MASK_CECSPRD (7 << 16)235#define MASK_CECDTRS (7 << 12)236#define MASK_CECDPRD (15 << 8)237#define MASK_CECBRD (1 << 4)238#define MASK_CECFREE (15 << 0)239 240#define CECRSTAT 0x062c241#define MASK_CECRIWA (1 << 6)242#define MASK_CECRIOR (1 << 5)243#define MASK_CECRIACK (1 << 4)244#define MASK_CECRIMIN (1 << 3)245#define MASK_CECRIMAX (1 << 2)246#define MASK_CECRISTA (1 << 1)247#define MASK_CECRIEND (1 << 0)248 249#define CECTSTAT 0x0630250#define MASK_CECTIUR (1 << 4)251#define MASK_CECTIACK (1 << 3)252#define MASK_CECTIAL (1 << 2)253#define MASK_CECTIEND (1 << 1)254 255#define CECRBUF1 0x0634256#define MASK_CECRACK (1 << 9)257#define MASK_CECEOM (1 << 8)258#define MASK_CECRBYTE (0xff << 0)259 260#define CECTBUF1 0x0674261#define MASK_CECTEOM (1 << 8)262#define MASK_CECTBYTE (0xff << 0)263 264#define CECRCTR 0x06b4265#define MASK_CECRCTR (0x1f << 0)266 267#define CECIMSK 0x06c0268#define MASK_CECTIM (1 << 1)269#define MASK_CECRIM (1 << 0)270 271#define CECICLR 0x06cc272#define MASK_CECTICLR (1 << 1)273#define MASK_CECRICLR (1 << 0)274 275 276#define HDMI_INT0 0x8500277#define MASK_I_KEY 0x80278#define MASK_I_MISC 0x02279#define MASK_I_PHYERR 0x01280 281#define HDMI_INT1 0x8501282#define MASK_I_GBD 0x80283#define MASK_I_HDCP 0x40284#define MASK_I_ERR 0x20285#define MASK_I_AUD 0x10286#define MASK_I_CBIT 0x08287#define MASK_I_PACKET 0x04288#define MASK_I_CLK 0x02289#define MASK_I_SYS 0x01290 291#define SYS_INT 0x8502292#define MASK_I_ACR_CTS 0x80293#define MASK_I_ACRN 0x40294#define MASK_I_DVI 0x20295#define MASK_I_HDMI 0x10296#define MASK_I_NOPMBDET 0x08297#define MASK_I_DPMBDET 0x04298#define MASK_I_TMDS 0x02299#define MASK_I_DDC 0x01300 301#define CLK_INT 0x8503302#define MASK_I_OUT_H_CHG 0x40303#define MASK_I_IN_DE_CHG 0x20304#define MASK_I_IN_HV_CHG 0x10305#define MASK_I_DC_CHG 0x08306#define MASK_I_PXCLK_CHG 0x04307#define MASK_I_PHYCLK_CHG 0x02308#define MASK_I_TMDSCLK_CHG 0x01309 310#define CBIT_INT 0x8505311#define MASK_I_AF_LOCK 0x80312#define MASK_I_AF_UNLOCK 0x40313#define MASK_I_CBIT_FS 0x02314 315#define AUDIO_INT 0x8506316 317#define ERR_INT 0x8507318#define MASK_I_EESS_ERR 0x80319 320#define HDCP_INT 0x8508321#define MASK_I_AVM_SET 0x80322#define MASK_I_AVM_CLR 0x40323#define MASK_I_LINKERR 0x20324#define MASK_I_SHA_END 0x10325#define MASK_I_R0_END 0x08326#define MASK_I_KM_END 0x04327#define MASK_I_AKSV_END 0x02328#define MASK_I_AN_END 0x01329 330#define MISC_INT 0x850B331#define MASK_I_AS_LAYOUT 0x10332#define MASK_I_NO_SPD 0x08333#define MASK_I_NO_VS 0x03334#define MASK_I_SYNC_CHG 0x02335#define MASK_I_AUDIO_MUTE 0x01336 337#define KEY_INT 0x850F338 339#define SYS_INTM 0x8512340#define MASK_M_ACR_CTS 0x80341#define MASK_M_ACR_N 0x40342#define MASK_M_DVI_DET 0x20343#define MASK_M_HDMI_DET 0x10344#define MASK_M_NOPMBDET 0x08345#define MASK_M_BPMBDET 0x04346#define MASK_M_TMDS 0x02347#define MASK_M_DDC 0x01348 349#define CLK_INTM 0x8513350#define MASK_M_OUT_H_CHG 0x40351#define MASK_M_IN_DE_CHG 0x20352#define MASK_M_IN_HV_CHG 0x10353#define MASK_M_DC_CHG 0x08354#define MASK_M_PXCLK_CHG 0x04355#define MASK_M_PHYCLK_CHG 0x02356#define MASK_M_TMDS_CHG 0x01357 358#define PACKET_INTM 0x8514359 360#define CBIT_INTM 0x8515361#define MASK_M_AF_LOCK 0x80362#define MASK_M_AF_UNLOCK 0x40363#define MASK_M_CBIT_FS 0x02364 365#define AUDIO_INTM 0x8516366#define MASK_M_BUFINIT_END 0x01367 368#define ERR_INTM 0x8517369#define MASK_M_EESS_ERR 0x80370 371#define HDCP_INTM 0x8518372#define MASK_M_AVM_SET 0x80373#define MASK_M_AVM_CLR 0x40374#define MASK_M_LINKERR 0x20375#define MASK_M_SHA_END 0x10376#define MASK_M_R0_END 0x08377#define MASK_M_KM_END 0x04378#define MASK_M_AKSV_END 0x02379#define MASK_M_AN_END 0x01380 381#define MISC_INTM 0x851B382#define MASK_M_AS_LAYOUT 0x10383#define MASK_M_NO_SPD 0x08384#define MASK_M_NO_VS 0x03385#define MASK_M_SYNC_CHG 0x02386#define MASK_M_AUDIO_MUTE 0x01387 388#define KEY_INTM 0x851F389 390#define SYS_STATUS 0x8520391#define MASK_S_SYNC 0x80392#define MASK_S_AVMUTE 0x40393#define MASK_S_HDCP 0x20394#define MASK_S_HDMI 0x10395#define MASK_S_PHY_SCDT 0x08396#define MASK_S_PHY_PLL 0x04397#define MASK_S_TMDS 0x02398#define MASK_S_DDC5V 0x01399 400#define CSI_STATUS 0x0410401#define MASK_S_WSYNC 0x0400402#define MASK_S_TXACT 0x0200403#define MASK_S_RXACT 0x0100404#define MASK_S_HLT 0x0001405 406#define VI_STATUS1 0x8522407#define MASK_S_V_GBD 0x08408#define MASK_S_DEEPCOLOR 0x0c409#define MASK_S_V_422 0x02410#define MASK_S_V_INTERLACE 0x01411 412#define AU_STATUS0 0x8523413#define MASK_S_A_SAMPLE 0x01414 415#define VI_STATUS3 0x8528416#define MASK_S_V_COLOR 0x1e417#define MASK_LIMITED 0x01418 419#define PHY_CTL0 0x8531420#define MASK_PHY_SYSCLK_IND 0x02421#define MASK_PHY_CTL 0x01422 423 424#define PHY_CTL1 0x8532 /* Not in REF_01 */425#define MASK_PHY_AUTO_RST1 0xf0426#define MASK_PHY_AUTO_RST1_OFF 0x00427#define SET_PHY_AUTO_RST1_US(us) ((((us) / 200) << 4) & \428 MASK_PHY_AUTO_RST1)429#define MASK_FREQ_RANGE_MODE 0x0f430#define SET_FREQ_RANGE_MODE_CYCLES(cycles) (((cycles) - 1) & \431 MASK_FREQ_RANGE_MODE)432 433#define PHY_CTL2 0x8533 /* Not in REF_01 */434#define MASK_PHY_AUTO_RST4 0x04435#define MASK_PHY_AUTO_RST3 0x02436#define MASK_PHY_AUTO_RST2 0x01437#define MASK_PHY_AUTO_RSTn (MASK_PHY_AUTO_RST4 | \438 MASK_PHY_AUTO_RST3 | \439 MASK_PHY_AUTO_RST2)440 441#define PHY_EN 0x8534442#define MASK_ENABLE_PHY 0x01443 444#define PHY_RST 0x8535445#define MASK_RESET_CTRL 0x01 /* Reset active low */446 447#define PHY_BIAS 0x8536 /* Not in REF_01 */448 449#define PHY_CSQ 0x853F /* Not in REF_01 */450#define MASK_CSQ_CNT 0x0f451#define SET_CSQ_CNT_LEVEL(n) (n & MASK_CSQ_CNT)452 453#define SYS_FREQ0 0x8540454#define SYS_FREQ1 0x8541455 456#define SYS_CLK 0x8542 /* Not in REF_01 */457#define MASK_CLK_DIFF 0x0C458#define MASK_CLK_DIV 0x03459 460#define DDC_CTL 0x8543461#define MASK_DDC_ACK_POL 0x08462#define MASK_DDC_ACTION 0x04463#define MASK_DDC5V_MODE 0x03464#define MASK_DDC5V_MODE_0MS 0x00465#define MASK_DDC5V_MODE_50MS 0x01466#define MASK_DDC5V_MODE_100MS 0x02467#define MASK_DDC5V_MODE_200MS 0x03468 469#define HPD_CTL 0x8544470#define MASK_HPD_CTL0 0x10471#define MASK_HPD_OUT0 0x01472 473#define ANA_CTL 0x8545474#define MASK_APPL_PCSX 0x30475#define MASK_APPL_PCSX_HIZ 0x00476#define MASK_APPL_PCSX_L_FIX 0x10477#define MASK_APPL_PCSX_H_FIX 0x20478#define MASK_APPL_PCSX_NORMAL 0x30479#define MASK_ANALOG_ON 0x01480 481#define AVM_CTL 0x8546482 483#define INIT_END 0x854A484#define MASK_INIT_END 0x01485 486#define HDMI_DET 0x8552 /* Not in REF_01 */487#define MASK_HDMI_DET_MOD1 0x80488#define MASK_HDMI_DET_MOD0 0x40489#define MASK_HDMI_DET_V 0x30490#define MASK_HDMI_DET_V_SYNC 0x00491#define MASK_HDMI_DET_V_ASYNC_25MS 0x10492#define MASK_HDMI_DET_V_ASYNC_50MS 0x20493#define MASK_HDMI_DET_V_ASYNC_100MS 0x30494#define MASK_HDMI_DET_NUM 0x0f495 496#define HDCP_MODE 0x8560497#define MASK_MODE_RST_TN 0x20498#define MASK_LINE_REKEY 0x10499#define MASK_AUTO_CLR 0x04500#define MASK_MANUAL_AUTHENTICATION 0x02 /* Not in REF_01 */501 502#define HDCP_REG1 0x8563 /* Not in REF_01 */503#define MASK_AUTH_UNAUTH_SEL 0x70504#define MASK_AUTH_UNAUTH_SEL_12_FRAMES 0x70505#define MASK_AUTH_UNAUTH_SEL_8_FRAMES 0x60506#define MASK_AUTH_UNAUTH_SEL_4_FRAMES 0x50507#define MASK_AUTH_UNAUTH_SEL_2_FRAMES 0x40508#define MASK_AUTH_UNAUTH_SEL_64_FRAMES 0x30509#define MASK_AUTH_UNAUTH_SEL_32_FRAMES 0x20510#define MASK_AUTH_UNAUTH_SEL_16_FRAMES 0x10511#define MASK_AUTH_UNAUTH_SEL_ONCE 0x00512#define MASK_AUTH_UNAUTH 0x01513#define MASK_AUTH_UNAUTH_AUTO 0x01514 515#define HDCP_REG2 0x8564 /* Not in REF_01 */516#define MASK_AUTO_P3_RESET 0x0F517#define SET_AUTO_P3_RESET_FRAMES(n) (n & MASK_AUTO_P3_RESET)518#define MASK_AUTO_P3_RESET_OFF 0x00519 520#define VI_MODE 0x8570521#define MASK_RGB_DVI 0x08 /* Not in REF_01 */522 523#define VOUT_SET2 0x8573524#define MASK_SEL422 0x80525#define MASK_VOUT_422FIL_100 0x40526#define MASK_VOUTCOLORMODE 0x03527#define MASK_VOUTCOLORMODE_THROUGH 0x00528#define MASK_VOUTCOLORMODE_AUTO 0x01529#define MASK_VOUTCOLORMODE_MANUAL 0x03530 531#define VOUT_SET3 0x8574532#define MASK_VOUT_EXTCNT 0x08533 534#define VI_REP 0x8576535#define MASK_VOUT_COLOR_SEL 0xe0536#define MASK_VOUT_COLOR_RGB_FULL 0x00537#define MASK_VOUT_COLOR_RGB_LIMITED 0x20538#define MASK_VOUT_COLOR_601_YCBCR_FULL 0x40539#define MASK_VOUT_COLOR_601_YCBCR_LIMITED 0x60540#define MASK_VOUT_COLOR_709_YCBCR_FULL 0x80541#define MASK_VOUT_COLOR_709_YCBCR_LIMITED 0xa0542#define MASK_VOUT_COLOR_FULL_TO_LIMITED 0xc0543#define MASK_VOUT_COLOR_LIMITED_TO_FULL 0xe0544#define MASK_IN_REP_HEN 0x10545#define MASK_IN_REP 0x0f546 547#define VI_MUTE 0x857F548#define MASK_AUTO_MUTE 0xc0549#define MASK_VI_MUTE 0x10550 551#define DE_WIDTH_H_LO 0x8582 /* Not in REF_01 */552#define DE_WIDTH_H_HI 0x8583 /* Not in REF_01 */553#define DE_WIDTH_V_LO 0x8588 /* Not in REF_01 */554#define DE_WIDTH_V_HI 0x8589 /* Not in REF_01 */555#define H_SIZE_LO 0x858A /* Not in REF_01 */556#define H_SIZE_HI 0x858B /* Not in REF_01 */557#define V_SIZE_LO 0x858C /* Not in REF_01 */558#define V_SIZE_HI 0x858D /* Not in REF_01 */559#define FV_CNT_LO 0x85A1 /* Not in REF_01 */560#define FV_CNT_HI 0x85A2 /* Not in REF_01 */561 562#define FH_MIN0 0x85AA /* Not in REF_01 */563#define FH_MIN1 0x85AB /* Not in REF_01 */564#define FH_MAX0 0x85AC /* Not in REF_01 */565#define FH_MAX1 0x85AD /* Not in REF_01 */566 567#define HV_RST 0x85AF /* Not in REF_01 */568#define MASK_H_PI_RST 0x20569#define MASK_V_PI_RST 0x10570 571#define EDID_MODE 0x85C7572#define MASK_EDID_SPEED 0x40573#define MASK_EDID_MODE 0x03574#define MASK_EDID_MODE_DISABLE 0x00575#define MASK_EDID_MODE_DDC2B 0x01576#define MASK_EDID_MODE_E_DDC 0x02577 578#define EDID_LEN1 0x85CA579#define EDID_LEN2 0x85CB580 581#define HDCP_REG3 0x85D1 /* Not in REF_01 */582#define KEY_RD_CMD 0x01583 584#define FORCE_MUTE 0x8600585#define MASK_FORCE_AMUTE 0x10586#define MASK_FORCE_DMUTE 0x01587 588#define CMD_AUD 0x8601589#define MASK_CMD_BUFINIT 0x04590#define MASK_CMD_LOCKDET 0x02591#define MASK_CMD_MUTE 0x01592 593#define AUTO_CMD0 0x8602594#define MASK_AUTO_MUTE7 0x80595#define MASK_AUTO_MUTE6 0x40596#define MASK_AUTO_MUTE5 0x20597#define MASK_AUTO_MUTE4 0x10598#define MASK_AUTO_MUTE3 0x08599#define MASK_AUTO_MUTE2 0x04600#define MASK_AUTO_MUTE1 0x02601#define MASK_AUTO_MUTE0 0x01602 603#define AUTO_CMD1 0x8603604#define MASK_AUTO_MUTE10 0x04605#define MASK_AUTO_MUTE9 0x02606#define MASK_AUTO_MUTE8 0x01607 608#define AUTO_CMD2 0x8604609#define MASK_AUTO_PLAY3 0x08610#define MASK_AUTO_PLAY2 0x04611 612#define BUFINIT_START 0x8606613#define SET_BUFINIT_START_MS(milliseconds) ((milliseconds) / 100)614 615#define FS_MUTE 0x8607616#define MASK_FS_ELSE_MUTE 0x80617#define MASK_FS22_MUTE 0x40618#define MASK_FS24_MUTE 0x20619#define MASK_FS88_MUTE 0x10620#define MASK_FS96_MUTE 0x08621#define MASK_FS176_MUTE 0x04622#define MASK_FS192_MUTE 0x02623#define MASK_FS_NO_MUTE 0x01624 625#define FS_IMODE 0x8620626#define MASK_NLPCM_HMODE 0x40627#define MASK_NLPCM_SMODE 0x20628#define MASK_NLPCM_IMODE 0x10629#define MASK_FS_HMODE 0x08630#define MASK_FS_AMODE 0x04631#define MASK_FS_SMODE 0x02632#define MASK_FS_IMODE 0x01633 634#define FS_SET 0x8621635#define MASK_FS 0x0f636 637#define LOCKDET_REF0 0x8630638#define LOCKDET_REF1 0x8631639#define LOCKDET_REF2 0x8632640 641#define ACR_MODE 0x8640642#define MASK_ACR_LOAD 0x10643#define MASK_N_MODE 0x04644#define MASK_CTS_MODE 0x01645 646#define ACR_MDF0 0x8641647#define MASK_ACR_L2MDF 0x70648#define MASK_ACR_L2MDF_0_PPM 0x00649#define MASK_ACR_L2MDF_61_PPM 0x10650#define MASK_ACR_L2MDF_122_PPM 0x20651#define MASK_ACR_L2MDF_244_PPM 0x30652#define MASK_ACR_L2MDF_488_PPM 0x40653#define MASK_ACR_L2MDF_976_PPM 0x50654#define MASK_ACR_L2MDF_1976_PPM 0x60655#define MASK_ACR_L2MDF_3906_PPM 0x70656#define MASK_ACR_L1MDF 0x07657#define MASK_ACR_L1MDF_0_PPM 0x00658#define MASK_ACR_L1MDF_61_PPM 0x01659#define MASK_ACR_L1MDF_122_PPM 0x02660#define MASK_ACR_L1MDF_244_PPM 0x03661#define MASK_ACR_L1MDF_488_PPM 0x04662#define MASK_ACR_L1MDF_976_PPM 0x05663#define MASK_ACR_L1MDF_1976_PPM 0x06664#define MASK_ACR_L1MDF_3906_PPM 0x07665 666#define ACR_MDF1 0x8642667#define MASK_ACR_L3MDF 0x07668#define MASK_ACR_L3MDF_0_PPM 0x00669#define MASK_ACR_L3MDF_61_PPM 0x01670#define MASK_ACR_L3MDF_122_PPM 0x02671#define MASK_ACR_L3MDF_244_PPM 0x03672#define MASK_ACR_L3MDF_488_PPM 0x04673#define MASK_ACR_L3MDF_976_PPM 0x05674#define MASK_ACR_L3MDF_1976_PPM 0x06675#define MASK_ACR_L3MDF_3906_PPM 0x07676 677#define SDO_MODE1 0x8652678#define MASK_SDO_BIT_LENG 0x70679#define MASK_SDO_FMT 0x03680#define MASK_SDO_FMT_RIGHT 0x00681#define MASK_SDO_FMT_LEFT 0x01682#define MASK_SDO_FMT_I2S 0x02683 684#define DIV_MODE 0x8665 /* Not in REF_01 */685#define MASK_DIV_DLY 0xf0686#define SET_DIV_DLY_MS(milliseconds) ((((milliseconds) / 100) << 4) & \687 MASK_DIV_DLY)688#define MASK_DIV_MODE 0x01689 690#define NCO_F0_MOD 0x8670691#define MASK_NCO_F0_MOD 0x03692#define MASK_NCO_F0_MOD_42MHZ 0x00693#define MASK_NCO_F0_MOD_27MHZ 0x01694 695#define PK_INT_MODE 0x8709696#define MASK_ISRC2_INT_MODE 0x80697#define MASK_ISRC_INT_MODE 0x40698#define MASK_ACP_INT_MODE 0x20699#define MASK_VS_INT_MODE 0x10700#define MASK_SPD_INT_MODE 0x08701#define MASK_MS_INT_MODE 0x04702#define MASK_AUD_INT_MODE 0x02703#define MASK_AVI_INT_MODE 0x01704 705#define NO_PKT_LIMIT 0x870B706#define MASK_NO_ACP_LIMIT 0xf0707#define SET_NO_ACP_LIMIT_MS(milliseconds) ((((milliseconds) / 80) << 4) & \708 MASK_NO_ACP_LIMIT)709#define MASK_NO_AVI_LIMIT 0x0f710#define SET_NO_AVI_LIMIT_MS(milliseconds) (((milliseconds) / 80) & \711 MASK_NO_AVI_LIMIT)712 713#define NO_PKT_CLR 0x870C714#define MASK_NO_VS_CLR 0x40715#define MASK_NO_SPD_CLR 0x20716#define MASK_NO_ACP_CLR 0x10717#define MASK_NO_AVI_CLR1 0x02718#define MASK_NO_AVI_CLR0 0x01719 720#define ERR_PK_LIMIT 0x870D721#define NO_PKT_LIMIT2 0x870E722#define PK_AVI_0HEAD 0x8710723#define PK_AVI_1HEAD 0x8711724#define PK_AVI_2HEAD 0x8712725#define PK_AVI_0BYTE 0x8713726#define PK_AVI_1BYTE 0x8714727#define PK_AVI_2BYTE 0x8715728#define PK_AVI_3BYTE 0x8716729#define PK_AVI_4BYTE 0x8717730#define PK_AVI_5BYTE 0x8718731#define PK_AVI_6BYTE 0x8719732#define PK_AVI_7BYTE 0x871A733#define PK_AVI_8BYTE 0x871B734#define PK_AVI_9BYTE 0x871C735#define PK_AVI_10BYTE 0x871D736#define PK_AVI_11BYTE 0x871E737#define PK_AVI_12BYTE 0x871F738#define PK_AVI_13BYTE 0x8720739#define PK_AVI_14BYTE 0x8721740#define PK_AVI_15BYTE 0x8722741#define PK_AVI_16BYTE 0x8723742 743#define BKSV 0x8800744 745#define BCAPS 0x8840746#define MASK_HDMI_RSVD 0x80747#define MASK_REPEATER 0x40748#define MASK_READY 0x20749#define MASK_FASTI2C 0x10750#define MASK_1_1_FEA 0x02751#define MASK_FAST_REAU 0x01752 753#define BSTATUS1 0x8842754#define MASK_MAX_EXCED 0x08755 756#define EDID_RAM 0x8C00757#define NO_GDB_LIMIT 0x9007758 759#endif760