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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * drivers/media/i2c/tvp514x_regs.h4 *5 * Copyright (C) 2008 Texas Instruments Inc6 * Author: Vaibhav Hiremath <hvaibhav@ti.com>7 *8 * Contributors:9 * Sivaraj R <sivaraj@ti.com>10 * Brijesh R Jadav <brijesh.j@ti.com>11 * Hardik Shah <hardik.shah@ti.com>12 * Manjunath Hadli <mrh@ti.com>13 * Karicheri Muralidharan <m-karicheri2@ti.com>14 */15 16#ifndef _TVP514X_REGS_H17#define _TVP514X_REGS_H18 19/*20 * TVP5146/47 registers21 */22#define REG_INPUT_SEL (0x00)23#define REG_AFE_GAIN_CTRL (0x01)24#define REG_VIDEO_STD (0x02)25#define REG_OPERATION_MODE (0x03)26#define REG_AUTOSWITCH_MASK (0x04)27 28#define REG_COLOR_KILLER (0x05)29#define REG_LUMA_CONTROL1 (0x06)30#define REG_LUMA_CONTROL2 (0x07)31#define REG_LUMA_CONTROL3 (0x08)32 33#define REG_BRIGHTNESS (0x09)34#define REG_CONTRAST (0x0A)35#define REG_SATURATION (0x0B)36#define REG_HUE (0x0C)37 38#define REG_CHROMA_CONTROL1 (0x0D)39#define REG_CHROMA_CONTROL2 (0x0E)40 41/* 0x0F Reserved */42 43#define REG_COMP_PR_SATURATION (0x10)44#define REG_COMP_Y_CONTRAST (0x11)45#define REG_COMP_PB_SATURATION (0x12)46 47/* 0x13 Reserved */48 49#define REG_COMP_Y_BRIGHTNESS (0x14)50 51/* 0x15 Reserved */52 53#define REG_AVID_START_PIXEL_LSB (0x16)54#define REG_AVID_START_PIXEL_MSB (0x17)55#define REG_AVID_STOP_PIXEL_LSB (0x18)56#define REG_AVID_STOP_PIXEL_MSB (0x19)57 58#define REG_HSYNC_START_PIXEL_LSB (0x1A)59#define REG_HSYNC_START_PIXEL_MSB (0x1B)60#define REG_HSYNC_STOP_PIXEL_LSB (0x1C)61#define REG_HSYNC_STOP_PIXEL_MSB (0x1D)62 63#define REG_VSYNC_START_LINE_LSB (0x1E)64#define REG_VSYNC_START_LINE_MSB (0x1F)65#define REG_VSYNC_STOP_LINE_LSB (0x20)66#define REG_VSYNC_STOP_LINE_MSB (0x21)67 68#define REG_VBLK_START_LINE_LSB (0x22)69#define REG_VBLK_START_LINE_MSB (0x23)70#define REG_VBLK_STOP_LINE_LSB (0x24)71#define REG_VBLK_STOP_LINE_MSB (0x25)72 73/* 0x26 - 0x27 Reserved */74 75#define REG_FAST_SWTICH_CONTROL (0x28)76 77/* 0x29 Reserved */78 79#define REG_FAST_SWTICH_SCART_DELAY (0x2A)80 81/* 0x2B Reserved */82 83#define REG_SCART_DELAY (0x2C)84#define REG_CTI_DELAY (0x2D)85#define REG_CTI_CONTROL (0x2E)86 87/* 0x2F - 0x31 Reserved */88 89#define REG_SYNC_CONTROL (0x32)90#define REG_OUTPUT_FORMATTER1 (0x33)91#define REG_OUTPUT_FORMATTER2 (0x34)92#define REG_OUTPUT_FORMATTER3 (0x35)93#define REG_OUTPUT_FORMATTER4 (0x36)94#define REG_OUTPUT_FORMATTER5 (0x37)95#define REG_OUTPUT_FORMATTER6 (0x38)96#define REG_CLEAR_LOST_LOCK (0x39)97 98#define REG_STATUS1 (0x3A)99#define REG_STATUS2 (0x3B)100 101#define REG_AGC_GAIN_STATUS_LSB (0x3C)102#define REG_AGC_GAIN_STATUS_MSB (0x3D)103 104/* 0x3E Reserved */105 106#define REG_VIDEO_STD_STATUS (0x3F)107#define REG_GPIO_INPUT1 (0x40)108#define REG_GPIO_INPUT2 (0x41)109 110/* 0x42 - 0x45 Reserved */111 112#define REG_AFE_COARSE_GAIN_CH1 (0x46)113#define REG_AFE_COARSE_GAIN_CH2 (0x47)114#define REG_AFE_COARSE_GAIN_CH3 (0x48)115#define REG_AFE_COARSE_GAIN_CH4 (0x49)116 117#define REG_AFE_FINE_GAIN_PB_B_LSB (0x4A)118#define REG_AFE_FINE_GAIN_PB_B_MSB (0x4B)119#define REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB (0x4C)120#define REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB (0x4D)121#define REG_AFE_FINE_GAIN_PR_R_LSB (0x4E)122#define REG_AFE_FINE_GAIN_PR_R_MSB (0x4F)123#define REG_AFE_FINE_GAIN_CVBS_LUMA_LSB (0x50)124#define REG_AFE_FINE_GAIN_CVBS_LUMA_MSB (0x51)125 126/* 0x52 - 0x68 Reserved */127 128#define REG_FBIT_VBIT_CONTROL1 (0x69)129 130/* 0x6A - 0x6B Reserved */131 132#define REG_BACKEND_AGC_CONTROL (0x6C)133 134/* 0x6D - 0x6E Reserved */135 136#define REG_AGC_DECREMENT_SPEED_CONTROL (0x6F)137#define REG_ROM_VERSION (0x70)138 139/* 0x71 - 0x73 Reserved */140 141#define REG_AGC_WHITE_PEAK_PROCESSING (0x74)142#define REG_FBIT_VBIT_CONTROL2 (0x75)143#define REG_VCR_TRICK_MODE_CONTROL (0x76)144#define REG_HORIZONTAL_SHAKE_INCREMENT (0x77)145#define REG_AGC_INCREMENT_SPEED (0x78)146#define REG_AGC_INCREMENT_DELAY (0x79)147 148/* 0x7A - 0x7F Reserved */149 150#define REG_CHIP_ID_MSB (0x80)151#define REG_CHIP_ID_LSB (0x81)152 153/* 0x82 Reserved */154 155#define REG_CPLL_SPEED_CONTROL (0x83)156 157/* 0x84 - 0x96 Reserved */158 159#define REG_STATUS_REQUEST (0x97)160 161/* 0x98 - 0x99 Reserved */162 163#define REG_VERTICAL_LINE_COUNT_LSB (0x9A)164#define REG_VERTICAL_LINE_COUNT_MSB (0x9B)165 166/* 0x9C - 0x9D Reserved */167 168#define REG_AGC_DECREMENT_DELAY (0x9E)169 170/* 0x9F - 0xB0 Reserved */171 172#define REG_VDP_TTX_FILTER_1_MASK1 (0xB1)173#define REG_VDP_TTX_FILTER_1_MASK2 (0xB2)174#define REG_VDP_TTX_FILTER_1_MASK3 (0xB3)175#define REG_VDP_TTX_FILTER_1_MASK4 (0xB4)176#define REG_VDP_TTX_FILTER_1_MASK5 (0xB5)177#define REG_VDP_TTX_FILTER_2_MASK1 (0xB6)178#define REG_VDP_TTX_FILTER_2_MASK2 (0xB7)179#define REG_VDP_TTX_FILTER_2_MASK3 (0xB8)180#define REG_VDP_TTX_FILTER_2_MASK4 (0xB9)181#define REG_VDP_TTX_FILTER_2_MASK5 (0xBA)182#define REG_VDP_TTX_FILTER_CONTROL (0xBB)183#define REG_VDP_FIFO_WORD_COUNT (0xBC)184#define REG_VDP_FIFO_INTERRUPT_THRLD (0xBD)185 186/* 0xBE Reserved */187 188#define REG_VDP_FIFO_RESET (0xBF)189#define REG_VDP_FIFO_OUTPUT_CONTROL (0xC0)190#define REG_VDP_LINE_NUMBER_INTERRUPT (0xC1)191#define REG_VDP_PIXEL_ALIGNMENT_LSB (0xC2)192#define REG_VDP_PIXEL_ALIGNMENT_MSB (0xC3)193 194/* 0xC4 - 0xD5 Reserved */195 196#define REG_VDP_LINE_START (0xD6)197#define REG_VDP_LINE_STOP (0xD7)198#define REG_VDP_GLOBAL_LINE_MODE (0xD8)199#define REG_VDP_FULL_FIELD_ENABLE (0xD9)200#define REG_VDP_FULL_FIELD_MODE (0xDA)201 202/* 0xDB - 0xDF Reserved */203 204#define REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR (0xE0)205#define REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR (0xE1)206#define REG_FIFO_READ_DATA (0xE2)207 208/* 0xE3 - 0xE7 Reserved */209 210#define REG_VBUS_ADDRESS_ACCESS1 (0xE8)211#define REG_VBUS_ADDRESS_ACCESS2 (0xE9)212#define REG_VBUS_ADDRESS_ACCESS3 (0xEA)213 214/* 0xEB - 0xEF Reserved */215 216#define REG_INTERRUPT_RAW_STATUS0 (0xF0)217#define REG_INTERRUPT_RAW_STATUS1 (0xF1)218#define REG_INTERRUPT_STATUS0 (0xF2)219#define REG_INTERRUPT_STATUS1 (0xF3)220#define REG_INTERRUPT_MASK0 (0xF4)221#define REG_INTERRUPT_MASK1 (0xF5)222#define REG_INTERRUPT_CLEAR0 (0xF6)223#define REG_INTERRUPT_CLEAR1 (0xF7)224 225/* 0xF8 - 0xFF Reserved */226 227/*228 * Mask and bit definitions of TVP5146/47 registers229 */230/* The ID values we are looking for */231#define TVP514X_CHIP_ID_MSB (0x51)232#define TVP5146_CHIP_ID_LSB (0x46)233#define TVP5147_CHIP_ID_LSB (0x47)234 235#define VIDEO_STD_MASK (0x07)236#define VIDEO_STD_AUTO_SWITCH_BIT (0x00)237#define VIDEO_STD_NTSC_MJ_BIT (0x01)238#define VIDEO_STD_PAL_BDGHIN_BIT (0x02)239#define VIDEO_STD_PAL_M_BIT (0x03)240#define VIDEO_STD_PAL_COMBINATION_N_BIT (0x04)241#define VIDEO_STD_NTSC_4_43_BIT (0x05)242#define VIDEO_STD_SECAM_BIT (0x06)243#define VIDEO_STD_PAL_60_BIT (0x07)244 245/*246 * Status bit247 */248#define STATUS_TV_VCR_BIT (1<<0)249#define STATUS_HORZ_SYNC_LOCK_BIT (1<<1)250#define STATUS_VIRT_SYNC_LOCK_BIT (1<<2)251#define STATUS_CLR_SUBCAR_LOCK_BIT (1<<3)252#define STATUS_LOST_LOCK_DETECT_BIT (1<<4)253#define STATUS_FEILD_RATE_BIT (1<<5)254#define STATUS_LINE_ALTERNATING_BIT (1<<6)255#define STATUS_PEAK_WHITE_DETECT_BIT (1<<7)256 257/* Tokens for register write */258#define TOK_WRITE (0) /* token for write operation */259#define TOK_TERM (1) /* terminating token */260#define TOK_DELAY (2) /* delay token for reg list */261#define TOK_SKIP (3) /* token to skip a register */262/**263 * struct tvp514x_reg - Structure for TVP5146/47 register initialization values264 * @token: Token: TOK_WRITE, TOK_TERM etc..265 * @reg: Register offset266 * @val: Register Value for TOK_WRITE or delay in ms for TOK_DELAY267 */268struct tvp514x_reg {269 u8 token;270 u8 reg;271 u32 val;272};273 274#endif /* ifndef _TVP514X_REGS_H */275