48 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright 2014-2015 Cisco Systems, Inc. and/or its affiliates.4 * All rights reserved.5 */6 7#ifndef M00389_CVI_MEMMAP_PACKAGE_H8#define M00389_CVI_MEMMAP_PACKAGE_H9 10/*******************************************************************11 * Register Block12 * M00389_CVI_MEMMAP_PACKAGE_VHD_REGMAP13 *******************************************************************/14struct m00389_cvi_regmap {15 uint32_t control; /* Reg 0x0000, Default=0x0 */16 uint32_t frame_width; /* Reg 0x0004, Default=0x10 */17 uint32_t frame_height; /* Reg 0x0008, Default=0xc */18 uint32_t freewheel_period; /* Reg 0x000c, Default=0x0 */19 uint32_t error_color; /* Reg 0x0010, Default=0x0 */20 uint32_t status; /* Reg 0x0014 */21};22 23#define M00389_CVI_REG_CONTROL_OFST 024#define M00389_CVI_REG_FRAME_WIDTH_OFST 425#define M00389_CVI_REG_FRAME_HEIGHT_OFST 826#define M00389_CVI_REG_FREEWHEEL_PERIOD_OFST 1227#define M00389_CVI_REG_ERROR_COLOR_OFST 1628#define M00389_CVI_REG_STATUS_OFST 2029 30/*******************************************************************31 * Bit Mask for register32 * M00389_CVI_MEMMAP_PACKAGE_VHD_BITMAP33 *******************************************************************/34/* control [2:0] */35#define M00389_CONTROL_BITMAP_ENABLE_OFST (0)36#define M00389_CONTROL_BITMAP_ENABLE_MSK (0x1 << M00389_CONTROL_BITMAP_ENABLE_OFST)37#define M00389_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST (1)38#define M00389_CONTROL_BITMAP_HSYNC_POLARITY_LOW_MSK (0x1 << M00389_CONTROL_BITMAP_HSYNC_POLARITY_LOW_OFST)39#define M00389_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST (2)40#define M00389_CONTROL_BITMAP_VSYNC_POLARITY_LOW_MSK (0x1 << M00389_CONTROL_BITMAP_VSYNC_POLARITY_LOW_OFST)41/* status [1:0] */42#define M00389_STATUS_BITMAP_LOCK_OFST (0)43#define M00389_STATUS_BITMAP_LOCK_MSK (0x1 << M00389_STATUS_BITMAP_LOCK_OFST)44#define M00389_STATUS_BITMAP_ERROR_OFST (1)45#define M00389_STATUS_BITMAP_ERROR_MSK (0x1 << M00389_STATUS_BITMAP_ERROR_OFST)46 47#endif /*M00389_CVI_MEMMAP_PACKAGE_H*/48