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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Driver for the Conexant CX23885 PCIe bridge4 *5 * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>6 */7 8#ifndef _CX23885_REG_H_9#define _CX23885_REG_H_10 11/*12Address Map130x00000000 -> 0x00009000 TX SRAM (Fifos)140x00010000 -> 0x00013c00 RX SRAM CMDS + CDT15 16EACH CMDS struct is 0x80 bytes long17 18DMAx_PTR1 = 0x03040 address of first cluster19DMAx_PTR2 = 0x10600 address of the CDT20DMAx_CNT1 = cluster size in (bytes >> 4) -121DMAx_CNT2 = total cdt size for all entries >> 322 23Cluster Descriptor entry = 4 DWORDS24 DWORD 0 -> ptr to cluster25 DWORD 1 Reserved26 DWORD 2 Reserved27 DWORD 3 Reserved28 29Channel manager Data Structure entry = 20 DWORD30 0 IntialProgramCounterLow31 1 IntialProgramCounterHigh32 2 ClusterDescriptorTableBase33 3 ClusterDescriptorTableSize34 4 InstructionQueueBase35 5 InstructionQueueSize36... Reserved37 19 Reserved38*/39 40/* Risc Instructions */41#define RISC_CNT_INC 0x0001000042#define RISC_CNT_RESET 0x0003000043#define RISC_IRQ1 0x0100000044#define RISC_IRQ2 0x0200000045#define RISC_EOL 0x0400000046#define RISC_SOL 0x0800000047#define RISC_WRITE 0x1000000048#define RISC_SKIP 0x2000000049#define RISC_JUMP 0x7000000050#define RISC_SYNC 0x8000000051#define RISC_RESYNC 0x8000800052#define RISC_READ 0x9000000053#define RISC_WRITERM 0xB000000054#define RISC_WRITECM 0xC000000055#define RISC_WRITECR 0xD000000056#define RISC_WRITEC 0x5000000057#define RISC_READC 0xA000000058 59 60/* Audio and Video Core */61#define HOST_REG1 0x0000000062#define HOST_REG2 0x0000000163#define HOST_REG3 0x0000000264 65/* Chip Configuration Registers */66#define CHIP_CTRL 0x0000010067#define AFE_CTRL 0x0000010468#define VID_PLL_INT_POST 0x0000010869#define VID_PLL_FRAC 0x0000010C70#define AUX_PLL_INT_POST 0x0000011071#define AUX_PLL_FRAC 0x0000011472#define SYS_PLL_INT_POST 0x0000011873#define SYS_PLL_FRAC 0x0000011C74#define PIN_CTRL 0x0000012075#define AUD_IO_CTRL 0x0000012476#define AUD_LOCK1 0x0000012877#define AUD_LOCK2 0x0000012C78#define POWER_CTRL 0x0000013079#define AFE_DIAG_CTRL1 0x0000013480#define AFE_DIAG_CTRL3 0x0000013C81#define PLL_DIAG_CTRL 0x0000014082#define AFE_CLK_OUT_CTRL 0x0000014483#define DLL1_DIAG_CTRL 0x0000015C84 85/* GPIO[23:19] Output Enable */86#define GPIO2_OUT_EN_REG 0x0000016087/* GPIO[23:19] Data Registers */88#define GPIO2 0x0000016489 90#define IFADC_CTRL 0x0000018091 92/* Infrared Remote Registers */93#define IR_CNTRL_REG 0x0000020094#define IR_TXCLK_REG 0x0000020495#define IR_RXCLK_REG 0x0000020896#define IR_CDUTY_REG 0x0000020C97#define IR_STAT_REG 0x0000021098#define IR_IRQEN_REG 0x0000021499#define IR_FILTR_REG 0x00000218100#define IR_FIFO_REG 0x0000023C101 102/* Video Decoder Registers */103#define MODE_CTRL 0x00000400104#define OUT_CTRL1 0x00000404105#define OUT_CTRL2 0x00000408106#define GEN_STAT 0x0000040C107#define INT_STAT_MASK 0x00000410108#define LUMA_CTRL 0x00000414109#define HSCALE_CTRL 0x00000418110#define VSCALE_CTRL 0x0000041C111#define CHROMA_CTRL 0x00000420112#define VBI_LINE_CTRL1 0x00000424113#define VBI_LINE_CTRL2 0x00000428114#define VBI_LINE_CTRL3 0x0000042C115#define VBI_LINE_CTRL4 0x00000430116#define VBI_LINE_CTRL5 0x00000434117#define VBI_FC_CFG 0x00000438118#define VBI_MISC_CFG1 0x0000043C119#define VBI_MISC_CFG2 0x00000440120#define VBI_PAY1 0x00000444121#define VBI_PAY2 0x00000448122#define VBI_CUST1_CFG1 0x0000044C123#define VBI_CUST1_CFG2 0x00000450124#define VBI_CUST1_CFG3 0x00000454125#define VBI_CUST2_CFG1 0x00000458126#define VBI_CUST2_CFG2 0x0000045C127#define VBI_CUST2_CFG3 0x00000460128#define VBI_CUST3_CFG1 0x00000464129#define VBI_CUST3_CFG2 0x00000468130#define VBI_CUST3_CFG3 0x0000046C131#define HORIZ_TIM_CTRL 0x00000470132#define VERT_TIM_CTRL 0x00000474133#define SRC_COMB_CFG 0x00000478134#define CHROMA_VBIOFF_CFG 0x0000047C135#define FIELD_COUNT 0x00000480136#define MISC_TIM_CTRL 0x00000484137#define DFE_CTRL1 0x00000488138#define DFE_CTRL2 0x0000048C139#define DFE_CTRL3 0x00000490140#define PLL_CTRL 0x00000494141#define HTL_CTRL 0x00000498142#define COMB_CTRL 0x0000049C143#define CRUSH_CTRL 0x000004A0144#define SOFT_RST_CTRL 0x000004A4145#define CX885_VERSION 0x000004B4146#define VBI_PASS_CTRL 0x000004BC147 148/* Audio Decoder Registers */149/* 8051 Configuration */150#define DL_CTL 0x00000800151#define STD_DET_STATUS 0x00000804152#define STD_DET_CTL 0x00000808153#define DW8051_INT 0x0000080C154#define GENERAL_CTL 0x00000810155#define AAGC_CTL 0x00000814156#define DEMATRIX_CTL 0x000008CC157#define PATH1_CTL1 0x000008D0158#define PATH1_VOL_CTL 0x000008D4159#define PATH1_EQ_CTL 0x000008D8160#define PATH1_SC_CTL 0x000008DC161#define PATH2_CTL1 0x000008E0162#define PATH2_VOL_CTL 0x000008E4163#define PATH2_EQ_CTL 0x000008E8164#define PATH2_SC_CTL 0x000008EC165 166/* Sample Rate Converter */167#define SRC_CTL 0x000008F0168#define SRC_LF_COEF 0x000008F4169#define SRC1_CTL 0x000008F8170#define SRC2_CTL 0x000008FC171#define SRC3_CTL 0x00000900172#define SRC4_CTL 0x00000904173#define SRC5_CTL 0x00000908174#define SRC6_CTL 0x0000090C175#define BAND_OUT_SEL 0x00000910176#define I2S_N_CTL 0x00000914177#define I2S_OUT_CTL 0x00000918178#define AUTOCONFIG_REG 0x000009C4179 180/* Audio ADC Registers */181#define DSM_CTRL1 0x00000000182#define DSM_CTRL2 0x00000001183#define CHP_EN_CTRL 0x00000002184#define CHP_CLK_CTRL1 0x00000004185#define CHP_CLK_CTRL2 0x00000005186#define BG_REF_CTRL 0x00000006187#define SD2_SW_CTRL1 0x00000008188#define SD2_SW_CTRL2 0x00000009189#define SD2_BIAS_CTRL 0x0000000A190#define AMP_BIAS_CTRL 0x0000000C191#define CH_PWR_CTRL1 0x0000000E192#define FLD_CH_SEL (1 << 3)193#define CH_PWR_CTRL2 0x0000000F194#define DSM_STATUS1 0x00000010195#define DSM_STATUS2 0x00000011196#define DIG_CTL1 0x00000012197#define DIG_CTL2 0x00000013198#define I2S_TX_CFG 0x0000001A199 200#define DEV_CNTRL2 0x00040000201 202#define PCI_MSK_IR (1 << 28)203#define PCI_MSK_AV_CORE (1 << 27)204#define PCI_MSK_GPIO1 (1 << 24)205#define PCI_MSK_GPIO0 (1 << 23)206#define PCI_MSK_APB_DMA (1 << 12)207#define PCI_MSK_AL_WR (1 << 11)208#define PCI_MSK_AL_RD (1 << 10)209#define PCI_MSK_RISC_WR (1 << 9)210#define PCI_MSK_RISC_RD (1 << 8)211#define PCI_MSK_AUD_EXT (1 << 4)212#define PCI_MSK_AUD_INT (1 << 3)213#define PCI_MSK_VID_C (1 << 2)214#define PCI_MSK_VID_B (1 << 1)215#define PCI_MSK_VID_A 1216#define PCI_INT_MSK 0x00040010217 218#define PCI_INT_STAT 0x00040014219#define PCI_INT_MSTAT 0x00040018220 221#define VID_A_INT_MSK 0x00040020222#define VID_A_INT_STAT 0x00040024223#define VID_A_INT_MSTAT 0x00040028224#define VID_A_INT_SSTAT 0x0004002C225 226#define VID_B_INT_MSK 0x00040030227#define VID_B_MSK_BAD_PKT (1 << 20)228#define VID_B_MSK_VBI_OPC_ERR (1 << 17)229#define VID_B_MSK_OPC_ERR (1 << 16)230#define VID_B_MSK_VBI_SYNC (1 << 13)231#define VID_B_MSK_SYNC (1 << 12)232#define VID_B_MSK_VBI_OF (1 << 9)233#define VID_B_MSK_OF (1 << 8)234#define VID_B_MSK_VBI_RISCI2 (1 << 5)235#define VID_B_MSK_RISCI2 (1 << 4)236#define VID_B_MSK_VBI_RISCI1 (1 << 1)237#define VID_B_MSK_RISCI1 1238#define VID_B_INT_STAT 0x00040034239#define VID_B_INT_MSTAT 0x00040038240#define VID_B_INT_SSTAT 0x0004003C241 242#define VID_B_MSK_BAD_PKT (1 << 20)243#define VID_B_MSK_OPC_ERR (1 << 16)244#define VID_B_MSK_SYNC (1 << 12)245#define VID_B_MSK_OF (1 << 8)246#define VID_B_MSK_RISCI2 (1 << 4)247#define VID_B_MSK_RISCI1 1248 249#define VID_C_MSK_BAD_PKT (1 << 20)250#define VID_C_MSK_OPC_ERR (1 << 16)251#define VID_C_MSK_SYNC (1 << 12)252#define VID_C_MSK_OF (1 << 8)253#define VID_C_MSK_RISCI2 (1 << 4)254#define VID_C_MSK_RISCI1 1255 256/* A superset for testing purposes */257#define VID_BC_MSK_BAD_PKT (1 << 20)258#define VID_BC_MSK_OPC_ERR (1 << 16)259#define VID_BC_MSK_SYNC (1 << 12)260#define VID_BC_MSK_OF (1 << 8)261#define VID_BC_MSK_VBI_RISCI2 (1 << 5)262#define VID_BC_MSK_RISCI2 (1 << 4)263#define VID_BC_MSK_VBI_RISCI1 (1 << 1)264#define VID_BC_MSK_RISCI1 1265 266#define VID_C_INT_MSK 0x00040040267#define VID_C_INT_STAT 0x00040044268#define VID_C_INT_MSTAT 0x00040048269#define VID_C_INT_SSTAT 0x0004004C270 271#define AUDIO_INT_INT_MSK 0x00040050272#define AUDIO_INT_INT_STAT 0x00040054273#define AUDIO_INT_INT_MSTAT 0x00040058274#define AUDIO_INT_INT_SSTAT 0x0004005C275 276#define AUDIO_EXT_INT_MSK 0x00040060277#define AUDIO_EXT_INT_STAT 0x00040064278#define AUDIO_EXT_INT_MSTAT 0x00040068279#define AUDIO_EXT_INT_SSTAT 0x0004006C280 281/* Bits [7:0] set in both TC_REQ and TC_REQ_SET282 * indicate a stall in the RISC engine for a283 * particular rider traffic class. This causes284 * the 885 and 888 bridges (unknown about 887)285 * to become inoperable. Setting bits in286 * TC_REQ_SET resets the corresponding bits287 * in TC_REQ (and TC_REQ_SET) allowing288 * operation to continue.289 */290#define TC_REQ 0x00040090291#define TC_REQ_SET 0x00040094292 293#define RDR_CFG0 0x00050000294#define RDR_CFG1 0x00050004295#define RDR_CFG2 0x00050008296#define RDR_RDRCTL1 0x0005030c297#define RDR_TLCTL0 0x00050318298 299/* APB DMAC Current Buffer Pointer */300#define DMA1_PTR1 0x00100000301#define DMA2_PTR1 0x00100004302#define DMA3_PTR1 0x00100008303#define DMA4_PTR1 0x0010000C304#define DMA5_PTR1 0x00100010305#define DMA6_PTR1 0x00100014306#define DMA7_PTR1 0x00100018307#define DMA8_PTR1 0x0010001C308 309/* APB DMAC Current Table Pointer */310#define DMA1_PTR2 0x00100040311#define DMA2_PTR2 0x00100044312#define DMA3_PTR2 0x00100048313#define DMA4_PTR2 0x0010004C314#define DMA5_PTR2 0x00100050315#define DMA6_PTR2 0x00100054316#define DMA7_PTR2 0x00100058317#define DMA8_PTR2 0x0010005C318 319/* APB DMAC Buffer Limit */320#define DMA1_CNT1 0x00100080321#define DMA2_CNT1 0x00100084322#define DMA3_CNT1 0x00100088323#define DMA4_CNT1 0x0010008C324#define DMA5_CNT1 0x00100090325#define DMA6_CNT1 0x00100094326#define DMA7_CNT1 0x00100098327#define DMA8_CNT1 0x0010009C328 329/* APB DMAC Table Size */330#define DMA1_CNT2 0x001000C0331#define DMA2_CNT2 0x001000C4332#define DMA3_CNT2 0x001000C8333#define DMA4_CNT2 0x001000CC334#define DMA5_CNT2 0x001000D0335#define DMA6_CNT2 0x001000D4336#define DMA7_CNT2 0x001000D8337#define DMA8_CNT2 0x001000DC338 339/* Timer Counters */340#define TM_CNT_LDW 0x00110000341#define TM_CNT_UW 0x00110004342#define TM_LMT_LDW 0x00110008343#define TM_LMT_UW 0x0011000C344 345/* GPIO */346#define GP0_IO 0x00110010347#define GPIO_ISM 0x00110014348#define SOFT_RESET 0x0011001C349 350/* GPIO (417 Microsoftcontroller) RW Data */351#define MC417_RWD 0x00110020352 353/* GPIO (417 Microsoftcontroller) Output Enable, Low Active */354#define MC417_OEN 0x00110024355#define MC417_CTL 0x00110028356#define ALT_PIN_OUT_SEL 0x0011002C357#define CLK_DELAY 0x00110048358#define PAD_CTRL 0x0011004C359 360/* Video A Interface */361#define VID_A_GPCNT 0x00130020362#define VBI_A_GPCNT 0x00130024363#define VID_A_GPCNT_CTL 0x00130030364#define VBI_A_GPCNT_CTL 0x00130034365#define VID_A_DMA_CTL 0x00130040366#define VID_A_VIP_CTRL 0x00130080367#define VID_A_PIXEL_FRMT 0x00130084368#define VID_A_VBI_CTRL 0x00130088369 370/* Video B Interface */371#define VID_B_DMA 0x00130100372#define VBI_B_DMA 0x00130108373#define VID_B_GPCNT 0x00130120374#define VBI_B_GPCNT 0x00130124375#define VID_B_GPCNT_CTL 0x00130134376#define VBI_B_GPCNT_CTL 0x00130138377#define VID_B_DMA_CTL 0x00130140378#define VID_B_SRC_SEL 0x00130144379#define VID_B_LNGTH 0x00130150380#define VID_B_HW_SOP_CTL 0x00130154381#define VID_B_GEN_CTL 0x00130158382#define VID_B_BD_PKT_STATUS 0x0013015C383#define VID_B_SOP_STATUS 0x00130160384#define VID_B_FIFO_OVFL_STAT 0x00130164385#define VID_B_VLD_MISC 0x00130168386#define VID_B_TS_CLK_EN 0x0013016C387#define VID_B_VIP_CTRL 0x00130180388#define VID_B_PIXEL_FRMT 0x00130184389 390/* Video C Interface */391#define VID_C_DMA 0x00130200392#define VBI_C_DMA 0x00130208393#define VID_C_GPCNT 0x00130220394#define VID_C_GPCNT_CTL 0x00130230395#define VBI_C_GPCNT_CTL 0x00130234396#define VID_C_DMA_CTL 0x00130240397#define VID_C_LNGTH 0x00130250398#define VID_C_HW_SOP_CTL 0x00130254399#define VID_C_GEN_CTL 0x00130258400#define VID_C_BD_PKT_STATUS 0x0013025C401#define VID_C_SOP_STATUS 0x00130260402#define VID_C_FIFO_OVFL_STAT 0x00130264403#define VID_C_VLD_MISC 0x00130268404#define VID_C_TS_CLK_EN 0x0013026C405 406/* Internal Audio Interface */407#define AUD_INT_A_GPCNT 0x00140020408#define AUD_INT_B_GPCNT 0x00140024409#define AUD_INT_A_GPCNT_CTL 0x00140030410#define AUD_INT_B_GPCNT_CTL 0x00140034411#define AUD_INT_DMA_CTL 0x00140040412#define AUD_INT_A_LNGTH 0x00140050413#define AUD_INT_B_LNGTH 0x00140054414#define AUD_INT_A_MODE 0x00140058415#define AUD_INT_B_MODE 0x0014005C416 417/* External Audio Interface */418#define AUD_EXT_DMA 0x00140100419#define AUD_EXT_GPCNT 0x00140120420#define AUD_EXT_GPCNT_CTL 0x00140130421#define AUD_EXT_DMA_CTL 0x00140140422#define AUD_EXT_LNGTH 0x00140150423#define AUD_EXT_A_MODE 0x00140158424 425/* I2C Bus 1 */426#define I2C1_ADDR 0x00180000427#define I2C1_WDATA 0x00180004428#define I2C1_CTRL 0x00180008429#define I2C1_RDATA 0x0018000C430#define I2C1_STAT 0x00180010431 432/* I2C Bus 2 */433#define I2C2_ADDR 0x00190000434#define I2C2_WDATA 0x00190004435#define I2C2_CTRL 0x00190008436#define I2C2_RDATA 0x0019000C437#define I2C2_STAT 0x00190010438 439/* I2C Bus 3 */440#define I2C3_ADDR 0x001A0000441#define I2C3_WDATA 0x001A0004442#define I2C3_CTRL 0x001A0008443#define I2C3_RDATA 0x001A000C444#define I2C3_STAT 0x001A0010445 446/* UART */447#define UART_CTL 0x001B0000448#define UART_BRD 0x001B0004449#define UART_ISR 0x001B000C450#define UART_CNT 0x001B0010451 452#endif /* _CX23885_REG_H_ */453