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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Driver for the Conexant CX25821 PCIe bridge4 *5 * Copyright (C) 2009 Conexant Systems Inc.6 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>7 */8 9#ifndef __CX25821_REGISTERS__10#define __CX25821_REGISTERS__11 12/* Risc Instructions */13#define RISC_CNT_INC 0x0001000014#define RISC_CNT_RESET 0x0003000015#define RISC_IRQ1 0x0100000016#define RISC_IRQ2 0x0200000017#define RISC_EOL 0x0400000018#define RISC_SOL 0x0800000019#define RISC_WRITE 0x1000000020#define RISC_SKIP 0x2000000021#define RISC_JUMP 0x7000000022#define RISC_SYNC 0x8000000023#define RISC_RESYNC 0x8000800024#define RISC_READ 0x9000000025#define RISC_WRITERM 0xB000000026#define RISC_WRITECM 0xC000000027#define RISC_WRITECR 0xD000000028#define RISC_WRITEC 0x5000000029#define RISC_READC 0xA000000030 31#define RISC_SYNC_ODD 0x0000000032#define RISC_SYNC_EVEN 0x0000020033#define RISC_SYNC_ODD_VBI 0x0000000634#define RISC_SYNC_EVEN_VBI 0x0000020735#define RISC_NOOP 0xF000000036 37/*****************************************************************************38* ASB SRAM39 *****************************************************************************/40#define TX_SRAM 0x000000 /* Transmit SRAM */41 42/*****************************************************************************/43#define RX_RAM 0x010000 /* Receive SRAM */44 45/*****************************************************************************46* Application Layer (AL)47 *****************************************************************************/48#define DEV_CNTRL2 0x040000 /* Device control */49#define FLD_RUN_RISC 0x0000002050 51/* ***************************************************************************** */52#define PCI_INT_MSK 0x040010 /* PCI interrupt mask */53#define PCI_INT_STAT 0x040014 /* PCI interrupt status */54#define PCI_INT_MSTAT 0x040018 /* PCI interrupt masked status */55#define FLD_HAMMERHEAD_INT (1 << 27)56#define FLD_UART_INT (1 << 26)57#define FLD_IRQN_INT (1 << 25)58#define FLD_TM_INT (1 << 28)59#define FLD_I2C_3_RACK (1 << 27)60#define FLD_I2C_3_INT (1 << 26)61#define FLD_I2C_2_RACK (1 << 25)62#define FLD_I2C_2_INT (1 << 24)63#define FLD_I2C_1_RACK (1 << 23)64#define FLD_I2C_1_INT (1 << 22)65 66#define FLD_APB_DMA_BERR_INT (1 << 21)67#define FLD_AL_WR_BERR_INT (1 << 20)68#define FLD_AL_RD_BERR_INT (1 << 19)69#define FLD_RISC_WR_BERR_INT (1 << 18)70#define FLD_RISC_RD_BERR_INT (1 << 17)71 72#define FLD_VID_I_INT (1 << 8)73#define FLD_VID_H_INT (1 << 7)74#define FLD_VID_G_INT (1 << 6)75#define FLD_VID_F_INT (1 << 5)76#define FLD_VID_E_INT (1 << 4)77#define FLD_VID_D_INT (1 << 3)78#define FLD_VID_C_INT (1 << 2)79#define FLD_VID_B_INT (1 << 1)80#define FLD_VID_A_INT (1 << 0)81 82/* ***************************************************************************** */83#define VID_A_INT_MSK 0x040020 /* Video A interrupt mask */84#define VID_A_INT_STAT 0x040024 /* Video A interrupt status */85#define VID_A_INT_MSTAT 0x040028 /* Video A interrupt masked status */86#define VID_A_INT_SSTAT 0x04002C /* Video A interrupt set status */87 88/* ***************************************************************************** */89#define VID_B_INT_MSK 0x040030 /* Video B interrupt mask */90#define VID_B_INT_STAT 0x040034 /* Video B interrupt status */91#define VID_B_INT_MSTAT 0x040038 /* Video B interrupt masked status */92#define VID_B_INT_SSTAT 0x04003C /* Video B interrupt set status */93 94/* ***************************************************************************** */95#define VID_C_INT_MSK 0x040040 /* Video C interrupt mask */96#define VID_C_INT_STAT 0x040044 /* Video C interrupt status */97#define VID_C_INT_MSTAT 0x040048 /* Video C interrupt masked status */98#define VID_C_INT_SSTAT 0x04004C /* Video C interrupt set status */99 100/* ***************************************************************************** */101#define VID_D_INT_MSK 0x040050 /* Video D interrupt mask */102#define VID_D_INT_STAT 0x040054 /* Video D interrupt status */103#define VID_D_INT_MSTAT 0x040058 /* Video D interrupt masked status */104#define VID_D_INT_SSTAT 0x04005C /* Video D interrupt set status */105 106/* ***************************************************************************** */107#define VID_E_INT_MSK 0x040060 /* Video E interrupt mask */108#define VID_E_INT_STAT 0x040064 /* Video E interrupt status */109#define VID_E_INT_MSTAT 0x040068 /* Video E interrupt masked status */110#define VID_E_INT_SSTAT 0x04006C /* Video E interrupt set status */111 112/* ***************************************************************************** */113#define VID_F_INT_MSK 0x040070 /* Video F interrupt mask */114#define VID_F_INT_STAT 0x040074 /* Video F interrupt status */115#define VID_F_INT_MSTAT 0x040078 /* Video F interrupt masked status */116#define VID_F_INT_SSTAT 0x04007C /* Video F interrupt set status */117 118/* ***************************************************************************** */119#define VID_G_INT_MSK 0x040080 /* Video G interrupt mask */120#define VID_G_INT_STAT 0x040084 /* Video G interrupt status */121#define VID_G_INT_MSTAT 0x040088 /* Video G interrupt masked status */122#define VID_G_INT_SSTAT 0x04008C /* Video G interrupt set status */123 124/* ***************************************************************************** */125#define VID_H_INT_MSK 0x040090 /* Video H interrupt mask */126#define VID_H_INT_STAT 0x040094 /* Video H interrupt status */127#define VID_H_INT_MSTAT 0x040098 /* Video H interrupt masked status */128#define VID_H_INT_SSTAT 0x04009C /* Video H interrupt set status */129 130/* ***************************************************************************** */131#define VID_I_INT_MSK 0x0400A0 /* Video I interrupt mask */132#define VID_I_INT_STAT 0x0400A4 /* Video I interrupt status */133#define VID_I_INT_MSTAT 0x0400A8 /* Video I interrupt masked status */134#define VID_I_INT_SSTAT 0x0400AC /* Video I interrupt set status */135 136/* ***************************************************************************** */137#define VID_J_INT_MSK 0x0400B0 /* Video J interrupt mask */138#define VID_J_INT_STAT 0x0400B4 /* Video J interrupt status */139#define VID_J_INT_MSTAT 0x0400B8 /* Video J interrupt masked status */140#define VID_J_INT_SSTAT 0x0400BC /* Video J interrupt set status */141 142#define FLD_VID_SRC_OPC_ERR 0x00020000143#define FLD_VID_DST_OPC_ERR 0x00010000144#define FLD_VID_SRC_SYNC 0x00002000145#define FLD_VID_DST_SYNC 0x00001000146#define FLD_VID_SRC_UF 0x00000200147#define FLD_VID_DST_OF 0x00000100148#define FLD_VID_SRC_RISC2 0x00000020149#define FLD_VID_DST_RISC2 0x00000010150#define FLD_VID_SRC_RISC1 0x00000002151#define FLD_VID_DST_RISC1 0x00000001152#define FLD_VID_SRC_ERRORS (FLD_VID_SRC_OPC_ERR | FLD_VID_SRC_SYNC | FLD_VID_SRC_UF)153#define FLD_VID_DST_ERRORS (FLD_VID_DST_OPC_ERR | FLD_VID_DST_SYNC | FLD_VID_DST_OF)154 155/* ***************************************************************************** */156#define AUD_A_INT_MSK 0x0400C0 /* Audio Int interrupt mask */157#define AUD_A_INT_STAT 0x0400C4 /* Audio Int interrupt status */158#define AUD_A_INT_MSTAT 0x0400C8 /* Audio Int interrupt masked status */159#define AUD_A_INT_SSTAT 0x0400CC /* Audio Int interrupt set status */160 161/* ***************************************************************************** */162#define AUD_B_INT_MSK 0x0400D0 /* Audio Int interrupt mask */163#define AUD_B_INT_STAT 0x0400D4 /* Audio Int interrupt status */164#define AUD_B_INT_MSTAT 0x0400D8 /* Audio Int interrupt masked status */165#define AUD_B_INT_SSTAT 0x0400DC /* Audio Int interrupt set status */166 167/* ***************************************************************************** */168#define AUD_C_INT_MSK 0x0400E0 /* Audio Int interrupt mask */169#define AUD_C_INT_STAT 0x0400E4 /* Audio Int interrupt status */170#define AUD_C_INT_MSTAT 0x0400E8 /* Audio Int interrupt masked status */171#define AUD_C_INT_SSTAT 0x0400EC /* Audio Int interrupt set status */172 173/* ***************************************************************************** */174#define AUD_D_INT_MSK 0x0400F0 /* Audio Int interrupt mask */175#define AUD_D_INT_STAT 0x0400F4 /* Audio Int interrupt status */176#define AUD_D_INT_MSTAT 0x0400F8 /* Audio Int interrupt masked status */177#define AUD_D_INT_SSTAT 0x0400FC /* Audio Int interrupt set status */178 179/* ***************************************************************************** */180#define AUD_E_INT_MSK 0x040100 /* Audio Int interrupt mask */181#define AUD_E_INT_STAT 0x040104 /* Audio Int interrupt status */182#define AUD_E_INT_MSTAT 0x040108 /* Audio Int interrupt masked status */183#define AUD_E_INT_SSTAT 0x04010C /* Audio Int interrupt set status */184 185#define FLD_AUD_SRC_OPC_ERR 0x00020000186#define FLD_AUD_DST_OPC_ERR 0x00010000187#define FLD_AUD_SRC_SYNC 0x00002000188#define FLD_AUD_DST_SYNC 0x00001000189#define FLD_AUD_SRC_OF 0x00000200190#define FLD_AUD_DST_OF 0x00000100191#define FLD_AUD_SRC_RISCI2 0x00000020192#define FLD_AUD_DST_RISCI2 0x00000010193#define FLD_AUD_SRC_RISCI1 0x00000002194#define FLD_AUD_DST_RISCI1 0x00000001195 196/* ***************************************************************************** */197#define MBIF_A_INT_MSK 0x040110 /* MBIF Int interrupt mask */198#define MBIF_A_INT_STAT 0x040114 /* MBIF Int interrupt status */199#define MBIF_A_INT_MSTAT 0x040118 /* MBIF Int interrupt masked status */200#define MBIF_A_INT_SSTAT 0x04011C /* MBIF Int interrupt set status */201 202/* ***************************************************************************** */203#define MBIF_B_INT_MSK 0x040120 /* MBIF Int interrupt mask */204#define MBIF_B_INT_STAT 0x040124 /* MBIF Int interrupt status */205#define MBIF_B_INT_MSTAT 0x040128 /* MBIF Int interrupt masked status */206#define MBIF_B_INT_SSTAT 0x04012C /* MBIF Int interrupt set status */207 208#define FLD_MBIF_DST_OPC_ERR 0x00010000209#define FLD_MBIF_DST_SYNC 0x00001000210#define FLD_MBIF_DST_OF 0x00000100211#define FLD_MBIF_DST_RISCI2 0x00000010212#define FLD_MBIF_DST_RISCI1 0x00000001213 214/* ***************************************************************************** */215#define AUD_EXT_INT_MSK 0x040060 /* Audio Ext interrupt mask */216#define AUD_EXT_INT_STAT 0x040064 /* Audio Ext interrupt status */217#define AUD_EXT_INT_MSTAT 0x040068 /* Audio Ext interrupt masked status */218#define AUD_EXT_INT_SSTAT 0x04006C /* Audio Ext interrupt set status */219#define FLD_AUD_EXT_OPC_ERR 0x00010000220#define FLD_AUD_EXT_SYNC 0x00001000221#define FLD_AUD_EXT_OF 0x00000100222#define FLD_AUD_EXT_RISCI2 0x00000010223#define FLD_AUD_EXT_RISCI1 0x00000001224 225/* ***************************************************************************** */226#define GPIO_LO 0x110010 /* Lower of GPIO pins [31:0] */227#define GPIO_HI 0x110014 /* Upper WORD of GPIO pins [47:31] */228 229#define GPIO_LO_OE 0x110018 /* Lower of GPIO output enable [31:0] */230#define GPIO_HI_OE 0x11001C /* Upper word of GPIO output enable [47:32] */231 232#define GPIO_LO_INT_MSK 0x11003C /* GPIO interrupt mask */233#define GPIO_LO_INT_STAT 0x110044 /* GPIO interrupt status */234#define GPIO_LO_INT_MSTAT 0x11004C /* GPIO interrupt masked status */235#define GPIO_LO_ISM_SNS 0x110054 /* GPIO interrupt sensitivity */236#define GPIO_LO_ISM_POL 0x11005C /* GPIO interrupt polarity */237 238#define GPIO_HI_INT_MSK 0x110040 /* GPIO interrupt mask */239#define GPIO_HI_INT_STAT 0x110048 /* GPIO interrupt status */240#define GPIO_HI_INT_MSTAT 0x110050 /* GPIO interrupt masked status */241#define GPIO_HI_ISM_SNS 0x110058 /* GPIO interrupt sensitivity */242#define GPIO_HI_ISM_POL 0x110060 /* GPIO interrupt polarity */243 244#define FLD_GPIO43_INT (1 << 11)245#define FLD_GPIO42_INT (1 << 10)246#define FLD_GPIO41_INT (1 << 9)247#define FLD_GPIO40_INT (1 << 8)248 249#define FLD_GPIO9_INT (1 << 9)250#define FLD_GPIO8_INT (1 << 8)251#define FLD_GPIO7_INT (1 << 7)252#define FLD_GPIO6_INT (1 << 6)253#define FLD_GPIO5_INT (1 << 5)254#define FLD_GPIO4_INT (1 << 4)255#define FLD_GPIO3_INT (1 << 3)256#define FLD_GPIO2_INT (1 << 2)257#define FLD_GPIO1_INT (1 << 1)258#define FLD_GPIO0_INT (1 << 0)259 260/* ***************************************************************************** */261#define TC_REQ 0x040090 /* Rider PCI Express traFFic class request */262 263/* ***************************************************************************** */264#define TC_REQ_SET 0x040094 /* Rider PCI Express traFFic class request set */265 266/* ***************************************************************************** */267/* Rider */268/* ***************************************************************************** */269 270/* PCI Compatible Header */271/* ***************************************************************************** */272#define RDR_CFG0 0x050000273#define RDR_VENDOR_DEVICE_ID_CFG 0x050000274 275/* ***************************************************************************** */276#define RDR_CFG1 0x050004277 278/* ***************************************************************************** */279#define RDR_CFG2 0x050008280 281/* ***************************************************************************** */282#define RDR_CFG3 0x05000C283 284/* ***************************************************************************** */285#define RDR_CFG4 0x050010286 287/* ***************************************************************************** */288#define RDR_CFG5 0x050014289 290/* ***************************************************************************** */291#define RDR_CFG6 0x050018292 293/* ***************************************************************************** */294#define RDR_CFG7 0x05001C295 296/* ***************************************************************************** */297#define RDR_CFG8 0x050020298 299/* ***************************************************************************** */300#define RDR_CFG9 0x050024301 302/* ***************************************************************************** */303#define RDR_CFGA 0x050028304 305/* ***************************************************************************** */306#define RDR_CFGB 0x05002C307#define RDR_SUSSYSTEM_ID_CFG 0x05002C308 309/* ***************************************************************************** */310#define RDR_CFGC 0x050030311 312/* ***************************************************************************** */313#define RDR_CFGD 0x050034314 315/* ***************************************************************************** */316#define RDR_CFGE 0x050038317 318/* ***************************************************************************** */319#define RDR_CFGF 0x05003C320 321/* ***************************************************************************** */322/* PCI-Express Capabilities */323/* ***************************************************************************** */324#define RDR_PECAP 0x050040325 326/* ***************************************************************************** */327#define RDR_PEDEVCAP 0x050044328 329/* ***************************************************************************** */330#define RDR_PEDEVSC 0x050048331 332/* ***************************************************************************** */333#define RDR_PELINKCAP 0x05004C334 335/* ***************************************************************************** */336#define RDR_PELINKSC 0x050050337 338/* ***************************************************************************** */339#define RDR_PMICAP 0x050080340 341/* ***************************************************************************** */342#define RDR_PMCSR 0x050084343 344/* ***************************************************************************** */345#define RDR_VPDCAP 0x050090346 347/* ***************************************************************************** */348#define RDR_VPDDATA 0x050094349 350/* ***************************************************************************** */351#define RDR_MSICAP 0x0500A0352 353/* ***************************************************************************** */354#define RDR_MSIARL 0x0500A4355 356/* ***************************************************************************** */357#define RDR_MSIARU 0x0500A8358 359/* ***************************************************************************** */360#define RDR_MSIDATA 0x0500AC361 362/* ***************************************************************************** */363/* PCI Express Extended Capabilities */364/* ***************************************************************************** */365#define RDR_AERXCAP 0x050100366 367/* ***************************************************************************** */368#define RDR_AERUESTA 0x050104369 370/* ***************************************************************************** */371#define RDR_AERUEMSK 0x050108372 373/* ***************************************************************************** */374#define RDR_AERUESEV 0x05010C375 376/* ***************************************************************************** */377#define RDR_AERCESTA 0x050110378 379/* ***************************************************************************** */380#define RDR_AERCEMSK 0x050114381 382/* ***************************************************************************** */383#define RDR_AERCC 0x050118384 385/* ***************************************************************************** */386#define RDR_AERHL0 0x05011C387 388/* ***************************************************************************** */389#define RDR_AERHL1 0x050120390 391/* ***************************************************************************** */392#define RDR_AERHL2 0x050124393 394/* ***************************************************************************** */395#define RDR_AERHL3 0x050128396 397/* ***************************************************************************** */398#define RDR_VCXCAP 0x050200399 400/* ***************************************************************************** */401#define RDR_VCCAP1 0x050204402 403/* ***************************************************************************** */404#define RDR_VCCAP2 0x050208405 406/* ***************************************************************************** */407#define RDR_VCSC 0x05020C408 409/* ***************************************************************************** */410#define RDR_VCR0_CAP 0x050210411 412/* ***************************************************************************** */413#define RDR_VCR0_CTRL 0x050214414 415/* ***************************************************************************** */416#define RDR_VCR0_STAT 0x050218417 418/* ***************************************************************************** */419#define RDR_VCR1_CAP 0x05021C420 421/* ***************************************************************************** */422#define RDR_VCR1_CTRL 0x050220423 424/* ***************************************************************************** */425#define RDR_VCR1_STAT 0x050224426 427/* ***************************************************************************** */428#define RDR_VCR2_CAP 0x050228429 430/* ***************************************************************************** */431#define RDR_VCR2_CTRL 0x05022C432 433/* ***************************************************************************** */434#define RDR_VCR2_STAT 0x050230435 436/* ***************************************************************************** */437#define RDR_VCR3_CAP 0x050234438 439/* ***************************************************************************** */440#define RDR_VCR3_CTRL 0x050238441 442/* ***************************************************************************** */443#define RDR_VCR3_STAT 0x05023C444 445/* ***************************************************************************** */446#define RDR_VCARB0 0x050240447 448/* ***************************************************************************** */449#define RDR_VCARB1 0x050244450 451/* ***************************************************************************** */452#define RDR_VCARB2 0x050248453 454/* ***************************************************************************** */455#define RDR_VCARB3 0x05024C456 457/* ***************************************************************************** */458#define RDR_VCARB4 0x050250459 460/* ***************************************************************************** */461#define RDR_VCARB5 0x050254462 463/* ***************************************************************************** */464#define RDR_VCARB6 0x050258465 466/* ***************************************************************************** */467#define RDR_VCARB7 0x05025C468 469/* ***************************************************************************** */470#define RDR_RDRSTAT0 0x050300471 472/* ***************************************************************************** */473#define RDR_RDRSTAT1 0x050304474 475/* ***************************************************************************** */476#define RDR_RDRCTL0 0x050308477 478/* ***************************************************************************** */479#define RDR_RDRCTL1 0x05030C480 481/* ***************************************************************************** */482/* Transaction Layer Registers */483/* ***************************************************************************** */484#define RDR_TLSTAT0 0x050310485 486/* ***************************************************************************** */487#define RDR_TLSTAT1 0x050314488 489/* ***************************************************************************** */490#define RDR_TLCTL0 0x050318491#define FLD_CFG_UR_CPL_MODE 0x00000040492#define FLD_CFG_CORR_ERR_QUITE 0x00000020493#define FLD_CFG_RCB_CK_EN 0x00000010494#define FLD_CFG_BNDRY_CK_EN 0x00000008495#define FLD_CFG_BYTE_EN_CK_EN 0x00000004496#define FLD_CFG_RELAX_ORDER_MSK 0x00000002497#define FLD_CFG_TAG_ORDER_EN 0x00000001498 499/* ***************************************************************************** */500#define RDR_TLCTL1 0x05031C501 502/* ***************************************************************************** */503#define RDR_REQRCAL 0x050320504 505/* ***************************************************************************** */506#define RDR_REQRCAU 0x050324507 508/* ***************************************************************************** */509#define RDR_REQEPA 0x050328510 511/* ***************************************************************************** */512#define RDR_REQCTRL 0x05032C513 514/* ***************************************************************************** */515#define RDR_REQSTAT 0x050330516 517/* ***************************************************************************** */518#define RDR_TL_TEST 0x050334519 520/* ***************************************************************************** */521#define RDR_VCR01_CTL 0x050348522 523/* ***************************************************************************** */524#define RDR_VCR23_CTL 0x05034C525 526/* ***************************************************************************** */527#define RDR_RX_VCR0_FC 0x050350528 529/* ***************************************************************************** */530#define RDR_RX_VCR1_FC 0x050354531 532/* ***************************************************************************** */533#define RDR_RX_VCR2_FC 0x050358534 535/* ***************************************************************************** */536#define RDR_RX_VCR3_FC 0x05035C537 538/* ***************************************************************************** */539/* Data Link Layer Registers */540/* ***************************************************************************** */541#define RDR_DLLSTAT 0x050360542 543/* ***************************************************************************** */544#define RDR_DLLCTRL 0x050364545 546/* ***************************************************************************** */547#define RDR_REPLAYTO 0x050368548 549/* ***************************************************************************** */550#define RDR_ACKLATTO 0x05036C551 552/* ***************************************************************************** */553/* MAC Layer Registers */554/* ***************************************************************************** */555#define RDR_MACSTAT0 0x050380556 557/* ***************************************************************************** */558#define RDR_MACSTAT1 0x050384559 560/* ***************************************************************************** */561#define RDR_MACCTRL0 0x050388562 563/* ***************************************************************************** */564#define RDR_MACCTRL1 0x05038C565 566/* ***************************************************************************** */567#define RDR_MACCTRL2 0x050390568 569/* ***************************************************************************** */570#define RDR_MAC_LB_DATA 0x050394571 572/* ***************************************************************************** */573#define RDR_L0S_EXIT_LAT 0x050398574 575/* ***************************************************************************** */576/* DMAC */577/* ***************************************************************************** */578#define DMA1_PTR1 0x100000 /* DMA Current Ptr : Ch#1 */579 580/* ***************************************************************************** */581#define DMA2_PTR1 0x100004 /* DMA Current Ptr : Ch#2 */582 583/* ***************************************************************************** */584#define DMA3_PTR1 0x100008 /* DMA Current Ptr : Ch#3 */585 586/* ***************************************************************************** */587#define DMA4_PTR1 0x10000C /* DMA Current Ptr : Ch#4 */588 589/* ***************************************************************************** */590#define DMA5_PTR1 0x100010 /* DMA Current Ptr : Ch#5 */591 592/* ***************************************************************************** */593#define DMA6_PTR1 0x100014 /* DMA Current Ptr : Ch#6 */594 595/* ***************************************************************************** */596#define DMA7_PTR1 0x100018 /* DMA Current Ptr : Ch#7 */597 598/* ***************************************************************************** */599#define DMA8_PTR1 0x10001C /* DMA Current Ptr : Ch#8 */600 601/* ***************************************************************************** */602#define DMA9_PTR1 0x100020 /* DMA Current Ptr : Ch#9 */603 604/* ***************************************************************************** */605#define DMA10_PTR1 0x100024 /* DMA Current Ptr : Ch#10 */606 607/* ***************************************************************************** */608#define DMA11_PTR1 0x100028 /* DMA Current Ptr : Ch#11 */609 610/* ***************************************************************************** */611#define DMA12_PTR1 0x10002C /* DMA Current Ptr : Ch#12 */612 613/* ***************************************************************************** */614#define DMA13_PTR1 0x100030 /* DMA Current Ptr : Ch#13 */615 616/* ***************************************************************************** */617#define DMA14_PTR1 0x100034 /* DMA Current Ptr : Ch#14 */618 619/* ***************************************************************************** */620#define DMA15_PTR1 0x100038 /* DMA Current Ptr : Ch#15 */621 622/* ***************************************************************************** */623#define DMA16_PTR1 0x10003C /* DMA Current Ptr : Ch#16 */624 625/* ***************************************************************************** */626#define DMA17_PTR1 0x100040 /* DMA Current Ptr : Ch#17 */627 628/* ***************************************************************************** */629#define DMA18_PTR1 0x100044 /* DMA Current Ptr : Ch#18 */630 631/* ***************************************************************************** */632#define DMA19_PTR1 0x100048 /* DMA Current Ptr : Ch#19 */633 634/* ***************************************************************************** */635#define DMA20_PTR1 0x10004C /* DMA Current Ptr : Ch#20 */636 637/* ***************************************************************************** */638#define DMA21_PTR1 0x100050 /* DMA Current Ptr : Ch#21 */639 640/* ***************************************************************************** */641#define DMA22_PTR1 0x100054 /* DMA Current Ptr : Ch#22 */642 643/* ***************************************************************************** */644#define DMA23_PTR1 0x100058 /* DMA Current Ptr : Ch#23 */645 646/* ***************************************************************************** */647#define DMA24_PTR1 0x10005C /* DMA Current Ptr : Ch#24 */648 649/* ***************************************************************************** */650#define DMA25_PTR1 0x100060 /* DMA Current Ptr : Ch#25 */651 652/* ***************************************************************************** */653#define DMA26_PTR1 0x100064 /* DMA Current Ptr : Ch#26 */654 655/* ***************************************************************************** */656#define DMA1_PTR2 0x100080 /* DMA Tab Ptr : Ch#1 */657 658/* ***************************************************************************** */659#define DMA2_PTR2 0x100084 /* DMA Tab Ptr : Ch#2 */660 661/* ***************************************************************************** */662#define DMA3_PTR2 0x100088 /* DMA Tab Ptr : Ch#3 */663 664/* ***************************************************************************** */665#define DMA4_PTR2 0x10008C /* DMA Tab Ptr : Ch#4 */666 667/* ***************************************************************************** */668#define DMA5_PTR2 0x100090 /* DMA Tab Ptr : Ch#5 */669 670/* ***************************************************************************** */671#define DMA6_PTR2 0x100094 /* DMA Tab Ptr : Ch#6 */672 673/* ***************************************************************************** */674#define DMA7_PTR2 0x100098 /* DMA Tab Ptr : Ch#7 */675 676/* ***************************************************************************** */677#define DMA8_PTR2 0x10009C /* DMA Tab Ptr : Ch#8 */678 679/* ***************************************************************************** */680#define DMA9_PTR2 0x1000A0 /* DMA Tab Ptr : Ch#9 */681 682/* ***************************************************************************** */683#define DMA10_PTR2 0x1000A4 /* DMA Tab Ptr : Ch#10 */684 685/* ***************************************************************************** */686#define DMA11_PTR2 0x1000A8 /* DMA Tab Ptr : Ch#11 */687 688/* ***************************************************************************** */689#define DMA12_PTR2 0x1000AC /* DMA Tab Ptr : Ch#12 */690 691/* ***************************************************************************** */692#define DMA13_PTR2 0x1000B0 /* DMA Tab Ptr : Ch#13 */693 694/* ***************************************************************************** */695#define DMA14_PTR2 0x1000B4 /* DMA Tab Ptr : Ch#14 */696 697/* ***************************************************************************** */698#define DMA15_PTR2 0x1000B8 /* DMA Tab Ptr : Ch#15 */699 700/* ***************************************************************************** */701#define DMA16_PTR2 0x1000BC /* DMA Tab Ptr : Ch#16 */702 703/* ***************************************************************************** */704#define DMA17_PTR2 0x1000C0 /* DMA Tab Ptr : Ch#17 */705 706/* ***************************************************************************** */707#define DMA18_PTR2 0x1000C4 /* DMA Tab Ptr : Ch#18 */708 709/* ***************************************************************************** */710#define DMA19_PTR2 0x1000C8 /* DMA Tab Ptr : Ch#19 */711 712/* ***************************************************************************** */713#define DMA20_PTR2 0x1000CC /* DMA Tab Ptr : Ch#20 */714 715/* ***************************************************************************** */716#define DMA21_PTR2 0x1000D0 /* DMA Tab Ptr : Ch#21 */717 718/* ***************************************************************************** */719#define DMA22_PTR2 0x1000D4 /* DMA Tab Ptr : Ch#22 */720 721/* ***************************************************************************** */722#define DMA23_PTR2 0x1000D8 /* DMA Tab Ptr : Ch#23 */723 724/* ***************************************************************************** */725#define DMA24_PTR2 0x1000DC /* DMA Tab Ptr : Ch#24 */726 727/* ***************************************************************************** */728#define DMA25_PTR2 0x1000E0 /* DMA Tab Ptr : Ch#25 */729 730/* ***************************************************************************** */731#define DMA26_PTR2 0x1000E4 /* DMA Tab Ptr : Ch#26 */732 733/* ***************************************************************************** */734#define DMA1_CNT1 0x100100 /* DMA BuFFer Size : Ch#1 */735 736/* ***************************************************************************** */737#define DMA2_CNT1 0x100104 /* DMA BuFFer Size : Ch#2 */738 739/* ***************************************************************************** */740#define DMA3_CNT1 0x100108 /* DMA BuFFer Size : Ch#3 */741 742/* ***************************************************************************** */743#define DMA4_CNT1 0x10010C /* DMA BuFFer Size : Ch#4 */744 745/* ***************************************************************************** */746#define DMA5_CNT1 0x100110 /* DMA BuFFer Size : Ch#5 */747 748/* ***************************************************************************** */749#define DMA6_CNT1 0x100114 /* DMA BuFFer Size : Ch#6 */750 751/* ***************************************************************************** */752#define DMA7_CNT1 0x100118 /* DMA BuFFer Size : Ch#7 */753 754/* ***************************************************************************** */755#define DMA8_CNT1 0x10011C /* DMA BuFFer Size : Ch#8 */756 757/* ***************************************************************************** */758#define DMA9_CNT1 0x100120 /* DMA BuFFer Size : Ch#9 */759 760/* ***************************************************************************** */761#define DMA10_CNT1 0x100124 /* DMA BuFFer Size : Ch#10 */762 763/* ***************************************************************************** */764#define DMA11_CNT1 0x100128 /* DMA BuFFer Size : Ch#11 */765 766/* ***************************************************************************** */767#define DMA12_CNT1 0x10012C /* DMA BuFFer Size : Ch#12 */768 769/* ***************************************************************************** */770#define DMA13_CNT1 0x100130 /* DMA BuFFer Size : Ch#13 */771 772/* ***************************************************************************** */773#define DMA14_CNT1 0x100134 /* DMA BuFFer Size : Ch#14 */774 775/* ***************************************************************************** */776#define DMA15_CNT1 0x100138 /* DMA BuFFer Size : Ch#15 */777 778/* ***************************************************************************** */779#define DMA16_CNT1 0x10013C /* DMA BuFFer Size : Ch#16 */780 781/* ***************************************************************************** */782#define DMA17_CNT1 0x100140 /* DMA BuFFer Size : Ch#17 */783 784/* ***************************************************************************** */785#define DMA18_CNT1 0x100144 /* DMA BuFFer Size : Ch#18 */786 787/* ***************************************************************************** */788#define DMA19_CNT1 0x100148 /* DMA BuFFer Size : Ch#19 */789 790/* ***************************************************************************** */791#define DMA20_CNT1 0x10014C /* DMA BuFFer Size : Ch#20 */792 793/* ***************************************************************************** */794#define DMA21_CNT1 0x100150 /* DMA BuFFer Size : Ch#21 */795 796/* ***************************************************************************** */797#define DMA22_CNT1 0x100154 /* DMA BuFFer Size : Ch#22 */798 799/* ***************************************************************************** */800#define DMA23_CNT1 0x100158 /* DMA BuFFer Size : Ch#23 */801 802/* ***************************************************************************** */803#define DMA24_CNT1 0x10015C /* DMA BuFFer Size : Ch#24 */804 805/* ***************************************************************************** */806#define DMA25_CNT1 0x100160 /* DMA BuFFer Size : Ch#25 */807 808/* ***************************************************************************** */809#define DMA26_CNT1 0x100164 /* DMA BuFFer Size : Ch#26 */810 811/* ***************************************************************************** */812#define DMA1_CNT2 0x100180 /* DMA Table Size : Ch#1 */813 814/* ***************************************************************************** */815#define DMA2_CNT2 0x100184 /* DMA Table Size : Ch#2 */816 817/* ***************************************************************************** */818#define DMA3_CNT2 0x100188 /* DMA Table Size : Ch#3 */819 820/* ***************************************************************************** */821#define DMA4_CNT2 0x10018C /* DMA Table Size : Ch#4 */822 823/* ***************************************************************************** */824#define DMA5_CNT2 0x100190 /* DMA Table Size : Ch#5 */825 826/* ***************************************************************************** */827#define DMA6_CNT2 0x100194 /* DMA Table Size : Ch#6 */828 829/* ***************************************************************************** */830#define DMA7_CNT2 0x100198 /* DMA Table Size : Ch#7 */831 832/* ***************************************************************************** */833#define DMA8_CNT2 0x10019C /* DMA Table Size : Ch#8 */834 835/* ***************************************************************************** */836#define DMA9_CNT2 0x1001A0 /* DMA Table Size : Ch#9 */837 838/* ***************************************************************************** */839#define DMA10_CNT2 0x1001A4 /* DMA Table Size : Ch#10 */840 841/* ***************************************************************************** */842#define DMA11_CNT2 0x1001A8 /* DMA Table Size : Ch#11 */843 844/* ***************************************************************************** */845#define DMA12_CNT2 0x1001AC /* DMA Table Size : Ch#12 */846 847/* ***************************************************************************** */848#define DMA13_CNT2 0x1001B0 /* DMA Table Size : Ch#13 */849 850/* ***************************************************************************** */851#define DMA14_CNT2 0x1001B4 /* DMA Table Size : Ch#14 */852 853/* ***************************************************************************** */854#define DMA15_CNT2 0x1001B8 /* DMA Table Size : Ch#15 */855 856/* ***************************************************************************** */857#define DMA16_CNT2 0x1001BC /* DMA Table Size : Ch#16 */858 859/* ***************************************************************************** */860#define DMA17_CNT2 0x1001C0 /* DMA Table Size : Ch#17 */861 862/* ***************************************************************************** */863#define DMA18_CNT2 0x1001C4 /* DMA Table Size : Ch#18 */864 865/* ***************************************************************************** */866#define DMA19_CNT2 0x1001C8 /* DMA Table Size : Ch#19 */867 868/* ***************************************************************************** */869#define DMA20_CNT2 0x1001CC /* DMA Table Size : Ch#20 */870 871/* ***************************************************************************** */872#define DMA21_CNT2 0x1001D0 /* DMA Table Size : Ch#21 */873 874/* ***************************************************************************** */875#define DMA22_CNT2 0x1001D4 /* DMA Table Size : Ch#22 */876 877/* ***************************************************************************** */878#define DMA23_CNT2 0x1001D8 /* DMA Table Size : Ch#23 */879 880/* ***************************************************************************** */881#define DMA24_CNT2 0x1001DC /* DMA Table Size : Ch#24 */882 883/* ***************************************************************************** */884#define DMA25_CNT2 0x1001E0 /* DMA Table Size : Ch#25 */885 886/* ***************************************************************************** */887#define DMA26_CNT2 0x1001E4 /* DMA Table Size : Ch#26 */888 889/* ***************************************************************************** */890 /* ITG */891/* ***************************************************************************** */892#define TM_CNT_LDW 0x110000 /* Timer : Counter low */893 894/* ***************************************************************************** */895#define TM_CNT_UW 0x110004 /* Timer : Counter high word */896 897/* ***************************************************************************** */898#define TM_LMT_LDW 0x110008 /* Timer : Limit low */899 900/* ***************************************************************************** */901#define TM_LMT_UW 0x11000C /* Timer : Limit high word */902 903/* ***************************************************************************** */904#define GP0_IO 0x110010 /* GPIO output enables data I/O */905#define FLD_GP_OE 0x00FF0000 /* GPIO: GP_OE output enable */906#define FLD_GP_IN 0x0000FF00 /* GPIO: GP_IN status */907#define FLD_GP_OUT 0x000000FF /* GPIO: GP_OUT control */908 909/* ***************************************************************************** */910#define GPIO_ISM 0x110014 /* GPIO interrupt sensitivity mode */911#define FLD_GP_ISM_SNS 0x00000070912#define FLD_GP_ISM_POL 0x00000007913 914/* ***************************************************************************** */915#define SOFT_RESET 0x11001C /* Output system reset reg */916#define FLD_PECOS_SOFT_RESET 0x00000001917 918/* ***************************************************************************** */919#define MC416_RWD 0x110020 /* MC416 GPIO[18:3] pin */920#define MC416_OEN 0x110024 /* Output enable of GPIO[18:3] */921#define MC416_CTL 0x110028922 923/* ***************************************************************************** */924#define ALT_PIN_OUT_SEL 0x11002C /* Alternate GPIO output select */925 926#define FLD_ALT_GPIO_OUT_SEL 0xF0000000927/* 0 Disabled <-- default */928/* 1 GPIO[0] */929/* 2 GPIO[10] */930/* 3 VIP_656_DATA_VAL */931/* 4 VIP_656_DATA[0] */932/* 5 VIP_656_CLK */933/* 6 VIP_656_DATA_EXT[1] */934/* 7 VIP_656_DATA_EXT[0] */935/* 8 ATT_IF */936 937#define FLD_AUX_PLL_CLK_ALT_SEL 0x0F000000938/* 0 AUX_PLL_CLK<-- default */939/* 1 GPIO[2] */940/* 2 GPIO[10] */941/* 3 VIP_656_DATA_VAL */942/* 4 VIP_656_DATA[0] */943/* 5 VIP_656_CLK */944/* 6 VIP_656_DATA_EXT[1] */945/* 7 VIP_656_DATA_EXT[0] */946 947#define FLD_IR_TX_ALT_SEL 0x00F00000948/* 0 IR_TX <-- default */949/* 1 GPIO[1] */950/* 2 GPIO[10] */951/* 3 VIP_656_DATA_VAL */952/* 4 VIP_656_DATA[0] */953/* 5 VIP_656_CLK */954/* 6 VIP_656_DATA_EXT[1] */955/* 7 VIP_656_DATA_EXT[0] */956 957#define FLD_IR_RX_ALT_SEL 0x000F0000958/* 0 IR_RX <-- default */959/* 1 GPIO[0] */960/* 2 GPIO[10] */961/* 3 VIP_656_DATA_VAL */962/* 4 VIP_656_DATA[0] */963/* 5 VIP_656_CLK */964/* 6 VIP_656_DATA_EXT[1] */965/* 7 VIP_656_DATA_EXT[0] */966 967#define FLD_GPIO10_ALT_SEL 0x0000F000968/* 0 GPIO[10] <-- default */969/* 1 GPIO[0] */970/* 2 GPIO[10] */971/* 3 VIP_656_DATA_VAL */972/* 4 VIP_656_DATA[0] */973/* 5 VIP_656_CLK */974/* 6 VIP_656_DATA_EXT[1] */975/* 7 VIP_656_DATA_EXT[0] */976 977#define FLD_GPIO2_ALT_SEL 0x00000F00978/* 0 GPIO[2] <-- default */979/* 1 GPIO[1] */980/* 2 GPIO[10] */981/* 3 VIP_656_DATA_VAL */982/* 4 VIP_656_DATA[0] */983/* 5 VIP_656_CLK */984/* 6 VIP_656_DATA_EXT[1] */985/* 7 VIP_656_DATA_EXT[0] */986 987#define FLD_GPIO1_ALT_SEL 0x000000F0988/* 0 GPIO[1] <-- default */989/* 1 GPIO[0] */990/* 2 GPIO[10] */991/* 3 VIP_656_DATA_VAL */992/* 4 VIP_656_DATA[0] */993/* 5 VIP_656_CLK */994/* 6 VIP_656_DATA_EXT[1] */995/* 7 VIP_656_DATA_EXT[0] */996 997#define FLD_GPIO0_ALT_SEL 0x0000000F998/* 0 GPIO[0] <-- default */999/* 1 GPIO[1] */1000/* 2 GPIO[10] */1001/* 3 VIP_656_DATA_VAL */1002/* 4 VIP_656_DATA[0] */1003/* 5 VIP_656_CLK */1004/* 6 VIP_656_DATA_EXT[1] */1005/* 7 VIP_656_DATA_EXT[0] */1006 1007#define ALT_PIN_IN_SEL 0x110030 /* Alternate GPIO input select */1008 1009#define FLD_GPIO10_ALT_IN_SEL 0x0000F0001010/* 0 GPIO[10] <-- default */1011/* 1 IR_RX */1012/* 2 IR_TX */1013/* 3 AUX_PLL_CLK */1014/* 4 IF_ATT_SEL */1015/* 5 GPIO[0] */1016/* 6 GPIO[1] */1017/* 7 GPIO[2] */1018 1019#define FLD_GPIO2_ALT_IN_SEL 0x00000F001020/* 0 GPIO[2] <-- default */1021/* 1 IR_RX */1022/* 2 IR_TX */1023/* 3 AUX_PLL_CLK */1024/* 4 IF_ATT_SEL */1025 1026#define FLD_GPIO1_ALT_IN_SEL 0x000000F01027/* 0 GPIO[1] <-- default */1028/* 1 IR_RX */1029/* 2 IR_TX */1030/* 3 AUX_PLL_CLK */1031/* 4 IF_ATT_SEL */1032 1033#define FLD_GPIO0_ALT_IN_SEL 0x0000000F1034/* 0 GPIO[0] <-- default */1035/* 1 IR_RX */1036/* 2 IR_TX */1037/* 3 AUX_PLL_CLK */1038/* 4 IF_ATT_SEL */1039 1040/* ***************************************************************************** */1041#define TEST_BUS_CTL1 0x110040 /* Test bus control register #1 */1042 1043/* ***************************************************************************** */1044#define TEST_BUS_CTL2 0x110044 /* Test bus control register #2 */1045 1046/* ***************************************************************************** */1047#define CLK_DELAY 0x110048 /* Clock delay */1048#define FLD_MOE_CLK_DIS 0x80000000 /* Disable MoE clock */1049 1050/* ***************************************************************************** */1051#define PAD_CTRL 0x110068 /* Pad drive strength control */1052 1053/* ***************************************************************************** */1054#define MBIST_CTRL 0x110050 /* SRAM memory built-in self test control */1055 1056/* ***************************************************************************** */1057#define MBIST_STAT 0x110054 /* SRAM memory built-in self test status */1058 1059/* ***************************************************************************** */1060/* PLL registers */1061/* ***************************************************************************** */1062#define PLL_A_INT_FRAC 0x1100881063#define PLL_A_POST_STAT_BIST 0x11008C1064#define PLL_B_INT_FRAC 0x1100901065#define PLL_B_POST_STAT_BIST 0x1100941066#define PLL_C_INT_FRAC 0x1100981067#define PLL_C_POST_STAT_BIST 0x11009C1068#define PLL_D_INT_FRAC 0x1100A01069#define PLL_D_POST_STAT_BIST 0x1100A41070 1071#define CLK_RST 0x11002C1072#define FLD_VID_I_CLK_NOE 0x000010001073#define FLD_VID_J_CLK_NOE 0x000020001074#define FLD_USE_ALT_PLL_REF 0x000040001075 1076#define VID_CH_MODE_SEL 0x1100781077#define VID_CH_CLK_SEL 0x11007C1078 1079/* ***************************************************************************** */1080#define VBI_A_DMA 0x130008 /* VBI A DMA data port */1081 1082/* ***************************************************************************** */1083#define VID_A_VIP_CTL 0x130080 /* Video A VIP format control */1084#define FLD_VIP_MODE 0x000000011085 1086/* ***************************************************************************** */1087#define VID_A_PIXEL_FRMT 0x130084 /* Video A pixel format */1088#define FLD_VID_A_GAMMA_DIS 0x000000081089#define FLD_VID_A_FORMAT 0x000000071090#define FLD_VID_A_GAMMA_FACTOR 0x000000101091 1092/* ***************************************************************************** */1093#define VID_A_VBI_CTL 0x130088 /* Video A VBI miscellaneous control */1094#define FLD_VID_A_VIP_EXT 0x000000031095 1096/* ***************************************************************************** */1097#define VID_B_DMA 0x130100 /* Video B DMA data port */1098 1099/* ***************************************************************************** */1100#define VBI_B_DMA 0x130108 /* VBI B DMA data port */1101 1102/* ***************************************************************************** */1103#define VID_B_SRC_SEL 0x130144 /* Video B source select */1104#define FLD_VID_B_SRC_SEL 0x000000001105 1106/* ***************************************************************************** */1107#define VID_B_LNGTH 0x130150 /* Video B line length */1108#define FLD_VID_B_LN_LNGTH 0x00000FFF1109 1110/* ***************************************************************************** */1111#define VID_B_VIP_CTL 0x130180 /* Video B VIP format control */1112 1113/* ***************************************************************************** */1114#define VID_B_PIXEL_FRMT 0x130184 /* Video B pixel format */1115#define FLD_VID_B_GAMMA_DIS 0x000000081116#define FLD_VID_B_FORMAT 0x000000071117#define FLD_VID_B_GAMMA_FACTOR 0x000000101118 1119/* ***************************************************************************** */1120#define VID_C_DMA 0x130200 /* Video C DMA data port */1121 1122/* ***************************************************************************** */1123#define VID_C_LNGTH 0x130250 /* Video C line length */1124#define FLD_VID_C_LN_LNGTH 0x00000FFF1125 1126/* ***************************************************************************** */1127/* Video Destination Channels */1128/* ***************************************************************************** */1129 1130#define VID_DST_A_GPCNT 0x130020 /* Video A general purpose counter */1131#define VID_DST_B_GPCNT 0x130120 /* Video B general purpose counter */1132#define VID_DST_C_GPCNT 0x130220 /* Video C general purpose counter */1133#define VID_DST_D_GPCNT 0x130320 /* Video D general purpose counter */1134#define VID_DST_E_GPCNT 0x130420 /* Video E general purpose counter */1135#define VID_DST_F_GPCNT 0x130520 /* Video F general purpose counter */1136#define VID_DST_G_GPCNT 0x130620 /* Video G general purpose counter */1137#define VID_DST_H_GPCNT 0x130720 /* Video H general purpose counter */1138 1139/* ***************************************************************************** */1140 1141#define VID_DST_A_GPCNT_CTL 0x130030 /* Video A general purpose control */1142#define VID_DST_B_GPCNT_CTL 0x130130 /* Video B general purpose control */1143#define VID_DST_C_GPCNT_CTL 0x130230 /* Video C general purpose control */1144#define VID_DST_D_GPCNT_CTL 0x130330 /* Video D general purpose control */1145#define VID_DST_E_GPCNT_CTL 0x130430 /* Video E general purpose control */1146#define VID_DST_F_GPCNT_CTL 0x130530 /* Video F general purpose control */1147#define VID_DST_G_GPCNT_CTL 0x130630 /* Video G general purpose control */1148#define VID_DST_H_GPCNT_CTL 0x130730 /* Video H general purpose control */1149 1150/* ***************************************************************************** */1151 1152#define VID_DST_A_DMA_CTL 0x130040 /* Video A DMA control */1153#define VID_DST_B_DMA_CTL 0x130140 /* Video B DMA control */1154#define VID_DST_C_DMA_CTL 0x130240 /* Video C DMA control */1155#define VID_DST_D_DMA_CTL 0x130340 /* Video D DMA control */1156#define VID_DST_E_DMA_CTL 0x130440 /* Video E DMA control */1157#define VID_DST_F_DMA_CTL 0x130540 /* Video F DMA control */1158#define VID_DST_G_DMA_CTL 0x130640 /* Video G DMA control */1159#define VID_DST_H_DMA_CTL 0x130740 /* Video H DMA control */1160 1161#define FLD_VID_RISC_EN 0x000000101162#define FLD_VID_FIFO_EN 0x000000011163 1164/* ***************************************************************************** */1165 1166#define VID_DST_A_VIP_CTL 0x130080 /* Video A VIP control */1167#define VID_DST_B_VIP_CTL 0x130180 /* Video B VIP control */1168#define VID_DST_C_VIP_CTL 0x130280 /* Video C VIP control */1169#define VID_DST_D_VIP_CTL 0x130380 /* Video D VIP control */1170#define VID_DST_E_VIP_CTL 0x130480 /* Video E VIP control */1171#define VID_DST_F_VIP_CTL 0x130580 /* Video F VIP control */1172#define VID_DST_G_VIP_CTL 0x130680 /* Video G VIP control */1173#define VID_DST_H_VIP_CTL 0x130780 /* Video H VIP control */1174 1175/* ***************************************************************************** */1176 1177#define VID_DST_A_PIX_FRMT 0x130084 /* Video A Pixel format */1178#define VID_DST_B_PIX_FRMT 0x130184 /* Video B Pixel format */1179#define VID_DST_C_PIX_FRMT 0x130284 /* Video C Pixel format */1180#define VID_DST_D_PIX_FRMT 0x130384 /* Video D Pixel format */1181#define VID_DST_E_PIX_FRMT 0x130484 /* Video E Pixel format */1182#define VID_DST_F_PIX_FRMT 0x130584 /* Video F Pixel format */1183#define VID_DST_G_PIX_FRMT 0x130684 /* Video G Pixel format */1184#define VID_DST_H_PIX_FRMT 0x130784 /* Video H Pixel format */1185 1186/* ***************************************************************************** */1187/* Video Source Channels */1188/* ***************************************************************************** */1189 1190#define VID_SRC_A_GPCNT_CTL 0x130804 /* Video A general purpose control */1191#define VID_SRC_B_GPCNT_CTL 0x130904 /* Video B general purpose control */1192#define VID_SRC_C_GPCNT_CTL 0x130A04 /* Video C general purpose control */1193#define VID_SRC_D_GPCNT_CTL 0x130B04 /* Video D general purpose control */1194#define VID_SRC_E_GPCNT_CTL 0x130C04 /* Video E general purpose control */1195#define VID_SRC_F_GPCNT_CTL 0x130D04 /* Video F general purpose control */1196#define VID_SRC_I_GPCNT_CTL 0x130E04 /* Video I general purpose control */1197#define VID_SRC_J_GPCNT_CTL 0x130F04 /* Video J general purpose control */1198 1199/* ***************************************************************************** */1200 1201#define VID_SRC_A_GPCNT 0x130808 /* Video A general purpose counter */1202#define VID_SRC_B_GPCNT 0x130908 /* Video B general purpose counter */1203#define VID_SRC_C_GPCNT 0x130A08 /* Video C general purpose counter */1204#define VID_SRC_D_GPCNT 0x130B08 /* Video D general purpose counter */1205#define VID_SRC_E_GPCNT 0x130C08 /* Video E general purpose counter */1206#define VID_SRC_F_GPCNT 0x130D08 /* Video F general purpose counter */1207#define VID_SRC_I_GPCNT 0x130E08 /* Video I general purpose counter */1208#define VID_SRC_J_GPCNT 0x130F08 /* Video J general purpose counter */1209 1210/* ***************************************************************************** */1211 1212#define VID_SRC_A_DMA_CTL 0x13080C /* Video A DMA control */1213#define VID_SRC_B_DMA_CTL 0x13090C /* Video B DMA control */1214#define VID_SRC_C_DMA_CTL 0x130A0C /* Video C DMA control */1215#define VID_SRC_D_DMA_CTL 0x130B0C /* Video D DMA control */1216#define VID_SRC_E_DMA_CTL 0x130C0C /* Video E DMA control */1217#define VID_SRC_F_DMA_CTL 0x130D0C /* Video F DMA control */1218#define VID_SRC_I_DMA_CTL 0x130E0C /* Video I DMA control */1219#define VID_SRC_J_DMA_CTL 0x130F0C /* Video J DMA control */1220 1221#define FLD_APB_RISC_EN 0x000000101222#define FLD_APB_FIFO_EN 0x000000011223 1224/* ***************************************************************************** */1225 1226#define VID_SRC_A_FMT_CTL 0x130810 /* Video A format control */1227#define VID_SRC_B_FMT_CTL 0x130910 /* Video B format control */1228#define VID_SRC_C_FMT_CTL 0x130A10 /* Video C format control */1229#define VID_SRC_D_FMT_CTL 0x130B10 /* Video D format control */1230#define VID_SRC_E_FMT_CTL 0x130C10 /* Video E format control */1231#define VID_SRC_F_FMT_CTL 0x130D10 /* Video F format control */1232#define VID_SRC_I_FMT_CTL 0x130E10 /* Video I format control */1233#define VID_SRC_J_FMT_CTL 0x130F10 /* Video J format control */1234 1235/* ***************************************************************************** */1236 1237#define VID_SRC_A_ACTIVE_CTL1 0x130814 /* Video A active control 1 */1238#define VID_SRC_B_ACTIVE_CTL1 0x130914 /* Video B active control 1 */1239#define VID_SRC_C_ACTIVE_CTL1 0x130A14 /* Video C active control 1 */1240#define VID_SRC_D_ACTIVE_CTL1 0x130B14 /* Video D active control 1 */1241#define VID_SRC_E_ACTIVE_CTL1 0x130C14 /* Video E active control 1 */1242#define VID_SRC_F_ACTIVE_CTL1 0x130D14 /* Video F active control 1 */1243#define VID_SRC_I_ACTIVE_CTL1 0x130E14 /* Video I active control 1 */1244#define VID_SRC_J_ACTIVE_CTL1 0x130F14 /* Video J active control 1 */1245 1246/* ***************************************************************************** */1247 1248#define VID_SRC_A_ACTIVE_CTL2 0x130818 /* Video A active control 2 */1249#define VID_SRC_B_ACTIVE_CTL2 0x130918 /* Video B active control 2 */1250#define VID_SRC_C_ACTIVE_CTL2 0x130A18 /* Video C active control 2 */1251#define VID_SRC_D_ACTIVE_CTL2 0x130B18 /* Video D active control 2 */1252#define VID_SRC_E_ACTIVE_CTL2 0x130C18 /* Video E active control 2 */1253#define VID_SRC_F_ACTIVE_CTL2 0x130D18 /* Video F active control 2 */1254#define VID_SRC_I_ACTIVE_CTL2 0x130E18 /* Video I active control 2 */1255#define VID_SRC_J_ACTIVE_CTL2 0x130F18 /* Video J active control 2 */1256 1257/* ***************************************************************************** */1258 1259#define VID_SRC_A_CDT_SZ 0x13081C /* Video A CDT size */1260#define VID_SRC_B_CDT_SZ 0x13091C /* Video B CDT size */1261#define VID_SRC_C_CDT_SZ 0x130A1C /* Video C CDT size */1262#define VID_SRC_D_CDT_SZ 0x130B1C /* Video D CDT size */1263#define VID_SRC_E_CDT_SZ 0x130C1C /* Video E CDT size */1264#define VID_SRC_F_CDT_SZ 0x130D1C /* Video F CDT size */1265#define VID_SRC_I_CDT_SZ 0x130E1C /* Video I CDT size */1266#define VID_SRC_J_CDT_SZ 0x130F1C /* Video J CDT size */1267 1268/* ***************************************************************************** */1269/* Audio I/F */1270/* ***************************************************************************** */1271#define AUD_DST_A_DMA 0x140000 /* Audio Int A DMA data port */1272#define AUD_SRC_A_DMA 0x140008 /* Audio Int A DMA data port */1273 1274#define AUD_A_GPCNT 0x140010 /* Audio Int A gp counter */1275#define FLD_AUD_A_GP_CNT 0x0000FFFF1276 1277#define AUD_A_GPCNT_CTL 0x140014 /* Audio Int A gp control */1278 1279#define AUD_A_LNGTH 0x140018 /* Audio Int A line length */1280 1281#define AUD_A_CFG 0x14001C /* Audio Int A configuration */1282 1283/* ***************************************************************************** */1284#define AUD_DST_B_DMA 0x140100 /* Audio Int B DMA data port */1285#define AUD_SRC_B_DMA 0x140108 /* Audio Int B DMA data port */1286 1287#define AUD_B_GPCNT 0x140110 /* Audio Int B gp counter */1288#define FLD_AUD_B_GP_CNT 0x0000FFFF1289 1290#define AUD_B_GPCNT_CTL 0x140114 /* Audio Int B gp control */1291 1292#define AUD_B_LNGTH 0x140118 /* Audio Int B line length */1293 1294#define AUD_B_CFG 0x14011C /* Audio Int B configuration */1295 1296/* ***************************************************************************** */1297#define AUD_DST_C_DMA 0x140200 /* Audio Int C DMA data port */1298#define AUD_SRC_C_DMA 0x140208 /* Audio Int C DMA data port */1299 1300#define AUD_C_GPCNT 0x140210 /* Audio Int C gp counter */1301#define FLD_AUD_C_GP_CNT 0x0000FFFF1302 1303#define AUD_C_GPCNT_CTL 0x140214 /* Audio Int C gp control */1304 1305#define AUD_C_LNGTH 0x140218 /* Audio Int C line length */1306 1307#define AUD_C_CFG 0x14021C /* Audio Int C configuration */1308 1309/* ***************************************************************************** */1310#define AUD_DST_D_DMA 0x140300 /* Audio Int D DMA data port */1311#define AUD_SRC_D_DMA 0x140308 /* Audio Int D DMA data port */1312 1313#define AUD_D_GPCNT 0x140310 /* Audio Int D gp counter */1314#define FLD_AUD_D_GP_CNT 0x0000FFFF1315 1316#define AUD_D_GPCNT_CTL 0x140314 /* Audio Int D gp control */1317 1318#define AUD_D_LNGTH 0x140318 /* Audio Int D line length */1319 1320#define AUD_D_CFG 0x14031C /* Audio Int D configuration */1321 1322/* ***************************************************************************** */1323#define AUD_SRC_E_DMA 0x140400 /* Audio Int E DMA data port */1324 1325#define AUD_E_GPCNT 0x140410 /* Audio Int E gp counter */1326#define FLD_AUD_E_GP_CNT 0x0000FFFF1327 1328#define AUD_E_GPCNT_CTL 0x140414 /* Audio Int E gp control */1329 1330#define AUD_E_CFG 0x14041C /* Audio Int E configuration */1331 1332/* ***************************************************************************** */1333 1334#define FLD_AUD_DST_LN_LNGTH 0x00000FFF1335 1336#define FLD_AUD_DST_PK_MODE 0x000040001337 1338#define FLD_AUD_CLK_ENABLE 0x000002001339 1340#define FLD_AUD_MASTER_MODE 0x000000021341 1342#define FLD_AUD_SONY_MODE 0x000000011343 1344#define FLD_AUD_CLK_SELECT_PLL_D 0x000018001345 1346#define FLD_AUD_DST_ENABLE 0x000200001347 1348#define FLD_AUD_SRC_ENABLE 0x000100001349 1350/* ***************************************************************************** */1351#define AUD_INT_DMA_CTL 0x140500 /* Audio Int DMA control */1352 1353#define FLD_AUD_SRC_E_RISC_EN 0x000080001354#define FLD_AUD_SRC_C_RISC_EN 0x000040001355#define FLD_AUD_SRC_B_RISC_EN 0x000020001356#define FLD_AUD_SRC_A_RISC_EN 0x000010001357 1358#define FLD_AUD_DST_D_RISC_EN 0x000008001359#define FLD_AUD_DST_C_RISC_EN 0x000004001360#define FLD_AUD_DST_B_RISC_EN 0x000002001361#define FLD_AUD_DST_A_RISC_EN 0x000001001362 1363#define FLD_AUD_SRC_E_FIFO_EN 0x000000801364#define FLD_AUD_SRC_C_FIFO_EN 0x000000401365#define FLD_AUD_SRC_B_FIFO_EN 0x000000201366#define FLD_AUD_SRC_A_FIFO_EN 0x000000101367 1368#define FLD_AUD_DST_D_FIFO_EN 0x000000081369#define FLD_AUD_DST_C_FIFO_EN 0x000000041370#define FLD_AUD_DST_B_FIFO_EN 0x000000021371#define FLD_AUD_DST_A_FIFO_EN 0x000000011372 1373/* ***************************************************************************** */1374/* */1375/* Mobilygen Interface Registers */1376/* */1377/* ***************************************************************************** */1378/* Mobilygen Interface A */1379/* ***************************************************************************** */1380#define MB_IF_A_DMA 0x150000 /* MBIF A DMA data port */1381#define MB_IF_A_GPCN 0x150008 /* MBIF A GP counter */1382#define MB_IF_A_GPCN_CTRL 0x15000C1383#define MB_IF_A_DMA_CTRL 0x1500101384#define MB_IF_A_LENGTH 0x1500141385#define MB_IF_A_HDMA_XFER_SZ 0x1500181386#define MB_IF_A_HCMD 0x15001C1387#define MB_IF_A_HCONFIG 0x1500201388#define MB_IF_A_DATA_STRUCT_0 0x1500241389#define MB_IF_A_DATA_STRUCT_1 0x1500281390#define MB_IF_A_DATA_STRUCT_2 0x15002C1391#define MB_IF_A_DATA_STRUCT_3 0x1500301392#define MB_IF_A_DATA_STRUCT_4 0x1500341393#define MB_IF_A_DATA_STRUCT_5 0x1500381394#define MB_IF_A_DATA_STRUCT_6 0x15003C1395#define MB_IF_A_DATA_STRUCT_7 0x1500401396#define MB_IF_A_DATA_STRUCT_8 0x1500441397#define MB_IF_A_DATA_STRUCT_9 0x1500481398#define MB_IF_A_DATA_STRUCT_A 0x15004C1399#define MB_IF_A_DATA_STRUCT_B 0x1500501400#define MB_IF_A_DATA_STRUCT_C 0x1500541401#define MB_IF_A_DATA_STRUCT_D 0x1500581402#define MB_IF_A_DATA_STRUCT_E 0x15005C1403#define MB_IF_A_DATA_STRUCT_F 0x1500601404/* ***************************************************************************** */1405/* Mobilygen Interface B */1406/* ***************************************************************************** */1407#define MB_IF_B_DMA 0x160000 /* MBIF A DMA data port */1408#define MB_IF_B_GPCN 0x160008 /* MBIF A GP counter */1409#define MB_IF_B_GPCN_CTRL 0x16000C1410#define MB_IF_B_DMA_CTRL 0x1600101411#define MB_IF_B_LENGTH 0x1600141412#define MB_IF_B_HDMA_XFER_SZ 0x1600181413#define MB_IF_B_HCMD 0x16001C1414#define MB_IF_B_HCONFIG 0x1600201415#define MB_IF_B_DATA_STRUCT_0 0x1600241416#define MB_IF_B_DATA_STRUCT_1 0x1600281417#define MB_IF_B_DATA_STRUCT_2 0x16002C1418#define MB_IF_B_DATA_STRUCT_3 0x1600301419#define MB_IF_B_DATA_STRUCT_4 0x1600341420#define MB_IF_B_DATA_STRUCT_5 0x1600381421#define MB_IF_B_DATA_STRUCT_6 0x16003C1422#define MB_IF_B_DATA_STRUCT_7 0x1600401423#define MB_IF_B_DATA_STRUCT_8 0x1600441424#define MB_IF_B_DATA_STRUCT_9 0x1600481425#define MB_IF_B_DATA_STRUCT_A 0x16004C1426#define MB_IF_B_DATA_STRUCT_B 0x1600501427#define MB_IF_B_DATA_STRUCT_C 0x1600541428#define MB_IF_B_DATA_STRUCT_D 0x1600581429#define MB_IF_B_DATA_STRUCT_E 0x16005C1430#define MB_IF_B_DATA_STRUCT_F 0x1600601431 1432/* MB_DMA_CTRL */1433#define FLD_MB_IF_RISC_EN 0x000000101434#define FLD_MB_IF_FIFO_EN 0x000000011435 1436/* MB_LENGTH */1437#define FLD_MB_IF_LN_LNGTH 0x00000FFF1438 1439/* MB_HCMD register */1440#define FLD_MB_HCMD_H_GO 0x800000001441#define FLD_MB_HCMD_H_BUSY 0x400000001442#define FLD_MB_HCMD_H_DMA_HOLD 0x100000001443#define FLD_MB_HCMD_H_DMA_BUSY 0x080000001444#define FLD_MB_HCMD_H_DMA_TYPE 0x040000001445#define FLD_MB_HCMD_H_DMA_XACT 0x020000001446#define FLD_MB_HCMD_H_RW_N 0x010000001447#define FLD_MB_HCMD_H_ADDR 0x00FF00001448#define FLD_MB_HCMD_H_DATA 0x0000FFFF1449 1450/* ***************************************************************************** */1451/* I2C #1 */1452/* ***************************************************************************** */1453#define I2C1_ADDR 0x180000 /* I2C #1 address */1454#define FLD_I2C_DADDR 0xfe000000 /* RW [31:25] I2C Device Address */1455 /* RO [24] reserved */1456/* ***************************************************************************** */1457#define FLD_I2C_SADDR 0x00FFFFFF /* RW [23:0] I2C Sub-address */1458 1459/* ***************************************************************************** */1460#define I2C1_WDATA 0x180004 /* I2C #1 write data */1461#define FLD_I2C_WDATA 0xFFFFFFFF /* RW [31:0] */1462 1463/* ***************************************************************************** */1464#define I2C1_CTRL 0x180008 /* I2C #1 control */1465#define FLD_I2C_PERIOD 0xFF000000 /* RW [31:24] */1466#define FLD_I2C_SCL_IN 0x00200000 /* RW [21] */1467#define FLD_I2C_SDA_IN 0x00100000 /* RW [20] */1468 /* RO [19:18] reserved */1469#define FLD_I2C_SCL_OUT 0x00020000 /* RW [17] */1470#define FLD_I2C_SDA_OUT 0x00010000 /* RW [16] */1471 /* RO [15] reserved */1472#define FLD_I2C_DATA_LEN 0x00007000 /* RW [14:12] */1473#define FLD_I2C_SADDR_INC 0x00000800 /* RW [11] */1474 /* RO [10:9] reserved */1475#define FLD_I2C_SADDR_LEN 0x00000300 /* RW [9:8] */1476 /* RO [7:6] reserved */1477#define FLD_I2C_SOFT 0x00000020 /* RW [5] */1478#define FLD_I2C_NOSTOP 0x00000010 /* RW [4] */1479#define FLD_I2C_EXTEND 0x00000008 /* RW [3] */1480#define FLD_I2C_SYNC 0x00000004 /* RW [2] */1481#define FLD_I2C_READ_SA 0x00000002 /* RW [1] */1482#define FLD_I2C_READ_WRN 0x00000001 /* RW [0] */1483 1484/* ***************************************************************************** */1485#define I2C1_RDATA 0x18000C /* I2C #1 read data */1486#define FLD_I2C_RDATA 0xFFFFFFFF /* RO [31:0] */1487 1488/* ***************************************************************************** */1489#define I2C1_STAT 0x180010 /* I2C #1 status */1490#define FLD_I2C_XFER_IN_PROG 0x00000002 /* RO [1] */1491#define FLD_I2C_RACK 0x00000001 /* RO [0] */1492 1493/* ***************************************************************************** */1494/* I2C #2 */1495/* ***************************************************************************** */1496#define I2C2_ADDR 0x190000 /* I2C #2 address */1497 1498/* ***************************************************************************** */1499#define I2C2_WDATA 0x190004 /* I2C #2 write data */1500 1501/* ***************************************************************************** */1502#define I2C2_CTRL 0x190008 /* I2C #2 control */1503 1504/* ***************************************************************************** */1505#define I2C2_RDATA 0x19000C /* I2C #2 read data */1506 1507/* ***************************************************************************** */1508#define I2C2_STAT 0x190010 /* I2C #2 status */1509 1510/* ***************************************************************************** */1511/* I2C #3 */1512/* ***************************************************************************** */1513#define I2C3_ADDR 0x1A0000 /* I2C #3 address */1514 1515/* ***************************************************************************** */1516#define I2C3_WDATA 0x1A0004 /* I2C #3 write data */1517 1518/* ***************************************************************************** */1519#define I2C3_CTRL 0x1A0008 /* I2C #3 control */1520 1521/* ***************************************************************************** */1522#define I2C3_RDATA 0x1A000C /* I2C #3 read data */1523 1524/* ***************************************************************************** */1525#define I2C3_STAT 0x1A0010 /* I2C #3 status */1526 1527/* ***************************************************************************** */1528/* UART */1529/* ***************************************************************************** */1530#define UART_CTL 0x1B0000 /* UART Control Register */1531#define FLD_LOOP_BACK_EN (1 << 7) /* RW field - default 0 */1532#define FLD_RX_TRG_SZ (3 << 2) /* RW field - default 0 */1533#define FLD_RX_EN (1 << 1) /* RW field - default 0 */1534#define FLD_TX_EN (1 << 0) /* RW field - default 0 */1535 1536/* ***************************************************************************** */1537#define UART_BRD 0x1B0004 /* UART Baud Rate Divisor */1538#define FLD_BRD 0x0000FFFF /* RW field - default 0x197 */1539 1540/* ***************************************************************************** */1541#define UART_DBUF 0x1B0008 /* UART Tx/Rx Data BuFFer */1542#define FLD_DB 0xFFFFFFFF /* RW field - default 0 */1543 1544/* ***************************************************************************** */1545#define UART_ISR 0x1B000C /* UART Interrupt Status */1546#define FLD_RXD_TIMEOUT_EN (1 << 7) /* RW field - default 0 */1547#define FLD_FRM_ERR_EN (1 << 6) /* RW field - default 0 */1548#define FLD_RXD_RDY_EN (1 << 5) /* RW field - default 0 */1549#define FLD_TXD_EMPTY_EN (1 << 4) /* RW field - default 0 */1550#define FLD_RXD_OVERFLOW (1 << 3) /* RW field - default 0 */1551#define FLD_FRM_ERR (1 << 2) /* RW field - default 0 */1552#define FLD_RXD_RDY (1 << 1) /* RW field - default 0 */1553#define FLD_TXD_EMPTY (1 << 0) /* RW field - default 0 */1554 1555/* ***************************************************************************** */1556#define UART_CNT 0x1B0010 /* UART Tx/Rx FIFO Byte Count */1557#define FLD_TXD_CNT (0x1F << 8) /* RW field - default 0 */1558#define FLD_RXD_CNT (0x1F << 0) /* RW field - default 0 */1559 1560/* ***************************************************************************** */1561/* Motion Detection */1562#define MD_CH0_GRID_BLOCK_YCNT 0x1700141563#define MD_CH1_GRID_BLOCK_YCNT 0x1700941564#define MD_CH2_GRID_BLOCK_YCNT 0x1701141565#define MD_CH3_GRID_BLOCK_YCNT 0x1701941566#define MD_CH4_GRID_BLOCK_YCNT 0x1702141567#define MD_CH5_GRID_BLOCK_YCNT 0x1702941568#define MD_CH6_GRID_BLOCK_YCNT 0x1703141569#define MD_CH7_GRID_BLOCK_YCNT 0x1703941570 1571#define PIXEL_FRMT_422 41572#define PIXEL_FRMT_411 51573#define PIXEL_FRMT_Y8 61574 1575#define PIXEL_ENGINE_VIP1 01576#define PIXEL_ENGINE_VIP2 11577 1578#endif /* Athena_REGISTERS */1579