248 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Driver for the Conexant CX25821 PCIe bridge4 *5 * Copyright (C) 2009 Conexant Systems Inc.6 * Authors <shu.lin@conexant.com>, <hiep.huynh@conexant.com>7 */8 9#ifndef __ATHENA_SRAM_H__10#define __ATHENA_SRAM_H__11 12/* #define RX_SRAM_START_SIZE = 0; // Start of reserved SRAM */13#define VID_CMDS_SIZE 80 /* Video CMDS size in bytes */14#define AUDIO_CMDS_SIZE 80 /* AUDIO CMDS size in bytes */15#define MBIF_CMDS_SIZE 80 /* MBIF CMDS size in bytes */16 17/* #define RX_SRAM_POOL_START_SIZE = 0; // Start of usable RX SRAM for buffers */18#define VID_IQ_SIZE 64 /* VID instruction queue size in bytes */19#define MBIF_IQ_SIZE 6420#define AUDIO_IQ_SIZE 64 /* AUD instruction queue size in bytes */21 22#define VID_CDT_SIZE 64 /* VID cluster descriptor table size in bytes */23#define MBIF_CDT_SIZE 64 /* MBIF/HBI cluster descriptor table size in bytes */24#define AUDIO_CDT_SIZE 48 /* AUD cluster descriptor table size in bytes */25 26/* #define RX_SRAM_POOL_FREE_SIZE = 16; // Start of available RX SRAM */27/* #define RX_SRAM_END_SIZE = 0; // End of RX SRAM */28 29/* #define TX_SRAM_POOL_START_SIZE = 0; // Start of transmit pool SRAM */30/* #define MSI_DATA_SIZE = 64; // Reserved (MSI Data, RISC working stora */31 32#define VID_CLUSTER_SIZE 1440 /* VID cluster data line */33#define AUDIO_CLUSTER_SIZE 128 /* AUDIO cluster data line */34#define MBIF_CLUSTER_SIZE 1440 /* MBIF/HBI cluster data line */35 36/* #define TX_SRAM_POOL_FREE_SIZE = 704; // Start of available TX SRAM */37/* #define TX_SRAM_END_SIZE = 0; // End of TX SRAM */38 39/* Receive SRAM */40#define RX_SRAM_START 0x1000041#define VID_A_DOWN_CMDS 0x1000042#define VID_B_DOWN_CMDS 0x1005043#define VID_C_DOWN_CMDS 0x100A044#define VID_D_DOWN_CMDS 0x100F045#define VID_E_DOWN_CMDS 0x1014046#define VID_F_DOWN_CMDS 0x1019047#define VID_G_DOWN_CMDS 0x101E048#define VID_H_DOWN_CMDS 0x1023049#define VID_A_UP_CMDS 0x1028050#define VID_B_UP_CMDS 0x102D051#define VID_C_UP_CMDS 0x1032052#define VID_D_UP_CMDS 0x1037053#define VID_E_UP_CMDS 0x103C054#define VID_F_UP_CMDS 0x1041055#define VID_I_UP_CMDS 0x1046056#define VID_J_UP_CMDS 0x104B057#define AUD_A_DOWN_CMDS 0x1050058#define AUD_B_DOWN_CMDS 0x1055059#define AUD_C_DOWN_CMDS 0x105A060#define AUD_D_DOWN_CMDS 0x105F061#define AUD_A_UP_CMDS 0x1064062#define AUD_B_UP_CMDS 0x1069063#define AUD_C_UP_CMDS 0x106E064#define AUD_E_UP_CMDS 0x1073065#define MBIF_A_DOWN_CMDS 0x1078066#define MBIF_B_DOWN_CMDS 0x107D067#define DMA_SCRATCH_PAD 0x10820 /* Scratch pad area from 0x10820 to 0x10B40 */68 69/* #define RX_SRAM_POOL_START = 0x105B0; */70 71#define VID_A_IQ 0x1100072#define VID_B_IQ 0x1104073#define VID_C_IQ 0x1108074#define VID_D_IQ 0x110C075#define VID_E_IQ 0x1110076#define VID_F_IQ 0x1114077#define VID_G_IQ 0x1118078#define VID_H_IQ 0x111C079#define VID_I_IQ 0x1120080#define VID_J_IQ 0x1124081#define AUD_A_IQ 0x1128082#define AUD_B_IQ 0x112C083#define AUD_C_IQ 0x1130084#define AUD_D_IQ 0x1134085#define AUD_E_IQ 0x1138086#define MBIF_A_IQ 0x1100087#define MBIF_B_IQ 0x110C088 89#define VID_A_CDT 0x10C0090#define VID_B_CDT 0x10C4091#define VID_C_CDT 0x10C8092#define VID_D_CDT 0x10CC093#define VID_E_CDT 0x10D0094#define VID_F_CDT 0x10D4095#define VID_G_CDT 0x10D8096#define VID_H_CDT 0x10DC097#define VID_I_CDT 0x10E0098#define VID_J_CDT 0x10E4099#define AUD_A_CDT 0x10E80100#define AUD_B_CDT 0x10EB0101#define AUD_C_CDT 0x10EE0102#define AUD_D_CDT 0x10F10103#define AUD_E_CDT 0x10F40104#define MBIF_A_CDT 0x10C00105#define MBIF_B_CDT 0x10CC0106 107/* Cluster Buffer for RX */108#define VID_A_UP_CLUSTER_1 0x11400109#define VID_A_UP_CLUSTER_2 0x119A0110#define VID_A_UP_CLUSTER_3 0x11F40111#define VID_A_UP_CLUSTER_4 0x124E0112 113#define VID_B_UP_CLUSTER_1 0x12A80114#define VID_B_UP_CLUSTER_2 0x13020115#define VID_B_UP_CLUSTER_3 0x135C0116#define VID_B_UP_CLUSTER_4 0x13B60117 118#define VID_C_UP_CLUSTER_1 0x14100119#define VID_C_UP_CLUSTER_2 0x146A0120#define VID_C_UP_CLUSTER_3 0x14C40121#define VID_C_UP_CLUSTER_4 0x151E0122 123#define VID_D_UP_CLUSTER_1 0x15780124#define VID_D_UP_CLUSTER_2 0x15D20125#define VID_D_UP_CLUSTER_3 0x162C0126#define VID_D_UP_CLUSTER_4 0x16860127 128#define VID_E_UP_CLUSTER_1 0x16E00129#define VID_E_UP_CLUSTER_2 0x173A0130#define VID_E_UP_CLUSTER_3 0x17940131#define VID_E_UP_CLUSTER_4 0x17EE0132 133#define VID_F_UP_CLUSTER_1 0x18480134#define VID_F_UP_CLUSTER_2 0x18A20135#define VID_F_UP_CLUSTER_3 0x18FC0136#define VID_F_UP_CLUSTER_4 0x19560137 138#define VID_I_UP_CLUSTER_1 0x19B00139#define VID_I_UP_CLUSTER_2 0x1A0A0140#define VID_I_UP_CLUSTER_3 0x1A640141#define VID_I_UP_CLUSTER_4 0x1ABE0142 143#define VID_J_UP_CLUSTER_1 0x1B180144#define VID_J_UP_CLUSTER_2 0x1B720145#define VID_J_UP_CLUSTER_3 0x1BCC0146#define VID_J_UP_CLUSTER_4 0x1C260147 148#define AUD_A_UP_CLUSTER_1 0x1C800149#define AUD_A_UP_CLUSTER_2 0x1C880150#define AUD_A_UP_CLUSTER_3 0x1C900151 152#define AUD_B_UP_CLUSTER_1 0x1C980153#define AUD_B_UP_CLUSTER_2 0x1CA00154#define AUD_B_UP_CLUSTER_3 0x1CA80155 156#define AUD_C_UP_CLUSTER_1 0x1CB00157#define AUD_C_UP_CLUSTER_2 0x1CB80158#define AUD_C_UP_CLUSTER_3 0x1CC00159 160#define AUD_E_UP_CLUSTER_1 0x1CC80161#define AUD_E_UP_CLUSTER_2 0x1CD00162#define AUD_E_UP_CLUSTER_3 0x1CD80163 164#define RX_SRAM_POOL_FREE 0x1CE00165#define RX_SRAM_END 0x1D000166 167/* Free Receive SRAM 144 Bytes */168 169/* Transmit SRAM */170#define TX_SRAM_POOL_START 0x00000171 172#define VID_A_DOWN_CLUSTER_1 0x00040173#define VID_A_DOWN_CLUSTER_2 0x005E0174#define VID_A_DOWN_CLUSTER_3 0x00B80175#define VID_A_DOWN_CLUSTER_4 0x01120176 177#define VID_B_DOWN_CLUSTER_1 0x016C0178#define VID_B_DOWN_CLUSTER_2 0x01C60179#define VID_B_DOWN_CLUSTER_3 0x02200180#define VID_B_DOWN_CLUSTER_4 0x027A0181 182#define VID_C_DOWN_CLUSTER_1 0x02D40183#define VID_C_DOWN_CLUSTER_2 0x032E0184#define VID_C_DOWN_CLUSTER_3 0x03880185#define VID_C_DOWN_CLUSTER_4 0x03E20186 187#define VID_D_DOWN_CLUSTER_1 0x043C0188#define VID_D_DOWN_CLUSTER_2 0x04960189#define VID_D_DOWN_CLUSTER_3 0x04F00190#define VID_D_DOWN_CLUSTER_4 0x054A0191 192#define VID_E_DOWN_CLUSTER_1 0x05a40193#define VID_E_DOWN_CLUSTER_2 0x05FE0194#define VID_E_DOWN_CLUSTER_3 0x06580195#define VID_E_DOWN_CLUSTER_4 0x06B20196 197#define VID_F_DOWN_CLUSTER_1 0x070C0198#define VID_F_DOWN_CLUSTER_2 0x07660199#define VID_F_DOWN_CLUSTER_3 0x07C00200#define VID_F_DOWN_CLUSTER_4 0x081A0201 202#define VID_G_DOWN_CLUSTER_1 0x08740203#define VID_G_DOWN_CLUSTER_2 0x08CE0204#define VID_G_DOWN_CLUSTER_3 0x09280205#define VID_G_DOWN_CLUSTER_4 0x09820206 207#define VID_H_DOWN_CLUSTER_1 0x09DC0208#define VID_H_DOWN_CLUSTER_2 0x0A360209#define VID_H_DOWN_CLUSTER_3 0x0A900210#define VID_H_DOWN_CLUSTER_4 0x0AEA0211 212#define AUD_A_DOWN_CLUSTER_1 0x0B500213#define AUD_A_DOWN_CLUSTER_2 0x0B580214#define AUD_A_DOWN_CLUSTER_3 0x0B600215 216#define AUD_B_DOWN_CLUSTER_1 0x0B680217#define AUD_B_DOWN_CLUSTER_2 0x0B700218#define AUD_B_DOWN_CLUSTER_3 0x0B780219 220#define AUD_C_DOWN_CLUSTER_1 0x0B800221#define AUD_C_DOWN_CLUSTER_2 0x0B880222#define AUD_C_DOWN_CLUSTER_3 0x0B900223 224#define AUD_D_DOWN_CLUSTER_1 0x0B980225#define AUD_D_DOWN_CLUSTER_2 0x0BA00226#define AUD_D_DOWN_CLUSTER_3 0x0BA80227 228#define TX_SRAM_POOL_FREE 0x0BB00229#define TX_SRAM_END 0x0C000230 231#define BYTES_TO_DWORDS(bcount) ((bcount) >> 2)232#define BYTES_TO_QWORDS(bcount) ((bcount) >> 3)233#define BYTES_TO_OWORDS(bcount) ((bcount) >> 4)234 235#define VID_IQ_SIZE_DW BYTES_TO_DWORDS(VID_IQ_SIZE)236#define VID_CDT_SIZE_QW BYTES_TO_QWORDS(VID_CDT_SIZE)237#define VID_CLUSTER_SIZE_OW BYTES_TO_OWORDS(VID_CLUSTER_SIZE)238 239#define AUDIO_IQ_SIZE_DW BYTES_TO_DWORDS(AUDIO_IQ_SIZE)240#define AUDIO_CDT_SIZE_QW BYTES_TO_QWORDS(AUDIO_CDT_SIZE)241#define AUDIO_CLUSTER_SIZE_QW BYTES_TO_QWORDS(AUDIO_CLUSTER_SIZE)242 243#define MBIF_IQ_SIZE_DW BYTES_TO_DWORDS(MBIF_IQ_SIZE)244#define MBIF_CDT_SIZE_QW BYTES_TO_QWORDS(MBIF_CDT_SIZE)245#define MBIF_CLUSTER_SIZE_OW BYTES_TO_OWORDS(MBIF_CLUSTER_SIZE)246 247#endif248