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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * cx88x-hw.h - CX2388x register offsets4 *5 * Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)6 * 2001 Michael Eskin7 * 2002 Yurij Sysoev <yurij@naturesoft.net>8 * 2003 Gerd Knorr <kraxel@bytesex.org>9 */10 11#ifndef _CX88_REG_H_12#define _CX88_REG_H_13 14/*15 * PCI IDs and config space16 */17 18#ifndef PCI_VENDOR_ID_CONEXANT19# define PCI_VENDOR_ID_CONEXANT 0x14F120#endif21#ifndef PCI_DEVICE_ID_CX2300_VID22# define PCI_DEVICE_ID_CX2300_VID 0x880023#endif24 25#define CX88X_DEVCTRL 0x4026#define CX88X_EN_TBFX 0x0227#define CX88X_EN_VSFX 0x0428 29/*30 * PCI controller registers31 */32 33/* Command and Status Register */34#define F0_CMD_STAT_MM 0x2f000435#define F1_CMD_STAT_MM 0x2f010436#define F2_CMD_STAT_MM 0x2f020437#define F3_CMD_STAT_MM 0x2f030438#define F4_CMD_STAT_MM 0x2f040439 40/* Device Control #1 */41#define F0_DEV_CNTRL1_MM 0x2f004042#define F1_DEV_CNTRL1_MM 0x2f014043#define F2_DEV_CNTRL1_MM 0x2f024044#define F3_DEV_CNTRL1_MM 0x2f034045#define F4_DEV_CNTRL1_MM 0x2f044046 47/* Device Control #1 */48#define F0_BAR0_MM 0x2f001049#define F1_BAR0_MM 0x2f011050#define F2_BAR0_MM 0x2f021051#define F3_BAR0_MM 0x2f031052#define F4_BAR0_MM 0x2f041053 54/*55 * DMA Controller registers56 */57 58#define MO_PDMA_STHRSH 0x200000 // Source threshold59#define MO_PDMA_STADRS 0x200004 // Source target address60#define MO_PDMA_SIADRS 0x200008 // Source internal address61#define MO_PDMA_SCNTRL 0x20000C // Source control62#define MO_PDMA_DTHRSH 0x200010 // Destination threshold63#define MO_PDMA_DTADRS 0x200014 // Destination target address64#define MO_PDMA_DIADRS 0x200018 // Destination internal address65#define MO_PDMA_DCNTRL 0x20001C // Destination control66#define MO_LD_SSID 0x200030 // Load subsystem ID67#define MO_DEV_CNTRL2 0x200034 // Device control68#define MO_PCI_INTMSK 0x200040 // PCI interrupt mask69#define MO_PCI_INTSTAT 0x200044 // PCI interrupt status70#define MO_PCI_INTMSTAT 0x200048 // PCI interrupt masked status71#define MO_VID_INTMSK 0x200050 // Video interrupt mask72#define MO_VID_INTSTAT 0x200054 // Video interrupt status73#define MO_VID_INTMSTAT 0x200058 // Video interrupt masked status74#define MO_VID_INTSSTAT 0x20005C // Video interrupt set status75#define MO_AUD_INTMSK 0x200060 // Audio interrupt mask76#define MO_AUD_INTSTAT 0x200064 // Audio interrupt status77#define MO_AUD_INTMSTAT 0x200068 // Audio interrupt masked status78#define MO_AUD_INTSSTAT 0x20006C // Audio interrupt set status79#define MO_TS_INTMSK 0x200070 // Transport stream interrupt mask80#define MO_TS_INTSTAT 0x200074 // Transport stream interrupt status81#define MO_TS_INTMSTAT 0x200078 // Transport stream interrupt mask status82#define MO_TS_INTSSTAT 0x20007C // Transport stream interrupt set status83#define MO_VIP_INTMSK 0x200080 // VIP interrupt mask84#define MO_VIP_INTSTAT 0x200084 // VIP interrupt status85#define MO_VIP_INTMSTAT 0x200088 // VIP interrupt masked status86#define MO_VIP_INTSSTAT 0x20008C // VIP interrupt set status87#define MO_GPHST_INTMSK 0x200090 // Host interrupt mask88#define MO_GPHST_INTSTAT 0x200094 // Host interrupt status89#define MO_GPHST_INTMSTAT 0x200098 // Host interrupt masked status90#define MO_GPHST_INTSSTAT 0x20009C // Host interrupt set status91 92// DMA Channels 1-6 belong to SPIPE93#define MO_DMA7_PTR1 0x300018 // {24}RW* DMA Current Ptr : Ch#794#define MO_DMA8_PTR1 0x30001C // {24}RW* DMA Current Ptr : Ch#895 96// DMA Channels 9-20 belong to SPIPE97#define MO_DMA21_PTR1 0x300080 // {24}R0* DMA Current Ptr : Ch#2198#define MO_DMA22_PTR1 0x300084 // {24}R0* DMA Current Ptr : Ch#2299#define MO_DMA23_PTR1 0x300088 // {24}R0* DMA Current Ptr : Ch#23100#define MO_DMA24_PTR1 0x30008C // {24}R0* DMA Current Ptr : Ch#24101#define MO_DMA25_PTR1 0x300090 // {24}R0* DMA Current Ptr : Ch#25102#define MO_DMA26_PTR1 0x300094 // {24}R0* DMA Current Ptr : Ch#26103#define MO_DMA27_PTR1 0x300098 // {24}R0* DMA Current Ptr : Ch#27104#define MO_DMA28_PTR1 0x30009C // {24}R0* DMA Current Ptr : Ch#28105#define MO_DMA29_PTR1 0x3000A0 // {24}R0* DMA Current Ptr : Ch#29106#define MO_DMA30_PTR1 0x3000A4 // {24}R0* DMA Current Ptr : Ch#30107#define MO_DMA31_PTR1 0x3000A8 // {24}R0* DMA Current Ptr : Ch#31108#define MO_DMA32_PTR1 0x3000AC // {24}R0* DMA Current Ptr : Ch#32109 110#define MO_DMA21_PTR2 0x3000C0 // {24}RW* DMA Tab Ptr : Ch#21111#define MO_DMA22_PTR2 0x3000C4 // {24}RW* DMA Tab Ptr : Ch#22112#define MO_DMA23_PTR2 0x3000C8 // {24}RW* DMA Tab Ptr : Ch#23113#define MO_DMA24_PTR2 0x3000CC // {24}RW* DMA Tab Ptr : Ch#24114#define MO_DMA25_PTR2 0x3000D0 // {24}RW* DMA Tab Ptr : Ch#25115#define MO_DMA26_PTR2 0x3000D4 // {24}RW* DMA Tab Ptr : Ch#26116#define MO_DMA27_PTR2 0x3000D8 // {24}RW* DMA Tab Ptr : Ch#27117#define MO_DMA28_PTR2 0x3000DC // {24}RW* DMA Tab Ptr : Ch#28118#define MO_DMA29_PTR2 0x3000E0 // {24}RW* DMA Tab Ptr : Ch#29119#define MO_DMA30_PTR2 0x3000E4 // {24}RW* DMA Tab Ptr : Ch#30120#define MO_DMA31_PTR2 0x3000E8 // {24}RW* DMA Tab Ptr : Ch#31121#define MO_DMA32_PTR2 0x3000EC // {24}RW* DMA Tab Ptr : Ch#32122 123#define MO_DMA21_CNT1 0x300100 // {11}RW* DMA Buffer Size : Ch#21124#define MO_DMA22_CNT1 0x300104 // {11}RW* DMA Buffer Size : Ch#22125#define MO_DMA23_CNT1 0x300108 // {11}RW* DMA Buffer Size : Ch#23126#define MO_DMA24_CNT1 0x30010C // {11}RW* DMA Buffer Size : Ch#24127#define MO_DMA25_CNT1 0x300110 // {11}RW* DMA Buffer Size : Ch#25128#define MO_DMA26_CNT1 0x300114 // {11}RW* DMA Buffer Size : Ch#26129#define MO_DMA27_CNT1 0x300118 // {11}RW* DMA Buffer Size : Ch#27130#define MO_DMA28_CNT1 0x30011C // {11}RW* DMA Buffer Size : Ch#28131#define MO_DMA29_CNT1 0x300120 // {11}RW* DMA Buffer Size : Ch#29132#define MO_DMA30_CNT1 0x300124 // {11}RW* DMA Buffer Size : Ch#30133#define MO_DMA31_CNT1 0x300128 // {11}RW* DMA Buffer Size : Ch#31134#define MO_DMA32_CNT1 0x30012C // {11}RW* DMA Buffer Size : Ch#32135 136#define MO_DMA21_CNT2 0x300140 // {11}RW* DMA Table Size : Ch#21137#define MO_DMA22_CNT2 0x300144 // {11}RW* DMA Table Size : Ch#22138#define MO_DMA23_CNT2 0x300148 // {11}RW* DMA Table Size : Ch#23139#define MO_DMA24_CNT2 0x30014C // {11}RW* DMA Table Size : Ch#24140#define MO_DMA25_CNT2 0x300150 // {11}RW* DMA Table Size : Ch#25141#define MO_DMA26_CNT2 0x300154 // {11}RW* DMA Table Size : Ch#26142#define MO_DMA27_CNT2 0x300158 // {11}RW* DMA Table Size : Ch#27143#define MO_DMA28_CNT2 0x30015C // {11}RW* DMA Table Size : Ch#28144#define MO_DMA29_CNT2 0x300160 // {11}RW* DMA Table Size : Ch#29145#define MO_DMA30_CNT2 0x300164 // {11}RW* DMA Table Size : Ch#30146#define MO_DMA31_CNT2 0x300168 // {11}RW* DMA Table Size : Ch#31147#define MO_DMA32_CNT2 0x30016C // {11}RW* DMA Table Size : Ch#32148 149/*150 * Video registers151 */152 153#define MO_VIDY_DMA 0x310000 // {64}RWp Video Y154#define MO_VIDU_DMA 0x310008 // {64}RWp Video U155#define MO_VIDV_DMA 0x310010 // {64}RWp Video V156#define MO_VBI_DMA 0x310018 // {64}RWp VBI (Vertical blanking interval)157 158#define MO_DEVICE_STATUS 0x310100159#define MO_INPUT_FORMAT 0x310104160#define MO_AGC_BURST 0x31010c161#define MO_CONTR_BRIGHT 0x310110162#define MO_UV_SATURATION 0x310114163#define MO_HUE 0x310118164#define MO_HTOTAL 0x310120165#define MO_HDELAY_EVEN 0x310124166#define MO_HDELAY_ODD 0x310128167#define MO_VDELAY_ODD 0x31012c168#define MO_VDELAY_EVEN 0x310130169#define MO_HACTIVE_EVEN 0x31013c170#define MO_HACTIVE_ODD 0x310140171#define MO_VACTIVE_EVEN 0x310144172#define MO_VACTIVE_ODD 0x310148173#define MO_HSCALE_EVEN 0x31014c174#define MO_HSCALE_ODD 0x310150175#define MO_VSCALE_EVEN 0x310154176#define MO_FILTER_EVEN 0x31015c177#define MO_VSCALE_ODD 0x310158178#define MO_FILTER_ODD 0x310160179#define MO_OUTPUT_FORMAT 0x310164180 181#define MO_PLL_REG 0x310168 // PLL register182#define MO_PLL_ADJ_CTRL 0x31016c // PLL adjust control register183#define MO_SCONV_REG 0x310170 // sample rate conversion register184#define MO_SCONV_FIFO 0x310174 // sample rate conversion fifo185#define MO_SUB_STEP 0x310178 // subcarrier step size186#define MO_SUB_STEP_DR 0x31017c // subcarrier step size for DR line187 188#define MO_CAPTURE_CTRL 0x310180 // capture control189#define MO_COLOR_CTRL 0x310184190#define MO_VBI_PACKET 0x310188 // vbi packet size / delay191#define MO_FIELD_COUNT 0x310190 // field counter192#define MO_VIP_CONFIG 0x310194193#define MO_VBOS_CONTROL 0x3101a8194 195#define MO_AGC_BACK_VBI 0x310200196#define MO_AGC_SYNC_TIP1 0x310208197 198#define MO_VIDY_GPCNT 0x31C020 // {16}RO Video Y general purpose counter199#define MO_VIDU_GPCNT 0x31C024 // {16}RO Video U general purpose counter200#define MO_VIDV_GPCNT 0x31C028 // {16}RO Video V general purpose counter201#define MO_VBI_GPCNT 0x31C02C // {16}RO VBI general purpose counter202#define MO_VIDY_GPCNTRL 0x31C030 // {2}WO Video Y general purpose control203#define MO_VIDU_GPCNTRL 0x31C034 // {2}WO Video U general purpose control204#define MO_VIDV_GPCNTRL 0x31C038 // {2}WO Video V general purpose control205#define MO_VBI_GPCNTRL 0x31C03C // {2}WO VBI general purpose counter206#define MO_VID_DMACNTRL 0x31C040 // {8}RW Video DMA control207#define MO_VID_XFR_STAT 0x31C044 // {1}RO Video transfer status208 209/*210 * audio registers211 */212 213#define MO_AUDD_DMA 0x320000 // {64}RWp Audio downstream214#define MO_AUDU_DMA 0x320008 // {64}RWp Audio upstream215#define MO_AUDR_DMA 0x320010 // {64}RWp Audio RDS (downstream)216#define MO_AUDD_GPCNT 0x32C020 // {16}RO Audio down general purpose counter217#define MO_AUDU_GPCNT 0x32C024 // {16}RO Audio up general purpose counter218#define MO_AUDR_GPCNT 0x32C028 // {16}RO Audio RDS general purpose counter219#define MO_AUDD_GPCNTRL 0x32C030 // {2}WO Audio down general purpose control220#define MO_AUDU_GPCNTRL 0x32C034 // {2}WO Audio up general purpose control221#define MO_AUDR_GPCNTRL 0x32C038 // {2}WO Audio RDS general purpose control222#define MO_AUD_DMACNTRL 0x32C040 // {6}RW Audio DMA control223#define MO_AUD_XFR_STAT 0x32C044 // {1}RO Audio transfer status224#define MO_AUDD_LNGTH 0x32C048 // {12}RW Audio down line length225#define MO_AUDR_LNGTH 0x32C04C // {12}RW Audio RDS line length226 227#define AUD_INIT 0x320100228#define AUD_INIT_LD 0x320104229#define AUD_SOFT_RESET 0x320108230#define AUD_I2SINPUTCNTL 0x320120231#define AUD_BAUDRATE 0x320124232#define AUD_I2SOUTPUTCNTL 0x320128233#define AAGC_HYST 0x320134234#define AAGC_GAIN 0x320138235#define AAGC_DEF 0x32013c236#define AUD_IIR1_0_SEL 0x320150237#define AUD_IIR1_0_SHIFT 0x320154238#define AUD_IIR1_1_SEL 0x320158239#define AUD_IIR1_1_SHIFT 0x32015c240#define AUD_IIR1_2_SEL 0x320160241#define AUD_IIR1_2_SHIFT 0x320164242#define AUD_IIR1_3_SEL 0x320168243#define AUD_IIR1_3_SHIFT 0x32016c244#define AUD_IIR1_4_SEL 0x320170245#define AUD_IIR1_4_SHIFT 0x32017c246#define AUD_IIR1_5_SEL 0x320180247#define AUD_IIR1_5_SHIFT 0x320184248#define AUD_IIR2_0_SEL 0x320190249#define AUD_IIR2_0_SHIFT 0x320194250#define AUD_IIR2_1_SEL 0x320198251#define AUD_IIR2_1_SHIFT 0x32019c252#define AUD_IIR2_2_SEL 0x3201a0253#define AUD_IIR2_2_SHIFT 0x3201a4254#define AUD_IIR2_3_SEL 0x3201a8255#define AUD_IIR2_3_SHIFT 0x3201ac256#define AUD_IIR3_0_SEL 0x3201c0257#define AUD_IIR3_0_SHIFT 0x3201c4258#define AUD_IIR3_1_SEL 0x3201c8259#define AUD_IIR3_1_SHIFT 0x3201cc260#define AUD_IIR3_2_SEL 0x3201d0261#define AUD_IIR3_2_SHIFT 0x3201d4262#define AUD_IIR4_0_SEL 0x3201e0263#define AUD_IIR4_0_SHIFT 0x3201e4264#define AUD_IIR4_1_SEL 0x3201e8265#define AUD_IIR4_1_SHIFT 0x3201ec266#define AUD_IIR4_2_SEL 0x3201f0267#define AUD_IIR4_2_SHIFT 0x3201f4268#define AUD_IIR4_0_CA0 0x320200269#define AUD_IIR4_0_CA1 0x320204270#define AUD_IIR4_0_CA2 0x320208271#define AUD_IIR4_0_CB0 0x32020c272#define AUD_IIR4_0_CB1 0x320210273#define AUD_IIR4_1_CA0 0x320214274#define AUD_IIR4_1_CA1 0x320218275#define AUD_IIR4_1_CA2 0x32021c276#define AUD_IIR4_1_CB0 0x320220277#define AUD_IIR4_1_CB1 0x320224278#define AUD_IIR4_2_CA0 0x320228279#define AUD_IIR4_2_CA1 0x32022c280#define AUD_IIR4_2_CA2 0x320230281#define AUD_IIR4_2_CB0 0x320234282#define AUD_IIR4_2_CB1 0x320238283#define AUD_HP_MD_IIR4_1 0x320250284#define AUD_HP_PROG_IIR4_1 0x320254285#define AUD_FM_MODE_ENABLE 0x320258286#define AUD_POLY0_DDS_CONSTANT 0x320270287#define AUD_DN0_FREQ 0x320274288#define AUD_DN1_FREQ 0x320278289#define AUD_DN1_FREQ_SHIFT 0x32027c290#define AUD_DN1_AFC 0x320280291#define AUD_DN1_SRC_SEL 0x320284292#define AUD_DN1_SHFT 0x320288293#define AUD_DN2_FREQ 0x32028c294#define AUD_DN2_FREQ_SHIFT 0x320290295#define AUD_DN2_AFC 0x320294296#define AUD_DN2_SRC_SEL 0x320298297#define AUD_DN2_SHFT 0x32029c298#define AUD_CRDC0_SRC_SEL 0x320300299#define AUD_CRDC0_SHIFT 0x320304300#define AUD_CORDIC_SHIFT_0 0x320308301#define AUD_CRDC1_SRC_SEL 0x32030c302#define AUD_CRDC1_SHIFT 0x320310303#define AUD_CORDIC_SHIFT_1 0x320314304#define AUD_DCOC_0_SRC 0x320320305#define AUD_DCOC0_SHIFT 0x320324306#define AUD_DCOC_0_SHIFT_IN0 0x320328307#define AUD_DCOC_0_SHIFT_IN1 0x32032c308#define AUD_DCOC_1_SRC 0x320330309#define AUD_DCOC1_SHIFT 0x320334310#define AUD_DCOC_1_SHIFT_IN0 0x320338311#define AUD_DCOC_1_SHIFT_IN1 0x32033c312#define AUD_DCOC_2_SRC 0x320340313#define AUD_DCOC2_SHIFT 0x320344314#define AUD_DCOC_2_SHIFT_IN0 0x320348315#define AUD_DCOC_2_SHIFT_IN1 0x32034c316#define AUD_DCOC_PASS_IN 0x320350317#define AUD_PDET_SRC 0x320370318#define AUD_PDET_SHIFT 0x320374319#define AUD_PILOT_BQD_1_K0 0x320380320#define AUD_PILOT_BQD_1_K1 0x320384321#define AUD_PILOT_BQD_1_K2 0x320388322#define AUD_PILOT_BQD_1_K3 0x32038c323#define AUD_PILOT_BQD_1_K4 0x320390324#define AUD_PILOT_BQD_2_K0 0x320394325#define AUD_PILOT_BQD_2_K1 0x320398326#define AUD_PILOT_BQD_2_K2 0x32039c327#define AUD_PILOT_BQD_2_K3 0x3203a0328#define AUD_PILOT_BQD_2_K4 0x3203a4329#define AUD_THR_FR 0x3203c0330#define AUD_X_PROG 0x3203c4331#define AUD_Y_PROG 0x3203c8332#define AUD_HARMONIC_MULT 0x3203cc333#define AUD_C1_UP_THR 0x3203d0334#define AUD_C1_LO_THR 0x3203d4335#define AUD_C2_UP_THR 0x3203d8336#define AUD_C2_LO_THR 0x3203dc337#define AUD_PLL_EN 0x320400338#define AUD_PLL_SRC 0x320404339#define AUD_PLL_SHIFT 0x320408340#define AUD_PLL_IF_SEL 0x32040c341#define AUD_PLL_IF_SHIFT 0x320410342#define AUD_BIQUAD_PLL_K0 0x320414343#define AUD_BIQUAD_PLL_K1 0x320418344#define AUD_BIQUAD_PLL_K2 0x32041c345#define AUD_BIQUAD_PLL_K3 0x320420346#define AUD_BIQUAD_PLL_K4 0x320424347#define AUD_DEEMPH0_SRC_SEL 0x320440348#define AUD_DEEMPH0_SHIFT 0x320444349#define AUD_DEEMPH0_G0 0x320448350#define AUD_DEEMPH0_A0 0x32044c351#define AUD_DEEMPH0_B0 0x320450352#define AUD_DEEMPH0_A1 0x320454353#define AUD_DEEMPH0_B1 0x320458354#define AUD_DEEMPH1_SRC_SEL 0x32045c355#define AUD_DEEMPH1_SHIFT 0x320460356#define AUD_DEEMPH1_G0 0x320464357#define AUD_DEEMPH1_A0 0x320468358#define AUD_DEEMPH1_B0 0x32046c359#define AUD_DEEMPH1_A1 0x320470360#define AUD_DEEMPH1_B1 0x320474361#define AUD_OUT0_SEL 0x320490362#define AUD_OUT0_SHIFT 0x320494363#define AUD_OUT1_SEL 0x320498364#define AUD_OUT1_SHIFT 0x32049c365#define AUD_RDSI_SEL 0x3204a0366#define AUD_RDSI_SHIFT 0x3204a4367#define AUD_RDSQ_SEL 0x3204a8368#define AUD_RDSQ_SHIFT 0x3204ac369#define AUD_DBX_IN_GAIN 0x320500370#define AUD_DBX_WBE_GAIN 0x320504371#define AUD_DBX_SE_GAIN 0x320508372#define AUD_DBX_RMS_WBE 0x32050c373#define AUD_DBX_RMS_SE 0x320510374#define AUD_DBX_SE_BYPASS 0x320514375#define AUD_FAWDETCTL 0x320530376#define AUD_FAWDETWINCTL 0x320534377#define AUD_DEEMPHGAIN_R 0x320538378#define AUD_DEEMPHNUMER1_R 0x32053c379#define AUD_DEEMPHNUMER2_R 0x320540380#define AUD_DEEMPHDENOM1_R 0x320544381#define AUD_DEEMPHDENOM2_R 0x320548382#define AUD_ERRLOGPERIOD_R 0x32054c383#define AUD_ERRINTRPTTHSHLD1_R 0x320550384#define AUD_ERRINTRPTTHSHLD2_R 0x320554385#define AUD_ERRINTRPTTHSHLD3_R 0x320558386#define AUD_NICAM_STATUS1 0x32055c387#define AUD_NICAM_STATUS2 0x320560388#define AUD_ERRLOG1 0x320564389#define AUD_ERRLOG2 0x320568390#define AUD_ERRLOG3 0x32056c391#define AUD_DAC_BYPASS_L 0x320580392#define AUD_DAC_BYPASS_R 0x320584393#define AUD_DAC_BYPASS_CTL 0x320588394#define AUD_CTL 0x32058c395#define AUD_STATUS 0x320590396#define AUD_VOL_CTL 0x320594397#define AUD_BAL_CTL 0x320598398#define AUD_START_TIMER 0x3205b0399#define AUD_MODE_CHG_TIMER 0x3205b4400#define AUD_POLYPH80SCALEFAC 0x3205b8401#define AUD_DMD_RA_DDS 0x3205bc402#define AUD_I2S_RA_DDS 0x3205c0403#define AUD_RATE_THRES_DMD 0x3205d0404#define AUD_RATE_THRES_I2S 0x3205d4405#define AUD_RATE_ADJ1 0x3205d8406#define AUD_RATE_ADJ2 0x3205dc407#define AUD_RATE_ADJ3 0x3205e0408#define AUD_RATE_ADJ4 0x3205e4409#define AUD_RATE_ADJ5 0x3205e8410#define AUD_APB_IN_RATE_ADJ 0x3205ec411#define AUD_I2SCNTL 0x3205ec412#define AUD_PHASE_FIX_CTL 0x3205f0413#define AUD_PLL_PRESCALE 0x320600414#define AUD_PLL_DDS 0x320604415#define AUD_PLL_INT 0x320608416#define AUD_PLL_FRAC 0x32060c417#define AUD_PLL_JTAG 0x320620418#define AUD_PLL_SPMP 0x320624419#define AUD_AFE_12DB_EN 0x320628420 421// Audio QAM Register Addresses422#define AUD_PDF_DDS_CNST_BYTE2 0x320d01423#define AUD_PDF_DDS_CNST_BYTE1 0x320d02424#define AUD_PDF_DDS_CNST_BYTE0 0x320d03425#define AUD_PHACC_FREQ_8MSB 0x320d2a426#define AUD_PHACC_FREQ_8LSB 0x320d2b427#define AUD_QAM_MODE 0x320d04428 429/*430 * transport stream registers431 */432 433#define MO_TS_DMA 0x330000 // {64}RWp Transport stream downstream434#define MO_TS_GPCNT 0x33C020 // {16}RO TS general purpose counter435#define MO_TS_GPCNTRL 0x33C030 // {2}WO TS general purpose control436#define MO_TS_DMACNTRL 0x33C040 // {6}RW TS DMA control437#define MO_TS_XFR_STAT 0x33C044 // {1}RO TS transfer status438#define MO_TS_LNGTH 0x33C048 // {12}RW TS line length439 440#define TS_HW_SOP_CNTRL 0x33C04C441#define TS_GEN_CNTRL 0x33C050442#define TS_BD_PKT_STAT 0x33C054443#define TS_SOP_STAT 0x33C058444#define TS_FIFO_OVFL_STAT 0x33C05C445#define TS_VALERR_CNTRL 0x33C060446 447/*448 * VIP registers449 */450 451#define MO_VIPD_DMA 0x340000 // {64}RWp VIP downstream452#define MO_VIPU_DMA 0x340008 // {64}RWp VIP upstream453#define MO_VIPD_GPCNT 0x34C020 // {16}RO VIP down general purpose counter454#define MO_VIPU_GPCNT 0x34C024 // {16}RO VIP up general purpose counter455#define MO_VIPD_GPCNTRL 0x34C030 // {2}WO VIP down general purpose control456#define MO_VIPU_GPCNTRL 0x34C034 // {2}WO VIP up general purpose control457#define MO_VIP_DMACNTRL 0x34C040 // {6}RW VIP DMA control458#define MO_VIP_XFR_STAT 0x34C044 // {1}RO VIP transfer status459#define MO_VIP_CFG 0x340048 // VIP configuration460#define MO_VIPU_CNTRL 0x34004C // VIP upstream control #1461#define MO_VIPD_CNTRL 0x340050 // VIP downstream control #2462#define MO_VIPD_LNGTH 0x340054 // VIP downstream line length463#define MO_VIP_BRSTLN 0x340058 // VIP burst length464#define MO_VIP_INTCNTRL 0x34C05C // VIP Interrupt Control465#define MO_VIP_XFTERM 0x340060 // VIP transfer terminate466 467/*468 * misc registers469 */470 471#define MO_M2M_DMA 0x350000 // {64}RWp Mem2Mem DMA Bfr472#define MO_GP0_IO 0x350010 // {32}RW* GPIOoutput enablesdata I/O473#define MO_GP1_IO 0x350014 // {32}RW* GPIOoutput enablesdata I/O474#define MO_GP2_IO 0x350018 // {32}RW* GPIOoutput enablesdata I/O475#define MO_GP3_IO 0x35001C // {32}RW* GPIO Mode/Ctrloutput enables476#define MO_GPIO 0x350020 // {32}RW* GPIO I2C Ctrldata I/O477#define MO_GPOE 0x350024 // {32}RW GPIO I2C Ctrloutput enables478#define MO_GP_ISM 0x350028 // {16}WO GPIO Intr Sens/Pol479 480#define MO_PLL_B 0x35C008 // {32}RW* PLL Control for ASB bus clks481#define MO_M2M_CNT 0x35C024 // {32}RW Mem2Mem DMA Cnt482#define MO_M2M_XSUM 0x35C028 // {32}RO M2M XOR-Checksum483#define MO_CRC 0x35C02C // {16}RW CRC16 init/result484#define MO_CRC_D 0x35C030 // {32}WO CRC16 new data in485#define MO_TM_CNT_LDW 0x35C034 // {32}RO Timer : Counter low dword486#define MO_TM_CNT_UW 0x35C038 // {16}RO Timer : Counter high word487#define MO_TM_LMT_LDW 0x35C03C // {32}RW Timer : Limit low dword488#define MO_TM_LMT_UW 0x35C040 // {32}RW Timer : Limit high word489#define MO_PINMUX_IO 0x35C044 // {8}RW Pin Mux Control490#define MO_TSTSEL_IO 0x35C048 // {2}RW Pin Mux Control491#define MO_AFECFG_IO 0x35C04C // AFE configuration reg492#define MO_DDS_IO 0x35C050 // DDS Increment reg493#define MO_DDSCFG_IO 0x35C054 // DDS Configuration reg494#define MO_SAMPLE_IO 0x35C058 // IRIn sample reg495#define MO_SRST_IO 0x35C05C // Output system reset reg496 497#define MO_INT1_MSK 0x35C060 // DMA RISC interrupt mask498#define MO_INT1_STAT 0x35C064 // DMA RISC interrupt status499#define MO_INT1_MSTAT 0x35C068 // DMA RISC interrupt masked status500 501/*502 * i2c bus registers503 */504 505#define MO_I2C 0x368000 // I2C data/control506#define MO_I2C_DIV (0xf<<4)507#define MO_I2C_SYNC (1<<3)508#define MO_I2C_W3B (1<<2)509#define MO_I2C_SCL (1<<1)510#define MO_I2C_SDA (1<<0)511 512 513/*514 * general purpose host registers515 *516 * FIXME: tyops? s/0x35/0x38/ ??517 */518 519#define MO_GPHSTD_DMA 0x350000 // {64}RWp Host downstream520#define MO_GPHSTU_DMA 0x350008 // {64}RWp Host upstream521#define MO_GPHSTU_CNTRL 0x380048 // Host upstream control #1522#define MO_GPHSTD_CNTRL 0x38004C // Host downstream control #2523#define MO_GPHSTD_LNGTH 0x380050 // Host downstream line length524#define MO_GPHST_WSC 0x380054 // Host wait state control525#define MO_GPHST_XFR 0x380058 // Host transfer control526#define MO_GPHST_WDTH 0x38005C // Host interface width527#define MO_GPHST_HDSHK 0x380060 // Host peripheral handshake528#define MO_GPHST_MUX16 0x380064 // Host muxed 16-bit transfer parameters529#define MO_GPHST_MODE 0x380068 // Host mode select530 531#define MO_GPHSTD_GPCNT 0x35C020 // Host down general purpose counter532#define MO_GPHSTU_GPCNT 0x35C024 // Host up general purpose counter533#define MO_GPHSTD_GPCNTRL 0x38C030 // Host down general purpose control534#define MO_GPHSTU_GPCNTRL 0x38C034 // Host up general purpose control535#define MO_GPHST_DMACNTRL 0x38C040 // Host DMA control536#define MO_GPHST_XFR_STAT 0x38C044 // Host transfer status537#define MO_GPHST_SOFT_RST 0x38C06C // Host software reset538 539/*540 * RISC instructions541 */542 543#define RISC_SYNC 0x80000000544#define RISC_SYNC_ODD 0x80000000545#define RISC_SYNC_EVEN 0x80000200546#define RISC_RESYNC 0x80008000547#define RISC_RESYNC_ODD 0x80008000548#define RISC_RESYNC_EVEN 0x80008200549#define RISC_WRITE 0x10000000550#define RISC_WRITEC 0x50000000551#define RISC_READ 0x90000000552#define RISC_READC 0xA0000000553#define RISC_JUMP 0x70000000554#define RISC_SKIP 0x20000000555#define RISC_WRITERM 0xB0000000556#define RISC_WRITECM 0xC0000000557#define RISC_WRITECR 0xD0000000558#define RISC_IMM 0x00000001559 560#define RISC_SOL 0x08000000561#define RISC_EOL 0x04000000562 563#define RISC_IRQ2 0x02000000564#define RISC_IRQ1 0x01000000565 566#define RISC_CNT_NONE 0x00000000567#define RISC_CNT_INC 0x00010000568#define RISC_CNT_RSVR 0x00020000569#define RISC_CNT_RESET 0x00030000570#define RISC_JMP_SRP 0x01571 572/*573 * various constants574 */575 576// DMA577/* Interrupt mask/status */578#define PCI_INT_VIDINT (1 << 0)579#define PCI_INT_AUDINT (1 << 1)580#define PCI_INT_TSINT (1 << 2)581#define PCI_INT_VIPINT (1 << 3)582#define PCI_INT_HSTINT (1 << 4)583#define PCI_INT_TM1INT (1 << 5)584#define PCI_INT_SRCDMAINT (1 << 6)585#define PCI_INT_DSTDMAINT (1 << 7)586#define PCI_INT_RISC_RD_BERRINT (1 << 10)587#define PCI_INT_RISC_WR_BERRINT (1 << 11)588#define PCI_INT_BRDG_BERRINT (1 << 12)589#define PCI_INT_SRC_DMA_BERRINT (1 << 13)590#define PCI_INT_DST_DMA_BERRINT (1 << 14)591#define PCI_INT_IPB_DMA_BERRINT (1 << 15)592#define PCI_INT_I2CDONE (1 << 16)593#define PCI_INT_I2CRACK (1 << 17)594#define PCI_INT_IR_SMPINT (1 << 18)595#define PCI_INT_GPIO_INT0 (1 << 19)596#define PCI_INT_GPIO_INT1 (1 << 20)597 598#define SEL_BTSC 0x01599#define SEL_EIAJ 0x02600#define SEL_A2 0x04601#define SEL_SAP 0x08602#define SEL_NICAM 0x10603#define SEL_FMRADIO 0x20604 605// AUD_CTL606#define AUD_INT_DN_RISCI1 (1 << 0)607#define AUD_INT_UP_RISCI1 (1 << 1)608#define AUD_INT_RDS_DN_RISCI1 (1 << 2)609#define AUD_INT_DN_RISCI2 (1 << 4) /* yes, 3 is skipped */610#define AUD_INT_UP_RISCI2 (1 << 5)611#define AUD_INT_RDS_DN_RISCI2 (1 << 6)612#define AUD_INT_DN_SYNC (1 << 12)613#define AUD_INT_UP_SYNC (1 << 13)614#define AUD_INT_RDS_DN_SYNC (1 << 14)615#define AUD_INT_OPC_ERR (1 << 16)616#define AUD_INT_BER_IRQ (1 << 20)617#define AUD_INT_MCHG_IRQ (1 << 21)618 619#define EN_BTSC_FORCE_MONO 0620#define EN_BTSC_FORCE_STEREO 1621#define EN_BTSC_FORCE_SAP 2622#define EN_BTSC_AUTO_STEREO 3623#define EN_BTSC_AUTO_SAP 4624 625#define EN_A2_FORCE_MONO1 8626#define EN_A2_FORCE_MONO2 9627#define EN_A2_FORCE_STEREO 10628#define EN_A2_AUTO_MONO2 11629#define EN_A2_AUTO_STEREO 12630 631#define EN_EIAJ_FORCE_MONO1 16632#define EN_EIAJ_FORCE_MONO2 17633#define EN_EIAJ_FORCE_STEREO 18634#define EN_EIAJ_AUTO_MONO2 19635#define EN_EIAJ_AUTO_STEREO 20636 637#define EN_NICAM_FORCE_MONO1 32638#define EN_NICAM_FORCE_MONO2 33639#define EN_NICAM_FORCE_STEREO 34640#define EN_NICAM_AUTO_MONO2 35641#define EN_NICAM_AUTO_STEREO 36642 643#define EN_FMRADIO_FORCE_MONO 24644#define EN_FMRADIO_FORCE_STEREO 25645#define EN_FMRADIO_AUTO_STEREO 26646 647#define EN_NICAM_AUTO_FALLBACK 0x00000040648#define EN_FMRADIO_EN_RDS 0x00000200649#define EN_NICAM_TRY_AGAIN_BIT 0x00000400650#define EN_DAC_ENABLE 0x00001000651#define EN_I2SOUT_ENABLE 0x00002000652#define EN_I2SIN_STR2DAC 0x00004000653#define EN_I2SIN_ENABLE 0x00008000654 655#define EN_DMTRX_SUMDIFF (0 << 7)656#define EN_DMTRX_SUMR (1 << 7)657#define EN_DMTRX_LR (2 << 7)658#define EN_DMTRX_MONO (3 << 7)659#define EN_DMTRX_BYPASS (1 << 11)660 661// Video662#define VID_CAPTURE_CONTROL 0x310180663 664#define CX23880_CAP_CTL_CAPTURE_VBI_ODD (1<<3)665#define CX23880_CAP_CTL_CAPTURE_VBI_EVEN (1<<2)666#define CX23880_CAP_CTL_CAPTURE_ODD (1<<1)667#define CX23880_CAP_CTL_CAPTURE_EVEN (1<<0)668 669#define VideoInputMux0 0x0670#define VideoInputMux1 0x1671#define VideoInputMux2 0x2672#define VideoInputMux3 0x3673#define VideoInputTuner 0x0674#define VideoInputComposite 0x1675#define VideoInputSVideo 0x2676#define VideoInputOther 0x3677 678#define Xtal0 0x1679#define Xtal1 0x2680#define XtalAuto 0x3681 682#define VideoFormatAuto 0x0683#define VideoFormatNTSC 0x1684#define VideoFormatNTSCJapan 0x2685#define VideoFormatNTSC443 0x3686#define VideoFormatPAL 0x4687#define VideoFormatPALB 0x4688#define VideoFormatPALD 0x4689#define VideoFormatPALG 0x4690#define VideoFormatPALH 0x4691#define VideoFormatPALI 0x4692#define VideoFormatPALBDGHI 0x4693#define VideoFormatPALM 0x5694#define VideoFormatPALN 0x6695#define VideoFormatPALNC 0x7696#define VideoFormatPAL60 0x8697#define VideoFormatSECAM 0x9698 699#define VideoFormatAuto27MHz 0x10700#define VideoFormatNTSC27MHz 0x11701#define VideoFormatNTSCJapan27MHz 0x12702#define VideoFormatNTSC44327MHz 0x13703#define VideoFormatPAL27MHz 0x14704#define VideoFormatPALB27MHz 0x14705#define VideoFormatPALD27MHz 0x14706#define VideoFormatPALG27MHz 0x14707#define VideoFormatPALH27MHz 0x14708#define VideoFormatPALI27MHz 0x14709#define VideoFormatPALBDGHI27MHz 0x14710#define VideoFormatPALM27MHz 0x15711#define VideoFormatPALN27MHz 0x16712#define VideoFormatPALNC27MHz 0x17713#define VideoFormatPAL6027MHz 0x18714#define VideoFormatSECAM27MHz 0x19715 716#define NominalUSECAM 0x87717#define NominalVSECAM 0x85718#define NominalUNTSC 0xFE719#define NominalVNTSC 0xB4720 721#define NominalContrast 0xD8722 723#define HFilterAutoFormat 0x0724#define HFilterCIF 0x1725#define HFilterQCIF 0x2726#define HFilterICON 0x3727 728#define VFilter2TapInterpolate 0729#define VFilter3TapInterpolate 1730#define VFilter4TapInterpolate 2731#define VFilter5TapInterpolate 3732#define VFilter2TapNoInterpolate 4733#define VFilter3TapNoInterpolate 5734#define VFilter4TapNoInterpolate 6735#define VFilter5TapNoInterpolate 7736 737#define ColorFormatRGB32 0x0000738#define ColorFormatRGB24 0x0011739#define ColorFormatRGB16 0x0022740#define ColorFormatRGB15 0x0033741#define ColorFormatYUY2 0x0044742#define ColorFormatBTYUV 0x0055743#define ColorFormatY8 0x0066744#define ColorFormatRGB8 0x0077745#define ColorFormatPL422 0x0088746#define ColorFormatPL411 0x0099747#define ColorFormatYUV12 0x00AA748#define ColorFormatYUV9 0x00BB749#define ColorFormatRAW 0x00EE750#define ColorFormatBSWAP 0x0300751#define ColorFormatWSWAP 0x0c00752#define ColorFormatEvenMask 0x050f753#define ColorFormatOddMask 0x0af0754#define ColorFormatGamma 0x1000755 756#define Interlaced 0x1757#define NonInterlaced 0x0758 759#define FieldEven 0x1760#define FieldOdd 0x0761 762#define TGReadWriteMode 0x0763#define TGEnableMode 0x1764 765#define DV_CbAlign 0x0766#define DV_Y0Align 0x1767#define DV_CrAlign 0x2768#define DV_Y1Align 0x3769 770#define DVF_Analog 0x0771#define DVF_CCIR656 0x1772#define DVF_ByteStream 0x2773#define DVF_ExtVSYNC 0x4774#define DVF_ExtField 0x5775 776#define CHANNEL_VID_Y 0x1777#define CHANNEL_VID_U 0x2778#define CHANNEL_VID_V 0x3779#define CHANNEL_VID_VBI 0x4780#define CHANNEL_AUD_DN 0x5781#define CHANNEL_AUD_UP 0x6782#define CHANNEL_AUD_RDS_DN 0x7783#define CHANNEL_MPEG_DN 0x8784#define CHANNEL_VIP_DN 0x9785#define CHANNEL_VIP_UP 0xA786#define CHANNEL_HOST_DN 0xB787#define CHANNEL_HOST_UP 0xC788#define CHANNEL_FIRST 0x1789#define CHANNEL_LAST 0xC790 791#define GP_COUNT_CONTROL_NONE 0x0792#define GP_COUNT_CONTROL_INC 0x1793#define GP_COUNT_CONTROL_RESERVED 0x2794#define GP_COUNT_CONTROL_RESET 0x3795 796#define PLL_PRESCALE_BY_2 2797#define PLL_PRESCALE_BY_3 3798#define PLL_PRESCALE_BY_4 4799#define PLL_PRESCALE_BY_5 5800 801#define HLNotchFilter4xFsc 0802#define HLNotchFilterSquare 1803#define HLNotchFilter135NTSC 2804#define HLNotchFilter135PAL 3805 806#define NTSC_8x_SUB_CARRIER 28.63636E6807#define PAL_8x_SUB_CARRIER 35.46895E6808 809// Default analog settings810#define DEFAULT_HUE_NTSC 0x00811#define DEFAULT_BRIGHTNESS_NTSC 0x00812#define DEFAULT_CONTRAST_NTSC 0x39813#define DEFAULT_SAT_U_NTSC 0x7F814#define DEFAULT_SAT_V_NTSC 0x5A815 816#endif /* _CX88_REG_H_ */817