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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/***************************************************************************3 * Copyright (C) 2006-2010 by Marin Mitov *4 * mitov@issp.bas.bg *5 * *6 * *7 ***************************************************************************/8 9/* DT3155 header file */10#ifndef _DT3155_H_11#define _DT3155_H_12 13#include <linux/pci.h>14#include <linux/interrupt.h>15#include <media/v4l2-device.h>16#include <media/v4l2-dev.h>17#include <media/videobuf2-v4l2.h>18 19#define DT3155_NAME "dt3155"20#define DT3155_VER_MAJ 221#define DT3155_VER_MIN 022#define DT3155_VER_EXT 023#define DT3155_VERSION __stringify(DT3155_VER_MAJ) "." \24 __stringify(DT3155_VER_MIN) "." \25 __stringify(DT3155_VER_EXT)26 27/* DT3155 Base Register offsets (memory mapped) */28#define EVEN_DMA_START 0x0029#define ODD_DMA_START 0x0C30#define EVEN_DMA_STRIDE 0x1831#define ODD_DMA_STRIDE 0x2432#define EVEN_PIXEL_FMT 0x3033#define ODD_PIXEL_FMT 0x3434#define FIFO_TRIGGER 0x3835#define XFER_MODE 0x3C36#define CSR1 0x4037#define RETRY_WAIT_CNT 0x4438#define INT_CSR 0x4839#define EVEN_FLD_MASK 0x4C40#define ODD_FLD_MASK 0x5041#define MASK_LENGTH 0x5442#define FIFO_FLAG_CNT 0x5843#define IIC_CLK_DUR 0x5C44#define IIC_CSR1 0x6045#define IIC_CSR2 0x6446 47/* DT3155 Internal Registers indexes (i2c/IIC mapped) */48#define CSR2 0x1049#define EVEN_CSR 0x1150#define ODD_CSR 0x1251#define CONFIG 0x1352#define DT_ID 0x1F53#define X_CLIP_START 0x2054#define Y_CLIP_START 0x2255#define X_CLIP_END 0x2456#define Y_CLIP_END 0x2657#define AD_ADDR 0x3058#define AD_LUT 0x3159#define AD_CMD 0x3260#define DIG_OUT 0x4061#define PM_LUT_ADDR 0x5062#define PM_LUT_DATA 0x5163 64/* AD command register values */65#define AD_CMD_REG 0x0066#define AD_POS_REF 0x0167#define AD_NEG_REF 0x0268 69/* CSR1 bit masks */70#define RANGE_EN 0x0000800071#define CRPT_DIS 0x0000400072#define ADDR_ERR_ODD 0x0000080073#define ADDR_ERR_EVEN 0x0000040074#define FLD_CRPT_ODD 0x0000020075#define FLD_CRPT_EVEN 0x0000010076#define FIFO_EN 0x0000008077#define SRST 0x0000004078#define FLD_DN_ODD 0x0000002079#define FLD_DN_EVEN 0x0000001080/* These should not be used.81 * Use CAP_CONT_ODD/EVEN instead82#define CAP_SNGL_ODD 0x0000000883#define CAP_SNGL_EVEN 0x0000000484*/85#define CAP_CONT_ODD 0x0000000286#define CAP_CONT_EVEN 0x0000000187 88/* INT_CSR bit masks */89#define FLD_START_EN 0x0000040090#define FLD_END_ODD_EN 0x0000020091#define FLD_END_EVEN_EN 0x0000010092#define FLD_START 0x0000000493#define FLD_END_ODD 0x0000000294#define FLD_END_EVEN 0x0000000195 96/* IIC_CSR1 bit masks */97#define DIRECT_ABORT 0x0000020098 99/* IIC_CSR2 bit masks */100#define NEW_CYCLE 0x01000000101#define DIR_RD 0x00010000102#define IIC_READ 0x01010000103#define IIC_WRITE 0x01000000104 105/* CSR2 bit masks */106#define DISP_PASS 0x40107#define BUSY_ODD 0x20108#define BUSY_EVEN 0x10109#define SYNC_PRESENT 0x08110#define VT_50HZ 0x04111#define SYNC_SNTL 0x02112#define CHROM_FILT 0x01113#define VT_60HZ 0x00114 115/* CSR_EVEN/ODD bit masks */116#define CSR_ERROR 0x04117#define CSR_SNGL 0x02118#define CSR_DONE 0x01119 120/* CONFIG bit masks */121#define PM_LUT_PGM 0x80122#define PM_LUT_SEL 0x40123#define CLIP_EN 0x20124#define HSCALE_EN 0x10125#define EXT_TRIG_UP 0x0C126#define EXT_TRIG_DOWN 0x04127#define ACQ_MODE_NEXT 0x02128#define ACQ_MODE_ODD 0x01129#define ACQ_MODE_EVEN 0x00130 131/* AD_CMD bit masks */132#define VIDEO_CNL_1 0x00133#define VIDEO_CNL_2 0x40134#define VIDEO_CNL_3 0x80135#define VIDEO_CNL_4 0xC0136#define SYNC_CNL_1 0x00137#define SYNC_CNL_2 0x10138#define SYNC_CNL_3 0x20139#define SYNC_CNL_4 0x30140#define SYNC_LVL_1 0x00141#define SYNC_LVL_2 0x04142#define SYNC_LVL_3 0x08143#define SYNC_LVL_4 0x0C144 145/* DT3155 identificator */146#define DT3155_ID 0x20147 148/* per board private data structure */149/**150 * struct dt3155_priv - private data structure151 *152 * @v4l2_dev: v4l2_device structure153 * @vdev: video_device structure154 * @pdev: pointer to pci_dev structure155 * @vidq: vb2_queue structure156 * @curr_buf: pointer to curren buffer157 * @mux: mutex to protect the instance158 * @dmaq: queue for dma buffers159 * @lock: spinlock for dma queue160 * @std: input standard161 * @width: frame width162 * @height: frame height163 * @input: current input164 * @sequence: frame counter165 * @regs: local copy of mmio base register166 * @csr2: local copy of csr2 register167 * @config: local copy of config register168 */169struct dt3155_priv {170 struct v4l2_device v4l2_dev;171 struct video_device vdev;172 struct pci_dev *pdev;173 struct vb2_queue vidq;174 struct vb2_v4l2_buffer *curr_buf;175 struct mutex mux;176 struct list_head dmaq;177 spinlock_t lock;178 v4l2_std_id std;179 unsigned width, height;180 unsigned input;181 unsigned int sequence;182 void __iomem *regs;183 u8 csr2, config;184};185 186#endif /* _DT3155_H_ */187