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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (C) 2013--2024 Intel Corporation */3 4#ifndef IPU6_FW_ISYS_H5#define IPU6_FW_ISYS_H6 7#include <linux/types.h>8 9struct device;10struct ipu6_isys;11 12/* Max number of Input/Output Pins */13#define IPU6_MAX_IPINS 414 15#define IPU6_MAX_OPINS ((IPU6_MAX_IPINS) + 1)16 17#define IPU6_STREAM_ID_MAX 1618#define IPU6_NONSECURE_STREAM_ID_MAX 1219#define IPU6_DEV_SEND_QUEUE_SIZE (IPU6_STREAM_ID_MAX)20#define IPU6_NOF_SRAM_BLOCKS_MAX (IPU6_STREAM_ID_MAX)21#define IPU6_N_MAX_MSG_SEND_QUEUES (IPU6_STREAM_ID_MAX)22#define IPU6SE_STREAM_ID_MAX 823#define IPU6SE_NONSECURE_STREAM_ID_MAX 424#define IPU6SE_DEV_SEND_QUEUE_SIZE (IPU6SE_STREAM_ID_MAX)25#define IPU6SE_NOF_SRAM_BLOCKS_MAX (IPU6SE_STREAM_ID_MAX)26#define IPU6SE_N_MAX_MSG_SEND_QUEUES (IPU6SE_STREAM_ID_MAX)27 28/* Single return queue for all streams/commands type */29#define IPU6_N_MAX_MSG_RECV_QUEUES 130/* Single device queue for high priority commands (bypass in-order queue) */31#define IPU6_N_MAX_DEV_SEND_QUEUES 132/* Single dedicated send queue for proxy interface */33#define IPU6_N_MAX_PROXY_SEND_QUEUES 134/* Single dedicated recv queue for proxy interface */35#define IPU6_N_MAX_PROXY_RECV_QUEUES 136/* Send queues layout */37#define IPU6_BASE_PROXY_SEND_QUEUES 038#define IPU6_BASE_DEV_SEND_QUEUES \39 (IPU6_BASE_PROXY_SEND_QUEUES + IPU6_N_MAX_PROXY_SEND_QUEUES)40#define IPU6_BASE_MSG_SEND_QUEUES \41 (IPU6_BASE_DEV_SEND_QUEUES + IPU6_N_MAX_DEV_SEND_QUEUES)42/* Recv queues layout */43#define IPU6_BASE_PROXY_RECV_QUEUES 044#define IPU6_BASE_MSG_RECV_QUEUES \45 (IPU6_BASE_PROXY_RECV_QUEUES + IPU6_N_MAX_PROXY_RECV_QUEUES)46#define IPU6_N_MAX_RECV_QUEUES \47 (IPU6_BASE_MSG_RECV_QUEUES + IPU6_N_MAX_MSG_RECV_QUEUES)48 49#define IPU6_N_MAX_SEND_QUEUES \50 (IPU6_BASE_MSG_SEND_QUEUES + IPU6_N_MAX_MSG_SEND_QUEUES)51#define IPU6SE_N_MAX_SEND_QUEUES \52 (IPU6_BASE_MSG_SEND_QUEUES + IPU6SE_N_MAX_MSG_SEND_QUEUES)53 54/* Max number of planes for frame formats supported by the FW */55#define IPU6_PIN_PLANES_MAX 456 57#define IPU6_FW_ISYS_SENSOR_TYPE_START 1458#define IPU6_FW_ISYS_SENSOR_TYPE_END 1959#define IPU6SE_FW_ISYS_SENSOR_TYPE_START 660#define IPU6SE_FW_ISYS_SENSOR_TYPE_END 1161/*62 * Device close takes some time from last ack message to actual stopping63 * of the SP processor. As long as the SP processor runs we can't proceed with64 * clean up of resources.65 */66#define IPU6_ISYS_OPEN_RETRY 200067#define IPU6_ISYS_CLOSE_RETRY 200068#define IPU6_FW_CALL_TIMEOUT_JIFFIES msecs_to_jiffies(2000)69 70enum ipu6_fw_isys_resp_type {71 IPU6_FW_ISYS_RESP_TYPE_STREAM_OPEN_DONE = 0,72 IPU6_FW_ISYS_RESP_TYPE_STREAM_START_ACK,73 IPU6_FW_ISYS_RESP_TYPE_STREAM_START_AND_CAPTURE_ACK,74 IPU6_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_ACK,75 IPU6_FW_ISYS_RESP_TYPE_STREAM_STOP_ACK,76 IPU6_FW_ISYS_RESP_TYPE_STREAM_FLUSH_ACK,77 IPU6_FW_ISYS_RESP_TYPE_STREAM_CLOSE_ACK,78 IPU6_FW_ISYS_RESP_TYPE_PIN_DATA_READY,79 IPU6_FW_ISYS_RESP_TYPE_PIN_DATA_WATERMARK,80 IPU6_FW_ISYS_RESP_TYPE_FRAME_SOF,81 IPU6_FW_ISYS_RESP_TYPE_FRAME_EOF,82 IPU6_FW_ISYS_RESP_TYPE_STREAM_START_AND_CAPTURE_DONE,83 IPU6_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_DONE,84 IPU6_FW_ISYS_RESP_TYPE_PIN_DATA_SKIPPED,85 IPU6_FW_ISYS_RESP_TYPE_STREAM_CAPTURE_SKIPPED,86 IPU6_FW_ISYS_RESP_TYPE_FRAME_SOF_DISCARDED,87 IPU6_FW_ISYS_RESP_TYPE_FRAME_EOF_DISCARDED,88 IPU6_FW_ISYS_RESP_TYPE_STATS_DATA_READY,89 N_IPU6_FW_ISYS_RESP_TYPE90};91 92enum ipu6_fw_isys_send_type {93 IPU6_FW_ISYS_SEND_TYPE_STREAM_OPEN = 0,94 IPU6_FW_ISYS_SEND_TYPE_STREAM_START,95 IPU6_FW_ISYS_SEND_TYPE_STREAM_START_AND_CAPTURE,96 IPU6_FW_ISYS_SEND_TYPE_STREAM_CAPTURE,97 IPU6_FW_ISYS_SEND_TYPE_STREAM_STOP,98 IPU6_FW_ISYS_SEND_TYPE_STREAM_FLUSH,99 IPU6_FW_ISYS_SEND_TYPE_STREAM_CLOSE,100 N_IPU6_FW_ISYS_SEND_TYPE101};102 103enum ipu6_fw_isys_queue_type {104 IPU6_FW_ISYS_QUEUE_TYPE_PROXY = 0,105 IPU6_FW_ISYS_QUEUE_TYPE_DEV,106 IPU6_FW_ISYS_QUEUE_TYPE_MSG,107 N_IPU6_FW_ISYS_QUEUE_TYPE108};109 110enum ipu6_fw_isys_stream_source {111 IPU6_FW_ISYS_STREAM_SRC_PORT_0 = 0,112 IPU6_FW_ISYS_STREAM_SRC_PORT_1,113 IPU6_FW_ISYS_STREAM_SRC_PORT_2,114 IPU6_FW_ISYS_STREAM_SRC_PORT_3,115 IPU6_FW_ISYS_STREAM_SRC_PORT_4,116 IPU6_FW_ISYS_STREAM_SRC_PORT_5,117 IPU6_FW_ISYS_STREAM_SRC_PORT_6,118 IPU6_FW_ISYS_STREAM_SRC_PORT_7,119 IPU6_FW_ISYS_STREAM_SRC_PORT_8,120 IPU6_FW_ISYS_STREAM_SRC_PORT_9,121 IPU6_FW_ISYS_STREAM_SRC_PORT_10,122 IPU6_FW_ISYS_STREAM_SRC_PORT_11,123 IPU6_FW_ISYS_STREAM_SRC_PORT_12,124 IPU6_FW_ISYS_STREAM_SRC_PORT_13,125 IPU6_FW_ISYS_STREAM_SRC_PORT_14,126 IPU6_FW_ISYS_STREAM_SRC_PORT_15,127 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_0,128 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_1,129 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_2,130 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_3,131 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_4,132 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_5,133 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_6,134 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_7,135 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_8,136 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_9,137 N_IPU6_FW_ISYS_STREAM_SRC138};139 140#define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT0 IPU6_FW_ISYS_STREAM_SRC_PORT_0141#define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT1 IPU6_FW_ISYS_STREAM_SRC_PORT_1142#define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT2 IPU6_FW_ISYS_STREAM_SRC_PORT_2143#define IPU6_FW_ISYS_STREAM_SRC_CSI2_PORT3 IPU6_FW_ISYS_STREAM_SRC_PORT_3144 145#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_PORTA IPU6_FW_ISYS_STREAM_SRC_PORT_4146#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_PORTB IPU6_FW_ISYS_STREAM_SRC_PORT_5147#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT0 \148 IPU6_FW_ISYS_STREAM_SRC_PORT_6149#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT1 \150 IPU6_FW_ISYS_STREAM_SRC_PORT_7151#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT2 \152 IPU6_FW_ISYS_STREAM_SRC_PORT_8153#define IPU6_FW_ISYS_STREAM_SRC_CSI2_3PH_CPHY_PORT3 \154 IPU6_FW_ISYS_STREAM_SRC_PORT_9155 156#define IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_PORT0 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_0157#define IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_PORT1 IPU6_FW_ISYS_STREAM_SRC_MIPIGEN_1158 159/*160 * enum ipu6_fw_isys_mipi_vc: MIPI csi2 spec161 * supports up to 4 virtual per physical channel162 */163enum ipu6_fw_isys_mipi_vc {164 IPU6_FW_ISYS_MIPI_VC_0 = 0,165 IPU6_FW_ISYS_MIPI_VC_1,166 IPU6_FW_ISYS_MIPI_VC_2,167 IPU6_FW_ISYS_MIPI_VC_3,168 N_IPU6_FW_ISYS_MIPI_VC169};170 171enum ipu6_fw_isys_frame_format_type {172 IPU6_FW_ISYS_FRAME_FORMAT_NV11 = 0, /* 12 bit YUV 411, Y, UV plane */173 IPU6_FW_ISYS_FRAME_FORMAT_NV12, /* 12 bit YUV 420, Y, UV plane */174 IPU6_FW_ISYS_FRAME_FORMAT_NV12_16, /* 16 bit YUV 420, Y, UV plane */175 /* 12 bit YUV 420, Intel proprietary tiled format */176 IPU6_FW_ISYS_FRAME_FORMAT_NV12_TILEY,177 178 IPU6_FW_ISYS_FRAME_FORMAT_NV16, /* 16 bit YUV 422, Y, UV plane */179 IPU6_FW_ISYS_FRAME_FORMAT_NV21, /* 12 bit YUV 420, Y, VU plane */180 IPU6_FW_ISYS_FRAME_FORMAT_NV61, /* 16 bit YUV 422, Y, VU plane */181 IPU6_FW_ISYS_FRAME_FORMAT_YV12, /* 12 bit YUV 420, Y, V, U plane */182 IPU6_FW_ISYS_FRAME_FORMAT_YV16, /* 16 bit YUV 422, Y, V, U plane */183 IPU6_FW_ISYS_FRAME_FORMAT_YUV420, /* 12 bit YUV 420, Y, U, V plane */184 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_10, /* yuv420, 10 bits per subpixel */185 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_12, /* yuv420, 12 bits per subpixel */186 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_14, /* yuv420, 14 bits per subpixel */187 IPU6_FW_ISYS_FRAME_FORMAT_YUV420_16, /* yuv420, 16 bits per subpixel */188 IPU6_FW_ISYS_FRAME_FORMAT_YUV422, /* 16 bit YUV 422, Y, U, V plane */189 IPU6_FW_ISYS_FRAME_FORMAT_YUV422_16, /* yuv422, 16 bits per subpixel */190 IPU6_FW_ISYS_FRAME_FORMAT_UYVY, /* 16 bit YUV 422, UYVY interleaved */191 IPU6_FW_ISYS_FRAME_FORMAT_YUYV, /* 16 bit YUV 422, YUYV interleaved */192 IPU6_FW_ISYS_FRAME_FORMAT_YUV444, /* 24 bit YUV 444, Y, U, V plane */193 /* Internal format, 2 y lines followed by a uvinterleaved line */194 IPU6_FW_ISYS_FRAME_FORMAT_YUV_LINE,195 IPU6_FW_ISYS_FRAME_FORMAT_RAW8, /* RAW8, 1 plane */196 IPU6_FW_ISYS_FRAME_FORMAT_RAW10, /* RAW10, 1 plane */197 IPU6_FW_ISYS_FRAME_FORMAT_RAW12, /* RAW12, 1 plane */198 IPU6_FW_ISYS_FRAME_FORMAT_RAW14, /* RAW14, 1 plane */199 IPU6_FW_ISYS_FRAME_FORMAT_RAW16, /* RAW16, 1 plane */200 /**201 * 16 bit RGB, 1 plane. Each 3 sub pixels are packed into one 16 bit202 * value, 5 bits for R, 6 bits for G and 5 bits for B.203 */204 IPU6_FW_ISYS_FRAME_FORMAT_RGB565,205 IPU6_FW_ISYS_FRAME_FORMAT_PLANAR_RGB888, /* 24 bit RGB, 3 planes */206 IPU6_FW_ISYS_FRAME_FORMAT_RGBA888, /* 32 bit RGBA, 1 plane, A=Alpha */207 IPU6_FW_ISYS_FRAME_FORMAT_QPLANE6, /* Internal, for advanced ISP */208 IPU6_FW_ISYS_FRAME_FORMAT_BINARY_8, /* byte stream, used for jpeg. */209 N_IPU6_FW_ISYS_FRAME_FORMAT210};211 212enum ipu6_fw_isys_pin_type {213 /* captured as MIPI packets */214 IPU6_FW_ISYS_PIN_TYPE_MIPI = 0,215 /* captured through the SoC path */216 IPU6_FW_ISYS_PIN_TYPE_RAW_SOC = 3,217};218 219/*220 * enum ipu6_fw_isys_mipi_store_mode. Describes if long MIPI packets reach221 * MIPI SRAM with the long packet header or222 * if not, then only option is to capture it with pin type MIPI.223 */224enum ipu6_fw_isys_mipi_store_mode {225 IPU6_FW_ISYS_MIPI_STORE_MODE_NORMAL = 0,226 IPU6_FW_ISYS_MIPI_STORE_MODE_DISCARD_LONG_HEADER,227 N_IPU6_FW_ISYS_MIPI_STORE_MODE228};229 230enum ipu6_fw_isys_capture_mode {231 IPU6_FW_ISYS_CAPTURE_MODE_REGULAR = 0,232 IPU6_FW_ISYS_CAPTURE_MODE_BURST,233 N_IPU6_FW_ISYS_CAPTURE_MODE,234};235 236enum ipu6_fw_isys_sensor_mode {237 IPU6_FW_ISYS_SENSOR_MODE_NORMAL = 0,238 IPU6_FW_ISYS_SENSOR_MODE_TOBII,239 N_IPU6_FW_ISYS_SENSOR_MODE,240};241 242enum ipu6_fw_isys_error {243 IPU6_FW_ISYS_ERROR_NONE = 0,244 IPU6_FW_ISYS_ERROR_FW_INTERNAL_CONSISTENCY,245 IPU6_FW_ISYS_ERROR_HW_CONSISTENCY,246 IPU6_FW_ISYS_ERROR_DRIVER_INVALID_COMMAND_SEQUENCE,247 IPU6_FW_ISYS_ERROR_DRIVER_INVALID_DEVICE_CONFIGURATION,248 IPU6_FW_ISYS_ERROR_DRIVER_INVALID_STREAM_CONFIGURATION,249 IPU6_FW_ISYS_ERROR_DRIVER_INVALID_FRAME_CONFIGURATION,250 IPU6_FW_ISYS_ERROR_INSUFFICIENT_RESOURCES,251 IPU6_FW_ISYS_ERROR_HW_REPORTED_STR2MMIO,252 IPU6_FW_ISYS_ERROR_HW_REPORTED_SIG2CIO,253 IPU6_FW_ISYS_ERROR_SENSOR_FW_SYNC,254 IPU6_FW_ISYS_ERROR_STREAM_IN_SUSPENSION,255 IPU6_FW_ISYS_ERROR_RESPONSE_QUEUE_FULL,256 N_IPU6_FW_ISYS_ERROR257};258 259enum ipu6_fw_proxy_error {260 IPU6_FW_PROXY_ERROR_NONE = 0,261 IPU6_FW_PROXY_ERROR_INVALID_WRITE_REGION,262 IPU6_FW_PROXY_ERROR_INVALID_WRITE_OFFSET,263 N_IPU6_FW_PROXY_ERROR264};265 266/* firmware ABI structure below are aligned in firmware, no need pack */267struct ipu6_fw_isys_buffer_partition_abi {268 u32 num_gda_pages[IPU6_STREAM_ID_MAX];269};270 271struct ipu6_fw_isys_fw_config {272 struct ipu6_fw_isys_buffer_partition_abi buffer_partition;273 u32 num_send_queues[N_IPU6_FW_ISYS_QUEUE_TYPE];274 u32 num_recv_queues[N_IPU6_FW_ISYS_QUEUE_TYPE];275};276 277/*278 * struct ipu6_fw_isys_resolution_abi: Generic resolution structure.279 */280struct ipu6_fw_isys_resolution_abi {281 u32 width;282 u32 height;283};284 285/**286 * struct ipu6_fw_isys_output_pin_payload_abi - ISYS output pin buffer287 * @out_buf_id: Points to output pin buffer - buffer identifier288 * @addr: Points to output pin buffer - CSS Virtual Address289 * @compress: Request frame compression (1), or not (0)290 */291struct ipu6_fw_isys_output_pin_payload_abi {292 u64 out_buf_id;293 u32 addr;294 u32 compress;295};296 297/**298 * struct ipu6_fw_isys_output_pin_info_abi - ISYS output pin info299 * @output_res: output pin resolution300 * @stride: output stride in Bytes (not valid for statistics)301 * @watermark_in_lines: pin watermark level in lines302 * @payload_buf_size: minimum size in Bytes of all buffers that will be303 * supplied for capture on this pin304 * @ts_offsets: ts_offsets305 * @s2m_pixel_soc_pixel_remapping: pixel soc remapping (see the definition of306 * S2M_PIXEL_SOC_PIXEL_REMAPPING_FLAG_NO_REMAPPING)307 * @csi_be_soc_pixel_remapping: see s2m_pixel_soc_pixel_remapping308 * @send_irq: assert if pin event should trigger irq309 * @input_pin_id: related input pin id310 * @pt: pin type -real format "enum ipu6_fw_isys_pin_type"311 * @ft: frame format type -real format "enum ipu6_fw_isys_frame_format_type"312 * @reserved: a reserved field313 * @reserve_compression: reserve compression resources for pin314 * @snoopable: snoopable315 * @error_handling_enable: enable error handling316 * @sensor_type: sensor_type317 */318struct ipu6_fw_isys_output_pin_info_abi {319 struct ipu6_fw_isys_resolution_abi output_res;320 u32 stride;321 u32 watermark_in_lines;322 u32 payload_buf_size;323 u32 ts_offsets[IPU6_PIN_PLANES_MAX];324 u32 s2m_pixel_soc_pixel_remapping;325 u32 csi_be_soc_pixel_remapping;326 u8 send_irq;327 u8 input_pin_id;328 u8 pt;329 u8 ft;330 u8 reserved;331 u8 reserve_compression;332 u8 snoopable;333 u8 error_handling_enable;334 u32 sensor_type;335};336 337/**338 * struct ipu6_fw_isys_input_pin_info_abi - ISYS input pin info339 * @input_res: input resolution340 * @dt: mipi data type ((enum ipu6_fw_isys_mipi_data_type)341 * @mipi_store_mode: defines if legacy long packet header will be stored or342 * discarded if discarded, output pin type for this343 * input pin can only be MIPI344 * (enum ipu6_fw_isys_mipi_store_mode)345 * @bits_per_pix: native bits per pixel346 * @mapped_dt: actual data type from sensor347 * @mipi_decompression: defines which compression will be in mipi backend348 * @crop_first_and_last_lines: Control whether to crop the first and last line349 * of the input image. Crop done by HW device.350 * @capture_mode: mode of capture, regular or burst, default value is regular351 * @reserved: a reserved field352 */353struct ipu6_fw_isys_input_pin_info_abi {354 struct ipu6_fw_isys_resolution_abi input_res;355 u8 dt;356 u8 mipi_store_mode;357 u8 bits_per_pix;358 u8 mapped_dt;359 u8 mipi_decompression;360 u8 crop_first_and_last_lines;361 u8 capture_mode;362 u8 reserved;363};364 365/**366 * struct ipu6_fw_isys_cropping_abi - ISYS cropping coordinates367 * @top_offset: Top offset368 * @left_offset: Left offset369 * @bottom_offset: Bottom offset370 * @right_offset: Right offset371 */372struct ipu6_fw_isys_cropping_abi {373 s32 top_offset;374 s32 left_offset;375 s32 bottom_offset;376 s32 right_offset;377};378 379/**380 * struct ipu6_fw_isys_stream_cfg_data_abi - ISYS stream configuration data381 * ISYS stream configuration data structure382 * @crop: for extended use and is not used in FW currently383 * @input_pins: input pin descriptors384 * @output_pins: output pin descriptors385 * @compfmt: de-compression setting for User Defined Data386 * @nof_input_pins: number of input pins387 * @nof_output_pins: number of output pins388 * @send_irq_sof_discarded: send irq on discarded frame sof response389 * - if '1' it will override the send_resp_sof_discarded390 * and send the response391 * - if '0' the send_resp_sof_discarded will determine392 * whether to send the response393 * @send_irq_eof_discarded: send irq on discarded frame eof response394 * - if '1' it will override the send_resp_eof_discarded395 * and send the response396 * - if '0' the send_resp_eof_discarded will determine397 * whether to send the response398 * @send_resp_sof_discarded: send response for discarded frame sof detected,399 * used only when send_irq_sof_discarded is '0'400 * @send_resp_eof_discarded: send response for discarded frame eof detected,401 * used only when send_irq_eof_discarded is '0'402 * @src: Stream source index e.g. MIPI_generator_0, CSI2-rx_1403 * @vc: MIPI Virtual Channel (up to 4 virtual per physical channel)404 * @isl_use: indicates whether stream requires ISL and how405 * @sensor_type: type of connected sensor, tobii or others, default is 0406 * @reserved: a reserved field407 * @reserved2: a reserved field408 */409struct ipu6_fw_isys_stream_cfg_data_abi {410 struct ipu6_fw_isys_cropping_abi crop;411 struct ipu6_fw_isys_input_pin_info_abi input_pins[IPU6_MAX_IPINS];412 struct ipu6_fw_isys_output_pin_info_abi output_pins[IPU6_MAX_OPINS];413 u32 compfmt;414 u8 nof_input_pins;415 u8 nof_output_pins;416 u8 send_irq_sof_discarded;417 u8 send_irq_eof_discarded;418 u8 send_resp_sof_discarded;419 u8 send_resp_eof_discarded;420 u8 src;421 u8 vc;422 u8 isl_use;423 u8 sensor_type;424 u8 reserved;425 u8 reserved2;426};427 428/**429 * struct ipu6_fw_isys_frame_buff_set_abi - ISYS frame buffer set (request)430 * @output_pins: output pin addresses431 * @send_irq_sof: send irq on frame sof response432 * - if '1' it will override the send_resp_sof and433 * send the response434 * - if '0' the send_resp_sof will determine whether to435 * send the response436 * @send_irq_eof: send irq on frame eof response437 * - if '1' it will override the send_resp_eof and438 * send the response439 * - if '0' the send_resp_eof will determine whether to440 * send the response441 * @send_irq_capture_ack: send irq on capture ack442 * @send_irq_capture_done: send irq on capture done443 * @send_resp_sof: send response for frame sof detected,444 * used only when send_irq_sof is '0'445 * @send_resp_eof: send response for frame eof detected,446 * used only when send_irq_eof is '0'447 * @send_resp_capture_ack: send response for capture ack event448 * @send_resp_capture_done: send response for capture done event449 * @reserved: a reserved field450 */451struct ipu6_fw_isys_frame_buff_set_abi {452 struct ipu6_fw_isys_output_pin_payload_abi output_pins[IPU6_MAX_OPINS];453 u8 send_irq_sof;454 u8 send_irq_eof;455 u8 send_irq_capture_ack;456 u8 send_irq_capture_done;457 u8 send_resp_sof;458 u8 send_resp_eof;459 u8 send_resp_capture_ack;460 u8 send_resp_capture_done;461 u8 reserved[8];462};463 464/**465 * struct ipu6_fw_isys_error_info_abi - ISYS error information466 * @error: error code if something went wrong467 * @error_details: depending on error code, it may contain additional error info468 */469struct ipu6_fw_isys_error_info_abi {470 u32 error;471 u32 error_details;472};473 474/**475 * struct ipu6_fw_isys_resp_info_abi - ISYS firmware response476 * @buf_id: buffer ID477 * @pin: this var is only valid for pin event related responses,478 * contains pin addresses479 * @error_info: error information from the FW480 * @timestamp: Time information for event if available481 * @stream_handle: stream id the response corresponds to482 * @type: response type (enum ipu6_fw_isys_resp_type)483 * @pin_id: pin id that the pin payload corresponds to484 * @reserved: a reserved field485 * @reserved2: a reserved field486 */487struct ipu6_fw_isys_resp_info_abi {488 u64 buf_id;489 struct ipu6_fw_isys_output_pin_payload_abi pin;490 struct ipu6_fw_isys_error_info_abi error_info;491 u32 timestamp[2];492 u8 stream_handle;493 u8 type;494 u8 pin_id;495 u8 reserved;496 u32 reserved2;497};498 499/**500 * struct ipu6_fw_isys_proxy_error_info_abi - ISYS proxy error501 * @error: error code if something went wrong502 * @error_details: depending on error code, it may contain additional error info503 */504struct ipu6_fw_isys_proxy_error_info_abi {505 u32 error;506 u32 error_details;507};508 509struct ipu6_fw_isys_proxy_resp_info_abi {510 u32 request_id;511 struct ipu6_fw_isys_proxy_error_info_abi error_info;512};513 514/**515 * struct ipu6_fw_proxy_write_queue_token - ISYS proxy write queue token516 * @request_id: update id for the specific proxy write request517 * @region_index: Region id for the proxy write request518 * @offset: Offset of the write request according to the base address519 * of the region520 * @value: Value that is requested to be written with the proxy write request521 */522struct ipu6_fw_proxy_write_queue_token {523 u32 request_id;524 u32 region_index;525 u32 offset;526 u32 value;527};528 529/**530 * struct ipu6_fw_resp_queue_token - ISYS response queue token531 * @resp_info: response info532 */533struct ipu6_fw_resp_queue_token {534 struct ipu6_fw_isys_resp_info_abi resp_info;535};536 537/**538 * struct ipu6_fw_send_queue_token - ISYS send queue token539 * @buf_handle: buffer handle540 * @payload: payload541 * @send_type: send_type542 * @stream_id: stream_id543 */544struct ipu6_fw_send_queue_token {545 u64 buf_handle;546 u32 payload;547 u16 send_type;548 u16 stream_id;549};550 551/**552 * struct ipu6_fw_proxy_resp_queue_token - ISYS proxy response queue token553 * @proxy_resp_info: proxy response info554 */555struct ipu6_fw_proxy_resp_queue_token {556 struct ipu6_fw_isys_proxy_resp_info_abi proxy_resp_info;557};558 559/**560 * struct ipu6_fw_proxy_send_queue_token - SYS proxy send queue token561 * @request_id: request_id562 * @region_index: region_index563 * @offset: offset564 * @value: value565 */566struct ipu6_fw_proxy_send_queue_token {567 u32 request_id;568 u32 region_index;569 u32 offset;570 u32 value;571};572 573void574ipu6_fw_isys_dump_stream_cfg(struct device *dev,575 struct ipu6_fw_isys_stream_cfg_data_abi *cfg);576void577ipu6_fw_isys_dump_frame_buff_set(struct device *dev,578 struct ipu6_fw_isys_frame_buff_set_abi *buf,579 unsigned int outputs);580int ipu6_fw_isys_init(struct ipu6_isys *isys, unsigned int num_streams);581int ipu6_fw_isys_close(struct ipu6_isys *isys);582int ipu6_fw_isys_simple_cmd(struct ipu6_isys *isys,583 const unsigned int stream_handle, u16 send_type);584int ipu6_fw_isys_complex_cmd(struct ipu6_isys *isys,585 const unsigned int stream_handle,586 void *cpu_mapped_buf, dma_addr_t dma_mapped_buf,587 size_t size, u16 send_type);588int ipu6_fw_isys_send_proxy_token(struct ipu6_isys *isys,589 unsigned int req_id,590 unsigned int index,591 unsigned int offset, u32 value);592void ipu6_fw_isys_cleanup(struct ipu6_isys *isys);593struct ipu6_fw_isys_resp_info_abi *594ipu6_fw_isys_get_resp(void *context, unsigned int queue);595void ipu6_fw_isys_put_resp(void *context, unsigned int queue);596#endif597