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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (C) 2013--2024 Intel Corporation */3 4#ifndef IPU6_MMU_H5#define IPU6_MMU_H6 7#define ISYS_MMID 18#define PSYS_MMID 09 10#include <linux/list.h>11#include <linux/spinlock_types.h>12#include <linux/types.h>13 14struct device;15struct page;16struct ipu6_hw_variants;17 18struct ipu6_mmu_info {19 struct device *dev;20 21 u32 *l1_pt;22 u32 l1_pt_dma;23 u32 **l2_pts;24 25 u32 *dummy_l2_pt;26 u32 dummy_l2_pteval;27 void *dummy_page;28 u32 dummy_page_pteval;29 30 dma_addr_t aperture_start;31 dma_addr_t aperture_end;32 unsigned long pgsize_bitmap;33 34 spinlock_t lock; /* Serialize access to users */35 struct ipu6_dma_mapping *dmap;36};37 38struct ipu6_mmu {39 struct list_head node;40 41 struct ipu6_mmu_hw *mmu_hw;42 unsigned int nr_mmus;43 unsigned int mmid;44 45 phys_addr_t pgtbl;46 struct device *dev;47 48 struct ipu6_dma_mapping *dmap;49 struct list_head vma_list;50 51 struct page *trash_page;52 dma_addr_t pci_trash_page; /* IOVA from PCI DMA services (parent) */53 dma_addr_t iova_trash_page; /* IOVA for IPU6 child nodes to use */54 55 bool ready;56 spinlock_t ready_lock; /* Serialize access to bool ready */57 58 void (*tlb_invalidate)(struct ipu6_mmu *mmu);59};60 61struct ipu6_mmu *ipu6_mmu_init(struct device *dev,62 void __iomem *base, int mmid,63 const struct ipu6_hw_variants *hw);64void ipu6_mmu_cleanup(struct ipu6_mmu *mmu);65int ipu6_mmu_hw_init(struct ipu6_mmu *mmu);66void ipu6_mmu_hw_cleanup(struct ipu6_mmu *mmu);67int ipu6_mmu_map(struct ipu6_mmu_info *mmu_info, unsigned long iova,68 phys_addr_t paddr, size_t size);69size_t ipu6_mmu_unmap(struct ipu6_mmu_info *mmu_info, unsigned long iova,70 size_t size);71phys_addr_t ipu6_mmu_iova_to_phys(struct ipu6_mmu_info *mmu_info,72 dma_addr_t iova);73#endif74