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1/* SPDX-License-Identifier: GPL-2.0-only */2/* Copyright (C) 2023--2024 Intel Corporation */3 4#ifndef IPU6_PLATFORM_ISYS_CSI2_REG_H5#define IPU6_PLATFORM_ISYS_CSI2_REG_H6 7#include <linux/bits.h>8 9#define CSI_REG_BASE 0x22000010#define CSI_REG_PORT_BASE(id) (CSI_REG_BASE + (id) * 0x1000)11 12/* CSI Port Genral Purpose Registers */13#define CSI_REG_PORT_GPREG_SRST 0x014#define CSI_REG_PORT_GPREG_CSI2_SLV_REG_SRST 0x415#define CSI_REG_PORT_GPREG_CSI2_PORT_CONTROL 0x816 17/*18 * Port IRQs mapping events:19 * IRQ0 - CSI_FE event20 * IRQ1 - CSI_SYNC21 * IRQ2 - S2M_SIDS0TO722 * IRQ3 - S2M_SIDS8TO1523 */24#define CSI_PORT_REG_BASE_IRQ_CSI 0x8025#define CSI_PORT_REG_BASE_IRQ_CSI_SYNC 0xA026#define CSI_PORT_REG_BASE_IRQ_S2M_SIDS0TOS7 0xC027#define CSI_PORT_REG_BASE_IRQ_S2M_SIDS8TOS15 0xE028 29#define CSI_PORT_REG_BASE_IRQ_EDGE_OFFSET 0x030#define CSI_PORT_REG_BASE_IRQ_MASK_OFFSET 0x431#define CSI_PORT_REG_BASE_IRQ_STATUS_OFFSET 0x832#define CSI_PORT_REG_BASE_IRQ_CLEAR_OFFSET 0xc33#define CSI_PORT_REG_BASE_IRQ_ENABLE_OFFSET 0x1034#define CSI_PORT_REG_BASE_IRQ_LEVEL_NOT_PULSE_OFFSET 0x1435 36#define IPU6SE_CSI_RX_ERROR_IRQ_MASK GENMASK(18, 0)37#define IPU6_CSI_RX_ERROR_IRQ_MASK GENMASK(19, 0)38 39#define CSI_RX_NUM_ERRORS_IN_IRQ 2040#define CSI_RX_NUM_IRQ 3241 42#define IPU_CSI_RX_IRQ_FS_VC(chn) (1 << ((chn) * 2))43#define IPU_CSI_RX_IRQ_FE_VC(chn) (2 << ((chn) * 2))44 45/* PPI2CSI */46#define CSI_REG_PPI2CSI_ENABLE 0x20047#define CSI_REG_PPI2CSI_CONFIG_PPI_INTF 0x20448#define PPI_INTF_CONFIG_NOF_ENABLED_DLANES_MASK GENMASK(4, 3)49#define CSI_REG_PPI2CSI_CONFIG_CSI_FEATURE 0x20850 51enum CSI_PPI2CSI_CTRL {52 CSI_PPI2CSI_DISABLE = 0,53 CSI_PPI2CSI_ENABLE = 1,54};55 56/* CSI_FE */57#define CSI_REG_CSI_FE_ENABLE 0x28058#define CSI_REG_CSI_FE_MODE 0x28459#define CSI_REG_CSI_FE_MUX_CTRL 0x28860#define CSI_REG_CSI_FE_SYNC_CNTR_SEL 0x29061 62enum CSI_FE_ENABLE_TYPE {63 CSI_FE_DISABLE = 0,64 CSI_FE_ENABLE = 1,65};66 67enum CSI_FE_MODE_TYPE {68 CSI_FE_DPHY_MODE = 0,69 CSI_FE_CPHY_MODE = 1,70};71 72enum CSI_FE_INPUT_SELECTOR {73 CSI_SENSOR_INPUT = 0,74 CSI_MIPIGEN_INPUT = 1,75};76 77enum CSI_FE_SYNC_CNTR_SEL_TYPE {78 CSI_CNTR_SENSOR_LINE_ID = BIT(0),79 CSI_CNTR_INT_LINE_PKT_ID = ~CSI_CNTR_SENSOR_LINE_ID,80 CSI_CNTR_SENSOR_FRAME_ID = BIT(1),81 CSI_CNTR_INT_FRAME_PKT_ID = ~CSI_CNTR_SENSOR_FRAME_ID,82};83 84/* CSI HUB General Purpose Registers */85#define CSI_REG_HUB_GPREG_SRST (CSI_REG_BASE + 0x18000)86#define CSI_REG_HUB_GPREG_SLV_REG_SRST (CSI_REG_BASE + 0x18004)87 88#define CSI_REG_HUB_DRV_ACCESS_PORT(id) (CSI_REG_BASE + 0x18018 + (id) * 4)89#define CSI_REG_HUB_FW_ACCESS_PORT_OFS 0x1700090#define CSI_REG_HUB_FW_ACCESS_PORT_V6OFS 0x1600091#define CSI_REG_HUB_FW_ACCESS_PORT(ofs, id) \92 (CSI_REG_BASE + (ofs) + (id) * 4)93 94enum CSI_PORT_CLK_GATING_SWITCH {95 CSI_PORT_CLK_GATING_OFF = 0,96 CSI_PORT_CLK_GATING_ON = 1,97};98 99#define CSI_REG_BASE_HUB_IRQ 0x18200100 101#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_EDGE 0x238200102#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_MASK 0x238204103#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_STATUS 0x238208104#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_CLEAR 0x23820c105#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_ENABLE 0x238210106#define IPU6_REG_ISYS_CSI_TOP_CTRL0_IRQ_LEVEL_NOT_PULSE 0x238214107 108#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_EDGE 0x238220109#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_MASK 0x238224110#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_STATUS 0x238228111#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_CLEAR 0x23822c112#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_ENABLE 0x238230113#define IPU6_REG_ISYS_CSI_TOP_CTRL1_IRQ_LEVEL_NOT_PULSE 0x238234114 115/* MTL IPU6V6 irq ctrl0 & ctrl1 */116#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_EDGE 0x238700117#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_MASK 0x238704118#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_STATUS 0x238708119#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_CLEAR 0x23870c120#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_ENABLE 0x238710121#define IPU6V6_REG_ISYS_CSI_TOP_CTRL0_IRQ_LEVEL_NOT_PULSE 0x238714122 123#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_EDGE 0x238720124#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_MASK 0x238724125#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_STATUS 0x238728126#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_CLEAR 0x23872c127#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_ENABLE 0x238730128#define IPU6V6_REG_ISYS_CSI_TOP_CTRL1_IRQ_LEVEL_NOT_PULSE 0x238734129 130/*131 * 3:0 CSI_PORT.irq_out[3:0] CSI_PORT_CTRL0 IRQ outputs (4bits)132 * [0] CSI_PORT.IRQ_CTRL0_csi133 * [1] CSI_PORT.IRQ_CTRL1_csi_sync134 * [2] CSI_PORT.IRQ_CTRL2_s2m_sids0to7135 * [3] CSI_PORT.IRQ_CTRL3_s2m_sids8to15136 */137#define IPU6_ISYS_UNISPART_IRQ_CSI2(port) \138 (0x3 << ((port) * IPU6_CSI_IRQ_NUM_PER_PIPE))139 140/*141 * ipu6se support 2 front ends, 2 port per front end, 4 ports 0..3142 * sip0 - 0, 1143 * sip1 - 2, 3144 * 0 and 2 support 4 data lanes, 1 and 3 support 2 data lanes145 * all offset are base from isys base address146 */147 148#define CSI2_HUB_GPREG_SIP_SRST(sip) (0x238038 + (sip) * 4)149#define CSI2_HUB_GPREG_SIP_FB_PORT_CFG(sip) (0x238050 + (sip) * 4)150 151#define CSI2_HUB_GPREG_DPHY_TIMER_INCR 0x238040152#define CSI2_HUB_GPREG_HPLL_FREQ 0x238044153#define CSI2_HUB_GPREG_IS_CLK_RATIO 0x238048154#define CSI2_HUB_GPREG_HPLL_FREQ_ISCLK_RATE_OVERRIDE 0x23804c155#define CSI2_HUB_GPREG_PORT_CLKGATING_DISABLE 0x238058156#define CSI2_HUB_GPREG_SIP0_CSI_RX_A_CONTROL 0x23805c157#define CSI2_HUB_GPREG_SIP0_CSI_RX_B_CONTROL 0x238088158#define CSI2_HUB_GPREG_SIP1_CSI_RX_A_CONTROL 0x2380a4159#define CSI2_HUB_GPREG_SIP1_CSI_RX_B_CONTROL 0x2380d0160 161#define CSI2_SIP_TOP_CSI_RX_BASE(sip) (0x23805c + (sip) * 0x48)162#define CSI2_SIP_TOP_CSI_RX_PORT_BASE_0(port) (0x23805c + ((port) / 2) * 0x48)163#define CSI2_SIP_TOP_CSI_RX_PORT_BASE_1(port) (0x238088 + ((port) / 2) * 0x48)164 165/* offset from port base */166#define CSI2_SIP_TOP_CSI_RX_PORT_CONTROL 0x0167#define CSI2_SIP_TOP_CSI_RX_DLY_CNT_TERMEN_CLANE 0x4168#define CSI2_SIP_TOP_CSI_RX_DLY_CNT_SETTLE_CLANE 0x8169#define CSI2_SIP_TOP_CSI_RX_DLY_CNT_TERMEN_DLANE(lane) (0xc + (lane) * 8)170#define CSI2_SIP_TOP_CSI_RX_DLY_CNT_SETTLE_DLANE(lane) (0x10 + (lane) * 8)171 172#endif /* IPU6_ISYS_CSI2_REG_H */173