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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * ngene.h: nGene PCIe bridge driver4 *5 * Copyright (C) 2005-2007 Micronas6 */7 8#ifndef _NGENE_H_9#define _NGENE_H_10 11#include <linux/types.h>12#include <linux/sched.h>13#include <linux/interrupt.h>14#include <linux/i2c.h>15#include <asm/dma.h>16#include <linux/scatterlist.h>17 18#include <linux/dvb/frontend.h>19#include <linux/workqueue.h>20 21#include <media/dmxdev.h>22#include <media/dvbdev.h>23#include <media/dvb_demux.h>24#include <media/dvb_ca_en50221.h>25#include <media/dvb_frontend.h>26#include <media/dvb_ringbuffer.h>27#include <media/dvb_net.h>28#include "cxd2099.h"29 30#define DEVICE_NAME "ngene"31 32#define NGENE_VID 0x18c333#define NGENE_PID 0x072034 35#ifndef VIDEO_CAP_VC136#define VIDEO_CAP_AVC 12837#define VIDEO_CAP_H264 12838#define VIDEO_CAP_VC1 25639#define VIDEO_CAP_WMV9 25640#define VIDEO_CAP_MPEG4 51241#endif42 43#define DEMOD_TYPE_STV090X 044#define DEMOD_TYPE_DRXK 145#define DEMOD_TYPE_STV0367 246 47#define DEMOD_TYPE_XO2 3248#define DEMOD_TYPE_STV0910 (DEMOD_TYPE_XO2 + 0)49#define DEMOD_TYPE_SONY_CT2 (DEMOD_TYPE_XO2 + 1)50#define DEMOD_TYPE_SONY_ISDBT (DEMOD_TYPE_XO2 + 2)51#define DEMOD_TYPE_SONY_C2T2 (DEMOD_TYPE_XO2 + 3)52#define DEMOD_TYPE_ST_ATSC (DEMOD_TYPE_XO2 + 4)53#define DEMOD_TYPE_SONY_C2T2I (DEMOD_TYPE_XO2 + 5)54 55#define NGENE_XO2_TYPE_NONE 056#define NGENE_XO2_TYPE_DUOFLEX 157#define NGENE_XO2_TYPE_CI 258 59enum STREAM {60 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */61 STREAM_VIDEOIN2,62 STREAM_AUDIOIN1, /* I2S or SPI Input */63 STREAM_AUDIOIN2,64 STREAM_AUDIOOUT,65 MAX_STREAM66};67 68enum SMODE_BITS {69 SMODE_AUDIO_SPDIF = 0x20,70 SMODE_AVSYNC = 0x10,71 SMODE_TRANSPORT_STREAM = 0x08,72 SMODE_AUDIO_CAPTURE = 0x04,73 SMODE_VBI_CAPTURE = 0x02,74 SMODE_VIDEO_CAPTURE = 0x0175};76 77enum STREAM_FLAG_BITS {78 SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */79 SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */80 SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */81 SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */82 SFLAG_COLORBAR = 0x04, /* Select colorbar */83};84 85#define PROGRAM_ROM 0x000086#define PROGRAM_SRAM 0x100087#define PERIPHERALS0 0x800088#define PERIPHERALS1 0x900089#define SHARED_BUFFER 0xC00090 91#define HOST_TO_NGENE (SHARED_BUFFER+0x0000)92#define NGENE_TO_HOST (SHARED_BUFFER+0x0100)93#define NGENE_COMMAND (SHARED_BUFFER+0x0200)94#define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204)95#define NGENE_STATUS (SHARED_BUFFER+0x0208)96#define NGENE_STATUS_HI (SHARED_BUFFER+0x020C)97#define NGENE_EVENT (SHARED_BUFFER+0x0210)98#define NGENE_EVENT_HI (SHARED_BUFFER+0x0214)99#define VARIABLES (SHARED_BUFFER+0x0210)100 101#define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260)102#define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264)103#define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268)104 105#define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800)106#define BUFFER_GP_RECV (SHARED_BUFFER+0x0900)107#define EEPROM_AREA (SHARED_BUFFER+0x0A00)108 109#define SG_V_IN_1 (SHARED_BUFFER+0x0A80)110#define SG_VBI_1 (SHARED_BUFFER+0x0B00)111#define SG_A_IN_1 (SHARED_BUFFER+0x0B80)112#define SG_V_IN_2 (SHARED_BUFFER+0x0C00)113#define SG_VBI_2 (SHARED_BUFFER+0x0C80)114#define SG_A_IN_2 (SHARED_BUFFER+0x0D00)115#define SG_V_OUT (SHARED_BUFFER+0x0D80)116#define SG_A_OUT2 (SHARED_BUFFER+0x0E00)117 118#define DATA_A_IN_1 (SHARED_BUFFER+0x0E80)119#define DATA_A_IN_2 (SHARED_BUFFER+0x0F00)120#define DATA_A_OUT (SHARED_BUFFER+0x0F80)121#define DATA_V_IN_1 (SHARED_BUFFER+0x1000)122#define DATA_V_IN_2 (SHARED_BUFFER+0x2000)123#define DATA_V_OUT (SHARED_BUFFER+0x3000)124 125#define DATA_FIFO_AREA (SHARED_BUFFER+0x1000)126 127#define TIMESTAMPS 0xA000128#define SCRATCHPAD 0xA080129#define FORCE_INT 0xA088130#define FORCE_NMI 0xA090131#define INT_STATUS 0xA0A0132 133#define DEV_VER 0x9004134 135#define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF)136 137struct SG_ADDR {138 u64 start;139 u64 curr;140 u16 curr_ptr;141 u16 elements;142 u32 pad[3];143} __attribute__ ((__packed__));144 145struct SHARED_MEMORY {146 /* C000 */147 u32 HostToNgene[64];148 149 /* C100 */150 u32 NgeneToHost[64];151 152 /* C200 */153 u64 NgeneCommand;154 u64 NgeneStatus;155 u64 NgeneEvent;156 157 /* C210 */158 u8 pad1[0xc260 - 0xc218];159 160 /* C260 */161 u32 IntCounts;162 u32 IntEnable;163 164 /* C268 */165 u8 pad2[0xd000 - 0xc268];166 167} __attribute__ ((__packed__));168 169struct BUFFER_STREAM_RESULTS {170 u32 Clock; /* Stream time in 100ns units */171 u16 RemainingLines; /* Remaining lines in this field.172 0 for complete field */173 u8 FieldCount; /* Video field number */174 u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow,175 Bit 0 = FieldID */176 u16 BlockCount; /* Audio block count (unused) */177 u8 Reserved[2];178 u32 DTOUpdate;179} __attribute__ ((__packed__));180 181struct HW_SCATTER_GATHER_ELEMENT {182 u64 Address;183 u32 Length;184 u32 Reserved;185} __attribute__ ((__packed__));186 187struct BUFFER_HEADER {188 u64 Next;189 struct BUFFER_STREAM_RESULTS SR;190 191 u32 Number_of_entries_1;192 u32 Reserved5;193 u64 Address_of_first_entry_1;194 195 u32 Number_of_entries_2;196 u32 Reserved7;197 u64 Address_of_first_entry_2;198} __attribute__ ((__packed__));199 200struct EVENT_BUFFER {201 u32 TimeStamp;202 u8 GPIOStatus;203 u8 UARTStatus;204 u8 RXCharacter;205 u8 EventStatus;206 u32 Reserved[2];207} __attribute__ ((__packed__));208 209/* Firmware commands. */210 211enum OPCODES {212 CMD_NOP = 0,213 CMD_FWLOAD_PREPARE = 0x01,214 CMD_FWLOAD_FINISH = 0x02,215 CMD_I2C_READ = 0x03,216 CMD_I2C_WRITE = 0x04,217 218 CMD_I2C_WRITE_NOSTOP = 0x05,219 CMD_I2C_CONTINUE_WRITE = 0x06,220 CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07,221 222 CMD_DEBUG_OUTPUT = 0x09,223 224 CMD_CONTROL = 0x10,225 CMD_CONFIGURE_BUFFER = 0x11,226 CMD_CONFIGURE_FREE_BUFFER = 0x12,227 228 CMD_SPI_READ = 0x13,229 CMD_SPI_WRITE = 0x14,230 231 CMD_MEM_READ = 0x20,232 CMD_MEM_WRITE = 0x21,233 CMD_SFR_READ = 0x22,234 CMD_SFR_WRITE = 0x23,235 CMD_IRAM_READ = 0x24,236 CMD_IRAM_WRITE = 0x25,237 CMD_SET_GPIO_PIN = 0x26,238 CMD_SET_GPIO_INT = 0x27,239 CMD_CONFIGURE_UART = 0x28,240 CMD_WRITE_UART = 0x29,241 MAX_CMD242};243 244enum RESPONSES {245 OK = 0,246 ERROR = 1247};248 249struct FW_HEADER {250 u8 Opcode;251 u8 Length;252} __attribute__ ((__packed__));253 254struct FW_I2C_WRITE {255 struct FW_HEADER hdr;256 u8 Device;257 u8 Data[250];258} __attribute__ ((__packed__));259 260struct FW_I2C_CONTINUE_WRITE {261 struct FW_HEADER hdr;262 u8 Data[250];263} __attribute__ ((__packed__));264 265struct FW_I2C_READ {266 struct FW_HEADER hdr;267 u8 Device;268 u8 Data[252]; /* followed by two bytes of read data count */269} __attribute__ ((__packed__));270 271struct FW_SPI_WRITE {272 struct FW_HEADER hdr;273 u8 ModeSelect;274 u8 Data[250];275} __attribute__ ((__packed__));276 277struct FW_SPI_READ {278 struct FW_HEADER hdr;279 u8 ModeSelect;280 u8 Data[252]; /* followed by two bytes of read data count */281} __attribute__ ((__packed__));282 283struct FW_FWLOAD_PREPARE {284 struct FW_HEADER hdr;285} __attribute__ ((__packed__));286 287struct FW_FWLOAD_FINISH {288 struct FW_HEADER hdr;289 u16 Address; /* address of final block */290 u16 Length;291} __attribute__ ((__packed__));292 293/*294 * Meaning of FW_STREAM_CONTROL::Mode bits:295 * Bit 7: Loopback PEXin to PEXout using TVOut channel296 * Bit 6: AVLOOP297 * Bit 5: Audio select; 0=I2S, 1=SPDIF298 * Bit 4: AVSYNC299 * Bit 3: Enable transport stream300 * Bit 2: Enable audio capture301 * Bit 1: Enable ITU-Video VBI capture302 * Bit 0: Enable ITU-Video capture303 *304 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL)305 * Bit 7: continuous capture306 * Bit 6: capture one field307 * Bit 5: capture one frame308 * Bit 4: unused309 * Bit 3: starting field; 0=odd, 1=even310 * Bit 2: sample size; 0=8-bit, 1=10-bit311 * Bit 1: data format; 0=UYVY, 1=YUY2312 * Bit 0: resets buffer pointers313*/314 315enum FSC_MODE_BITS {316 SMODE_LOOPBACK = 0x80,317 SMODE_AVLOOP = 0x40,318 _SMODE_AUDIO_SPDIF = 0x20,319 _SMODE_AVSYNC = 0x10,320 _SMODE_TRANSPORT_STREAM = 0x08,321 _SMODE_AUDIO_CAPTURE = 0x04,322 _SMODE_VBI_CAPTURE = 0x02,323 _SMODE_VIDEO_CAPTURE = 0x01324};325 326 327/* Meaning of FW_STREAM_CONTROL::Stream bits:328 * Bit 3: Audio sample count: 0 = relative, 1 = absolute329 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder330 * Bits 1-0: stream select, UVI1, UVI2, TVOUT331 */332 333struct FW_STREAM_CONTROL {334 struct FW_HEADER hdr;335 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */336 u8 Control; /* Value written to UVI1_CTL */337 u8 Mode; /* Controls clock source */338 u8 SetupDataLen; /* Length of setup data, MSB=1 write339 backwards */340 u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer341 for TS and Audio */342 u64 Buffer_Address; /* Address of first buffer header */343 u16 BytesPerVideoLine;344 u16 MaxLinesPerField;345 u16 MinLinesPerField;346 u16 Reserved_1;347 u16 BytesPerVBILine;348 u16 MaxVBILinesPerField;349 u16 MinVBILinesPerField;350 u16 SetupDataAddr; /* ngene relative address of setup data */351 u8 SetupData[32]; /* setup data */352} __attribute__((__packed__));353 354#define AUDIO_BLOCK_SIZE 256355#define TS_BLOCK_SIZE 256356 357struct FW_MEM_READ {358 struct FW_HEADER hdr;359 u16 address;360} __attribute__ ((__packed__));361 362struct FW_MEM_WRITE {363 struct FW_HEADER hdr;364 u16 address;365 u8 data;366} __attribute__ ((__packed__));367 368struct FW_SFR_IRAM_READ {369 struct FW_HEADER hdr;370 u8 address;371} __attribute__ ((__packed__));372 373struct FW_SFR_IRAM_WRITE {374 struct FW_HEADER hdr;375 u8 address;376 u8 data;377} __attribute__ ((__packed__));378 379struct FW_SET_GPIO_PIN {380 struct FW_HEADER hdr;381 u8 select;382} __attribute__ ((__packed__));383 384struct FW_SET_GPIO_INT {385 struct FW_HEADER hdr;386 u8 select;387} __attribute__ ((__packed__));388 389struct FW_SET_DEBUGMODE {390 struct FW_HEADER hdr;391 u8 debug_flags;392} __attribute__ ((__packed__));393 394struct FW_CONFIGURE_BUFFERS {395 struct FW_HEADER hdr;396 u8 config;397} __attribute__ ((__packed__));398 399enum _BUFFER_CONFIGS {400 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */401 BUFFER_CONFIG_4422 = 0,402 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */403 BUFFER_CONFIG_3333 = 1,404 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */405 BUFFER_CONFIG_8022 = 2,406 BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */407};408 409struct FW_CONFIGURE_FREE_BUFFERS {410 struct FW_HEADER hdr;411 struct {412 u8 UVI1_BufferLength;413 u8 UVI2_BufferLength;414 u8 TVO_BufferLength;415 u8 AUD1_BufferLength;416 u8 AUD2_BufferLength;417 u8 TVA_BufferLength;418 } __packed config;419} __attribute__ ((__packed__));420 421struct FW_CONFIGURE_UART {422 struct FW_HEADER hdr;423 u8 UartControl;424} __attribute__ ((__packed__));425 426enum _UART_CONFIG {427 _UART_BAUDRATE_19200 = 0,428 _UART_BAUDRATE_9600 = 1,429 _UART_BAUDRATE_4800 = 2,430 _UART_BAUDRATE_2400 = 3,431 _UART_RX_ENABLE = 0x40,432 _UART_TX_ENABLE = 0x80,433};434 435struct FW_WRITE_UART {436 struct FW_HEADER hdr;437 u8 Data[252];438} __attribute__ ((__packed__));439 440 441struct ngene_command {442 u32 in_len;443 u32 out_len;444 union {445 u32 raw[64];446 u8 raw8[256];447 struct FW_HEADER hdr;448 struct FW_I2C_WRITE I2CWrite;449 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite;450 struct FW_I2C_READ I2CRead;451 struct FW_STREAM_CONTROL StreamControl;452 struct FW_FWLOAD_PREPARE FWLoadPrepare;453 struct FW_FWLOAD_FINISH FWLoadFinish;454 struct FW_MEM_READ MemoryRead;455 struct FW_MEM_WRITE MemoryWrite;456 struct FW_SFR_IRAM_READ SfrIramRead;457 struct FW_SFR_IRAM_WRITE SfrIramWrite;458 struct FW_SPI_WRITE SPIWrite;459 struct FW_SPI_READ SPIRead;460 struct FW_SET_GPIO_PIN SetGpioPin;461 struct FW_SET_GPIO_INT SetGpioInt;462 struct FW_SET_DEBUGMODE SetDebugMode;463 struct FW_CONFIGURE_BUFFERS ConfigureBuffers;464 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers;465 struct FW_CONFIGURE_UART ConfigureUart;466 struct FW_WRITE_UART WriteUart;467 } cmd;468} __attribute__ ((__packed__));469 470#define NGENE_INTERFACE_VERSION 0x103471#define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */472#define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */473#define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */474#define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */475#define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page476 Max: (1920x1080i60) */477 478#define OVERFLOW_BUFFER_SIZE (8192)479 480#define RING_SIZE_VIDEO 4481#define RING_SIZE_AUDIO 8482#define RING_SIZE_TS 8483 484#define NUM_SCATTER_GATHER_ENTRIES 8485 486#define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \487 RING_SIZE_VIDEO * 2) + \488 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \489 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \490 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \491 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \492 (RING_SIZE_TS * PAGE_SIZE * 4) + \493 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE)494 495#define EVENT_QUEUE_SIZE 16496 497/* Gathers the current state of a single channel. */498 499struct SBufferHeader {500 struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */501 struct SBufferHeader *Next;502 void *Buffer1;503 struct HW_SCATTER_GATHER_ELEMENT *scList1;504 void *Buffer2;505 struct HW_SCATTER_GATHER_ELEMENT *scList2;506};507 508/* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */509#define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63)510 511enum HWSTATE {512 HWSTATE_STOP,513 HWSTATE_STARTUP,514 HWSTATE_RUN,515 HWSTATE_PAUSE,516};517 518enum KSSTATE {519 KSSTATE_STOP,520 KSSTATE_ACQUIRE,521 KSSTATE_PAUSE,522 KSSTATE_RUN,523};524 525struct SRingBufferDescriptor {526 struct SBufferHeader *Head; /* Points to first buffer in ring buffer527 structure*/528 u64 PAHead; /* Physical address of first buffer */529 u32 MemSize; /* Memory size of allocated ring buffers530 (needed for freeing) */531 u32 NumBuffers; /* Number of buffers in the ring */532 u32 Buffer1Length; /* Allocated length of Buffer 1 */533 u32 Buffer2Length; /* Allocated length of Buffer 2 */534 void *SCListMem; /* Memory to hold scatter gather lists for this535 ring */536 u64 PASCListMem; /* Physical address .. */537 u32 SCListMemSize; /* Size of this memory */538};539 540enum STREAMMODEFLAGS {541 StreamMode_NONE = 0, /* Stream not used */542 StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */543 StreamMode_TSIN = 2, /* Transport stream input (all) */544 StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60545 (only stream 0) */546 StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */547};548 549 550enum BufferExchangeFlags {551 BEF_EVEN_FIELD = 0x00000001,552 BEF_CONTINUATION = 0x00000002,553 BEF_MORE_DATA = 0x00000004,554 BEF_OVERFLOW = 0x00000008,555 DF_SWAP32 = 0x00010000,556};557 558typedef void *(IBufferExchange)(void *, void *, u32, u32, u32);559 560struct MICI_STREAMINFO {561 IBufferExchange *pExchange;562 IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */563 u8 Stream;564 u8 Flags;565 u8 Mode;566 u8 Reserved;567 u16 nLinesVideo;568 u16 nBytesPerLineVideo;569 u16 nLinesVBI;570 u16 nBytesPerLineVBI;571 u32 CaptureLength; /* Used for audio and transport stream */572};573 574/****************************************************************************/575/* STRUCTS ******************************************************************/576/****************************************************************************/577 578/* sound hardware definition */579#define MIXER_ADDR_TVTUNER 0580#define MIXER_ADDR_LAST 0581 582struct ngene_channel;583 584/*struct sound chip*/585 586struct mychip {587 struct ngene_channel *chan;588 struct snd_card *card;589 struct pci_dev *pci;590 struct snd_pcm_substream *substream;591 struct snd_pcm *pcm;592 unsigned long port;593 int irq;594 spinlock_t mixer_lock;595 spinlock_t lock;596 int mixer_volume[MIXER_ADDR_LAST + 1][2];597 int capture_source[MIXER_ADDR_LAST + 1][2];598};599 600struct ngene_channel {601 struct device device;602 struct i2c_adapter i2c_adapter;603 struct i2c_client *i2c_client[1];604 int i2c_client_fe;605 606 struct ngene *dev;607 int number;608 int type;609 int mode;610 bool has_adapter;611 bool has_demux;612 int demod_type;613 int (*gate_ctrl)(struct dvb_frontend *, int);614 615 struct dvb_frontend *fe;616 struct dvb_frontend *fe2;617 struct dmxdev dmxdev;618 struct dvb_demux demux;619 struct dvb_net dvbnet;620 struct dmx_frontend hw_frontend;621 struct dmx_frontend mem_frontend;622 int users;623 struct video_device *v4l_dev;624 struct dvb_device *ci_dev;625 struct work_struct demux_bh_work;626 627 struct SBufferHeader *nextBuffer;628 enum KSSTATE State;629 enum HWSTATE HWState;630 u8 Stream;631 u8 Flags;632 u8 Mode;633 IBufferExchange *pBufferExchange;634 IBufferExchange *pBufferExchange2;635 636 spinlock_t state_lock;637 u16 nLines;638 u16 nBytesPerLine;639 u16 nVBILines;640 u16 nBytesPerVBILine;641 u16 itumode;642 u32 Capture1Length;643 u32 Capture2Length;644 struct SRingBufferDescriptor RingBuffer;645 struct SRingBufferDescriptor TSRingBuffer;646 struct SRingBufferDescriptor TSIdleBuffer;647 648 u32 DataFormatFlags;649 650 int AudioDTOUpdated;651 u32 AudioDTOValue;652 653 int (*set_tone)(struct dvb_frontend *, enum fe_sec_tone_mode);654 u8 lnbh;655 656 /* stuff from analog driver */657 658 int minor;659 struct mychip *mychip;660 struct snd_card *soundcard;661 u8 *evenbuffer;662 u8 dma_on;663 int soundstreamon;664 int audiomute;665 int soundbuffisallocated;666 int sndbuffflag;667 int tun_rdy;668 int dec_rdy;669 int tun_dec_rdy;670 int lastbufferflag;671 672 struct ngene_tvnorm *tvnorms;673 int tvnorm_num;674 int tvnorm;675 676 int running;677 678 int tsin_offset;679 u8 tsin_buffer[188];680};681 682 683struct ngene_ci {684 struct device device;685 struct i2c_adapter i2c_adapter;686 687 struct ngene *dev;688 struct dvb_ca_en50221 *en;689};690 691struct ngene;692 693typedef void (rx_cb_t)(struct ngene *, u32, u8);694typedef void (tx_cb_t)(struct ngene *, u32);695 696struct ngene {697 int nr;698 struct pci_dev *pci_dev;699 unsigned char __iomem *iomem;700 701 /*struct i2c_adapter i2c_adapter;*/702 703 u32 device_version;704 u32 fw_interface_version;705 u32 icounts;706 bool msi_enabled;707 bool cmd_timeout_workaround;708 709 u8 *CmdDoneByte;710 int BootFirmware;711 void *OverflowBuffer;712 dma_addr_t PAOverflowBuffer;713 void *FWInterfaceBuffer;714 dma_addr_t PAFWInterfaceBuffer;715 u8 *ngenetohost;716 u8 *hosttongene;717 718 struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE];719 int EventQueueOverflowCount;720 int EventQueueOverflowFlag;721 struct work_struct event_bh_work;722 struct EVENT_BUFFER *EventBuffer;723 int EventQueueWriteIndex;724 int EventQueueReadIndex;725 726 wait_queue_head_t cmd_wq;727 int cmd_done;728 struct mutex cmd_mutex;729 struct mutex stream_mutex;730 struct semaphore pll_mutex;731 struct mutex i2c_switch_mutex;732 int i2c_current_channel;733 int i2c_current_bus;734 spinlock_t cmd_lock;735 736 struct dvb_adapter adapter[MAX_STREAM];737 struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */738 struct ngene_channel channel[MAX_STREAM];739 740 struct ngene_info *card_info;741 742 tx_cb_t *TxEventNotify;743 rx_cb_t *RxEventNotify;744 int tx_busy;745 wait_queue_head_t tx_wq;746 wait_queue_head_t rx_wq;747#define UART_RBUF_LEN 4096748 u8 uart_rbuf[UART_RBUF_LEN];749 int uart_rp, uart_wp;750 751#define TS_FILLER 0x6f752 753 u8 *tsout_buf;754#define TSOUT_BUF_SIZE (512*188*8)755 struct dvb_ringbuffer tsout_rbuf;756 757 u8 *tsin_buf;758#define TSIN_BUF_SIZE (512*188*8)759 struct dvb_ringbuffer tsin_rbuf;760 761 u8 *ain_buf;762#define AIN_BUF_SIZE (128*1024)763 struct dvb_ringbuffer ain_rbuf;764 765 766 u8 *vin_buf;767#define VIN_BUF_SIZE (4*1920*1080)768 struct dvb_ringbuffer vin_rbuf;769 770 unsigned long exp_val;771 int prev_cmd;772 773 struct ngene_ci ci;774};775 776struct ngene_info {777 int type;778#define NGENE_APP 0779#define NGENE_TERRATEC 1780#define NGENE_SIDEWINDER 2781#define NGENE_RACER 3782#define NGENE_VIPER 4783#define NGENE_PYTHON 5784#define NGENE_VBOX_V1 6785#define NGENE_VBOX_V2 7786 787 int fw_version;788 bool msi_supported;789 char *name;790 791 int io_type[MAX_STREAM];792#define NGENE_IO_NONE 0793#define NGENE_IO_TV 1794#define NGENE_IO_HDTV 2795#define NGENE_IO_TSIN 4796#define NGENE_IO_TSOUT 8797#define NGENE_IO_AIN 16798 799 void *fe_config[4];800 void *tuner_config[4];801 802 int (*demod_attach[4])(struct ngene_channel *);803 int (*tuner_attach[4])(struct ngene_channel *);804 805 u8 avf[4];806 u8 msp[4];807 u8 demoda[4];808 u8 lnb[4];809 int i2c_access;810 u8 ntsc;811 u8 tsf[4];812 u8 i2s[4];813 814 int (*gate_ctrl)(struct dvb_frontend *, int);815 int (*switch_ctrl)(struct ngene_channel *, int, int);816};817 818 819/* Provided by ngene-core.c */820int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id);821void ngene_remove(struct pci_dev *pdev);822void ngene_shutdown(struct pci_dev *pdev);823int ngene_command(struct ngene *dev, struct ngene_command *com);824int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level);825void set_transfer(struct ngene_channel *chan, int state);826void FillTSBuffer(void *Buffer, int Length, u32 Flags);827 828/* Provided by ngene-cards.c */829int ngene_port_has_cxd2099(struct i2c_adapter *i2c, u8 *type);830 831/* Provided by ngene-i2c.c */832int ngene_i2c_init(struct ngene *dev, int dev_nr);833 834/* Provided by ngene-dvb.c */835extern struct dvb_device ngene_dvbdev_ci;836void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);837void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags);838int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed);839int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed);840int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id,841 int (*start_feed)(struct dvb_demux_feed *),842 int (*stop_feed)(struct dvb_demux_feed *),843 void *priv);844int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev,845 struct dvb_demux *dvbdemux,846 struct dmx_frontend *hw_frontend,847 struct dmx_frontend *mem_frontend,848 struct dvb_adapter *dvb_adapter);849 850#endif851 852/* LocalWords: Endif853 */854