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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * SMI PCIe driver for DVBSky cards.4 *5 * Copyright (C) 2014 Max nibble <nibble.max@gmail.com>6 */7 8#ifndef _SMI_PCIE_H_9#define _SMI_PCIE_H_10 11#include <linux/i2c.h>12#include <linux/i2c-algo-bit.h>13#include <linux/init.h>14#include <linux/interrupt.h>15#include <linux/kernel.h>16#include <linux/module.h>17#include <linux/pci.h>18#include <linux/dma-mapping.h>19#include <linux/slab.h>20#include <linux/workqueue.h>21#include <media/rc-core.h>22 23#include <media/demux.h>24#include <media/dmxdev.h>25#include <media/dvb_demux.h>26#include <media/dvb_frontend.h>27#include <media/dvb_net.h>28#include <media/dvbdev.h>29 30/* -------- Register Base -------- */31#define MSI_CONTROL_REG_BASE 0x080032#define SYSTEM_CONTROL_REG_BASE 0x088033#define PCIE_EP_DEBUG_REG_BASE 0x08C034#define IR_CONTROL_REG_BASE 0x090035#define I2C_A_CONTROL_REG_BASE 0x094036#define I2C_B_CONTROL_REG_BASE 0x098037#define ATV_PORTA_CONTROL_REG_BASE 0x09C038#define DTV_PORTA_CONTROL_REG_BASE 0x0A0039#define AES_PORTA_CONTROL_REG_BASE 0x0A8040#define DMA_PORTA_CONTROL_REG_BASE 0x0AC041#define ATV_PORTB_CONTROL_REG_BASE 0x0B0042#define DTV_PORTB_CONTROL_REG_BASE 0x0B4043#define AES_PORTB_CONTROL_REG_BASE 0x0BC044#define DMA_PORTB_CONTROL_REG_BASE 0x0C0045#define UART_A_REGISTER_BASE 0x0C4046#define UART_B_REGISTER_BASE 0x0C8047#define GPS_CONTROL_REG_BASE 0x0CC048#define DMA_PORTC_CONTROL_REG_BASE 0x0D0049#define DMA_PORTD_CONTROL_REG_BASE 0x0D0050#define AES_RANDOM_DATA_BASE 0x0D8051#define AES_KEY_IN_BASE 0x0D9052#define RANDOM_DATA_LIB_BASE 0x0E0053#define IR_DATA_BUFFER_BASE 0x0F0054#define PORTA_TS_BUFFER_BASE 0x100055#define PORTA_I2S_BUFFER_BASE 0x140056#define PORTB_TS_BUFFER_BASE 0x180057#define PORTB_I2S_BUFFER_BASE 0x1C0058 59/* -------- MSI control and state register -------- */60#define MSI_DELAY_TIMER (MSI_CONTROL_REG_BASE + 0x00)61#define MSI_INT_STATUS (MSI_CONTROL_REG_BASE + 0x08)62#define MSI_INT_STATUS_CLR (MSI_CONTROL_REG_BASE + 0x0C)63#define MSI_INT_STATUS_SET (MSI_CONTROL_REG_BASE + 0x10)64#define MSI_INT_ENA (MSI_CONTROL_REG_BASE + 0x14)65#define MSI_INT_ENA_CLR (MSI_CONTROL_REG_BASE + 0x18)66#define MSI_INT_ENA_SET (MSI_CONTROL_REG_BASE + 0x1C)67#define MSI_SOFT_RESET (MSI_CONTROL_REG_BASE + 0x20)68#define MSI_CFG_SRC0 (MSI_CONTROL_REG_BASE + 0x24)69 70/* -------- Hybird Controller System Control register -------- */71#define MUX_MODE_CTRL (SYSTEM_CONTROL_REG_BASE + 0x00)72 #define rbPaMSMask 0x0773 #define rbPaMSDtvNoGpio 0x00 /*[2:0], DTV Simple mode */74 #define rbPaMSDtv4bitGpio 0x01 /*[2:0], DTV TS2 Serial mode)*/75 #define rbPaMSDtv7bitGpio 0x02 /*[2:0], DTV TS0 Serial mode*/76 #define rbPaMS8bitGpio 0x03 /*[2:0], GPIO mode selected;(8bit GPIO)*/77 #define rbPaMSAtv 0x04 /*[2:0], 3'b1xx: ATV mode select*/78 #define rbPbMSMask 0x3879 #define rbPbMSDtvNoGpio 0x00 /*[5:3], DTV Simple mode */80 #define rbPbMSDtv4bitGpio 0x08 /*[5:3], DTV TS2 Serial mode*/81 #define rbPbMSDtv7bitGpio 0x10 /*[5:3], DTV TS0 Serial mode*/82 #define rbPbMS8bitGpio 0x18 /*[5:3], GPIO mode selected;(8bit GPIO)*/83 #define rbPbMSAtv 0x20 /*[5:3], 3'b1xx: ATV mode select*/84 #define rbPaAESEN 0x40 /*[6], port A AES enable bit*/85 #define rbPbAESEN 0x80 /*[7], port B AES enable bit*/86 87#define INTERNAL_RST (SYSTEM_CONTROL_REG_BASE + 0x04)88#define PERIPHERAL_CTRL (SYSTEM_CONTROL_REG_BASE + 0x08)89#define GPIO_0to7_CTRL (SYSTEM_CONTROL_REG_BASE + 0x0C)90#define GPIO_8to15_CTRL (SYSTEM_CONTROL_REG_BASE + 0x10)91#define GPIO_16to24_CTRL (SYSTEM_CONTROL_REG_BASE + 0x14)92#define GPIO_INT_SRC_CFG (SYSTEM_CONTROL_REG_BASE + 0x18)93#define SYS_BUF_STATUS (SYSTEM_CONTROL_REG_BASE + 0x1C)94#define PCIE_IP_REG_ACS (SYSTEM_CONTROL_REG_BASE + 0x20)95#define PCIE_IP_REG_ACS_ADDR (SYSTEM_CONTROL_REG_BASE + 0x24)96#define PCIE_IP_REG_ACS_DATA (SYSTEM_CONTROL_REG_BASE + 0x28)97 98/* -------- IR Control register -------- */99#define IR_Init_Reg (IR_CONTROL_REG_BASE + 0x00)100#define IR_Idle_Cnt_Low (IR_CONTROL_REG_BASE + 0x04)101#define IR_Idle_Cnt_High (IR_CONTROL_REG_BASE + 0x05)102#define IR_Unit_Cnt_Low (IR_CONTROL_REG_BASE + 0x06)103#define IR_Unit_Cnt_High (IR_CONTROL_REG_BASE + 0x07)104#define IR_Data_Cnt (IR_CONTROL_REG_BASE + 0x08)105#define rbIRen 0x80106#define rbIRhighidle 0x10107#define rbIRlowidle 0x00108#define rbIRVld 0x04109 110/* -------- I2C A control and state register -------- */111#define I2C_A_CTL_STATUS (I2C_A_CONTROL_REG_BASE + 0x00)112#define I2C_A_ADDR (I2C_A_CONTROL_REG_BASE + 0x04)113#define I2C_A_SW_CTL (I2C_A_CONTROL_REG_BASE + 0x08)114#define I2C_A_TIME_OUT_CNT (I2C_A_CONTROL_REG_BASE + 0x0C)115#define I2C_A_FIFO_STATUS (I2C_A_CONTROL_REG_BASE + 0x10)116#define I2C_A_FS_EN (I2C_A_CONTROL_REG_BASE + 0x14)117#define I2C_A_FIFO_DATA (I2C_A_CONTROL_REG_BASE + 0x20)118 119/* -------- I2C B control and state register -------- */120#define I2C_B_CTL_STATUS (I2C_B_CONTROL_REG_BASE + 0x00)121#define I2C_B_ADDR (I2C_B_CONTROL_REG_BASE + 0x04)122#define I2C_B_SW_CTL (I2C_B_CONTROL_REG_BASE + 0x08)123#define I2C_B_TIME_OUT_CNT (I2C_B_CONTROL_REG_BASE + 0x0C)124#define I2C_B_FIFO_STATUS (I2C_B_CONTROL_REG_BASE + 0x10)125#define I2C_B_FS_EN (I2C_B_CONTROL_REG_BASE + 0x14)126#define I2C_B_FIFO_DATA (I2C_B_CONTROL_REG_BASE + 0x20)127 128#define VIDEO_CTRL_STATUS_A (ATV_PORTA_CONTROL_REG_BASE + 0x04)129 130/* -------- Digital TV control register, Port A -------- */131#define MPEG2_CTRL_A (DTV_PORTA_CONTROL_REG_BASE + 0x00)132#define SERIAL_IN_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x4C)133#define VLD_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x60)134#define ERR_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x64)135#define BRD_CNT_ADDR_A (DTV_PORTA_CONTROL_REG_BASE + 0x68)136 137/* -------- DMA Control Register, Port A -------- */138#define DMA_PORTA_CHAN0_ADDR_LOW (DMA_PORTA_CONTROL_REG_BASE + 0x00)139#define DMA_PORTA_CHAN0_ADDR_HI (DMA_PORTA_CONTROL_REG_BASE + 0x04)140#define DMA_PORTA_CHAN0_TRANS_STATE (DMA_PORTA_CONTROL_REG_BASE + 0x08)141#define DMA_PORTA_CHAN0_CONTROL (DMA_PORTA_CONTROL_REG_BASE + 0x0C)142#define DMA_PORTA_CHAN1_ADDR_LOW (DMA_PORTA_CONTROL_REG_BASE + 0x10)143#define DMA_PORTA_CHAN1_ADDR_HI (DMA_PORTA_CONTROL_REG_BASE + 0x14)144#define DMA_PORTA_CHAN1_TRANS_STATE (DMA_PORTA_CONTROL_REG_BASE + 0x18)145#define DMA_PORTA_CHAN1_CONTROL (DMA_PORTA_CONTROL_REG_BASE + 0x1C)146#define DMA_PORTA_MANAGEMENT (DMA_PORTA_CONTROL_REG_BASE + 0x20)147#define VIDEO_CTRL_STATUS_B (ATV_PORTB_CONTROL_REG_BASE + 0x04)148 149/* -------- Digital TV control register, Port B -------- */150#define MPEG2_CTRL_B (DTV_PORTB_CONTROL_REG_BASE + 0x00)151#define SERIAL_IN_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x4C)152#define VLD_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x60)153#define ERR_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x64)154#define BRD_CNT_ADDR_B (DTV_PORTB_CONTROL_REG_BASE + 0x68)155 156/* -------- AES control register, Port B -------- */157#define AES_CTRL_B (AES_PORTB_CONTROL_REG_BASE + 0x00)158#define AES_KEY_BASE_B (AES_PORTB_CONTROL_REG_BASE + 0x04)159 160/* -------- DMA Control Register, Port B -------- */161#define DMA_PORTB_CHAN0_ADDR_LOW (DMA_PORTB_CONTROL_REG_BASE + 0x00)162#define DMA_PORTB_CHAN0_ADDR_HI (DMA_PORTB_CONTROL_REG_BASE + 0x04)163#define DMA_PORTB_CHAN0_TRANS_STATE (DMA_PORTB_CONTROL_REG_BASE + 0x08)164#define DMA_PORTB_CHAN0_CONTROL (DMA_PORTB_CONTROL_REG_BASE + 0x0C)165#define DMA_PORTB_CHAN1_ADDR_LOW (DMA_PORTB_CONTROL_REG_BASE + 0x10)166#define DMA_PORTB_CHAN1_ADDR_HI (DMA_PORTB_CONTROL_REG_BASE + 0x14)167#define DMA_PORTB_CHAN1_TRANS_STATE (DMA_PORTB_CONTROL_REG_BASE + 0x18)168#define DMA_PORTB_CHAN1_CONTROL (DMA_PORTB_CONTROL_REG_BASE + 0x1C)169#define DMA_PORTB_MANAGEMENT (DMA_PORTB_CONTROL_REG_BASE + 0x20)170 171#define DMA_TRANS_UNIT_188 (0x00000007)172 173/* -------- Macro define of 24 interrupt resource --------*/174#define DMA_A_CHAN0_DONE_INT (0x00000001)175#define DMA_A_CHAN1_DONE_INT (0x00000002)176#define DMA_B_CHAN0_DONE_INT (0x00000004)177#define DMA_B_CHAN1_DONE_INT (0x00000008)178#define DMA_C_CHAN0_DONE_INT (0x00000010)179#define DMA_C_CHAN1_DONE_INT (0x00000020)180#define DMA_D_CHAN0_DONE_INT (0x00000040)181#define DMA_D_CHAN1_DONE_INT (0x00000080)182#define DATA_BUF_OVERFLOW_INT (0x00000100)183#define UART_0_X_INT (0x00000200)184#define UART_1_X_INT (0x00000400)185#define IR_X_INT (0x00000800)186#define GPIO_0_INT (0x00001000)187#define GPIO_1_INT (0x00002000)188#define GPIO_2_INT (0x00004000)189#define GPIO_3_INT (0x00008000)190#define ALL_INT (0x0000FFFF)191 192/* software I2C bit mask */193#define SW_I2C_MSK_MODE 0x01194#define SW_I2C_MSK_CLK_OUT 0x02195#define SW_I2C_MSK_DAT_OUT 0x04196#define SW_I2C_MSK_CLK_EN 0x08197#define SW_I2C_MSK_DAT_EN 0x10198#define SW_I2C_MSK_DAT_IN 0x40199#define SW_I2C_MSK_CLK_IN 0x80200 201#define SMI_VID 0x1ADE202#define SMI_PID 0x3038203#define SMI_TS_DMA_BUF_SIZE (1024 * 188)204 205struct smi_cfg_info {206#define SMI_DVBSKY_S952 0207#define SMI_DVBSKY_S950 1208#define SMI_DVBSKY_T9580 2209#define SMI_DVBSKY_T982 3210#define SMI_TECHNOTREND_S2_4200 4211 int type;212 char *name;213#define SMI_TS_NULL 0214#define SMI_TS_DMA_SINGLE 1215#define SMI_TS_DMA_BOTH 3216/* SMI_TS_NULL: not use;217 * SMI_TS_DMA_SINGLE: use DMA 0 only;218 * SMI_TS_DMA_BOTH:use DMA 0 and 1.*/219 int ts_0;220 int ts_1;221#define DVBSKY_FE_NULL 0222#define DVBSKY_FE_M88RS6000 1223#define DVBSKY_FE_M88DS3103 2224#define DVBSKY_FE_SIT2 3225 int fe_0;226 int fe_1;227 char *rc_map;228};229 230struct smi_rc {231 struct smi_dev *dev;232 struct rc_dev *rc_dev;233 char input_phys[64];234 char device_name[64];235 u8 irData[256];236 237 int users;238};239 240struct smi_port {241 struct smi_dev *dev;242 int idx;243 int enable;244 int fe_type;245 /* regs */246 u32 DMA_CHAN0_ADDR_LOW;247 u32 DMA_CHAN0_ADDR_HI;248 u32 DMA_CHAN0_TRANS_STATE;249 u32 DMA_CHAN0_CONTROL;250 u32 DMA_CHAN1_ADDR_LOW;251 u32 DMA_CHAN1_ADDR_HI;252 u32 DMA_CHAN1_TRANS_STATE;253 u32 DMA_CHAN1_CONTROL;254 u32 DMA_MANAGEMENT;255 /* dma */256 dma_addr_t dma_addr[2];257 u8 *cpu_addr[2];258 u32 _dmaInterruptCH0;259 u32 _dmaInterruptCH1;260 u32 _int_status;261 struct work_struct bh_work;262 /* dvb */263 struct dmx_frontend hw_frontend;264 struct dmx_frontend mem_frontend;265 struct dmxdev dmxdev;266 struct dvb_adapter dvb_adapter;267 struct dvb_demux demux;268 struct dvb_net dvbnet;269 int users;270 struct dvb_frontend *fe;271 /* frontend i2c module */272 struct i2c_client *i2c_client_demod;273 struct i2c_client *i2c_client_tuner;274};275 276struct smi_dev {277 int nr;278 struct smi_cfg_info *info;279 280 /* pcie */281 struct pci_dev *pci_dev;282 u32 __iomem *lmmio;283 284 /* ts port */285 struct smi_port ts_port[2];286 287 /* i2c */288 struct i2c_adapter i2c_bus[2];289 struct i2c_algo_bit_data i2c_bit[2];290 291 /* ir */292 struct smi_rc ir;293};294 295#define smi_read(reg) readl(dev->lmmio + ((reg)>>2))296#define smi_write(reg, value) writel((value), dev->lmmio + ((reg)>>2))297 298#define smi_andor(reg, mask, value) \299 writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\300 ((value) & (mask)), dev->lmmio+((reg)>>2))301 302#define smi_set(reg, bit) smi_andor((reg), (bit), (bit))303#define smi_clear(reg, bit) smi_andor((reg), (bit), 0)304 305int smi_ir_irq(struct smi_rc *ir, u32 int_status);306void smi_ir_start(struct smi_rc *ir);307void smi_ir_exit(struct smi_dev *dev);308int smi_ir_init(struct smi_dev *dev);309 310#endif /* #ifndef _SMI_PCIE_H_ */311