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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Zoran ZR36050 basic configuration functions - header file4 *5 * Copyright (C) 2001 Wolfgang Scherr <scherr@net4you.at>6 */7 8#ifndef ZR36050_H9#define ZR36050_H10 11#include "videocodec.h"12 13/* data stored for each zoran jpeg codec chip */14struct zr36050 {15	char name[32];16	int num;17	/* io datastructure */18	struct videocodec *codec;19	// last coder status20	__u8 status1;21	// actual coder setup22	int mode;23 24	__u16 width;25	__u16 height;26 27	__u16 bitrate_ctrl;28 29	__u32 total_code_vol;30	__u32 real_code_vol;31	__u16 max_block_vol;32 33	__u8 h_samp_ratio[8];34	__u8 v_samp_ratio[8];35	__u16 scalefact;36	__u16 dri;37 38	/* com/app marker */39	struct jpeg_com_marker com;40	struct jpeg_app_marker app;41};42 43/* zr36050 register addresses */44#define ZR050_GO                  0x00045#define ZR050_HARDWARE            0x00246#define ZR050_MODE                0x00347#define ZR050_OPTIONS             0x00448#define ZR050_MBCV                0x00549#define ZR050_MARKERS_EN          0x00650#define ZR050_INT_REQ_0           0x00751#define ZR050_INT_REQ_1           0x00852#define ZR050_TCV_NET_HI          0x00953#define ZR050_TCV_NET_MH          0x00a54#define ZR050_TCV_NET_ML          0x00b55#define ZR050_TCV_NET_LO          0x00c56#define ZR050_TCV_DATA_HI         0x00d57#define ZR050_TCV_DATA_MH         0x00e58#define ZR050_TCV_DATA_ML         0x00f59#define ZR050_TCV_DATA_LO         0x01060#define ZR050_SF_HI               0x01161#define ZR050_SF_LO               0x01262#define ZR050_AF_HI               0x01363#define ZR050_AF_M                0x01464#define ZR050_AF_LO               0x01565#define ZR050_ACV_HI              0x01666#define ZR050_ACV_MH              0x01767#define ZR050_ACV_ML              0x01868#define ZR050_ACV_LO              0x01969#define ZR050_ACT_HI              0x01a70#define ZR050_ACT_MH              0x01b71#define ZR050_ACT_ML              0x01c72#define ZR050_ACT_LO              0x01d73#define ZR050_ACV_TURN_HI         0x01e74#define ZR050_ACV_TURN_MH         0x01f75#define ZR050_ACV_TURN_ML         0x02076#define ZR050_ACV_TURN_LO         0x02177#define ZR050_STATUS_0            0x02e78#define ZR050_STATUS_1            0x02f79 80#define ZR050_SOF_IDX             0x04081#define ZR050_SOS1_IDX            0x07a82#define ZR050_SOS2_IDX            0x08a83#define ZR050_SOS3_IDX            0x09a84#define ZR050_SOS4_IDX            0x0aa85#define ZR050_DRI_IDX             0x0c086#define ZR050_DNL_IDX             0x0c687#define ZR050_DQT_IDX             0x0cc88#define ZR050_DHT_IDX             0x1d489#define ZR050_APP_IDX             0x38090#define ZR050_COM_IDX             0x3c091 92/* zr36050 hardware register bits */93 94#define ZR050_HW_BSWD                0x8095#define ZR050_HW_MSTR                0x4096#define ZR050_HW_DMA                 0x2097#define ZR050_HW_CFIS_1_CLK          0x0098#define ZR050_HW_CFIS_2_CLK          0x0499#define ZR050_HW_CFIS_3_CLK          0x08100#define ZR050_HW_CFIS_4_CLK          0x0C101#define ZR050_HW_CFIS_5_CLK          0x10102#define ZR050_HW_CFIS_6_CLK          0x14103#define ZR050_HW_CFIS_7_CLK          0x18104#define ZR050_HW_CFIS_8_CLK          0x1C105#define ZR050_HW_BELE                0x01106 107/* zr36050 mode register bits */108 109#define ZR050_MO_COMP                0x80110#define ZR050_MO_ATP                 0x40111#define ZR050_MO_PASS2               0x20112#define ZR050_MO_TLM                 0x10113#define ZR050_MO_DCONLY              0x08114#define ZR050_MO_BRC                 0x04115 116#define ZR050_MO_ATP                 0x40117#define ZR050_MO_PASS2               0x20118#define ZR050_MO_TLM                 0x10119#define ZR050_MO_DCONLY              0x08120 121/* zr36050 option register bits */122 123#define ZR050_OP_NSCN_1              0x00124#define ZR050_OP_NSCN_2              0x20125#define ZR050_OP_NSCN_3              0x40126#define ZR050_OP_NSCN_4              0x60127#define ZR050_OP_NSCN_5              0x80128#define ZR050_OP_NSCN_6              0xA0129#define ZR050_OP_NSCN_7              0xC0130#define ZR050_OP_NSCN_8              0xE0131#define ZR050_OP_OVF                 0x10132 133/* zr36050 markers-enable register bits */134 135#define ZR050_ME_APP                 0x80136#define ZR050_ME_COM                 0x40137#define ZR050_ME_DRI                 0x20138#define ZR050_ME_DQT                 0x10139#define ZR050_ME_DHT                 0x08140#define ZR050_ME_DNL                 0x04141#define ZR050_ME_DQTI                0x02142#define ZR050_ME_DHTI                0x01143 144/* zr36050 status0/1 register bit masks */145 146#define ZR050_ST_RST_MASK            0x20147#define ZR050_ST_SOF_MASK            0x02148#define ZR050_ST_SOS_MASK            0x02149#define ZR050_ST_DATRDY_MASK         0x80150#define ZR050_ST_MRKDET_MASK         0x40151#define ZR050_ST_RFM_MASK            0x10152#define ZR050_ST_RFD_MASK            0x08153#define ZR050_ST_END_MASK            0x04154#define ZR050_ST_TCVOVF_MASK         0x02155#define ZR050_ST_DATOVF_MASK         0x01156 157/* pixel component idx */158 159#define ZR050_Y_COMPONENT         0160#define ZR050_U_COMPONENT         1161#define ZR050_V_COMPONENT         2162 163int zr36050_init_module(void);164void zr36050_cleanup_module(void);165#endif				/*fndef ZR36050_H */166