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1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * zr36057.h - zr36057 register offsets4 *5 * Copyright (C) 1998 Dave Perks <dperks@ibm.net>6 */7 8#ifndef _ZR36057_H_9#define _ZR36057_H_10 11/* Zoran ZR36057 registers */12 13#define ZR36057_VFEHCR 0x000 /* Video Front End, Horizontal Configuration Register */14#define ZR36057_VFEHCR_HS_POL BIT(30)15#define ZR36057_VFEHCR_H_START 1016#define ZR36057_VFEHCR_H_END 017#define ZR36057_VFEHCR_HMASK 0x3ff18 19#define ZR36057_VFEVCR 0x004 /* Video Front End, Vertical Configuration Register */20#define ZR36057_VFEVCR_VS_POL BIT(30)21#define ZR36057_VFEVCR_V_START 1022#define ZR36057_VFEVCR_V_END 023#define ZR36057_VFEVCR_VMASK 0x3ff24 25#define ZR36057_VFESPFR 0x008 /* Video Front End, Scaler and Pixel Format Register */26#define ZR36057_VFESPFR_EXT_FL BIT(26)27#define ZR36057_VFESPFR_TOP_FIELD BIT(25)28#define ZR36057_VFESPFR_VCLK_POL BIT(24)29#define ZR36057_VFESPFR_H_FILTER 2130#define ZR36057_VFESPFR_HOR_DCM 1431#define ZR36057_VFESPFR_VER_DCM 832#define ZR36057_VFESPFR_DISP_MODE 633#define ZR36057_VFESPFR_YUV422 (0 << 3)34#define ZR36057_VFESPFR_RGB888 (1 << 3)35#define ZR36057_VFESPFR_RGB565 (2 << 3)36#define ZR36057_VFESPFR_RGB555 (3 << 3)37#define ZR36057_VFESPFR_ERR_DIF BIT(2)38#define ZR36057_VFESPFR_PACK24 BIT(1)39#define ZR36057_VFESPFR_LITTLE_ENDIAN BIT(0)40 41#define ZR36057_VDTR 0x00c /* Video Display "Top" Register */42 43#define ZR36057_VDBR 0x010 /* Video Display "Bottom" Register */44 45#define ZR36057_VSSFGR 0x014 /* Video Stride, Status, and Frame Grab Register */46#define ZR36057_VSSFGR_DISP_STRIDE 1647#define ZR36057_VSSFGR_VID_OVF BIT(8)48#define ZR36057_VSSFGR_SNAP_SHOT BIT(1)49#define ZR36057_VSSFGR_FRAME_GRAB BIT(0)50 51#define ZR36057_VDCR 0x018 /* Video Display Configuration Register */52#define ZR36057_VDCR_VID_EN BIT(31)53#define ZR36057_VDCR_MIN_PIX 2454#define ZR36057_VDCR_TRITON BIT(24)55#define ZR36057_VDCR_VID_WIN_HT 1256#define ZR36057_VDCR_VID_WIN_WID 057 58#define ZR36057_MMTR 0x01c /* Masking Map "Top" Register */59 60#define ZR36057_MMBR 0x020 /* Masking Map "Bottom" Register */61 62#define ZR36057_OCR 0x024 /* Overlay Control Register */63#define ZR36057_OCR_OVL_ENABLE BIT(15)64#define ZR36057_OCR_MASK_STRIDE 065 66#define ZR36057_SPGPPCR 0x028 /* System, PCI, and General Purpose Pins Control Register */67#define ZR36057_SPGPPCR_SOFT_RESET BIT(24)68 69#define ZR36057_GPPGCR1 0x02c /* General Purpose Pins and GuestBus Control Register (1) */70 71#define ZR36057_MCSAR 0x030 /* MPEG Code Source Address Register */72 73#define ZR36057_MCTCR 0x034 /* MPEG Code Transfer Control Register */74#define ZR36057_MCTCR_COD_TIME BIT(30)75#define ZR36057_MCTCR_C_EMPTY BIT(29)76#define ZR36057_MCTCR_C_FLUSH BIT(28)77#define ZR36057_MCTCR_COD_GUEST_ID 2078#define ZR36057_MCTCR_COD_GUEST_REG 1679 80#define ZR36057_MCMPR 0x038 /* MPEG Code Memory Pointer Register */81 82#define ZR36057_ISR 0x03c /* Interrupt Status Register */83#define ZR36057_ISR_GIRQ1 BIT(30)84#define ZR36057_ISR_GIRQ0 BIT(29)85#define ZR36057_ISR_COD_REP_IRQ BIT(28)86#define ZR36057_ISR_JPEG_REP_IRQ BIT(27)87 88#define ZR36057_ICR 0x040 /* Interrupt Control Register */89#define ZR36057_ICR_GIRQ1 BIT(30)90#define ZR36057_ICR_GIRQ0 BIT(29)91#define ZR36057_ICR_COD_REP_IRQ BIT(28)92#define ZR36057_ICR_JPEG_REP_IRQ BIT(27)93#define ZR36057_ICR_INT_PIN_EN BIT(24)94 95#define ZR36057_I2CBR 0x044 /* I2C Bus Register */96#define ZR36057_I2CBR_SDA BIT(1)97#define ZR36057_I2CBR_SCL BIT(0)98 99#define ZR36057_JMC 0x100 /* JPEG Mode and Control */100#define ZR36057_JMC_JPG BIT(31)101#define ZR36057_JMC_JPG_EXP_MODE (0 << 29)102#define ZR36057_JMC_JPG_CMP_MODE BIT(29)103#define ZR36057_JMC_MJPG_EXP_MODE (2 << 29)104#define ZR36057_JMC_MJPG_CMP_MODE (3 << 29)105#define ZR36057_JMC_RTBUSY_FB BIT(6)106#define ZR36057_JMC_GO_EN BIT(5)107#define ZR36057_JMC_SYNC_MSTR BIT(4)108#define ZR36057_JMC_FLD_PER_BUFF BIT(3)109#define ZR36057_JMC_VFIFO_FB BIT(2)110#define ZR36057_JMC_CFIFO_FB BIT(1)111#define ZR36057_JMC_STLL_LIT_ENDIAN BIT(0)112 113#define ZR36057_JPC 0x104 /* JPEG Process Control */114#define ZR36057_JPC_P_RESET BIT(7)115#define ZR36057_JPC_COD_TRNS_EN BIT(5)116#define ZR36057_JPC_ACTIVE BIT(0)117 118#define ZR36057_VSP 0x108 /* Vertical Sync Parameters */119#define ZR36057_VSP_VSYNC_SIZE 16120#define ZR36057_VSP_FRM_TOT 0121 122#define ZR36057_HSP 0x10c /* Horizontal Sync Parameters */123#define ZR36057_HSP_HSYNC_START 16124#define ZR36057_HSP_LINE_TOT 0125 126#define ZR36057_FHAP 0x110 /* Field Horizontal Active Portion */127#define ZR36057_FHAP_NAX 16128#define ZR36057_FHAP_PAX 0129 130#define ZR36057_FVAP 0x114 /* Field Vertical Active Portion */131#define ZR36057_FVAP_NAY 16132#define ZR36057_FVAP_PAY 0133 134#define ZR36057_FPP 0x118 /* Field Process Parameters */135#define ZR36057_FPP_ODD_EVEN BIT(0)136 137#define ZR36057_JCBA 0x11c /* JPEG Code Base Address */138 139#define ZR36057_JCFT 0x120 /* JPEG Code FIFO Threshold */140 141#define ZR36057_JCGI 0x124 /* JPEG Codec Guest ID */142#define ZR36057_JCGI_JPE_GUEST_ID 4143#define ZR36057_JCGI_JPE_GUEST_REG 0144 145#define ZR36057_GCR2 0x12c /* GuestBus Control Register (2) */146 147#define ZR36057_POR 0x200 /* Post Office Register */148#define ZR36057_POR_PO_PEN BIT(25)149#define ZR36057_POR_PO_TIME BIT(24)150#define ZR36057_POR_PO_DIR BIT(23)151 152#define ZR36057_STR 0x300 /* "Still" Transfer Register */153 154#endif155