204 lines · c
1/* SPDX-License-Identifier: GPL-2.0-or-later */2/*3 * Zoran ZR36060 basic configuration functions - header file4 *5 * Copyright (C) 2002 Laurent Pinchart <laurent.pinchart@skynet.be>6 */7 8#ifndef ZR36060_H9#define ZR36060_H10 11#include "videocodec.h"12 13/* data stored for each zoran jpeg codec chip */14struct zr36060 {15 char name[32];16 int num;17 /* io datastructure */18 struct videocodec *codec;19 // last coder status20 __u8 status;21 // actual coder setup22 int mode;23 24 __u16 width;25 __u16 height;26 27 __u16 bitrate_ctrl;28 29 __u32 total_code_vol;30 __u32 real_code_vol;31 __u16 max_block_vol;32 33 __u8 h_samp_ratio[8];34 __u8 v_samp_ratio[8];35 __u16 scalefact;36 __u16 dri;37 38 /* app/com marker data */39 struct jpeg_app_marker app;40 struct jpeg_com_marker com;41};42 43/* ZR36060 register addresses */44#define ZR060_LOAD 0x00045#define ZR060_CFSR 0x00146#define ZR060_CIR 0x00247#define ZR060_CMR 0x00348#define ZR060_MBZ 0x00449#define ZR060_MBCVR 0x00550#define ZR060_MER 0x00651#define ZR060_IMR 0x00752#define ZR060_ISR 0x00853#define ZR060_TCV_NET_HI 0x00954#define ZR060_TCV_NET_MH 0x00a55#define ZR060_TCV_NET_ML 0x00b56#define ZR060_TCV_NET_LO 0x00c57#define ZR060_TCV_DATA_HI 0x00d58#define ZR060_TCV_DATA_MH 0x00e59#define ZR060_TCV_DATA_ML 0x00f60#define ZR060_TCV_DATA_LO 0x01061#define ZR060_SF_HI 0x01162#define ZR060_SF_LO 0x01263#define ZR060_AF_HI 0x01364#define ZR060_AF_M 0x01465#define ZR060_AF_LO 0x01566#define ZR060_ACV_HI 0x01667#define ZR060_ACV_MH 0x01768#define ZR060_ACV_ML 0x01869#define ZR060_ACV_LO 0x01970#define ZR060_ACT_HI 0x01a71#define ZR060_ACT_MH 0x01b72#define ZR060_ACT_ML 0x01c73#define ZR060_ACT_LO 0x01d74#define ZR060_ACV_TURN_HI 0x01e75#define ZR060_ACV_TURN_MH 0x01f76#define ZR060_ACV_TURN_ML 0x02077#define ZR060_ACV_TURN_LO 0x02178#define ZR060_IDR_DEV 0x02279#define ZR060_IDR_REV 0x02380#define ZR060_TCR_HI 0x02481#define ZR060_TCR_LO 0x02582#define ZR060_VCR 0x03083#define ZR060_VPR 0x03184#define ZR060_SR 0x03285#define ZR060_BCR_Y 0x03386#define ZR060_BCR_U 0x03487#define ZR060_BCR_V 0x03588#define ZR060_SGR_VTOTAL_HI 0x03689#define ZR060_SGR_VTOTAL_LO 0x03790#define ZR060_SGR_HTOTAL_HI 0x03891#define ZR060_SGR_HTOTAL_LO 0x03992#define ZR060_SGR_VSYNC 0x03a93#define ZR060_SGR_HSYNC 0x03b94#define ZR060_SGR_BVSTART 0x03c95#define ZR060_SGR_BHSTART 0x03d96#define ZR060_SGR_BVEND_HI 0x03e97#define ZR060_SGR_BVEND_LO 0x03f98#define ZR060_SGR_BHEND_HI 0x04099#define ZR060_SGR_BHEND_LO 0x041100#define ZR060_AAR_VSTART_HI 0x042101#define ZR060_AAR_VSTART_LO 0x043102#define ZR060_AAR_VEND_HI 0x044103#define ZR060_AAR_VEND_LO 0x045104#define ZR060_AAR_HSTART_HI 0x046105#define ZR060_AAR_HSTART_LO 0x047106#define ZR060_AAR_HEND_HI 0x048107#define ZR060_AAR_HEND_LO 0x049108#define ZR060_SWR_VSTART_HI 0x04a109#define ZR060_SWR_VSTART_LO 0x04b110#define ZR060_SWR_VEND_HI 0x04c111#define ZR060_SWR_VEND_LO 0x04d112#define ZR060_SWR_HSTART_HI 0x04e113#define ZR060_SWR_HSTART_LO 0x04f114#define ZR060_SWR_HEND_HI 0x050115#define ZR060_SWR_HEND_LO 0x051116 117#define ZR060_SOF_IDX 0x060118#define ZR060_SOS_IDX 0x07a119#define ZR060_DRI_IDX 0x0c0120#define ZR060_DQT_IDX 0x0cc121#define ZR060_DHT_IDX 0x1d4122#define ZR060_APP_IDX 0x380123#define ZR060_COM_IDX 0x3c0124 125/* ZR36060 LOAD register bits */126 127#define ZR060_LOAD_LOAD BIT(7)128#define ZR060_LOAD_SYNC_RST BIT(0)129 130/* ZR36060 Code FIFO Status register bits */131 132#define ZR060_CFSR_BUSY BIT(7)133#define ZR060_CFSR_C_BUSY BIT(2)134#define ZR060_CFSR_CFIFO (3 << 0)135 136/* ZR36060 Code Interface register */137 138#define ZR060_CIR_CODE16 BIT(7)139#define ZR060_CIR_ENDIAN BIT(6)140#define ZR060_CIR_CFIS BIT(2)141#define ZR060_CIR_CODE_MSTR BIT(0)142 143/* ZR36060 Codec Mode register */144 145#define ZR060_CMR_COMP BIT(7)146#define ZR060_CMR_ATP BIT(6)147#define ZR060_CMR_PASS2 BIT(5)148#define ZR060_CMR_TLM BIT(4)149#define ZR060_CMR_BRB BIT(2)150#define ZR060_CMR_FSF BIT(1)151 152/* ZR36060 Markers Enable register */153 154#define ZR060_MER_APP BIT(7)155#define ZR060_MER_COM BIT(6)156#define ZR060_MER_DRI BIT(5)157#define ZR060_MER_DQT BIT(4)158#define ZR060_MER_DHT BIT(3)159 160/* ZR36060 Interrupt Mask register */161 162#define ZR060_IMR_EOAV BIT(3)163#define ZR060_IMR_EOI BIT(2)164#define ZR060_IMR_END BIT(1)165#define ZR060_IMR_DATA_ERR BIT(0)166 167/* ZR36060 Interrupt Status register */168 169#define ZR060_ISR_PRO_CNT (3 << 6)170#define ZR060_ISR_EOAV BIT(3)171#define ZR060_ISR_EOI BIT(2)172#define ZR060_ISR_END BIT(1)173#define ZR060_ISR_DATA_ERR BIT(0)174 175/* ZR36060 Video Control register */176 177#define ZR060_VCR_VIDEO8 BIT(7)178#define ZR060_VCR_RANGE BIT(6)179#define ZR060_VCR_FI_DET BIT(3)180#define ZR060_VCR_FI_VEDGE BIT(2)181#define ZR060_VCR_FI_EXT BIT(1)182#define ZR060_VCR_SYNC_MSTR BIT(0)183 184/* ZR36060 Video Polarity register */185 186#define ZR060_VPR_VCLK_POL BIT(7)187#define ZR060_VPR_P_VAL_POL BIT(6)188#define ZR060_VPR_POE_POL BIT(5)189#define ZR060_VPR_S_IMG_POL BIT(4)190#define ZR060_VPR_BL_POL BIT(3)191#define ZR060_VPR_FI_POL BIT(2)192#define ZR060_VPR_HS_POL BIT(1)193#define ZR060_VPR_VS_POL BIT(0)194 195/* ZR36060 Scaling register */196 197#define ZR060_SR_V_SCALE BIT(2)198#define ZR060_SR_H_SCALE2 BIT(0)199#define ZR060_SR_H_SCALE4 (2 << 0)200 201int zr36060_init_module(void);202void zr36060_cleanup_module(void);203#endif /*fndef ZR36060_H */204