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1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * Copyright 2020-2021 NXP4 */5 6#ifndef _AMPHION_VPU_IMX8Q_H7#define _AMPHION_VPU_IMX8Q_H8 9#define SCB_XREG_SLV_BASE 0x0000000010#define SCB_SCB_BLK_CTRL 0x0007000011#define SCB_BLK_CTRL_XMEM_RESET_SET 0x0000009012#define SCB_BLK_CTRL_CACHE_RESET_SET 0x000000A013#define SCB_BLK_CTRL_CACHE_RESET_CLR 0x000000A414#define SCB_BLK_CTRL_SCB_CLK_ENABLE_SET 0x0000010015 16#define XMEM_CONTROL 0x0004100017 18#define MC_CACHE_0_BASE 0x0006000019#define MC_CACHE_1_BASE 0x0006800020 21#define DEC_MFD_XREG_SLV_BASE 0x0018000022#define ENC_MFD_XREG_SLV_0_BASE 0x0080000023#define ENC_MFD_XREG_SLV_1_BASE 0x00A0000024 25#define MFD_HIF 0x0001C00026#define MFD_HIF_MSD_REG_INTERRUPT_STATUS 0x0000001827#define MFD_SIF 0x0001D00028#define MFD_SIF_CTRL_STATUS 0x000000F029#define MFD_SIF_INTR_STATUS 0x000000F430#define MFD_MCX 0x0002080031#define MFD_MCX_OFF 0x0000002032#define MFD_PIX_IF 0x0002000033 34#define MFD_BLK_CTRL 0x0003000035#define MFD_BLK_CTRL_MFD_SYS_RESET_SET 0x0000000036#define MFD_BLK_CTRL_MFD_SYS_RESET_CLR 0x0000000437#define MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET 0x0000010038#define MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_CLR 0x0000010439 40#define VID_API_NUM_STREAMS 841#define VID_API_MAX_BUF_PER_STR 342#define VID_API_MAX_NUM_MVC_VIEWS 443#define MEDIAIP_MAX_NUM_MALONES 244#define MEDIAIP_MAX_NUM_MALONE_IRQ_PINS 245#define MEDIAIP_MAX_NUM_WINDSORS 146#define MEDIAIP_MAX_NUM_WINDSOR_IRQ_PINS 247#define MEDIAIP_MAX_NUM_CMD_IRQ_PINS 248#define MEDIAIP_MAX_NUM_MSG_IRQ_PINS 149#define MEDIAIP_MAX_NUM_TIMER_IRQ_PINS 450#define MEDIAIP_MAX_NUM_TIMER_IRQ_SLOTS 451 52#define WINDSOR_PAL_IRQ_PIN_L 0x453#define WINDSOR_PAL_IRQ_PIN_H 0x554 55struct vpu_rpc_system_config {56 u32 cfg_cookie;57 58 u32 num_malones;59 u32 malone_base_addr[MEDIAIP_MAX_NUM_MALONES];60 u32 hif_offset[MEDIAIP_MAX_NUM_MALONES];61 u32 malone_irq_pin[MEDIAIP_MAX_NUM_MALONES][MEDIAIP_MAX_NUM_MALONE_IRQ_PINS];62 u32 malone_irq_target[MEDIAIP_MAX_NUM_MALONES][MEDIAIP_MAX_NUM_MALONE_IRQ_PINS];63 64 u32 num_windsors;65 u32 windsor_base_addr[MEDIAIP_MAX_NUM_WINDSORS];66 u32 windsor_irq_pin[MEDIAIP_MAX_NUM_WINDSORS][MEDIAIP_MAX_NUM_WINDSOR_IRQ_PINS];67 u32 windsor_irq_target[MEDIAIP_MAX_NUM_WINDSORS][MEDIAIP_MAX_NUM_WINDSOR_IRQ_PINS];68 69 u32 cmd_irq_pin[MEDIAIP_MAX_NUM_CMD_IRQ_PINS];70 u32 cmd_irq_target[MEDIAIP_MAX_NUM_CMD_IRQ_PINS];71 72 u32 msg_irq_pin[MEDIAIP_MAX_NUM_MSG_IRQ_PINS];73 u32 msg_irq_target[MEDIAIP_MAX_NUM_MSG_IRQ_PINS];74 75 u32 sys_clk_freq;76 u32 num_timers;77 u32 timer_base_addr;78 u32 timer_irq_pin[MEDIAIP_MAX_NUM_TIMER_IRQ_PINS];79 u32 timer_irq_target[MEDIAIP_MAX_NUM_TIMER_IRQ_PINS];80 u32 timer_slots[MEDIAIP_MAX_NUM_TIMER_IRQ_SLOTS];81 82 u32 gic_base_addr;83 u32 uart_base_addr;84 85 u32 dpv_base_addr;86 u32 dpv_irq_pin;87 u32 dpv_irq_target;88 89 u32 pixif_base_addr;90 91 u32 pal_trace_level;92 u32 pal_trace_destination;93 94 u32 pal_trace_level1;95 u32 pal_trace_destination1;96 97 u32 heap_base;98 u32 heap_size;99 100 u32 cache_base_addr[2];101};102 103int vpu_imx8q_setup_dec(struct vpu_dev *vpu);104int vpu_imx8q_setup_enc(struct vpu_dev *vpu);105int vpu_imx8q_setup(struct vpu_dev *vpu);106int vpu_imx8q_reset(struct vpu_dev *vpu);107int vpu_imx8q_set_system_cfg_common(struct vpu_rpc_system_config *config, u32 regs, u32 core_id);108int vpu_imx8q_boot_core(struct vpu_core *core);109int vpu_imx8q_get_power_state(struct vpu_core *core);110int vpu_imx8q_on_firmware_loaded(struct vpu_core *core);111int vpu_imx8q_check_memory_region(dma_addr_t base, dma_addr_t addr, u32 size);112bool vpu_imx8q_check_codec(enum vpu_core_type type);113bool vpu_imx8q_check_fmt(enum vpu_core_type type, u32 pixelfmt);114 115#endif116