738 lines · c
1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */2/*3 * Wave5 series multi-standard codec IP - wave5 register definitions4 *5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC6 */7 8#ifndef __WAVE5_REGISTER_DEFINE_H__9#define __WAVE5_REGISTER_DEFINE_H__10 11enum W5_VPU_COMMAND {12 W5_INIT_VPU = 0x0001,13 W5_WAKEUP_VPU = 0x0002,14 W5_SLEEP_VPU = 0x0004,15 W5_CREATE_INSTANCE = 0x0008, /* queuing command */16 W5_FLUSH_INSTANCE = 0x0010,17 W5_DESTROY_INSTANCE = 0x0020, /* queuing command */18 W5_INIT_SEQ = 0x0040, /* queuing command */19 W5_SET_FB = 0x0080,20 W5_DEC_ENC_PIC = 0x0100, /* queuing command */21 W5_ENC_SET_PARAM = 0x0200, /* queuing command */22 W5_QUERY = 0x4000,23 W5_UPDATE_BS = 0x8000,24 W5_MAX_VPU_COMD = 0x10000,25};26 27enum query_opt {28 GET_VPU_INFO = 0,29 SET_WRITE_PROT = 1,30 GET_RESULT = 2,31 UPDATE_DISP_FLAG = 3,32 GET_BW_REPORT = 4,33 GET_BS_RD_PTR = 5, /* for decoder */34 GET_BS_WR_PTR = 6, /* for encoder */35 GET_SRC_BUF_FLAG = 7, /* for encoder */36 SET_BS_RD_PTR = 8, /* for decoder */37 GET_DEBUG_INFO = 0x61,38};39 40#define W5_REG_BASE 0x0000000041#define W5_CMD_REG_BASE 0x0000010042#define W5_CMD_REG_END 0x0000020043 44/*45 * COMMON46 *47 * ----48 *49 * Power on configuration50 * PO_DEBUG_MODE [0] 1 - power on with debug mode51 * USE_PO_CONF [3] 1 - use power-on-configuration52 */53#define W5_PO_CONF (W5_REG_BASE + 0x0000)54#define W5_VCPU_CUR_PC (W5_REG_BASE + 0x0004)55#define W5_VCPU_CUR_LR (W5_REG_BASE + 0x0008)56#define W5_VPU_PDBG_STEP_MASK_V (W5_REG_BASE + 0x000C)57#define W5_VPU_PDBG_CTRL (W5_REG_BASE + 0x0010) /* v_cpu debugger ctrl register */58#define W5_VPU_PDBG_IDX_REG (W5_REG_BASE + 0x0014) /* v_cpu debugger index register */59#define W5_VPU_PDBG_WDATA_REG (W5_REG_BASE + 0x0018) /* v_cpu debugger write data reg */60#define W5_VPU_PDBG_RDATA_REG (W5_REG_BASE + 0x001C) /* v_cpu debugger read data reg */61 62#define W5_VPU_FIO_CTRL_ADDR (W5_REG_BASE + 0x0020)63#define W5_VPU_FIO_DATA (W5_REG_BASE + 0x0024)64#define W5_VPU_VINT_REASON_USR (W5_REG_BASE + 0x0030)65#define W5_VPU_VINT_REASON_CLR (W5_REG_BASE + 0x0034)66#define W5_VPU_HOST_INT_REQ (W5_REG_BASE + 0x0038)67#define W5_VPU_VINT_CLEAR (W5_REG_BASE + 0x003C)68#define W5_VPU_HINT_CLEAR (W5_REG_BASE + 0x0040)69#define W5_VPU_VPU_INT_STS (W5_REG_BASE + 0x0044)70#define W5_VPU_VINT_ENABLE (W5_REG_BASE + 0x0048)71#define W5_VPU_VINT_REASON (W5_REG_BASE + 0x004C)72#define W5_VPU_RESET_REQ (W5_REG_BASE + 0x0050)73#define W5_RST_BLOCK_CCLK(_core) BIT((_core))74#define W5_RST_BLOCK_CCLK_ALL (0xff)75#define W5_RST_BLOCK_BCLK(_core) (0x100 << (_core))76#define W5_RST_BLOCK_BCLK_ALL (0xff00)77#define W5_RST_BLOCK_ACLK(_core) (0x10000 << (_core))78#define W5_RST_BLOCK_ACLK_ALL (0xff0000)79#define W5_RST_BLOCK_VCPU_ALL (0x3f000000)80#define W5_RST_BLOCK_ALL (0x3fffffff)81#define W5_VPU_RESET_STATUS (W5_REG_BASE + 0x0054)82 83#define W5_VCPU_RESTART (W5_REG_BASE + 0x0058)84#define W5_VPU_CLK_MASK (W5_REG_BASE + 0x005C)85 86/* REMAP_CTRL87 * PAGE SIZE: [8:0] 0x001 - 4K88 * 0x002 - 8K89 * 0x004 - 16K90 * ...91 * 0x100 - 1M92 * REGION ATTR1 [10] 0 - normal93 * 1 - make bus error for the region94 * REGION ATTR2 [11] 0 - normal95 * 1 - bypass region96 * REMAP INDEX [15:12] - 0 ~ 397 * ENDIAN [19:16] - NOTE: Currently not supported in this driver98 * AXI-ID [23:20] - upper AXI-ID99 * BUS_ERROR [29] 0 - bypass100 * 1 - make BUS_ERROR for unmapped region101 * BYPASS_ALL [30] 1 - bypass all102 * ENABLE [31] 1 - update control register[30:16]103 */104#define W5_VPU_REMAP_CTRL (W5_REG_BASE + 0x0060)105#define W5_VPU_REMAP_VADDR (W5_REG_BASE + 0x0064)106#define W5_VPU_REMAP_PADDR (W5_REG_BASE + 0x0068)107#define W5_VPU_REMAP_CORE_START (W5_REG_BASE + 0x006C)108#define W5_VPU_BUSY_STATUS (W5_REG_BASE + 0x0070)109#define W5_VPU_HALT_STATUS (W5_REG_BASE + 0x0074)110#define W5_VPU_VCPU_STATUS (W5_REG_BASE + 0x0078)111#define W5_VPU_RET_PRODUCT_VERSION (W5_REG_BASE + 0x0094)112/*113 * assign vpu_config0 = {conf_map_converter_reg, // [31]114 * conf_map_converter_sig, // [30]115 * 8'd0, // [29:22]116 * conf_std_switch_en, // [21]117 * conf_bg_detect, // [20]118 * conf_3dnr_en, // [19]119 * conf_one_axi_en, // [18]120 * conf_sec_axi_en, // [17]121 * conf_bus_info, // [16]122 * conf_afbc_en, // [15]123 * conf_afbc_version_id, // [14:12]124 * conf_fbc_en, // [11]125 * conf_fbc_version_id, // [10:08]126 * conf_scaler_en, // [07]127 * conf_scaler_version_id, // [06:04]128 * conf_bwb_en, // [03]129 * 3'd0}; // [02:00]130 */131#define W5_VPU_RET_VPU_CONFIG0 (W5_REG_BASE + 0x0098)132/*133 * assign vpu_config1 = {4'd0, // [31:28]134 * conf_perf_timer_en, // [27]135 * conf_multi_core_en, // [26]136 * conf_gcu_en, // [25]137 * conf_cu_report, // [24]138 * 4'd0, // [23:20]139 * conf_vcore_id_3, // [19]140 * conf_vcore_id_2, // [18]141 * conf_vcore_id_1, // [17]142 * conf_vcore_id_0, // [16]143 * conf_bwb_opt, // [15]144 * 7'd0, // [14:08]145 * conf_cod_std_en_reserved_7, // [7]146 * conf_cod_std_en_reserved_6, // [6]147 * conf_cod_std_en_reserved_5, // [5]148 * conf_cod_std_en_reserved_4, // [4]149 * conf_cod_std_en_reserved_3, // [3]150 * conf_cod_std_en_reserved_2, // [2]151 * conf_cod_std_en_vp9, // [1]152 * conf_cod_std_en_hevc}; // [0]153 * }154 */155#define W5_VPU_RET_VPU_CONFIG1 (W5_REG_BASE + 0x009C)156 157#define W5_VPU_DBG_REG0 (W5_REG_BASE + 0x00f0)158#define W5_VPU_DBG_REG1 (W5_REG_BASE + 0x00f4)159#define W5_VPU_DBG_REG2 (W5_REG_BASE + 0x00f8)160#define W5_VPU_DBG_REG3 (W5_REG_BASE + 0x00fc)161 162/************************************************************************/163/* PRODUCT INFORMATION */164/************************************************************************/165#define W5_PRODUCT_NAME (W5_REG_BASE + 0x1040)166#define W5_PRODUCT_NUMBER (W5_REG_BASE + 0x1044)167 168/************************************************************************/169/* DECODER/ENCODER COMMON */170/************************************************************************/171#define W5_COMMAND (W5_REG_BASE + 0x0100)172#define W5_COMMAND_OPTION (W5_REG_BASE + 0x0104)173#define W5_QUERY_OPTION (W5_REG_BASE + 0x0104)174#define W5_RET_SUCCESS (W5_REG_BASE + 0x0108)175#define W5_RET_FAIL_REASON (W5_REG_BASE + 0x010C)176#define W5_RET_QUEUE_FAIL_REASON (W5_REG_BASE + 0x0110)177#define W5_CMD_INSTANCE_INFO (W5_REG_BASE + 0x0110)178 179#define W5_RET_QUEUE_STATUS (W5_REG_BASE + 0x01E0)180#define W5_RET_BS_EMPTY_INST (W5_REG_BASE + 0x01E4)181#define W5_RET_QUEUE_CMD_DONE_INST (W5_REG_BASE + 0x01E8)182#define W5_RET_STAGE0_INSTANCE_INFO (W5_REG_BASE + 0x01EC)183#define W5_RET_STAGE1_INSTANCE_INFO (W5_REG_BASE + 0x01F0)184#define W5_RET_STAGE2_INSTANCE_INFO (W5_REG_BASE + 0x01F4)185 186#define W5_RET_SEQ_DONE_INSTANCE_INFO (W5_REG_BASE + 0x01FC)187 188#define W5_BS_OPTION (W5_REG_BASE + 0x0120)189 190/* return info when QUERY (GET_RESULT) for en/decoder */191#define W5_RET_VLC_BUF_SIZE (W5_REG_BASE + 0x01B0)192/* return info when QUERY (GET_RESULT) for en/decoder */193#define W5_RET_PARAM_BUF_SIZE (W5_REG_BASE + 0x01B4)194 195/* set when SET_FB for en/decoder */196#define W5_CMD_SET_FB_ADDR_TASK_BUF (W5_REG_BASE + 0x01D4)197#define W5_CMD_SET_FB_TASK_BUF_SIZE (W5_REG_BASE + 0x01D8)198/************************************************************************/199/* INIT_VPU - COMMON */200/************************************************************************/201/* note: W5_ADDR_CODE_BASE should be aligned to 4KB */202#define W5_ADDR_CODE_BASE (W5_REG_BASE + 0x0110)203#define W5_CODE_SIZE (W5_REG_BASE + 0x0114)204#define W5_CODE_PARAM (W5_REG_BASE + 0x0118)205#define W5_ADDR_TEMP_BASE (W5_REG_BASE + 0x011C)206#define W5_TEMP_SIZE (W5_REG_BASE + 0x0120)207#define W5_HW_OPTION (W5_REG_BASE + 0x012C)208#define W5_CMD_INIT_NUM_TASK_BUF (W5_REG_BASE + 0x0134)209#define W5_CMD_INIT_ADDR_TASK_BUF0 (W5_REG_BASE + 0x0138)210#define W5_CMD_INIT_TASK_BUF_SIZE (W5_REG_BASE + 0x0178)211#define W5_SEC_AXI_PARAM (W5_REG_BASE + 0x0180)212 213/************************************************************************/214/* CREATE_INSTANCE - COMMON */215/************************************************************************/216#define W5_ADDR_WORK_BASE (W5_REG_BASE + 0x0114)217#define W5_WORK_SIZE (W5_REG_BASE + 0x0118)218#define W5_CMD_DEC_BS_START_ADDR (W5_REG_BASE + 0x011C)219#define W5_CMD_DEC_BS_SIZE (W5_REG_BASE + 0x0120)220#define W5_CMD_BS_PARAM (W5_REG_BASE + 0x0124)221#define W5_CMD_ADDR_SEC_AXI (W5_REG_BASE + 0x0130)222#define W515_CMD_ADDR_SEC_AXI (W5_REG_BASE + 0x0124)223#define W5_CMD_SEC_AXI_SIZE (W5_REG_BASE + 0x0134)224#define W515_CMD_SEC_AXI_SIZE (W5_REG_BASE + 0x0128)225#define W5_CMD_EXT_ADDR (W5_REG_BASE + 0x0138)226#define W5_CMD_NUM_CQ_DEPTH_M1 (W5_REG_BASE + 0x013C)227#define W5_CMD_ERR_CONCEAL (W5_REG_BASE + 0x0140)228 229/************************************************************************/230/* DECODER - INIT_SEQ */231/************************************************************************/232#define W5_BS_RD_PTR (W5_REG_BASE + 0x0118)233#define W5_BS_WR_PTR (W5_REG_BASE + 0x011C)234/************************************************************************/235/* SET_FRAME_BUF */236/************************************************************************/237/* SET_FB_OPTION 0x00 REGISTER FRAMEBUFFERS238 * 0x01 UPDATE FRAMEBUFFER, just one framebuffer(linear, fbc and mvcol)239 */240#define W5_SFB_OPTION (W5_REG_BASE + 0x0104)241#define W5_COMMON_PIC_INFO (W5_REG_BASE + 0x0118)242#define W5_PIC_SIZE (W5_REG_BASE + 0x011C)243#define W5_SET_FB_NUM (W5_REG_BASE + 0x0120)244#define W5_EXTRA_PIC_INFO (W5_REG_BASE + 0x0124)245 246#define W5_ADDR_LUMA_BASE0 (W5_REG_BASE + 0x0134)247#define W5_ADDR_CB_BASE0 (W5_REG_BASE + 0x0138)248#define W5_ADDR_CR_BASE0 (W5_REG_BASE + 0x013C)249/* compression offset table for luma */250#define W5_ADDR_FBC_Y_OFFSET0 (W5_REG_BASE + 0x013C)251/* compression offset table for chroma */252#define W5_ADDR_FBC_C_OFFSET0 (W5_REG_BASE + 0x0140)253#define W5_ADDR_LUMA_BASE1 (W5_REG_BASE + 0x0144)254#define W5_ADDR_CB_ADDR1 (W5_REG_BASE + 0x0148)255#define W5_ADDR_CR_ADDR1 (W5_REG_BASE + 0x014C)256/* compression offset table for luma */257#define W5_ADDR_FBC_Y_OFFSET1 (W5_REG_BASE + 0x014C)258/* compression offset table for chroma */259#define W5_ADDR_FBC_C_OFFSET1 (W5_REG_BASE + 0x0150)260#define W5_ADDR_LUMA_BASE2 (W5_REG_BASE + 0x0154)261#define W5_ADDR_CB_ADDR2 (W5_REG_BASE + 0x0158)262#define W5_ADDR_CR_ADDR2 (W5_REG_BASE + 0x015C)263/* compression offset table for luma */264#define W5_ADDR_FBC_Y_OFFSET2 (W5_REG_BASE + 0x015C)265/* compression offset table for chroma */266#define W5_ADDR_FBC_C_OFFSET2 (W5_REG_BASE + 0x0160)267#define W5_ADDR_LUMA_BASE3 (W5_REG_BASE + 0x0164)268#define W5_ADDR_CB_ADDR3 (W5_REG_BASE + 0x0168)269#define W5_ADDR_CR_ADDR3 (W5_REG_BASE + 0x016C)270/* compression offset table for luma */271#define W5_ADDR_FBC_Y_OFFSET3 (W5_REG_BASE + 0x016C)272/* compression offset table for chroma */273#define W5_ADDR_FBC_C_OFFSET3 (W5_REG_BASE + 0x0170)274#define W5_ADDR_LUMA_BASE4 (W5_REG_BASE + 0x0174)275#define W5_ADDR_CB_ADDR4 (W5_REG_BASE + 0x0178)276#define W5_ADDR_CR_ADDR4 (W5_REG_BASE + 0x017C)277/* compression offset table for luma */278#define W5_ADDR_FBC_Y_OFFSET4 (W5_REG_BASE + 0x017C)279/* compression offset table for chroma */280#define W5_ADDR_FBC_C_OFFSET4 (W5_REG_BASE + 0x0180)281#define W5_ADDR_LUMA_BASE5 (W5_REG_BASE + 0x0184)282#define W5_ADDR_CB_ADDR5 (W5_REG_BASE + 0x0188)283#define W5_ADDR_CR_ADDR5 (W5_REG_BASE + 0x018C)284/* compression offset table for luma */285#define W5_ADDR_FBC_Y_OFFSET5 (W5_REG_BASE + 0x018C)286/* compression offset table for chroma */287#define W5_ADDR_FBC_C_OFFSET5 (W5_REG_BASE + 0x0190)288#define W5_ADDR_LUMA_BASE6 (W5_REG_BASE + 0x0194)289#define W5_ADDR_CB_ADDR6 (W5_REG_BASE + 0x0198)290#define W5_ADDR_CR_ADDR6 (W5_REG_BASE + 0x019C)291/* compression offset table for luma */292#define W5_ADDR_FBC_Y_OFFSET6 (W5_REG_BASE + 0x019C)293/* compression offset table for chroma */294#define W5_ADDR_FBC_C_OFFSET6 (W5_REG_BASE + 0x01A0)295#define W5_ADDR_LUMA_BASE7 (W5_REG_BASE + 0x01A4)296#define W5_ADDR_CB_ADDR7 (W5_REG_BASE + 0x01A8)297#define W5_ADDR_CR_ADDR7 (W5_REG_BASE + 0x01AC)298/* compression offset table for luma */299#define W5_ADDR_FBC_Y_OFFSET7 (W5_REG_BASE + 0x01AC)300/* compression offset table for chroma */301#define W5_ADDR_FBC_C_OFFSET7 (W5_REG_BASE + 0x01B0)302#define W5_ADDR_MV_COL0 (W5_REG_BASE + 0x01B4)303#define W5_ADDR_MV_COL1 (W5_REG_BASE + 0x01B8)304#define W5_ADDR_MV_COL2 (W5_REG_BASE + 0x01BC)305#define W5_ADDR_MV_COL3 (W5_REG_BASE + 0x01C0)306#define W5_ADDR_MV_COL4 (W5_REG_BASE + 0x01C4)307#define W5_ADDR_MV_COL5 (W5_REG_BASE + 0x01C8)308#define W5_ADDR_MV_COL6 (W5_REG_BASE + 0x01CC)309#define W5_ADDR_MV_COL7 (W5_REG_BASE + 0x01D0)310 311/* UPDATE_FB */312/* CMD_SET_FB_STRIDE [15:0] - FBC framebuffer stride313 * [31:15] - linear framebuffer stride314 */315#define W5_CMD_SET_FB_STRIDE (W5_REG_BASE + 0x0118)316#define W5_CMD_SET_FB_INDEX (W5_REG_BASE + 0x0120)317#define W5_ADDR_LUMA_BASE (W5_REG_BASE + 0x0134)318#define W5_ADDR_CB_BASE (W5_REG_BASE + 0x0138)319#define W5_ADDR_CR_BASE (W5_REG_BASE + 0x013C)320#define W5_ADDR_MV_COL (W5_REG_BASE + 0x0140)321#define W5_ADDR_FBC_Y_BASE (W5_REG_BASE + 0x0144)322#define W5_ADDR_FBC_C_BASE (W5_REG_BASE + 0x0148)323#define W5_ADDR_FBC_Y_OFFSET (W5_REG_BASE + 0x014C)324#define W5_ADDR_FBC_C_OFFSET (W5_REG_BASE + 0x0150)325 326/************************************************************************/327/* DECODER - DEC_PIC */328/************************************************************************/329#define W5_CMD_DEC_VCORE_INFO (W5_REG_BASE + 0x0194)330/* sequence change enable mask register331 * CMD_SEQ_CHANGE_ENABLE_FLAG [5] profile_idc332 * [16] pic_width/height_in_luma_sample333 * [19] sps_max_dec_pic_buffering, max_num_reorder, max_latency_increase334 */335#define W5_CMD_SEQ_CHANGE_ENABLE_FLAG (W5_REG_BASE + 0x0128)336#define W5_CMD_DEC_USER_MASK (W5_REG_BASE + 0x012C)337#define W5_CMD_DEC_TEMPORAL_ID_PLUS1 (W5_REG_BASE + 0x0130)338#define W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1 (W5_REG_BASE + 0x0134)339#define W5_USE_SEC_AXI (W5_REG_BASE + 0x0150)340 341/************************************************************************/342/* DECODER - QUERY : GET_VPU_INFO */343/************************************************************************/344#define W5_RET_FW_VERSION (W5_REG_BASE + 0x0118)345#define W5_RET_PRODUCT_NAME (W5_REG_BASE + 0x011C)346#define W5_RET_PRODUCT_VERSION (W5_REG_BASE + 0x0120)347#define W5_RET_STD_DEF0 (W5_REG_BASE + 0x0124)348#define W5_RET_STD_DEF1 (W5_REG_BASE + 0x0128)349#define W5_RET_CONF_FEATURE (W5_REG_BASE + 0x012C)350#define W5_RET_CONF_DATE (W5_REG_BASE + 0x0130)351#define W5_RET_CONF_REVISION (W5_REG_BASE + 0x0134)352#define W5_RET_CONF_TYPE (W5_REG_BASE + 0x0138)353#define W5_RET_PRODUCT_ID (W5_REG_BASE + 0x013C)354#define W5_RET_CUSTOMER_ID (W5_REG_BASE + 0x0140)355 356/************************************************************************/357/* DECODER - QUERY : GET_RESULT */358/************************************************************************/359#define W5_CMD_DEC_ADDR_REPORT_BASE (W5_REG_BASE + 0x0114)360#define W5_CMD_DEC_REPORT_SIZE (W5_REG_BASE + 0x0118)361#define W5_CMD_DEC_REPORT_PARAM (W5_REG_BASE + 0x011C)362 363#define W5_RET_DEC_BS_RD_PTR (W5_REG_BASE + 0x011C)364#define W5_RET_DEC_SEQ_PARAM (W5_REG_BASE + 0x0120)365#define W5_RET_DEC_COLOR_SAMPLE_INFO (W5_REG_BASE + 0x0124)366#define W5_RET_DEC_ASPECT_RATIO (W5_REG_BASE + 0x0128)367#define W5_RET_DEC_BIT_RATE (W5_REG_BASE + 0x012C)368#define W5_RET_DEC_FRAME_RATE_NR (W5_REG_BASE + 0x0130)369#define W5_RET_DEC_FRAME_RATE_DR (W5_REG_BASE + 0x0134)370#define W5_RET_DEC_NUM_REQUIRED_FB (W5_REG_BASE + 0x0138)371#define W5_RET_DEC_NUM_REORDER_DELAY (W5_REG_BASE + 0x013C)372#define W5_RET_DEC_SUB_LAYER_INFO (W5_REG_BASE + 0x0140)373#define W5_RET_DEC_NOTIFICATION (W5_REG_BASE + 0x0144)374/*375 * USER_DATA_FLAGS for HEVC/H264 only.376 * Bits:377 * [1] - User data buffer full boolean378 * [2] - VUI parameter flag379 * [4] - Pic_timing SEI flag380 * [5] - 1st user_data_registed_itu_t_t35 prefix SEI flag381 * [6] - user_data_unregistered prefix SEI flag382 * [7] - 1st user_data_registed_itu_t_t35 suffix SEI flag383 * [8] - user_data_unregistered suffix SEI flag384 * [10]- mastering_display_color_volume prefix SEI flag385 * [11]- chroma_resampling_display_color_volume prefix SEI flag386 * [12]- knee_function_info SEI flag387 * [13]- tone_mapping_info prefix SEI flag388 * [14]- film_grain_characteristics_info prefix SEI flag389 * [15]- content_light_level_info prefix SEI flag390 * [16]- color_remapping_info prefix SEI flag391 * [28]- 2nd user_data_registed_itu_t_t35 prefix SEI flag392 * [29]- 3rd user_data_registed_itu_t_t35 prefix SEI flag393 * [30]- 2nd user_data_registed_itu_t_t35 suffix SEI flag394 * [31]- 3rd user_data_registed_itu_t_t35 suffix SEI flag395 */396#define W5_RET_DEC_USERDATA_IDC (W5_REG_BASE + 0x0148)397#define W5_RET_DEC_PIC_SIZE (W5_REG_BASE + 0x014C)398#define W5_RET_DEC_CROP_TOP_BOTTOM (W5_REG_BASE + 0x0150)399#define W5_RET_DEC_CROP_LEFT_RIGHT (W5_REG_BASE + 0x0154)400/*401 * #define W5_RET_DEC_AU_START_POS (W5_REG_BASE + 0x0158)402 * => Access unit (AU) Bitstream start position403 * #define W5_RET_DEC_AU_END_POS (W5_REG_BASE + 0x015C)404 * => Access unit (AU) Bitstream end position405 */406 407/*408 * Decoded picture type:409 * reg_val & 0x7 => picture type410 * (reg_val >> 4) & 0x3f => VCL NAL unit type411 * (reg_val >> 31) & 0x1 => output_flag412 * 16 << ((reg_val >> 10) & 0x3) => ctu_size413 */414#define W5_RET_DEC_PIC_TYPE (W5_REG_BASE + 0x0160)415#define W5_RET_DEC_PIC_POC (W5_REG_BASE + 0x0164)416/*417 * #define W5_RET_DEC_RECOVERY_POINT (W5_REG_BASE + 0x0168)418 * => HEVC recovery point419 * reg_val & 0xff => number of signed recovery picture order counts420 * (reg_val >> 16) & 0x1 => exact match flag421 * (reg_val >> 17) & 0x1 => broken link flag422 * (reg_val >> 18) & 0x1 => exist flag423 */424#define W5_RET_DEC_DEBUG_INDEX (W5_REG_BASE + 0x016C)425#define W5_RET_DEC_DECODED_INDEX (W5_REG_BASE + 0x0170)426#define W5_RET_DEC_DISPLAY_INDEX (W5_REG_BASE + 0x0174)427/*428 * #define W5_RET_DEC_REALLOC_INDEX (W5_REG_BASE + 0x0178)429 * => display picture index in decoded picture buffer430 * reg_val & 0xf => display picture index for FBC buffer (by reordering)431 */432#define W5_RET_DEC_DISP_IDC (W5_REG_BASE + 0x017C)433/*434 * #define W5_RET_DEC_ERR_CTB_NUM (W5_REG_BASE + 0x0180)435 * => Number of error CTUs436 * reg_val >> 16 => erroneous CTUs in bitstream437 * reg_val & 0xffff => total CTUs in bitstream438 *439 * #define W5_RET_DEC_PIC_PARAM (W5_REG_BASE + 0x01A0)440 * => Bitstream sequence/picture parameter information (AV1 only)441 * reg_val & 0x1 => intrabc tool enable442 * (reg_val >> 1) & 0x1 => screen content tools enable443 */444#define W5_RET_DEC_HOST_CMD_TICK (W5_REG_BASE + 0x01B8)445/*446 * #define W5_RET_DEC_SEEK_START_TICK (W5_REG_BASE + 0x01BC)447 * #define W5_RET_DEC_SEEK_END_TICK (W5_REG_BASE + 0x01C0)448 * => Start and end ticks for seeking slices of the picture449 * #define W5_RET_DEC_PARSING_START_TICK (W5_REG_BASE + 0x01C4)450 * #define W5_RET_DEC_PARSING_END_TICK (W5_REG_BASE + 0x01C8)451 * => Start and end ticks for parsing slices of the picture452 * #define W5_RET_DEC_DECODING_START_TICK (W5_REG_BASE + 0x01CC)453 * => Start tick for decoding slices of the picture454 */455#define W5_RET_DEC_DECODING_ENC_TICK (W5_REG_BASE + 0x01D0)456#define W5_RET_DEC_WARN_INFO (W5_REG_BASE + 0x01D4)457#define W5_RET_DEC_ERR_INFO (W5_REG_BASE + 0x01D8)458#define W5_RET_DEC_DECODING_SUCCESS (W5_REG_BASE + 0x01DC)459 460/************************************************************************/461/* DECODER - FLUSH_INSTANCE */462/************************************************************************/463#define W5_CMD_FLUSH_INST_OPT (W5_REG_BASE + 0x104)464 465/************************************************************************/466/* DECODER - QUERY : UPDATE_DISP_FLAG */467/************************************************************************/468#define W5_CMD_DEC_SET_DISP_IDC (W5_REG_BASE + 0x0118)469#define W5_CMD_DEC_CLR_DISP_IDC (W5_REG_BASE + 0x011C)470 471/************************************************************************/472/* DECODER - QUERY : SET_BS_RD_PTR */473/************************************************************************/474#define W5_RET_QUERY_DEC_SET_BS_RD_PTR (W5_REG_BASE + 0x011C)475 476/************************************************************************/477/* DECODER - QUERY : GET_BS_RD_PTR */478/************************************************************************/479#define W5_RET_QUERY_DEC_BS_RD_PTR (W5_REG_BASE + 0x011C)480 481/************************************************************************/482/* QUERY : GET_DEBUG_INFO */483/************************************************************************/484#define W5_RET_QUERY_DEBUG_PRI_REASON (W5_REG_BASE + 0x114)485 486/************************************************************************/487/* GDI register for debugging */488/************************************************************************/489#define W5_GDI_BASE 0x8800490#define W5_GDI_BUS_CTRL (W5_GDI_BASE + 0x0F0)491#define W5_GDI_BUS_STATUS (W5_GDI_BASE + 0x0F4)492 493#define W5_BACKBONE_BASE_VCPU 0xFE00494#define W5_BACKBONE_BUS_CTRL_VCPU (W5_BACKBONE_BASE_VCPU + 0x010)495#define W5_BACKBONE_BUS_STATUS_VCPU (W5_BACKBONE_BASE_VCPU + 0x014)496#define W5_BACKBONE_PROG_AXI_ID (W5_BACKBONE_BASE_VCPU + 0x00C)497 498#define W5_BACKBONE_PROC_EXT_ADDR (W5_BACKBONE_BASE_VCPU + 0x0C0)499#define W5_BACKBONE_AXI_PARAM (W5_BACKBONE_BASE_VCPU + 0x0E0)500 501#define W5_BACKBONE_BASE_VCORE0 0x8E00502#define W5_BACKBONE_BUS_CTRL_VCORE0 (W5_BACKBONE_BASE_VCORE0 + 0x010)503#define W5_BACKBONE_BUS_STATUS_VCORE0 (W5_BACKBONE_BASE_VCORE0 + 0x014)504 505#define W5_BACKBONE_BASE_VCORE1 0x9E00 /* for dual-core product */506#define W5_BACKBONE_BUS_CTRL_VCORE1 (W5_BACKBONE_BASE_VCORE1 + 0x010)507#define W5_BACKBONE_BUS_STATUS_VCORE1 (W5_BACKBONE_BASE_VCORE1 + 0x014)508 509#define W5_COMBINED_BACKBONE_BASE 0xFE00510#define W5_COMBINED_BACKBONE_BUS_CTRL (W5_COMBINED_BACKBONE_BASE + 0x010)511#define W5_COMBINED_BACKBONE_BUS_STATUS (W5_COMBINED_BACKBONE_BASE + 0x014)512 513/************************************************************************/514/* */515/* for ENCODER */516/* */517/************************************************************************/518#define W5_RET_STAGE3_INSTANCE_INFO (W5_REG_BASE + 0x1F8)519/************************************************************************/520/* ENCODER - CREATE_INSTANCE */521/************************************************************************/522/* 0x114 ~ 0x124 : defined above (CREATE_INSTANCE COMMON) */523#define W5_CMD_ENC_VCORE_INFO (W5_REG_BASE + 0x0194)524#define W5_CMD_ENC_SRC_OPTIONS (W5_REG_BASE + 0x0128)525 526/************************************************************************/527/* ENCODER - SET_FB */528/************************************************************************/529#define W5_FBC_STRIDE (W5_REG_BASE + 0x128)530#define W5_ADDR_SUB_SAMPLED_FB_BASE (W5_REG_BASE + 0x12C)531#define W5_SUB_SAMPLED_ONE_FB_SIZE (W5_REG_BASE + 0x130)532 533/************************************************************************/534/* ENCODER - ENC_SET_PARAM (COMMON & CHANGE_PARAM) */535/************************************************************************/536#define W5_CMD_ENC_SEQ_SET_PARAM_OPTION (W5_REG_BASE + 0x104)537#define W5_CMD_ENC_SEQ_SET_PARAM_ENABLE (W5_REG_BASE + 0x118)538#define W5_CMD_ENC_SEQ_SRC_SIZE (W5_REG_BASE + 0x11C)539#define W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN (W5_REG_BASE + 0x120)540#define W5_CMD_ENC_SEQ_SPS_PARAM (W5_REG_BASE + 0x124)541#define W5_CMD_ENC_SEQ_PPS_PARAM (W5_REG_BASE + 0x128)542#define W5_CMD_ENC_SEQ_GOP_PARAM (W5_REG_BASE + 0x12C)543#define W5_CMD_ENC_SEQ_INTRA_PARAM (W5_REG_BASE + 0x130)544#define W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT (W5_REG_BASE + 0x134)545#define W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT (W5_REG_BASE + 0x138)546#define W5_CMD_ENC_SEQ_RDO_PARAM (W5_REG_BASE + 0x13C)547#define W5_CMD_ENC_SEQ_INDEPENDENT_SLICE (W5_REG_BASE + 0x140)548#define W5_CMD_ENC_SEQ_DEPENDENT_SLICE (W5_REG_BASE + 0x144)549#define W5_CMD_ENC_SEQ_INTRA_REFRESH (W5_REG_BASE + 0x148)550#define W5_CMD_ENC_SEQ_INPUT_SRC_PARAM (W5_REG_BASE + 0x14C)551 552#define W5_CMD_ENC_SEQ_RC_FRAME_RATE (W5_REG_BASE + 0x150)553#define W5_CMD_ENC_SEQ_RC_TARGET_RATE (W5_REG_BASE + 0x154)554#define W5_CMD_ENC_SEQ_RC_PARAM (W5_REG_BASE + 0x158)555#define W5_CMD_ENC_SEQ_RC_MIN_MAX_QP (W5_REG_BASE + 0x15C)556#define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3 (W5_REG_BASE + 0x160)557#define W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7 (W5_REG_BASE + 0x164)558#define W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP (W5_REG_BASE + 0x168)559#define W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM (W5_REG_BASE + 0x16C)560 561#define W5_CMD_ENC_SEQ_ROT_PARAM (W5_REG_BASE + 0x170)562#define W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK (W5_REG_BASE + 0x174)563#define W5_CMD_ENC_SEQ_TIME_SCALE (W5_REG_BASE + 0x178)564#define W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE (W5_REG_BASE + 0x17C)565 566#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU04 (W5_REG_BASE + 0x184)567#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU08 (W5_REG_BASE + 0x188)568#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU16 (W5_REG_BASE + 0x18C)569#define W5_CMD_ENC_SEQ_CUSTOM_MD_PU32 (W5_REG_BASE + 0x190)570#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU08 (W5_REG_BASE + 0x194)571#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU16 (W5_REG_BASE + 0x198)572#define W5_CMD_ENC_SEQ_CUSTOM_MD_CU32 (W5_REG_BASE + 0x19C)573#define W5_CMD_ENC_SEQ_NR_PARAM (W5_REG_BASE + 0x1A0)574#define W5_CMD_ENC_SEQ_NR_WEIGHT (W5_REG_BASE + 0x1A4)575#define W5_CMD_ENC_SEQ_BG_PARAM (W5_REG_BASE + 0x1A8)576#define W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR (W5_REG_BASE + 0x1AC)577#define W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR (W5_REG_BASE + 0x1B0)578#define W5_CMD_ENC_SEQ_VUI_HRD_PARAM (W5_REG_BASE + 0x180)579#define W5_CMD_ENC_SEQ_VUI_RBSP_ADDR (W5_REG_BASE + 0x1B8)580#define W5_CMD_ENC_SEQ_HRD_RBSP_ADDR (W5_REG_BASE + 0x1BC)581 582/************************************************************************/583/* ENCODER - ENC_SET_PARAM (CUSTOM_GOP) */584/************************************************************************/585#define W5_CMD_ENC_CUSTOM_GOP_PARAM (W5_REG_BASE + 0x11C)586#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_0 (W5_REG_BASE + 0x120)587#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_1 (W5_REG_BASE + 0x124)588#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_2 (W5_REG_BASE + 0x128)589#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_3 (W5_REG_BASE + 0x12C)590#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_4 (W5_REG_BASE + 0x130)591#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_5 (W5_REG_BASE + 0x134)592#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_6 (W5_REG_BASE + 0x138)593#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_7 (W5_REG_BASE + 0x13C)594#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_8 (W5_REG_BASE + 0x140)595#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_9 (W5_REG_BASE + 0x144)596#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_10 (W5_REG_BASE + 0x148)597#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_11 (W5_REG_BASE + 0x14C)598#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_12 (W5_REG_BASE + 0x150)599#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_13 (W5_REG_BASE + 0x154)600#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_14 (W5_REG_BASE + 0x158)601#define W5_CMD_ENC_CUSTOM_GOP_PIC_PARAM_15 (W5_REG_BASE + 0x15C)602 603/************************************************************************/604/* ENCODER - ENC_PIC */605/************************************************************************/606#define W5_CMD_ENC_BS_START_ADDR (W5_REG_BASE + 0x118)607#define W5_CMD_ENC_BS_SIZE (W5_REG_BASE + 0x11C)608#define W5_CMD_ENC_PIC_USE_SEC_AXI (W5_REG_BASE + 0x124)609#define W5_CMD_ENC_PIC_REPORT_PARAM (W5_REG_BASE + 0x128)610 611#define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM (W5_REG_BASE + 0x138)612#define W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR (W5_REG_BASE + 0x13C)613#define W5_CMD_ENC_PIC_SRC_PIC_IDX (W5_REG_BASE + 0x144)614#define W5_CMD_ENC_PIC_SRC_ADDR_Y (W5_REG_BASE + 0x148)615#define W5_CMD_ENC_PIC_SRC_ADDR_U (W5_REG_BASE + 0x14C)616#define W5_CMD_ENC_PIC_SRC_ADDR_V (W5_REG_BASE + 0x150)617#define W5_CMD_ENC_PIC_SRC_STRIDE (W5_REG_BASE + 0x154)618#define W5_CMD_ENC_PIC_SRC_FORMAT (W5_REG_BASE + 0x158)619#define W5_CMD_ENC_PIC_SRC_AXI_SEL (W5_REG_BASE + 0x160)620#define W5_CMD_ENC_PIC_CODE_OPTION (W5_REG_BASE + 0x164)621#define W5_CMD_ENC_PIC_PIC_PARAM (W5_REG_BASE + 0x168)622#define W5_CMD_ENC_PIC_LONGTERM_PIC (W5_REG_BASE + 0x16C)623#define W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y (W5_REG_BASE + 0x170)624#define W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C (W5_REG_BASE + 0x174)625#define W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y (W5_REG_BASE + 0x178)626#define W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C (W5_REG_BASE + 0x17C)627#define W5_CMD_ENC_PIC_CF50_Y_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x190)628#define W5_CMD_ENC_PIC_CF50_CB_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x194)629#define W5_CMD_ENC_PIC_CF50_CR_OFFSET_TABLE_ADDR (W5_REG_BASE + 0x198)630#define W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR (W5_REG_BASE + 0x180)631#define W5_CMD_ENC_PIC_PREFIX_SEI_INFO (W5_REG_BASE + 0x184)632#define W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR (W5_REG_BASE + 0x188)633#define W5_CMD_ENC_PIC_SUFFIX_SEI_INFO (W5_REG_BASE + 0x18c)634 635/************************************************************************/636/* ENCODER - QUERY (GET_RESULT) */637/************************************************************************/638#define W5_RET_ENC_NUM_REQUIRED_FB (W5_REG_BASE + 0x11C)639#define W5_RET_ENC_MIN_SRC_BUF_NUM (W5_REG_BASE + 0x120)640#define W5_RET_ENC_PIC_TYPE (W5_REG_BASE + 0x124)641/*642 * #define W5_RET_ENC_PIC_POC (W5_REG_BASE + 0x128)643 * => picture order count value of current encoded picture644 */645#define W5_RET_ENC_PIC_IDX (W5_REG_BASE + 0x12C)646/*647 * #define W5_RET_ENC_PIC_SLICE_NUM (W5_REG_BASE + 0x130)648 * reg_val & 0xffff = total independent slice segment number (16 bits)649 * (reg_val >> 16) & 0xffff = total dependent slice segment number (16 bits)650 *651 * #define W5_RET_ENC_PIC_SKIP (W5_REG_BASE + 0x134)652 * reg_val & 0xfe = picture skip flag (7 bits)653 *654 * #define W5_RET_ENC_PIC_NUM_INTRA (W5_REG_BASE + 0x138)655 * => number of intra blocks in 8x8 (32 bits)656 *657 * #define W5_RET_ENC_PIC_NUM_MERGE (W5_REG_BASE + 0x13C)658 * => number of merge blocks in 8x8 (32 bits)659 *660 * #define W5_RET_ENC_PIC_NUM_SKIP (W5_REG_BASE + 0x144)661 * => number of skip blocks in 8x8 (32 bits)662 *663 * #define W5_RET_ENC_PIC_AVG_CTU_QP (W5_REG_BASE + 0x148)664 * => Average CTU QP value (32 bits)665 */666#define W5_RET_ENC_PIC_BYTE (W5_REG_BASE + 0x14C)667/*668 * #define W5_RET_ENC_GOP_PIC_IDX (W5_REG_BASE + 0x150)669 * => picture index in group of pictures670 */671#define W5_RET_ENC_USED_SRC_IDX (W5_REG_BASE + 0x154)672/*673 * #define W5_RET_ENC_PIC_NUM (W5_REG_BASE + 0x158)674 * => encoded picture number675 */676#define W5_RET_ENC_VCL_NUT (W5_REG_BASE + 0x15C)677/*678 * Only for H264:679 * #define W5_RET_ENC_PIC_DIST_LOW (W5_REG_BASE + 0x164)680 * => lower 32 bits of the sum of squared difference between source Y picture681 * and reconstructed Y picture682 * #define W5_RET_ENC_PIC_DIST_HIGH (W5_REG_BASE + 0x168)683 * => upper 32 bits of the sum of squared difference between source Y picture684 * and reconstructed Y picture685 */686#define W5_RET_ENC_PIC_MAX_LATENCY_PICS (W5_REG_BASE + 0x16C)687 688#define W5_RET_ENC_HOST_CMD_TICK (W5_REG_BASE + 0x1B8)689/*690 * #define W5_RET_ENC_PREPARE_START_TICK (W5_REG_BASE + 0x1BC)691 * #define W5_RET_ENC_PREPARE_END_TICK (W5_REG_BASE + 0x1C0)692 * => Start and end ticks for preparing slices of the picture693 * #define W5_RET_ENC_PROCESSING_START_TICK (W5_REG_BASE + 0x1C4)694 * #define W5_RET_ENC_PROCESSING_END_TICK (W5_REG_BASE + 0x1C8)695 * => Start and end ticks for processing slices of the picture696 * #define W5_RET_ENC_ENCODING_START_TICK (W5_REG_BASE + 0x1CC)697 * => Start tick for encoding slices of the picture698 */699#define W5_RET_ENC_ENCODING_END_TICK (W5_REG_BASE + 0x1D0)700 701#define W5_RET_ENC_WARN_INFO (W5_REG_BASE + 0x1D4)702#define W5_RET_ENC_ERR_INFO (W5_REG_BASE + 0x1D8)703#define W5_RET_ENC_ENCODING_SUCCESS (W5_REG_BASE + 0x1DC)704 705/************************************************************************/706/* ENCODER - QUERY (GET_BS_WR_PTR) */707/************************************************************************/708#define W5_RET_ENC_RD_PTR (W5_REG_BASE + 0x114)709#define W5_RET_ENC_WR_PTR (W5_REG_BASE + 0x118)710#define W5_CMD_ENC_REASON_SEL (W5_REG_BASE + 0x11C)711 712/************************************************************************/713/* ENCODER - QUERY (GET_BW_REPORT) */714/************************************************************************/715#define RET_QUERY_BW_PRP_AXI_READ (W5_REG_BASE + 0x118)716#define RET_QUERY_BW_PRP_AXI_WRITE (W5_REG_BASE + 0x11C)717#define RET_QUERY_BW_FBD_Y_AXI_READ (W5_REG_BASE + 0x120)718#define RET_QUERY_BW_FBC_Y_AXI_WRITE (W5_REG_BASE + 0x124)719#define RET_QUERY_BW_FBD_C_AXI_READ (W5_REG_BASE + 0x128)720#define RET_QUERY_BW_FBC_C_AXI_WRITE (W5_REG_BASE + 0x12C)721#define RET_QUERY_BW_PRI_AXI_READ (W5_REG_BASE + 0x130)722#define RET_QUERY_BW_PRI_AXI_WRITE (W5_REG_BASE + 0x134)723#define RET_QUERY_BW_SEC_AXI_READ (W5_REG_BASE + 0x138)724#define RET_QUERY_BW_SEC_AXI_WRITE (W5_REG_BASE + 0x13C)725#define RET_QUERY_BW_PROC_AXI_READ (W5_REG_BASE + 0x140)726#define RET_QUERY_BW_PROC_AXI_WRITE (W5_REG_BASE + 0x144)727#define RET_QUERY_BW_BWB_AXI_WRITE (W5_REG_BASE + 0x148)728#define W5_CMD_BW_OPTION (W5_REG_BASE + 0x14C)729 730/************************************************************************/731/* ENCODER - QUERY (GET_SRC_FLAG) */732/************************************************************************/733#define W5_RET_RELEASED_SRC_INSTANCE (W5_REG_BASE + 0x1EC)734 735#define W5_ENC_PIC_SUB_FRAME_SYNC_IF (W5_REG_BASE + 0x0300)736 737#endif /* __WAVE5_REGISTER_DEFINE_H__ */738