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1// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)2/*3 * Wave5 series multi-standard codec IP - platform driver4 *5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC6 */7#include <linux/kernel.h>8#include <linux/module.h>9#include <linux/platform_device.h>10#include <linux/clk.h>11#include <linux/firmware.h>12#include <linux/interrupt.h>13#include <linux/reset.h>14#include "wave5-vpu.h"15#include "wave5-regdefine.h"16#include "wave5-vpuconfig.h"17#include "wave5.h"18 19#define VPU_PLATFORM_DEVICE_NAME "vdec"20#define VPU_CLK_NAME "vcodec"21 22#define WAVE5_IS_ENC BIT(0)23#define WAVE5_IS_DEC BIT(1)24 25struct wave5_match_data {26 int flags;27 const char *fw_name;28 u32 sram_size;29};30 31static int vpu_poll_interval = 5;32module_param(vpu_poll_interval, int, 0644);33 34int wave5_vpu_wait_interrupt(struct vpu_instance *inst, unsigned int timeout)35{36 int ret;37 38 ret = wait_for_completion_timeout(&inst->irq_done,39 msecs_to_jiffies(timeout));40 if (!ret)41 return -ETIMEDOUT;42 43 reinit_completion(&inst->irq_done);44 45 return 0;46}47 48static void wave5_vpu_handle_irq(void *dev_id)49{50 u32 seq_done;51 u32 cmd_done;52 u32 irq_reason;53 struct vpu_instance *inst;54 struct vpu_device *dev = dev_id;55 56 irq_reason = wave5_vdi_read_register(dev, W5_VPU_VINT_REASON);57 wave5_vdi_write_register(dev, W5_VPU_VINT_REASON_CLR, irq_reason);58 wave5_vdi_write_register(dev, W5_VPU_VINT_CLEAR, 0x1);59 60 list_for_each_entry(inst, &dev->instances, list) {61 seq_done = wave5_vdi_read_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO);62 cmd_done = wave5_vdi_read_register(dev, W5_RET_QUEUE_CMD_DONE_INST);63 64 if (irq_reason & BIT(INT_WAVE5_INIT_SEQ) ||65 irq_reason & BIT(INT_WAVE5_ENC_SET_PARAM)) {66 if (dev->product_code == WAVE515_CODE &&67 (cmd_done & BIT(inst->id))) {68 cmd_done &= ~BIT(inst->id);69 wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST,70 cmd_done);71 complete(&inst->irq_done);72 } else if (seq_done & BIT(inst->id)) {73 seq_done &= ~BIT(inst->id);74 wave5_vdi_write_register(dev, W5_RET_SEQ_DONE_INSTANCE_INFO,75 seq_done);76 complete(&inst->irq_done);77 }78 }79 80 if (irq_reason & BIT(INT_WAVE5_DEC_PIC) ||81 irq_reason & BIT(INT_WAVE5_ENC_PIC)) {82 if (cmd_done & BIT(inst->id)) {83 cmd_done &= ~BIT(inst->id);84 wave5_vdi_write_register(dev, W5_RET_QUEUE_CMD_DONE_INST,85 cmd_done);86 inst->ops->finish_process(inst);87 }88 }89 90 wave5_vpu_clear_interrupt(inst, irq_reason);91 }92}93 94static irqreturn_t wave5_vpu_irq_thread(int irq, void *dev_id)95{96 struct vpu_device *dev = dev_id;97 98 if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS))99 wave5_vpu_handle_irq(dev);100 101 return IRQ_HANDLED;102}103 104static void wave5_vpu_irq_work_fn(struct kthread_work *work)105{106 struct vpu_device *dev = container_of(work, struct vpu_device, work);107 108 if (wave5_vdi_read_register(dev, W5_VPU_VPU_INT_STS))109 wave5_vpu_handle_irq(dev);110}111 112static enum hrtimer_restart wave5_vpu_timer_callback(struct hrtimer *timer)113{114 struct vpu_device *dev =115 container_of(timer, struct vpu_device, hrtimer);116 117 kthread_queue_work(dev->worker, &dev->work);118 hrtimer_forward_now(timer, ns_to_ktime(vpu_poll_interval * NSEC_PER_MSEC));119 120 return HRTIMER_RESTART;121}122 123static int wave5_vpu_load_firmware(struct device *dev, const char *fw_name,124 u32 *revision)125{126 const struct firmware *fw;127 int ret;128 unsigned int product_id;129 130 ret = request_firmware(&fw, fw_name, dev);131 if (ret) {132 dev_err(dev, "request_firmware, fail: %d\n", ret);133 return ret;134 }135 136 ret = wave5_vpu_init_with_bitcode(dev, (u8 *)fw->data, fw->size);137 if (ret) {138 dev_err(dev, "vpu_init_with_bitcode, fail: %d\n", ret);139 release_firmware(fw);140 return ret;141 }142 release_firmware(fw);143 144 ret = wave5_vpu_get_version_info(dev, revision, &product_id);145 if (ret) {146 dev_err(dev, "vpu_get_version_info fail: %d\n", ret);147 return ret;148 }149 150 dev_dbg(dev, "%s: enum product_id: %08x, fw revision: %u\n",151 __func__, product_id, *revision);152 153 return 0;154}155 156static int wave5_vpu_probe(struct platform_device *pdev)157{158 int ret;159 struct vpu_device *dev;160 const struct wave5_match_data *match_data;161 u32 fw_revision;162 163 match_data = device_get_match_data(&pdev->dev);164 if (!match_data) {165 dev_err(&pdev->dev, "missing device match data\n");166 return -EINVAL;167 }168 169 /* physical addresses limited to 32 bits */170 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));171 if (ret) {172 dev_err(&pdev->dev, "Failed to set DMA mask: %d\n", ret);173 return ret;174 }175 176 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);177 if (!dev)178 return -ENOMEM;179 180 dev->vdb_register = devm_platform_ioremap_resource(pdev, 0);181 if (IS_ERR(dev->vdb_register))182 return PTR_ERR(dev->vdb_register);183 ida_init(&dev->inst_ida);184 185 mutex_init(&dev->dev_lock);186 mutex_init(&dev->hw_lock);187 dev_set_drvdata(&pdev->dev, dev);188 dev->dev = &pdev->dev;189 190 dev->resets = devm_reset_control_array_get_optional_exclusive(&pdev->dev);191 if (IS_ERR(dev->resets)) {192 return dev_err_probe(&pdev->dev, PTR_ERR(dev->resets),193 "Failed to get reset control\n");194 }195 196 ret = reset_control_deassert(dev->resets);197 if (ret)198 return dev_err_probe(&pdev->dev, ret, "Failed to deassert resets\n");199 200 ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks);201 202 /* continue without clock, assume externally managed */203 if (ret < 0) {204 dev_warn(&pdev->dev, "Getting clocks, fail: %d\n", ret);205 ret = 0;206 }207 dev->num_clks = ret;208 209 ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks);210 if (ret) {211 dev_err(&pdev->dev, "Enabling clocks, fail: %d\n", ret);212 goto err_reset_assert;213 }214 215 dev->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0);216 if (!dev->sram_pool)217 dev_warn(&pdev->dev, "sram node not found\n");218 219 dev->sram_size = match_data->sram_size;220 221 dev->product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER);222 ret = wave5_vdi_init(&pdev->dev);223 if (ret < 0) {224 dev_err(&pdev->dev, "wave5_vdi_init, fail: %d\n", ret);225 goto err_clk_dis;226 }227 dev->product = wave5_vpu_get_product_id(dev);228 229 dev->irq = platform_get_irq(pdev, 0);230 if (dev->irq < 0) {231 dev_err(&pdev->dev, "failed to get irq resource, falling back to polling\n");232 hrtimer_init(&dev->hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED);233 dev->hrtimer.function = &wave5_vpu_timer_callback;234 dev->worker = kthread_create_worker(0, "vpu_irq_thread");235 if (IS_ERR(dev->worker)) {236 dev_err(&pdev->dev, "failed to create vpu irq worker\n");237 ret = PTR_ERR(dev->worker);238 goto err_vdi_release;239 }240 dev->vpu_poll_interval = vpu_poll_interval;241 kthread_init_work(&dev->work, wave5_vpu_irq_work_fn);242 } else {243 ret = devm_request_threaded_irq(&pdev->dev, dev->irq, NULL,244 wave5_vpu_irq_thread, IRQF_ONESHOT, "vpu_irq", dev);245 if (ret) {246 dev_err(&pdev->dev, "Register interrupt handler, fail: %d\n", ret);247 goto err_enc_unreg;248 }249 }250 251 INIT_LIST_HEAD(&dev->instances);252 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);253 if (ret) {254 dev_err(&pdev->dev, "v4l2_device_register, fail: %d\n", ret);255 goto err_vdi_release;256 }257 258 if (match_data->flags & WAVE5_IS_DEC) {259 ret = wave5_vpu_dec_register_device(dev);260 if (ret) {261 dev_err(&pdev->dev, "wave5_vpu_dec_register_device, fail: %d\n", ret);262 goto err_v4l2_unregister;263 }264 }265 if (match_data->flags & WAVE5_IS_ENC) {266 ret = wave5_vpu_enc_register_device(dev);267 if (ret) {268 dev_err(&pdev->dev, "wave5_vpu_enc_register_device, fail: %d\n", ret);269 goto err_dec_unreg;270 }271 }272 273 ret = wave5_vpu_load_firmware(&pdev->dev, match_data->fw_name, &fw_revision);274 if (ret) {275 dev_err(&pdev->dev, "wave5_vpu_load_firmware, fail: %d\n", ret);276 goto err_enc_unreg;277 }278 279 dev_info(&pdev->dev, "Added wave5 driver with caps: %s %s\n",280 (match_data->flags & WAVE5_IS_ENC) ? "'ENCODE'" : "",281 (match_data->flags & WAVE5_IS_DEC) ? "'DECODE'" : "");282 dev_info(&pdev->dev, "Product Code: 0x%x\n", dev->product_code);283 dev_info(&pdev->dev, "Firmware Revision: %u\n", fw_revision);284 return 0;285 286err_enc_unreg:287 if (match_data->flags & WAVE5_IS_ENC)288 wave5_vpu_enc_unregister_device(dev);289err_dec_unreg:290 if (match_data->flags & WAVE5_IS_DEC)291 wave5_vpu_dec_unregister_device(dev);292err_v4l2_unregister:293 v4l2_device_unregister(&dev->v4l2_dev);294err_vdi_release:295 wave5_vdi_release(&pdev->dev);296err_clk_dis:297 clk_bulk_disable_unprepare(dev->num_clks, dev->clks);298err_reset_assert:299 reset_control_assert(dev->resets);300 301 return ret;302}303 304static void wave5_vpu_remove(struct platform_device *pdev)305{306 struct vpu_device *dev = dev_get_drvdata(&pdev->dev);307 308 if (dev->irq < 0) {309 kthread_destroy_worker(dev->worker);310 hrtimer_cancel(&dev->hrtimer);311 }312 313 mutex_destroy(&dev->dev_lock);314 mutex_destroy(&dev->hw_lock);315 reset_control_assert(dev->resets);316 clk_bulk_disable_unprepare(dev->num_clks, dev->clks);317 wave5_vpu_enc_unregister_device(dev);318 wave5_vpu_dec_unregister_device(dev);319 v4l2_device_unregister(&dev->v4l2_dev);320 wave5_vdi_release(&pdev->dev);321 ida_destroy(&dev->inst_ida);322}323 324static const struct wave5_match_data ti_wave521c_data = {325 .flags = WAVE5_IS_ENC | WAVE5_IS_DEC,326 .fw_name = "cnm/wave521c_k3_codec_fw.bin",327 .sram_size = (64 * 1024),328};329 330static const struct of_device_id wave5_dt_ids[] = {331 { .compatible = "ti,j721s2-wave521c", .data = &ti_wave521c_data },332 { /* sentinel */ }333};334MODULE_DEVICE_TABLE(of, wave5_dt_ids);335 336static struct platform_driver wave5_vpu_driver = {337 .driver = {338 .name = VPU_PLATFORM_DEVICE_NAME,339 .of_match_table = of_match_ptr(wave5_dt_ids),340 },341 .probe = wave5_vpu_probe,342 .remove_new = wave5_vpu_remove,343};344 345module_platform_driver(wave5_vpu_driver);346MODULE_DESCRIPTION("chips&media VPU V4L2 driver");347MODULE_LICENSE("Dual BSD/GPL");348