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1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */2/*3 * Wave5 series multi-standard codec IP - product config definitions4 *5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC6 */7 8#ifndef _VPU_CONFIG_H_9#define _VPU_CONFIG_H_10 11#define WAVE515_CODE 0x515012#define WAVE517_CODE 0x517013#define WAVE537_CODE 0x537014#define WAVE511_CODE 0x511015#define WAVE521_CODE 0x521016#define WAVE521C_CODE 0x521c17#define WAVE521C_DUAL_CODE 0x521d // wave521 dual core18#define WAVE521E1_CODE 0x521119 20#define PRODUCT_CODE_W_SERIES(x) ({ \21 int c = x; \22 ((c) == WAVE517_CODE || (c) == WAVE537_CODE || \23 (c) == WAVE511_CODE || (c) == WAVE521_CODE || \24 (c) == WAVE521E1_CODE || (c) == WAVE521C_CODE || \25 (c) == WAVE521C_DUAL_CODE) || (c) == WAVE515_CODE; \26})27 28#define WAVE517_WORKBUF_SIZE (2 * 1024 * 1024)29#define WAVE521ENC_WORKBUF_SIZE (128 * 1024) //HEVC 128K, AVC 40K30#define WAVE521DEC_WORKBUF_SIZE (1784 * 1024)31#define WAVE515DEC_WORKBUF_SIZE (2 * 1024 * 1024)32 33#define MAX_NUM_INSTANCE 3234 35#define W5_MIN_ENC_PIC_WIDTH 25636#define W5_MIN_ENC_PIC_HEIGHT 12837#define W5_MAX_ENC_PIC_WIDTH 819238#define W5_MAX_ENC_PIC_HEIGHT 819239 40// application specific configuration41#define VPU_ENC_TIMEOUT 6000042#define VPU_DEC_TIMEOUT 6000043 44// for WAVE encoder45#define USE_SRC_PRP_AXI 046#define USE_SRC_PRI_AXI 147#define DEFAULT_SRC_AXI USE_SRC_PRP_AXI48 49/************************************************************************/50/* VPU COMMON MEMORY */51/************************************************************************/52#define VLC_BUF_NUM (2)53 54#define WAVE521_COMMAND_QUEUE_DEPTH (2)55#define WAVE515_COMMAND_QUEUE_DEPTH (4)56 57#define W5_REMAP_INDEX0 058#define W5_REMAP_INDEX1 159#define W5_REMAP_MAX_SIZE (1024 * 1024)60 61#define WAVE521_MAX_CODE_BUF_SIZE (2 * 1024 * 1024)62#define WAVE515_MAX_CODE_BUF_SIZE (1024 * 1024)63#define WAVE5_TEMPBUF_SIZE (1024 * 1024)64 65#define WAVE521_SIZE_COMMON (WAVE521_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE)66#define WAVE515_ONE_TASKBUF_SIZE (8 * 1024 * 1024)67#define WAVE515_SIZE_COMMON (WAVE515_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE + \68 WAVE515_COMMAND_QUEUE_DEPTH * WAVE515_ONE_TASKBUF_SIZE)69 70//=====4. VPU REPORT MEMORY ======================//71 72#define WAVE5_UPPER_PROC_AXI_ID 0x073 74#define WAVE5_PROC_AXI_ID 0x075#define WAVE5_PRP_AXI_ID 0x076#define WAVE5_FBD_Y_AXI_ID 0x077#define WAVE5_FBC_Y_AXI_ID 0x078#define WAVE5_FBD_C_AXI_ID 0x079#define WAVE5_FBC_C_AXI_ID 0x080#define WAVE5_SEC_AXI_ID 0x081#define WAVE5_PRI_AXI_ID 0x082 83#endif /* _VPU_CONFIG_H_ */84